diff --git a/llvm/test/CodeGen/X86/fmf-reduction.ll b/llvm/test/CodeGen/X86/fmf-reduction.ll
new file mode 100644
index 0000000000000..e959ef8fdba86
--- /dev/null
+++ b/llvm/test/CodeGen/X86/fmf-reduction.ll
@@ -0,0 +1,27 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-- -mattr=fma | FileCheck %s
+
+; FIXME: Propagation of IR FMF should not drop flags when adding the DAG reduction flag.
+; This should include an FMA instruction, not separate FMUL/FADD.
+
+define double @julia_dotf(<4 x double> %x, <4 x double> %y, <4 x double> %z, i1 %t3) {
+; CHECK-LABEL: julia_dotf:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vmulpd %ymm1, %ymm0, %ymm0
+; CHECK-NEXT:    vaddpd %ymm0, %ymm2, %ymm0
+; CHECK-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; CHECK-NEXT:    vaddpd %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
+; CHECK-NEXT:    vaddsd %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    vzeroupper
+; CHECK-NEXT:    retq
+  %t1 = fmul contract <4 x double> %x, %y
+  %t2 = fadd fast <4 x double> %z, %t1
+  %rdx.shuf = shufflevector <4 x double> %t2, <4 x double> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
+  %bin.rdx22 = fadd fast <4 x double> %t2, %rdx.shuf
+  %rdx.shuf23 = shufflevector <4 x double> %bin.rdx22, <4 x double> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
+  %bin.rdx24 = fadd fast <4 x double> %bin.rdx22, %rdx.shuf23
+  %t4 = extractelement <4 x double> %bin.rdx24, i32 0
+  ret double %t4
+}
+