diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index 02d3c47bb1a434..2f5ea98c7d4d0f 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -268,7 +268,7 @@ void RISCVPassConfig::addPreEmitPass2() {
 
 void RISCVPassConfig::addMachineSSAOptimization() {
   TargetPassConfig::addMachineSSAOptimization();
-  if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableMachineCombiner)
+  if (EnableMachineCombiner)
     addPass(&MachineCombinerID);
 
   if (TM->getTargetTriple().getArch() == Triple::riscv64)
diff --git a/llvm/test/CodeGen/RISCV/machine-combiner-mir.ll b/llvm/test/CodeGen/RISCV/machine-combiner-mir.ll
index adb05ee50697eb..9965fa96e8719c 100644
--- a/llvm/test/CodeGen/RISCV/machine-combiner-mir.ll
+++ b/llvm/test/CodeGen/RISCV/machine-combiner-mir.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 ; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs -mcpu=sifive-u74 \
-; RUN: -O3 -riscv-enable-machine-combiner=true        \
+; RUN: -O1 -riscv-enable-machine-combiner=true        \
 ; RUN: -stop-after machine-combiner < %s | FileCheck %s
 
 define double @test_reassoc_fadd1(double %a0, double %a1, double %a2, double %a3) {
diff --git a/llvm/test/CodeGen/RISCV/machine-combiner.ll b/llvm/test/CodeGen/RISCV/machine-combiner.ll
index 6d9a7e92680699..58e5ed9d77b8da 100644
--- a/llvm/test/CodeGen/RISCV/machine-combiner.ll
+++ b/llvm/test/CodeGen/RISCV/machine-combiner.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs -mcpu=sifive-u74 \
-; RUN: -O3 -riscv-enable-machine-combiner=true < %s | \
+; RUN: -O1 -riscv-enable-machine-combiner=true < %s | \
 ; RUN: FileCheck %s
 
 define double @test_reassoc_fadd1(double %a0, double %a1, double %a2, double %a3) {