From 1658b8d7ddb65eb78e1304b009f1043ab6d9463f Mon Sep 17 00:00:00 2001
From: Jay Foad <jay.foad@amd.com>
Date: Tue, 14 Jul 2020 09:03:12 +0100
Subject: [PATCH] [AMDGPU] Avoid using s_cmpk when src0 is not register

The hardware spec require src0 of s_cmpk should be a register. So, we
should not optimize s_cmp to s_cmpk if src0 is not register.

Patch by Ruiling Song!
---
 llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp |  5 +++++
 llvm/test/CodeGen/AMDGPU/cmp_shrink.mir         | 11 +++++++++++
 2 files changed, 16 insertions(+)
 create mode 100644 llvm/test/CodeGen/AMDGPU/cmp_shrink.mir

diff --git a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
index 53b7f7d3ca0a9..9c6833a7dab61 100644
--- a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
+++ b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
@@ -185,6 +185,11 @@ static void shrinkScalarCompare(const SIInstrInfo *TII, MachineInstr &MI) {
   if (!MI.getOperand(0).isReg())
     TII->commuteInstruction(MI, false, 0, 1);
 
+  // cmpk requires src0 to be a register
+  const MachineOperand &Src0 = MI.getOperand(0);
+  if (!Src0.isReg())
+    return;
+
   const MachineOperand &Src1 = MI.getOperand(1);
   if (!Src1.isImm())
     return;
diff --git a/llvm/test/CodeGen/AMDGPU/cmp_shrink.mir b/llvm/test/CodeGen/AMDGPU/cmp_shrink.mir
new file mode 100644
index 0000000000000..e7bf09ab49b2a
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/cmp_shrink.mir
@@ -0,0 +1,11 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass si-shrink-instructions -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
+
+---
+name:             not_shrink_icmp
+body:             |
+  bb.0:
+    ; GCN-LABEL: name: not_shrink_icmp
+    ; GCN: S_CMP_GT_I32 1, 65, implicit-def $scc
+    S_CMP_GT_I32 1, 65, implicit-def $scc
+...