diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index d5b4a98147192..413af1ff4b943 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -779,15 +779,22 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, // Splice setOperationAction(ISD::VECTOR_SPLICE, VT, Custom); + if (Subtarget.hasStdExtZvkb()) { + setOperationAction(ISD::BSWAP, VT, Legal); + setOperationAction(ISD::VP_BSWAP, VT, Custom); + } else { + setOperationAction({ISD::BSWAP, ISD::VP_BSWAP}, VT, Expand); + setOperationAction({ISD::ROTL, ISD::ROTR}, VT, Expand); + } + if (Subtarget.hasStdExtZvbb()) { - setOperationAction({ISD::BITREVERSE, ISD::BSWAP}, VT, Legal); - setOperationAction({ISD::VP_BITREVERSE, ISD::VP_BSWAP}, VT, Custom); + setOperationAction(ISD::BITREVERSE, VT, Legal); + setOperationAction(ISD::VP_BITREVERSE, VT, Custom); setOperationAction({ISD::VP_CTLZ, ISD::VP_CTLZ_ZERO_UNDEF, ISD::VP_CTTZ, ISD::VP_CTTZ_ZERO_UNDEF, ISD::VP_CTPOP}, VT, Custom); } else { - setOperationAction({ISD::BITREVERSE, ISD::BSWAP}, VT, Expand); - setOperationAction({ISD::VP_BITREVERSE, ISD::VP_BSWAP}, VT, Expand); + setOperationAction({ISD::BITREVERSE, ISD::VP_BITREVERSE}, VT, Expand); setOperationAction({ISD::CTLZ, ISD::CTTZ, ISD::CTPOP}, VT, Expand); setOperationAction({ISD::VP_CTLZ, ISD::VP_CTLZ_ZERO_UNDEF, ISD::VP_CTTZ, ISD::VP_CTTZ_ZERO_UNDEF, ISD::VP_CTPOP}, @@ -802,8 +809,6 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, ISD::VP_CTLZ_ZERO_UNDEF, ISD::VP_CTTZ_ZERO_UNDEF}, VT, Custom); } - - setOperationAction({ISD::ROTL, ISD::ROTR}, VT, Expand); } } @@ -1109,11 +1114,12 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, setOperationAction(IntegerVPOps, VT, Custom); + if (Subtarget.hasStdExtZvkb()) + setOperationAction({ISD::BSWAP, ISD::ROTL, ISD::ROTR}, VT, Custom); + if (Subtarget.hasStdExtZvbb()) { - setOperationAction({ISD::BITREVERSE, ISD::BSWAP, ISD::CTLZ, - ISD::CTLZ_ZERO_UNDEF, ISD::CTTZ, - ISD::CTTZ_ZERO_UNDEF, ISD::CTPOP, ISD::ROTL, - ISD::ROTR}, + setOperationAction({ISD::BITREVERSE, ISD::CTLZ, ISD::CTLZ_ZERO_UNDEF, + ISD::CTTZ, ISD::CTTZ_ZERO_UNDEF, ISD::CTPOP}, VT, Custom); } else { // Lower CTLZ_ZERO_UNDEF and CTTZ_ZERO_UNDEF if element of VT in the @@ -4376,7 +4382,7 @@ static SDValue lowerBitreverseShuffle(ShuffleVectorSDNode *SVN, // Given a shuffle mask like <3, 0, 1, 2, 7, 4, 5, 6> for v8i8, we can // reinterpret it as a v2i32 and rotate it right by 8 instead. We can lower this -// as a vror.vi if we have zvbb, or otherwise as a vsll, vsrl and vor. +// as a vror.vi if we have Zvkb, or otherwise as a vsll, vsrl and vor. static SDValue lowerVECTOR_SHUFFLEAsRotate(ShuffleVectorSDNode *SVN, SelectionDAG &DAG, const RISCVSubtarget &Subtarget) { @@ -4527,9 +4533,9 @@ static SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG, lowerVECTOR_SHUFFLEAsVSlidedown(DL, VT, V1, V2, Mask, Subtarget, DAG)) return V; - // A bitrotate will be one instruction on zvbb, so try to lower to it first if + // A bitrotate will be one instruction on Zvkb, so try to lower to it first if // available. - if (Subtarget.hasStdExtZvbb()) + if (Subtarget.hasStdExtZvkb()) if (SDValue V = lowerVECTOR_SHUFFLEAsRotate(SVN, DAG, Subtarget)) return V; @@ -4660,7 +4666,7 @@ static SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG, return DAG.getNode(ISD::VSELECT, DL, VT, SelectMask, V1, V2); // We might be able to express the shuffle as a bitrotate. But even if we - // don't have zvbb and have to expand, the expanded sequence of approx. 2 + // don't have Zvkb and have to expand, the expanded sequence of approx. 2 // shifts and a vor will have a higher throughput than a vrgather. if (SDValue V = lowerVECTOR_SHUFFLEAsRotate(SVN, DAG, Subtarget)) return V; @@ -5482,7 +5488,7 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op, case ISD::ROTL: case ISD::ROTR: if (Op.getValueType().isFixedLengthVector()) { - assert(Subtarget.hasStdExtZvbb()); + assert(Subtarget.hasStdExtZvkb()); return lowerToScalableOp(Op, DAG); } assert(Subtarget.hasVendorXTHeadBb() && diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td index b904323a3bfb5..272d7f64b4d99 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td @@ -410,9 +410,10 @@ let Predicates = [HasStdExtZvksh] in { // SDNode patterns //===----------------------------------------------------------------------===// -multiclass VPatUnarySDNode_V { +multiclass VPatUnarySDNode_V { foreach vti = AllIntegerVectors in { - let Predicates = !listconcat([HasStdExtZvbb], + let Predicates = !listconcat([predicate], GetVTypePredicates.Predicates) in { def : Pat<(vti.Vector (op (vti.Vector vti.RegClass:$rs1))), (!cast(instruction_name#"_V_"#vti.LMul.MX) @@ -431,7 +432,7 @@ def riscv_vnot : PatFrag<(ops node:$rs1), (xor node:$rs1, (riscv_splat_vector -1))>; foreach vti = AllIntegerVectors in { - let Predicates = !listconcat([HasStdExtZvbb], + let Predicates = !listconcat([HasStdExtZvkb], GetVTypePredicates.Predicates) in { def : Pat<(vti.Vector (and (riscv_vnot vti.RegClass:$rs1), vti.RegClass:$rs2)), @@ -452,7 +453,7 @@ foreach vti = AllIntegerVectors in { } defm : VPatUnarySDNode_V; -defm : VPatUnarySDNode_V; +defm : VPatUnarySDNode_V; defm : VPatUnarySDNode_V; defm : VPatUnarySDNode_V; defm : VPatUnarySDNode_V; @@ -480,7 +481,7 @@ def InvRot64Imm : SDNodeXForm.Predicates) in { def : Pat<(vti.Vector (rotl vti.RegClass:$rs2, (vti.Vector (SplatPat_uimm6 uimm6:$rs1)))), @@ -526,9 +527,10 @@ foreach vtiToWti = AllWidenableIntVectors in { // VL patterns //===----------------------------------------------------------------------===// -multiclass VPatUnaryVL_V { +multiclass VPatUnaryVL_V { foreach vti = AllIntegerVectors in { - let Predicates = !listconcat([HasStdExtZvbb], + let Predicates = !listconcat([predicate], GetVTypePredicates.Predicates) in { def : Pat<(vti.Vector (op (vti.Vector vti.RegClass:$rs1), (vti.Vector vti.RegClass:$merge), @@ -546,7 +548,7 @@ multiclass VPatUnaryVL_V { } foreach vti = AllIntegerVectors in { - let Predicates = !listconcat([HasStdExtZvbb], + let Predicates = !listconcat([HasStdExtZvkb], GetVTypePredicates.Predicates) in { def : Pat<(vti.Vector (riscv_and_vl (riscv_xor_vl (vti.Vector vti.RegClass:$rs1), @@ -585,7 +587,7 @@ foreach vti = AllIntegerVectors in { } defm : VPatUnaryVL_V; -defm : VPatUnaryVL_V; +defm : VPatUnaryVL_V; defm : VPatUnaryVL_V; defm : VPatUnaryVL_V; defm : VPatUnaryVL_V; @@ -594,7 +596,7 @@ defm : VPatBinaryVL_VV_VX; // Although there is no vrol.vi, an immediate rotate left can be achieved by // negating the immediate in vror.vi foreach vti = AllIntegerVectors in { - let Predicates = !listconcat([HasStdExtZvbb], + let Predicates = !listconcat([HasStdExtZvkb], GetVTypePredicates.Predicates) in { def : Pat<(riscv_rotl_vl vti.RegClass:$rs2, (vti.Vector (SplatPat_uimm6 uimm6:$rs1)), diff --git a/llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll index 690ecc6eab33b..884bb206a31eb 100644 --- a/llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 ; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 -; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB -; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB +; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB +; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB define @bswap_nxv1i16( %va) { ; CHECK-LABEL: bswap_nxv1i16: @@ -13,11 +13,11 @@ define @bswap_nxv1i16( %va) { ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: bswap_nxv1i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, mf4, ta, ma -; CHECK-ZVBB-NEXT: vrev8.v v8, v8 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: bswap_nxv1i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, mf4, ta, ma +; CHECK-ZVKB-NEXT: vrev8.v v8, v8 +; CHECK-ZVKB-NEXT: ret %a = call @llvm.bswap.nxv1i16( %va) ret %a } @@ -32,11 +32,11 @@ define @bswap_nxv2i16( %va) { ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: bswap_nxv2i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, mf2, ta, ma -; CHECK-ZVBB-NEXT: vrev8.v v8, v8 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: bswap_nxv2i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, mf2, ta, ma +; CHECK-ZVKB-NEXT: vrev8.v v8, v8 +; CHECK-ZVKB-NEXT: ret %a = call @llvm.bswap.nxv2i16( %va) ret %a } @@ -51,11 +51,11 @@ define @bswap_nxv4i16( %va) { ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: bswap_nxv4i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m1, ta, ma -; CHECK-ZVBB-NEXT: vrev8.v v8, v8 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: bswap_nxv4i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, m1, ta, ma +; CHECK-ZVKB-NEXT: vrev8.v v8, v8 +; CHECK-ZVKB-NEXT: ret %a = call @llvm.bswap.nxv4i16( %va) ret %a } @@ -70,11 +70,11 @@ define @bswap_nxv8i16( %va) { ; CHECK-NEXT: vor.vv v8, v8, v10 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: bswap_nxv8i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m2, ta, ma -; CHECK-ZVBB-NEXT: vrev8.v v8, v8 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: bswap_nxv8i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, m2, ta, ma +; CHECK-ZVKB-NEXT: vrev8.v v8, v8 +; CHECK-ZVKB-NEXT: ret %a = call @llvm.bswap.nxv8i16( %va) ret %a } @@ -89,11 +89,11 @@ define @bswap_nxv16i16( %va) { ; CHECK-NEXT: vor.vv v8, v8, v12 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: bswap_nxv16i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m4, ta, ma -; CHECK-ZVBB-NEXT: vrev8.v v8, v8 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: bswap_nxv16i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, m4, ta, ma +; CHECK-ZVKB-NEXT: vrev8.v v8, v8 +; CHECK-ZVKB-NEXT: ret %a = call @llvm.bswap.nxv16i16( %va) ret %a } @@ -108,11 +108,11 @@ define @bswap_nxv32i16( %va) { ; CHECK-NEXT: vor.vv v8, v8, v16 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: bswap_nxv32i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m8, ta, ma -; CHECK-ZVBB-NEXT: vrev8.v v8, v8 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: bswap_nxv32i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, m8, ta, ma +; CHECK-ZVKB-NEXT: vrev8.v v8, v8 +; CHECK-ZVKB-NEXT: ret %a = call @llvm.bswap.nxv32i16( %va) ret %a } @@ -151,11 +151,11 @@ define @bswap_nxv1i32( %va) { ; RV64-NEXT: vor.vv v8, v8, v9 ; RV64-NEXT: ret ; -; CHECK-ZVBB-LABEL: bswap_nxv1i32: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, mf2, ta, ma -; CHECK-ZVBB-NEXT: vrev8.v v8, v8 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: bswap_nxv1i32: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a0, zero, e32, mf2, ta, ma +; CHECK-ZVKB-NEXT: vrev8.v v8, v8 +; CHECK-ZVKB-NEXT: ret %a = call @llvm.bswap.nxv1i32( %va) ret %a } @@ -194,11 +194,11 @@ define @bswap_nxv2i32( %va) { ; RV64-NEXT: vor.vv v8, v8, v9 ; RV64-NEXT: ret ; -; CHECK-ZVBB-LABEL: bswap_nxv2i32: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m1, ta, ma -; CHECK-ZVBB-NEXT: vrev8.v v8, v8 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: bswap_nxv2i32: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a0, zero, e32, m1, ta, ma +; CHECK-ZVKB-NEXT: vrev8.v v8, v8 +; CHECK-ZVKB-NEXT: ret %a = call @llvm.bswap.nxv2i32( %va) ret %a } @@ -237,11 +237,11 @@ define @bswap_nxv4i32( %va) { ; RV64-NEXT: vor.vv v8, v8, v10 ; RV64-NEXT: ret ; -; CHECK-ZVBB-LABEL: bswap_nxv4i32: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m2, ta, ma -; CHECK-ZVBB-NEXT: vrev8.v v8, v8 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: bswap_nxv4i32: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a0, zero, e32, m2, ta, ma +; CHECK-ZVKB-NEXT: vrev8.v v8, v8 +; CHECK-ZVKB-NEXT: ret %a = call @llvm.bswap.nxv4i32( %va) ret %a } @@ -280,11 +280,11 @@ define @bswap_nxv8i32( %va) { ; RV64-NEXT: vor.vv v8, v8, v12 ; RV64-NEXT: ret ; -; CHECK-ZVBB-LABEL: bswap_nxv8i32: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; CHECK-ZVBB-NEXT: vrev8.v v8, v8 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: bswap_nxv8i32: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a0, zero, e32, m4, ta, ma +; CHECK-ZVKB-NEXT: vrev8.v v8, v8 +; CHECK-ZVKB-NEXT: ret %a = call @llvm.bswap.nxv8i32( %va) ret %a } @@ -323,11 +323,11 @@ define @bswap_nxv16i32( %va) { ; RV64-NEXT: vor.vv v8, v8, v16 ; RV64-NEXT: ret ; -; CHECK-ZVBB-LABEL: bswap_nxv16i32: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m8, ta, ma -; CHECK-ZVBB-NEXT: vrev8.v v8, v8 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: bswap_nxv16i32: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a0, zero, e32, m8, ta, ma +; CHECK-ZVKB-NEXT: vrev8.v v8, v8 +; CHECK-ZVKB-NEXT: ret %a = call @llvm.bswap.nxv16i32( %va) ret %a } @@ -406,11 +406,11 @@ define @bswap_nxv1i64( %va) { ; RV64-NEXT: vor.vv v8, v8, v9 ; RV64-NEXT: ret ; -; CHECK-ZVBB-LABEL: bswap_nxv1i64: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m1, ta, ma -; CHECK-ZVBB-NEXT: vrev8.v v8, v8 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: bswap_nxv1i64: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a0, zero, e64, m1, ta, ma +; CHECK-ZVKB-NEXT: vrev8.v v8, v8 +; CHECK-ZVKB-NEXT: ret %a = call @llvm.bswap.nxv1i64( %va) ret %a } @@ -489,11 +489,11 @@ define @bswap_nxv2i64( %va) { ; RV64-NEXT: vor.vv v8, v8, v10 ; RV64-NEXT: ret ; -; CHECK-ZVBB-LABEL: bswap_nxv2i64: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m2, ta, ma -; CHECK-ZVBB-NEXT: vrev8.v v8, v8 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: bswap_nxv2i64: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a0, zero, e64, m2, ta, ma +; CHECK-ZVKB-NEXT: vrev8.v v8, v8 +; CHECK-ZVKB-NEXT: ret %a = call @llvm.bswap.nxv2i64( %va) ret %a } @@ -572,11 +572,11 @@ define @bswap_nxv4i64( %va) { ; RV64-NEXT: vor.vv v8, v8, v12 ; RV64-NEXT: ret ; -; CHECK-ZVBB-LABEL: bswap_nxv4i64: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m4, ta, ma -; CHECK-ZVBB-NEXT: vrev8.v v8, v8 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: bswap_nxv4i64: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a0, zero, e64, m4, ta, ma +; CHECK-ZVKB-NEXT: vrev8.v v8, v8 +; CHECK-ZVKB-NEXT: ret %a = call @llvm.bswap.nxv4i64( %va) ret %a } @@ -669,11 +669,11 @@ define @bswap_nxv8i64( %va) { ; RV64-NEXT: vor.vv v8, v8, v16 ; RV64-NEXT: ret ; -; CHECK-ZVBB-LABEL: bswap_nxv8i64: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m8, ta, ma -; CHECK-ZVBB-NEXT: vrev8.v v8, v8 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: bswap_nxv8i64: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a0, zero, e64, m8, ta, ma +; CHECK-ZVKB-NEXT: vrev8.v v8, v8 +; CHECK-ZVKB-NEXT: ret %a = call @llvm.bswap.nxv8i64( %va) ret %a } diff --git a/llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll b/llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll index be79222b5c5a7..3c4ff5e7d1cef 100644 --- a/llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll @@ -3,10 +3,10 @@ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 ; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 -; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvbb,+m -target-abi=ilp32d \ -; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB -; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvbb,+m -target-abi=lp64d \ -; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB +; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvkb,+m -target-abi=ilp32d \ +; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB +; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvkb,+m -target-abi=lp64d \ +; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB declare @llvm.vp.bswap.nxv1i16(, , i32) @@ -19,11 +19,11 @@ define @vp_bswap_nxv1i16( %va, @llvm.vp.bswap.nxv1i16( %va, %m, i32 %evl) ret %v } @@ -37,11 +37,11 @@ define @vp_bswap_nxv1i16_unmasked( %va, i32 ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vp_bswap_nxv1i16_unmasked: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-ZVBB-NEXT: vrev8.v v8, v8 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vp_bswap_nxv1i16_unmasked: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma +; CHECK-ZVKB-NEXT: vrev8.v v8, v8 +; CHECK-ZVKB-NEXT: ret %head = insertelement poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer %v = call @llvm.vp.bswap.nxv1i16( %va, %m, i32 %evl) @@ -59,11 +59,11 @@ define @vp_bswap_nxv2i16( %va, @llvm.vp.bswap.nxv2i16( %va, %m, i32 %evl) ret %v } @@ -77,11 +77,11 @@ define @vp_bswap_nxv2i16_unmasked( %va, i32 ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vp_bswap_nxv2i16_unmasked: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-ZVBB-NEXT: vrev8.v v8, v8 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vp_bswap_nxv2i16_unmasked: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli zero, a0, e16, mf2, ta, ma +; CHECK-ZVKB-NEXT: vrev8.v v8, v8 +; CHECK-ZVKB-NEXT: ret %head = insertelement poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer %v = call @llvm.vp.bswap.nxv2i16( %va, %m, i32 %evl) @@ -99,11 +99,11 @@ define @vp_bswap_nxv4i16( %va, @llvm.vp.bswap.nxv4i16( %va, %m, i32 %evl) ret %v } @@ -117,11 +117,11 @@ define @vp_bswap_nxv4i16_unmasked( %va, i32 ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vp_bswap_nxv4i16_unmasked: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-ZVBB-NEXT: vrev8.v v8, v8 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vp_bswap_nxv4i16_unmasked: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli zero, a0, e16, m1, ta, ma +; CHECK-ZVKB-NEXT: vrev8.v v8, v8 +; CHECK-ZVKB-NEXT: ret %head = insertelement poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer %v = call @llvm.vp.bswap.nxv4i16( %va, %m, i32 %evl) @@ -139,11 +139,11 @@ define @vp_bswap_nxv8i16( %va, @llvm.vp.bswap.nxv8i16( %va, %m, i32 %evl) ret %v } @@ -157,11 +157,11 @@ define @vp_bswap_nxv8i16_unmasked( %va, i32 ; CHECK-NEXT: vor.vv v8, v8, v10 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vp_bswap_nxv8i16_unmasked: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-ZVBB-NEXT: vrev8.v v8, v8 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vp_bswap_nxv8i16_unmasked: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli zero, a0, e16, m2, ta, ma +; CHECK-ZVKB-NEXT: vrev8.v v8, v8 +; CHECK-ZVKB-NEXT: ret %head = insertelement poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer %v = call @llvm.vp.bswap.nxv8i16( %va, %m, i32 %evl) @@ -179,11 +179,11 @@ define @vp_bswap_nxv16i16( %va, @llvm.vp.bswap.nxv16i16( %va, %m, i32 %evl) ret %v } @@ -197,11 +197,11 @@ define @vp_bswap_nxv16i16_unmasked( %va, ; CHECK-NEXT: vor.vv v8, v8, v12 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vp_bswap_nxv16i16_unmasked: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-ZVBB-NEXT: vrev8.v v8, v8 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vp_bswap_nxv16i16_unmasked: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli zero, a0, e16, m4, ta, ma +; CHECK-ZVKB-NEXT: vrev8.v v8, v8 +; CHECK-ZVKB-NEXT: ret %head = insertelement poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer %v = call @llvm.vp.bswap.nxv16i16( %va, %m, i32 %evl) @@ -219,11 +219,11 @@ define @vp_bswap_nxv32i16( %va, @llvm.vp.bswap.nxv32i16( %va, %m, i32 %evl) ret %v } @@ -237,11 +237,11 @@ define @vp_bswap_nxv32i16_unmasked( %va, ; CHECK-NEXT: vor.vv v8, v8, v16 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vp_bswap_nxv32i16_unmasked: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m8, ta, ma -; CHECK-ZVBB-NEXT: vrev8.v v8, v8 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vp_bswap_nxv32i16_unmasked: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli zero, a0, e16, m8, ta, ma +; CHECK-ZVKB-NEXT: vrev8.v v8, v8 +; CHECK-ZVKB-NEXT: ret %head = insertelement poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer %v = call @llvm.vp.bswap.nxv32i16( %va, %m, i32 %evl) @@ -283,11 +283,11 @@ define @vp_bswap_nxv1i32( %va, @llvm.vp.bswap.nxv1i32( %va, %m, i32 %evl) ret %v } @@ -325,11 +325,11 @@ define @vp_bswap_nxv1i32_unmasked( %va, i32 ; RV64-NEXT: vor.vv v8, v8, v9 ; RV64-NEXT: ret ; -; CHECK-ZVBB-LABEL: vp_bswap_nxv1i32_unmasked: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-ZVBB-NEXT: vrev8.v v8, v8 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vp_bswap_nxv1i32_unmasked: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; CHECK-ZVKB-NEXT: vrev8.v v8, v8 +; CHECK-ZVKB-NEXT: ret %head = insertelement poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer %v = call @llvm.vp.bswap.nxv1i32( %va, %m, i32 %evl) @@ -371,11 +371,11 @@ define @vp_bswap_nxv2i32( %va, @llvm.vp.bswap.nxv2i32( %va, %m, i32 %evl) ret %v } @@ -413,11 +413,11 @@ define @vp_bswap_nxv2i32_unmasked( %va, i32 ; RV64-NEXT: vor.vv v8, v8, v9 ; RV64-NEXT: ret ; -; CHECK-ZVBB-LABEL: vp_bswap_nxv2i32_unmasked: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-ZVBB-NEXT: vrev8.v v8, v8 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vp_bswap_nxv2i32_unmasked: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; CHECK-ZVKB-NEXT: vrev8.v v8, v8 +; CHECK-ZVKB-NEXT: ret %head = insertelement poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer %v = call @llvm.vp.bswap.nxv2i32( %va, %m, i32 %evl) @@ -459,11 +459,11 @@ define @vp_bswap_nxv4i32( %va, @llvm.vp.bswap.nxv4i32( %va, %m, i32 %evl) ret %v } @@ -501,11 +501,11 @@ define @vp_bswap_nxv4i32_unmasked( %va, i32 ; RV64-NEXT: vor.vv v8, v8, v10 ; RV64-NEXT: ret ; -; CHECK-ZVBB-LABEL: vp_bswap_nxv4i32_unmasked: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-ZVBB-NEXT: vrev8.v v8, v8 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vp_bswap_nxv4i32_unmasked: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; CHECK-ZVKB-NEXT: vrev8.v v8, v8 +; CHECK-ZVKB-NEXT: ret %head = insertelement poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer %v = call @llvm.vp.bswap.nxv4i32( %va, %m, i32 %evl) @@ -547,11 +547,11 @@ define @vp_bswap_nxv8i32( %va, @llvm.vp.bswap.nxv8i32( %va, %m, i32 %evl) ret %v } @@ -589,11 +589,11 @@ define @vp_bswap_nxv8i32_unmasked( %va, i32 ; RV64-NEXT: vor.vv v8, v8, v12 ; RV64-NEXT: ret ; -; CHECK-ZVBB-LABEL: vp_bswap_nxv8i32_unmasked: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-ZVBB-NEXT: vrev8.v v8, v8 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vp_bswap_nxv8i32_unmasked: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; CHECK-ZVKB-NEXT: vrev8.v v8, v8 +; CHECK-ZVKB-NEXT: ret %head = insertelement poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer %v = call @llvm.vp.bswap.nxv8i32( %va, %m, i32 %evl) @@ -635,11 +635,11 @@ define @vp_bswap_nxv16i32( %va, @llvm.vp.bswap.nxv16i32( %va, %m, i32 %evl) ret %v } @@ -677,11 +677,11 @@ define @vp_bswap_nxv16i32_unmasked( %va, ; RV64-NEXT: vor.vv v8, v8, v16 ; RV64-NEXT: ret ; -; CHECK-ZVBB-LABEL: vp_bswap_nxv16i32_unmasked: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m8, ta, ma -; CHECK-ZVBB-NEXT: vrev8.v v8, v8 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vp_bswap_nxv16i32_unmasked: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; CHECK-ZVKB-NEXT: vrev8.v v8, v8 +; CHECK-ZVKB-NEXT: ret %head = insertelement poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer %v = call @llvm.vp.bswap.nxv16i32( %va, %m, i32 %evl) @@ -765,11 +765,11 @@ define @vp_bswap_nxv1i64( %va, @llvm.vp.bswap.nxv1i64( %va, %m, i32 %evl) ret %v } @@ -849,11 +849,11 @@ define @vp_bswap_nxv1i64_unmasked( %va, i32 ; RV64-NEXT: vor.vv v8, v9, v8 ; RV64-NEXT: ret ; -; CHECK-ZVBB-LABEL: vp_bswap_nxv1i64_unmasked: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m1, ta, ma -; CHECK-ZVBB-NEXT: vrev8.v v8, v8 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vp_bswap_nxv1i64_unmasked: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli zero, a0, e64, m1, ta, ma +; CHECK-ZVKB-NEXT: vrev8.v v8, v8 +; CHECK-ZVKB-NEXT: ret %head = insertelement poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer %v = call @llvm.vp.bswap.nxv1i64( %va, %m, i32 %evl) @@ -937,11 +937,11 @@ define @vp_bswap_nxv2i64( %va, @llvm.vp.bswap.nxv2i64( %va, %m, i32 %evl) ret %v } @@ -1021,11 +1021,11 @@ define @vp_bswap_nxv2i64_unmasked( %va, i32 ; RV64-NEXT: vor.vv v8, v10, v8 ; RV64-NEXT: ret ; -; CHECK-ZVBB-LABEL: vp_bswap_nxv2i64_unmasked: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m2, ta, ma -; CHECK-ZVBB-NEXT: vrev8.v v8, v8 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vp_bswap_nxv2i64_unmasked: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli zero, a0, e64, m2, ta, ma +; CHECK-ZVKB-NEXT: vrev8.v v8, v8 +; CHECK-ZVKB-NEXT: ret %head = insertelement poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer %v = call @llvm.vp.bswap.nxv2i64( %va, %m, i32 %evl) @@ -1109,11 +1109,11 @@ define @vp_bswap_nxv4i64( %va, @llvm.vp.bswap.nxv4i64( %va, %m, i32 %evl) ret %v } @@ -1193,11 +1193,11 @@ define @vp_bswap_nxv4i64_unmasked( %va, i32 ; RV64-NEXT: vor.vv v8, v12, v8 ; RV64-NEXT: ret ; -; CHECK-ZVBB-LABEL: vp_bswap_nxv4i64_unmasked: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m4, ta, ma -; CHECK-ZVBB-NEXT: vrev8.v v8, v8 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vp_bswap_nxv4i64_unmasked: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli zero, a0, e64, m4, ta, ma +; CHECK-ZVKB-NEXT: vrev8.v v8, v8 +; CHECK-ZVKB-NEXT: ret %head = insertelement poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer %v = call @llvm.vp.bswap.nxv4i64( %va, %m, i32 %evl) @@ -1345,11 +1345,11 @@ define @vp_bswap_nxv7i64( %va, @llvm.vp.bswap.nxv7i64( %va, %m, i32 %evl) ret %v } @@ -1442,11 +1442,11 @@ define @vp_bswap_nxv7i64_unmasked( %va, i32 ; RV64-NEXT: vor.vv v8, v16, v8 ; RV64-NEXT: ret ; -; CHECK-ZVBB-LABEL: vp_bswap_nxv7i64_unmasked: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m8, ta, ma -; CHECK-ZVBB-NEXT: vrev8.v v8, v8 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vp_bswap_nxv7i64_unmasked: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli zero, a0, e64, m8, ta, ma +; CHECK-ZVKB-NEXT: vrev8.v v8, v8 +; CHECK-ZVKB-NEXT: ret %head = insertelement poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer %v = call @llvm.vp.bswap.nxv7i64( %va, %m, i32 %evl) @@ -1594,11 +1594,11 @@ define @vp_bswap_nxv8i64( %va, @llvm.vp.bswap.nxv8i64( %va, %m, i32 %evl) ret %v } @@ -1691,11 +1691,11 @@ define @vp_bswap_nxv8i64_unmasked( %va, i32 ; RV64-NEXT: vor.vv v8, v16, v8 ; RV64-NEXT: ret ; -; CHECK-ZVBB-LABEL: vp_bswap_nxv8i64_unmasked: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m8, ta, ma -; CHECK-ZVBB-NEXT: vrev8.v v8, v8 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vp_bswap_nxv8i64_unmasked: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli zero, a0, e64, m8, ta, ma +; CHECK-ZVKB-NEXT: vrev8.v v8, v8 +; CHECK-ZVKB-NEXT: ret %head = insertelement poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer %v = call @llvm.vp.bswap.nxv8i64( %va, %m, i32 %evl) @@ -1757,28 +1757,28 @@ define @vp_bswap_nxv64i16( %va, @llvm.vp.bswap.nxv64i16( %va, %m, i32 %evl) ret %v } @@ -1806,23 +1806,23 @@ define @vp_bswap_nxv64i16_unmasked( %va, ; CHECK-NEXT: vor.vv v8, v8, v24 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vp_bswap_nxv64i16_unmasked: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: csrr a1, vlenb -; CHECK-ZVBB-NEXT: slli a1, a1, 2 -; CHECK-ZVBB-NEXT: sub a2, a0, a1 -; CHECK-ZVBB-NEXT: sltu a3, a0, a2 -; CHECK-ZVBB-NEXT: addi a3, a3, -1 -; CHECK-ZVBB-NEXT: and a2, a3, a2 -; CHECK-ZVBB-NEXT: vsetvli zero, a2, e16, m8, ta, ma -; CHECK-ZVBB-NEXT: vrev8.v v16, v16 -; CHECK-ZVBB-NEXT: bltu a0, a1, .LBB33_2 -; CHECK-ZVBB-NEXT: # %bb.1: -; CHECK-ZVBB-NEXT: mv a0, a1 -; CHECK-ZVBB-NEXT: .LBB33_2: -; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m8, ta, ma -; CHECK-ZVBB-NEXT: vrev8.v v8, v8 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vp_bswap_nxv64i16_unmasked: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: csrr a1, vlenb +; CHECK-ZVKB-NEXT: slli a1, a1, 2 +; CHECK-ZVKB-NEXT: sub a2, a0, a1 +; CHECK-ZVKB-NEXT: sltu a3, a0, a2 +; CHECK-ZVKB-NEXT: addi a3, a3, -1 +; CHECK-ZVKB-NEXT: and a2, a3, a2 +; CHECK-ZVKB-NEXT: vsetvli zero, a2, e16, m8, ta, ma +; CHECK-ZVKB-NEXT: vrev8.v v16, v16 +; CHECK-ZVKB-NEXT: bltu a0, a1, .LBB33_2 +; CHECK-ZVKB-NEXT: # %bb.1: +; CHECK-ZVKB-NEXT: mv a0, a1 +; CHECK-ZVKB-NEXT: .LBB33_2: +; CHECK-ZVKB-NEXT: vsetvli zero, a0, e16, m8, ta, ma +; CHECK-ZVKB-NEXT: vrev8.v v8, v8 +; CHECK-ZVKB-NEXT: ret %head = insertelement poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer %v = call @llvm.vp.bswap.nxv64i16( %va, %m, i32 %evl) @@ -1908,12 +1908,12 @@ define @vp_bswap_nxv1i48( %va, @llvm.vp.bswap.nxv1i48( %va, %m, i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll index 7fa1f4270525d..4d78da2d64760 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll @@ -3,8 +3,8 @@ ; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,LMULMAX2-RV64 ; RUN: llc -mtriple=riscv32 -mattr=+v -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,LMULMAX1-RV32 ; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,LMULMAX1-RV64 -; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVBB -; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVBB +; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVKB +; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVKB define void @bswap_v8i16(ptr %x, ptr %y) { ; CHECK-LABEL: bswap_v8i16: @@ -17,13 +17,13 @@ define void @bswap_v8i16(ptr %x, ptr %y) { ; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret ; -; ZVBB-LABEL: bswap_v8i16: -; ZVBB: # %bb.0: -; ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma -; ZVBB-NEXT: vle16.v v8, (a0) -; ZVBB-NEXT: vrev8.v v8, v8 -; ZVBB-NEXT: vse16.v v8, (a0) -; ZVBB-NEXT: ret +; ZVKB-LABEL: bswap_v8i16: +; ZVKB: # %bb.0: +; ZVKB-NEXT: vsetivli zero, 8, e16, m1, ta, ma +; ZVKB-NEXT: vle16.v v8, (a0) +; ZVKB-NEXT: vrev8.v v8, v8 +; ZVKB-NEXT: vse16.v v8, (a0) +; ZVKB-NEXT: ret %a = load <8 x i16>, ptr %x %b = load <8 x i16>, ptr %y %c = call <8 x i16> @llvm.bswap.v8i16(<8 x i16> %a) @@ -69,13 +69,13 @@ define void @bswap_v4i32(ptr %x, ptr %y) { ; RV64-NEXT: vse32.v v8, (a0) ; RV64-NEXT: ret ; -; ZVBB-LABEL: bswap_v4i32: -; ZVBB: # %bb.0: -; ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma -; ZVBB-NEXT: vle32.v v8, (a0) -; ZVBB-NEXT: vrev8.v v8, v8 -; ZVBB-NEXT: vse32.v v8, (a0) -; ZVBB-NEXT: ret +; ZVKB-LABEL: bswap_v4i32: +; ZVKB: # %bb.0: +; ZVKB-NEXT: vsetivli zero, 4, e32, m1, ta, ma +; ZVKB-NEXT: vle32.v v8, (a0) +; ZVKB-NEXT: vrev8.v v8, v8 +; ZVKB-NEXT: vse32.v v8, (a0) +; ZVKB-NEXT: ret %a = load <4 x i32>, ptr %x %b = load <4 x i32>, ptr %y %c = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %a) @@ -161,13 +161,13 @@ define void @bswap_v2i64(ptr %x, ptr %y) { ; RV64-NEXT: vse64.v v8, (a0) ; RV64-NEXT: ret ; -; ZVBB-LABEL: bswap_v2i64: -; ZVBB: # %bb.0: -; ZVBB-NEXT: vsetivli zero, 2, e64, m1, ta, ma -; ZVBB-NEXT: vle64.v v8, (a0) -; ZVBB-NEXT: vrev8.v v8, v8 -; ZVBB-NEXT: vse64.v v8, (a0) -; ZVBB-NEXT: ret +; ZVKB-LABEL: bswap_v2i64: +; ZVKB: # %bb.0: +; ZVKB-NEXT: vsetivli zero, 2, e64, m1, ta, ma +; ZVKB-NEXT: vle64.v v8, (a0) +; ZVKB-NEXT: vrev8.v v8, v8 +; ZVKB-NEXT: vse64.v v8, (a0) +; ZVKB-NEXT: ret %a = load <2 x i64>, ptr %x %b = load <2 x i64>, ptr %y %c = call <2 x i64> @llvm.bswap.v2i64(<2 x i64> %a) @@ -229,13 +229,13 @@ define void @bswap_v16i16(ptr %x, ptr %y) { ; LMULMAX1-RV64-NEXT: vse16.v v8, (a1) ; LMULMAX1-RV64-NEXT: ret ; -; ZVBB-LABEL: bswap_v16i16: -; ZVBB: # %bb.0: -; ZVBB-NEXT: vsetivli zero, 16, e16, m2, ta, ma -; ZVBB-NEXT: vle16.v v8, (a0) -; ZVBB-NEXT: vrev8.v v8, v8 -; ZVBB-NEXT: vse16.v v8, (a0) -; ZVBB-NEXT: ret +; ZVKB-LABEL: bswap_v16i16: +; ZVKB: # %bb.0: +; ZVKB-NEXT: vsetivli zero, 16, e16, m2, ta, ma +; ZVKB-NEXT: vle16.v v8, (a0) +; ZVKB-NEXT: vrev8.v v8, v8 +; ZVKB-NEXT: vse16.v v8, (a0) +; ZVKB-NEXT: ret %a = load <16 x i16>, ptr %x %b = load <16 x i16>, ptr %y %c = call <16 x i16> @llvm.bswap.v16i16(<16 x i16> %a) @@ -341,13 +341,13 @@ define void @bswap_v8i32(ptr %x, ptr %y) { ; LMULMAX1-RV64-NEXT: vse32.v v8, (a1) ; LMULMAX1-RV64-NEXT: ret ; -; ZVBB-LABEL: bswap_v8i32: -; ZVBB: # %bb.0: -; ZVBB-NEXT: vsetivli zero, 8, e32, m2, ta, ma -; ZVBB-NEXT: vle32.v v8, (a0) -; ZVBB-NEXT: vrev8.v v8, v8 -; ZVBB-NEXT: vse32.v v8, (a0) -; ZVBB-NEXT: ret +; ZVKB-LABEL: bswap_v8i32: +; ZVKB: # %bb.0: +; ZVKB-NEXT: vsetivli zero, 8, e32, m2, ta, ma +; ZVKB-NEXT: vle32.v v8, (a0) +; ZVKB-NEXT: vrev8.v v8, v8 +; ZVKB-NEXT: vse32.v v8, (a0) +; ZVKB-NEXT: ret %a = load <8 x i32>, ptr %x %b = load <8 x i32>, ptr %y %c = call <8 x i32> @llvm.bswap.v8i32(<8 x i32> %a) @@ -557,13 +557,13 @@ define void @bswap_v4i64(ptr %x, ptr %y) { ; LMULMAX1-RV64-NEXT: vse64.v v8, (a1) ; LMULMAX1-RV64-NEXT: ret ; -; ZVBB-LABEL: bswap_v4i64: -; ZVBB: # %bb.0: -; ZVBB-NEXT: vsetivli zero, 4, e64, m2, ta, ma -; ZVBB-NEXT: vle64.v v8, (a0) -; ZVBB-NEXT: vrev8.v v8, v8 -; ZVBB-NEXT: vse64.v v8, (a0) -; ZVBB-NEXT: ret +; ZVKB-LABEL: bswap_v4i64: +; ZVKB: # %bb.0: +; ZVKB-NEXT: vsetivli zero, 4, e64, m2, ta, ma +; ZVKB-NEXT: vle64.v v8, (a0) +; ZVKB-NEXT: vrev8.v v8, v8 +; ZVKB-NEXT: vse64.v v8, (a0) +; ZVKB-NEXT: ret %a = load <4 x i64>, ptr %x %b = load <4 x i64>, ptr %y %c = call <4 x i64> @llvm.bswap.v4i64(<4 x i64> %a) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll index 4b7bfba06377d..49cd4b85693b6 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll @@ -1,10 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 ; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfh -verify-machineinstrs < %s | FileCheck %s -check-prefixes=CHECK,RV32 ; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfh -verify-machineinstrs < %s | FileCheck %s -check-prefixes=CHECK,RV64 -; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfh,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s -check-prefixes=ZVBB-V -; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfh,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s -check-prefixes=ZVBB-V -; RUN: llc -mtriple=riscv32 -mattr=+zve32x,+zvfh,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s -check-prefixes=ZVBB-ZVE32X -; RUN: llc -mtriple=riscv64 -mattr=+zve32x,+zvfh,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s -check-prefixes=ZVBB-ZVE32X +; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfh,+experimental-zvkb -verify-machineinstrs < %s | FileCheck %s -check-prefixes=ZVKB-V +; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfh,+experimental-zvkb -verify-machineinstrs < %s | FileCheck %s -check-prefixes=ZVKB-V +; RUN: llc -mtriple=riscv32 -mattr=+zve32x,+zvfh,+experimental-zvkb -verify-machineinstrs < %s | FileCheck %s -check-prefixes=ZVKB-ZVE32X +; RUN: llc -mtriple=riscv64 -mattr=+zve32x,+zvfh,+experimental-zvkb -verify-machineinstrs < %s | FileCheck %s -check-prefixes=ZVKB-ZVE32X define <8 x i1> @shuffle_v8i1_as_i8_1(<8 x i1> %v) { ; CHECK-LABEL: shuffle_v8i1_as_i8_1: @@ -15,17 +15,17 @@ define <8 x i1> @shuffle_v8i1_as_i8_1(<8 x i1> %v) { ; CHECK-NEXT: vor.vv v0, v9, v8 ; CHECK-NEXT: ret ; -; ZVBB-V-LABEL: shuffle_v8i1_as_i8_1: -; ZVBB-V: # %bb.0: -; ZVBB-V-NEXT: vsetivli zero, 1, e8, mf8, ta, ma -; ZVBB-V-NEXT: vror.vi v0, v0, 1 -; ZVBB-V-NEXT: ret -; -; ZVBB-ZVE32X-LABEL: shuffle_v8i1_as_i8_1: -; ZVBB-ZVE32X: # %bb.0: -; ZVBB-ZVE32X-NEXT: vsetivli zero, 1, e8, mf4, ta, ma -; ZVBB-ZVE32X-NEXT: vror.vi v0, v0, 1 -; ZVBB-ZVE32X-NEXT: ret +; ZVKB-V-LABEL: shuffle_v8i1_as_i8_1: +; ZVKB-V: # %bb.0: +; ZVKB-V-NEXT: vsetivli zero, 1, e8, mf8, ta, ma +; ZVKB-V-NEXT: vror.vi v0, v0, 1 +; ZVKB-V-NEXT: ret +; +; ZVKB-ZVE32X-LABEL: shuffle_v8i1_as_i8_1: +; ZVKB-ZVE32X: # %bb.0: +; ZVKB-ZVE32X-NEXT: vsetivli zero, 1, e8, mf4, ta, ma +; ZVKB-ZVE32X-NEXT: vror.vi v0, v0, 1 +; ZVKB-ZVE32X-NEXT: ret %shuffle = shufflevector <8 x i1> %v, <8 x i1> poison, <8 x i32> ret <8 x i1> %shuffle } @@ -39,17 +39,17 @@ define <8 x i1> @shuffle_v8i1_as_i8_2(<8 x i1> %v) { ; CHECK-NEXT: vor.vv v0, v9, v8 ; CHECK-NEXT: ret ; -; ZVBB-V-LABEL: shuffle_v8i1_as_i8_2: -; ZVBB-V: # %bb.0: -; ZVBB-V-NEXT: vsetivli zero, 1, e8, mf8, ta, ma -; ZVBB-V-NEXT: vror.vi v0, v0, 2 -; ZVBB-V-NEXT: ret -; -; ZVBB-ZVE32X-LABEL: shuffle_v8i1_as_i8_2: -; ZVBB-ZVE32X: # %bb.0: -; ZVBB-ZVE32X-NEXT: vsetivli zero, 1, e8, mf4, ta, ma -; ZVBB-ZVE32X-NEXT: vror.vi v0, v0, 2 -; ZVBB-ZVE32X-NEXT: ret +; ZVKB-V-LABEL: shuffle_v8i1_as_i8_2: +; ZVKB-V: # %bb.0: +; ZVKB-V-NEXT: vsetivli zero, 1, e8, mf8, ta, ma +; ZVKB-V-NEXT: vror.vi v0, v0, 2 +; ZVKB-V-NEXT: ret +; +; ZVKB-ZVE32X-LABEL: shuffle_v8i1_as_i8_2: +; ZVKB-ZVE32X: # %bb.0: +; ZVKB-ZVE32X-NEXT: vsetivli zero, 1, e8, mf4, ta, ma +; ZVKB-ZVE32X-NEXT: vror.vi v0, v0, 2 +; ZVKB-ZVE32X-NEXT: ret %shuffle = shufflevector <8 x i1> %v, <8 x i1> poison, <8 x i32> ret <8 x i1> %shuffle } @@ -63,17 +63,17 @@ define <8 x i1> @shuffle_v8i1_as_i8_3(<8 x i1> %v) { ; CHECK-NEXT: vor.vv v0, v9, v8 ; CHECK-NEXT: ret ; -; ZVBB-V-LABEL: shuffle_v8i1_as_i8_3: -; ZVBB-V: # %bb.0: -; ZVBB-V-NEXT: vsetivli zero, 1, e8, mf8, ta, ma -; ZVBB-V-NEXT: vror.vi v0, v0, 3 -; ZVBB-V-NEXT: ret -; -; ZVBB-ZVE32X-LABEL: shuffle_v8i1_as_i8_3: -; ZVBB-ZVE32X: # %bb.0: -; ZVBB-ZVE32X-NEXT: vsetivli zero, 1, e8, mf4, ta, ma -; ZVBB-ZVE32X-NEXT: vror.vi v0, v0, 3 -; ZVBB-ZVE32X-NEXT: ret +; ZVKB-V-LABEL: shuffle_v8i1_as_i8_3: +; ZVKB-V: # %bb.0: +; ZVKB-V-NEXT: vsetivli zero, 1, e8, mf8, ta, ma +; ZVKB-V-NEXT: vror.vi v0, v0, 3 +; ZVKB-V-NEXT: ret +; +; ZVKB-ZVE32X-LABEL: shuffle_v8i1_as_i8_3: +; ZVKB-ZVE32X: # %bb.0: +; ZVKB-ZVE32X-NEXT: vsetivli zero, 1, e8, mf4, ta, ma +; ZVKB-ZVE32X-NEXT: vror.vi v0, v0, 3 +; ZVKB-ZVE32X-NEXT: ret %shuffle = shufflevector <8 x i1> %v, <8 x i1> poison, <8 x i32> ret <8 x i1> %shuffle } @@ -87,17 +87,17 @@ define <8 x i1> @shuffle_v8i1_as_i8_4(<8 x i1> %v) { ; CHECK-NEXT: vor.vv v0, v9, v8 ; CHECK-NEXT: ret ; -; ZVBB-V-LABEL: shuffle_v8i1_as_i8_4: -; ZVBB-V: # %bb.0: -; ZVBB-V-NEXT: vsetivli zero, 1, e8, mf8, ta, ma -; ZVBB-V-NEXT: vror.vi v0, v0, 4 -; ZVBB-V-NEXT: ret -; -; ZVBB-ZVE32X-LABEL: shuffle_v8i1_as_i8_4: -; ZVBB-ZVE32X: # %bb.0: -; ZVBB-ZVE32X-NEXT: vsetivli zero, 1, e8, mf4, ta, ma -; ZVBB-ZVE32X-NEXT: vror.vi v0, v0, 4 -; ZVBB-ZVE32X-NEXT: ret +; ZVKB-V-LABEL: shuffle_v8i1_as_i8_4: +; ZVKB-V: # %bb.0: +; ZVKB-V-NEXT: vsetivli zero, 1, e8, mf8, ta, ma +; ZVKB-V-NEXT: vror.vi v0, v0, 4 +; ZVKB-V-NEXT: ret +; +; ZVKB-ZVE32X-LABEL: shuffle_v8i1_as_i8_4: +; ZVKB-ZVE32X: # %bb.0: +; ZVKB-ZVE32X-NEXT: vsetivli zero, 1, e8, mf4, ta, ma +; ZVKB-ZVE32X-NEXT: vror.vi v0, v0, 4 +; ZVKB-ZVE32X-NEXT: ret %shuffle = shufflevector <8 x i1> %v, <8 x i1> poison, <8 x i32> ret <8 x i1> %shuffle } @@ -111,17 +111,17 @@ define <8 x i1> @shuffle_v8i1_as_i8_5(<8 x i1> %v) { ; CHECK-NEXT: vor.vv v0, v9, v8 ; CHECK-NEXT: ret ; -; ZVBB-V-LABEL: shuffle_v8i1_as_i8_5: -; ZVBB-V: # %bb.0: -; ZVBB-V-NEXT: vsetivli zero, 1, e8, mf8, ta, ma -; ZVBB-V-NEXT: vror.vi v0, v0, 5 -; ZVBB-V-NEXT: ret -; -; ZVBB-ZVE32X-LABEL: shuffle_v8i1_as_i8_5: -; ZVBB-ZVE32X: # %bb.0: -; ZVBB-ZVE32X-NEXT: vsetivli zero, 1, e8, mf4, ta, ma -; ZVBB-ZVE32X-NEXT: vror.vi v0, v0, 5 -; ZVBB-ZVE32X-NEXT: ret +; ZVKB-V-LABEL: shuffle_v8i1_as_i8_5: +; ZVKB-V: # %bb.0: +; ZVKB-V-NEXT: vsetivli zero, 1, e8, mf8, ta, ma +; ZVKB-V-NEXT: vror.vi v0, v0, 5 +; ZVKB-V-NEXT: ret +; +; ZVKB-ZVE32X-LABEL: shuffle_v8i1_as_i8_5: +; ZVKB-ZVE32X: # %bb.0: +; ZVKB-ZVE32X-NEXT: vsetivli zero, 1, e8, mf4, ta, ma +; ZVKB-ZVE32X-NEXT: vror.vi v0, v0, 5 +; ZVKB-ZVE32X-NEXT: ret %shuffle = shufflevector <8 x i1> %v, <8 x i1> poison, <8 x i32> ret <8 x i1> %shuffle } @@ -135,17 +135,17 @@ define <8 x i1> @shuffle_v8i1_as_i8_6(<8 x i1> %v) { ; CHECK-NEXT: vor.vv v0, v9, v8 ; CHECK-NEXT: ret ; -; ZVBB-V-LABEL: shuffle_v8i1_as_i8_6: -; ZVBB-V: # %bb.0: -; ZVBB-V-NEXT: vsetivli zero, 1, e8, mf8, ta, ma -; ZVBB-V-NEXT: vror.vi v0, v0, 6 -; ZVBB-V-NEXT: ret -; -; ZVBB-ZVE32X-LABEL: shuffle_v8i1_as_i8_6: -; ZVBB-ZVE32X: # %bb.0: -; ZVBB-ZVE32X-NEXT: vsetivli zero, 1, e8, mf4, ta, ma -; ZVBB-ZVE32X-NEXT: vror.vi v0, v0, 6 -; ZVBB-ZVE32X-NEXT: ret +; ZVKB-V-LABEL: shuffle_v8i1_as_i8_6: +; ZVKB-V: # %bb.0: +; ZVKB-V-NEXT: vsetivli zero, 1, e8, mf8, ta, ma +; ZVKB-V-NEXT: vror.vi v0, v0, 6 +; ZVKB-V-NEXT: ret +; +; ZVKB-ZVE32X-LABEL: shuffle_v8i1_as_i8_6: +; ZVKB-ZVE32X: # %bb.0: +; ZVKB-ZVE32X-NEXT: vsetivli zero, 1, e8, mf4, ta, ma +; ZVKB-ZVE32X-NEXT: vror.vi v0, v0, 6 +; ZVKB-ZVE32X-NEXT: ret %shuffle = shufflevector <8 x i1> %v, <8 x i1> poison, <8 x i32> ret <8 x i1> %shuffle } @@ -159,17 +159,17 @@ define <8 x i1> @shuffle_v8i1_as_i8_7(<8 x i1> %v) { ; CHECK-NEXT: vor.vv v0, v9, v8 ; CHECK-NEXT: ret ; -; ZVBB-V-LABEL: shuffle_v8i1_as_i8_7: -; ZVBB-V: # %bb.0: -; ZVBB-V-NEXT: vsetivli zero, 1, e8, mf8, ta, ma -; ZVBB-V-NEXT: vror.vi v0, v0, 7 -; ZVBB-V-NEXT: ret -; -; ZVBB-ZVE32X-LABEL: shuffle_v8i1_as_i8_7: -; ZVBB-ZVE32X: # %bb.0: -; ZVBB-ZVE32X-NEXT: vsetivli zero, 1, e8, mf4, ta, ma -; ZVBB-ZVE32X-NEXT: vror.vi v0, v0, 7 -; ZVBB-ZVE32X-NEXT: ret +; ZVKB-V-LABEL: shuffle_v8i1_as_i8_7: +; ZVKB-V: # %bb.0: +; ZVKB-V-NEXT: vsetivli zero, 1, e8, mf8, ta, ma +; ZVKB-V-NEXT: vror.vi v0, v0, 7 +; ZVKB-V-NEXT: ret +; +; ZVKB-ZVE32X-LABEL: shuffle_v8i1_as_i8_7: +; ZVKB-ZVE32X: # %bb.0: +; ZVKB-ZVE32X-NEXT: vsetivli zero, 1, e8, mf4, ta, ma +; ZVKB-ZVE32X-NEXT: vror.vi v0, v0, 7 +; ZVKB-ZVE32X-NEXT: ret %shuffle = shufflevector <8 x i1> %v, <8 x i1> poison, <8 x i32> ret <8 x i1> %shuffle } @@ -183,17 +183,17 @@ define <8 x i8> @shuffle_v8i8_as_i16(<8 x i8> %v) { ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret ; -; ZVBB-V-LABEL: shuffle_v8i8_as_i16: -; ZVBB-V: # %bb.0: -; ZVBB-V-NEXT: vsetivli zero, 4, e16, mf2, ta, ma -; ZVBB-V-NEXT: vrev8.v v8, v8 -; ZVBB-V-NEXT: ret -; -; ZVBB-ZVE32X-LABEL: shuffle_v8i8_as_i16: -; ZVBB-ZVE32X: # %bb.0: -; ZVBB-ZVE32X-NEXT: vsetivli zero, 4, e16, m2, ta, ma -; ZVBB-ZVE32X-NEXT: vrev8.v v8, v8 -; ZVBB-ZVE32X-NEXT: ret +; ZVKB-V-LABEL: shuffle_v8i8_as_i16: +; ZVKB-V: # %bb.0: +; ZVKB-V-NEXT: vsetivli zero, 4, e16, mf2, ta, ma +; ZVKB-V-NEXT: vrev8.v v8, v8 +; ZVKB-V-NEXT: ret +; +; ZVKB-ZVE32X-LABEL: shuffle_v8i8_as_i16: +; ZVKB-ZVE32X: # %bb.0: +; ZVKB-ZVE32X-NEXT: vsetivli zero, 4, e16, m2, ta, ma +; ZVKB-ZVE32X-NEXT: vrev8.v v8, v8 +; ZVKB-ZVE32X-NEXT: ret %shuffle = shufflevector <8 x i8> %v, <8 x i8> poison, <8 x i32> ret <8 x i8> %shuffle } @@ -207,17 +207,17 @@ define <8 x i8> @shuffle_v8i8_as_i32_8(<8 x i8> %v) { ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret ; -; ZVBB-V-LABEL: shuffle_v8i8_as_i32_8: -; ZVBB-V: # %bb.0: -; ZVBB-V-NEXT: vsetivli zero, 2, e32, mf2, ta, ma -; ZVBB-V-NEXT: vror.vi v8, v8, 8 -; ZVBB-V-NEXT: ret -; -; ZVBB-ZVE32X-LABEL: shuffle_v8i8_as_i32_8: -; ZVBB-ZVE32X: # %bb.0: -; ZVBB-ZVE32X-NEXT: vsetivli zero, 2, e32, m2, ta, ma -; ZVBB-ZVE32X-NEXT: vror.vi v8, v8, 8 -; ZVBB-ZVE32X-NEXT: ret +; ZVKB-V-LABEL: shuffle_v8i8_as_i32_8: +; ZVKB-V: # %bb.0: +; ZVKB-V-NEXT: vsetivli zero, 2, e32, mf2, ta, ma +; ZVKB-V-NEXT: vror.vi v8, v8, 8 +; ZVKB-V-NEXT: ret +; +; ZVKB-ZVE32X-LABEL: shuffle_v8i8_as_i32_8: +; ZVKB-ZVE32X: # %bb.0: +; ZVKB-ZVE32X-NEXT: vsetivli zero, 2, e32, m2, ta, ma +; ZVKB-ZVE32X-NEXT: vror.vi v8, v8, 8 +; ZVKB-ZVE32X-NEXT: ret %shuffle = shufflevector <8 x i8> %v, <8 x i8> poison, <8 x i32> ret <8 x i8> %shuffle } @@ -231,17 +231,17 @@ define <8 x i8> @shuffle_v8i8_as_i32_16(<8 x i8> %v) { ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret ; -; ZVBB-V-LABEL: shuffle_v8i8_as_i32_16: -; ZVBB-V: # %bb.0: -; ZVBB-V-NEXT: vsetivli zero, 2, e32, mf2, ta, ma -; ZVBB-V-NEXT: vror.vi v8, v8, 16 -; ZVBB-V-NEXT: ret -; -; ZVBB-ZVE32X-LABEL: shuffle_v8i8_as_i32_16: -; ZVBB-ZVE32X: # %bb.0: -; ZVBB-ZVE32X-NEXT: vsetivli zero, 2, e32, m2, ta, ma -; ZVBB-ZVE32X-NEXT: vror.vi v8, v8, 16 -; ZVBB-ZVE32X-NEXT: ret +; ZVKB-V-LABEL: shuffle_v8i8_as_i32_16: +; ZVKB-V: # %bb.0: +; ZVKB-V-NEXT: vsetivli zero, 2, e32, mf2, ta, ma +; ZVKB-V-NEXT: vror.vi v8, v8, 16 +; ZVKB-V-NEXT: ret +; +; ZVKB-ZVE32X-LABEL: shuffle_v8i8_as_i32_16: +; ZVKB-ZVE32X: # %bb.0: +; ZVKB-ZVE32X-NEXT: vsetivli zero, 2, e32, m2, ta, ma +; ZVKB-ZVE32X-NEXT: vror.vi v8, v8, 16 +; ZVKB-ZVE32X-NEXT: ret %shuffle = shufflevector <8 x i8> %v, <8 x i8> poison, <8 x i32> ret <8 x i8> %shuffle } @@ -255,17 +255,17 @@ define <8 x i8> @shuffle_v8i8_as_i32_24(<8 x i8> %v) { ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret ; -; ZVBB-V-LABEL: shuffle_v8i8_as_i32_24: -; ZVBB-V: # %bb.0: -; ZVBB-V-NEXT: vsetivli zero, 2, e32, mf2, ta, ma -; ZVBB-V-NEXT: vror.vi v8, v8, 24 -; ZVBB-V-NEXT: ret -; -; ZVBB-ZVE32X-LABEL: shuffle_v8i8_as_i32_24: -; ZVBB-ZVE32X: # %bb.0: -; ZVBB-ZVE32X-NEXT: vsetivli zero, 2, e32, m2, ta, ma -; ZVBB-ZVE32X-NEXT: vror.vi v8, v8, 24 -; ZVBB-ZVE32X-NEXT: ret +; ZVKB-V-LABEL: shuffle_v8i8_as_i32_24: +; ZVKB-V: # %bb.0: +; ZVKB-V-NEXT: vsetivli zero, 2, e32, mf2, ta, ma +; ZVKB-V-NEXT: vror.vi v8, v8, 24 +; ZVKB-V-NEXT: ret +; +; ZVKB-ZVE32X-LABEL: shuffle_v8i8_as_i32_24: +; ZVKB-ZVE32X: # %bb.0: +; ZVKB-ZVE32X-NEXT: vsetivli zero, 2, e32, m2, ta, ma +; ZVKB-ZVE32X-NEXT: vror.vi v8, v8, 24 +; ZVKB-ZVE32X-NEXT: ret %shuffle = shufflevector <8 x i8> %v, <8 x i8> poison, <8 x i32> ret <8 x i8> %shuffle } @@ -279,19 +279,19 @@ define <8 x i8> @shuffle_v8i8_as_i64_8(<8 x i8> %v) { ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret ; -; ZVBB-V-LABEL: shuffle_v8i8_as_i64_8: -; ZVBB-V: # %bb.0: -; ZVBB-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma -; ZVBB-V-NEXT: vror.vi v8, v8, 8 -; ZVBB-V-NEXT: ret -; -; ZVBB-ZVE32X-LABEL: shuffle_v8i8_as_i64_8: -; ZVBB-ZVE32X: # %bb.0: -; ZVBB-ZVE32X-NEXT: vsetivli zero, 8, e8, m2, ta, ma -; ZVBB-ZVE32X-NEXT: vslidedown.vi v10, v8, 1 -; ZVBB-ZVE32X-NEXT: vslideup.vi v10, v8, 7 -; ZVBB-ZVE32X-NEXT: vmv.v.v v8, v10 -; ZVBB-ZVE32X-NEXT: ret +; ZVKB-V-LABEL: shuffle_v8i8_as_i64_8: +; ZVKB-V: # %bb.0: +; ZVKB-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma +; ZVKB-V-NEXT: vror.vi v8, v8, 8 +; ZVKB-V-NEXT: ret +; +; ZVKB-ZVE32X-LABEL: shuffle_v8i8_as_i64_8: +; ZVKB-ZVE32X: # %bb.0: +; ZVKB-ZVE32X-NEXT: vsetivli zero, 8, e8, m2, ta, ma +; ZVKB-ZVE32X-NEXT: vslidedown.vi v10, v8, 1 +; ZVKB-ZVE32X-NEXT: vslideup.vi v10, v8, 7 +; ZVKB-ZVE32X-NEXT: vmv.v.v v8, v10 +; ZVKB-ZVE32X-NEXT: ret %shuffle = shufflevector <8 x i8> %v, <8 x i8> poison, <8 x i32> ret <8 x i8> %shuffle } @@ -305,19 +305,19 @@ define <8 x i8> @shuffle_v8i8_as_i64_16(<8 x i8> %v) { ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret ; -; ZVBB-V-LABEL: shuffle_v8i8_as_i64_16: -; ZVBB-V: # %bb.0: -; ZVBB-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma -; ZVBB-V-NEXT: vror.vi v8, v8, 16 -; ZVBB-V-NEXT: ret -; -; ZVBB-ZVE32X-LABEL: shuffle_v8i8_as_i64_16: -; ZVBB-ZVE32X: # %bb.0: -; ZVBB-ZVE32X-NEXT: vsetivli zero, 8, e8, m2, ta, ma -; ZVBB-ZVE32X-NEXT: vslidedown.vi v10, v8, 2 -; ZVBB-ZVE32X-NEXT: vslideup.vi v10, v8, 6 -; ZVBB-ZVE32X-NEXT: vmv.v.v v8, v10 -; ZVBB-ZVE32X-NEXT: ret +; ZVKB-V-LABEL: shuffle_v8i8_as_i64_16: +; ZVKB-V: # %bb.0: +; ZVKB-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma +; ZVKB-V-NEXT: vror.vi v8, v8, 16 +; ZVKB-V-NEXT: ret +; +; ZVKB-ZVE32X-LABEL: shuffle_v8i8_as_i64_16: +; ZVKB-ZVE32X: # %bb.0: +; ZVKB-ZVE32X-NEXT: vsetivli zero, 8, e8, m2, ta, ma +; ZVKB-ZVE32X-NEXT: vslidedown.vi v10, v8, 2 +; ZVKB-ZVE32X-NEXT: vslideup.vi v10, v8, 6 +; ZVKB-ZVE32X-NEXT: vmv.v.v v8, v10 +; ZVKB-ZVE32X-NEXT: ret %shuffle = shufflevector <8 x i8> %v, <8 x i8> poison, <8 x i32> ret <8 x i8> %shuffle } @@ -331,19 +331,19 @@ define <8 x i8> @shuffle_v8i8_as_i64_24(<8 x i8> %v) { ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret ; -; ZVBB-V-LABEL: shuffle_v8i8_as_i64_24: -; ZVBB-V: # %bb.0: -; ZVBB-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma -; ZVBB-V-NEXT: vror.vi v8, v8, 24 -; ZVBB-V-NEXT: ret -; -; ZVBB-ZVE32X-LABEL: shuffle_v8i8_as_i64_24: -; ZVBB-ZVE32X: # %bb.0: -; ZVBB-ZVE32X-NEXT: vsetivli zero, 8, e8, m2, ta, ma -; ZVBB-ZVE32X-NEXT: vslidedown.vi v10, v8, 3 -; ZVBB-ZVE32X-NEXT: vslideup.vi v10, v8, 5 -; ZVBB-ZVE32X-NEXT: vmv.v.v v8, v10 -; ZVBB-ZVE32X-NEXT: ret +; ZVKB-V-LABEL: shuffle_v8i8_as_i64_24: +; ZVKB-V: # %bb.0: +; ZVKB-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma +; ZVKB-V-NEXT: vror.vi v8, v8, 24 +; ZVKB-V-NEXT: ret +; +; ZVKB-ZVE32X-LABEL: shuffle_v8i8_as_i64_24: +; ZVKB-ZVE32X: # %bb.0: +; ZVKB-ZVE32X-NEXT: vsetivli zero, 8, e8, m2, ta, ma +; ZVKB-ZVE32X-NEXT: vslidedown.vi v10, v8, 3 +; ZVKB-ZVE32X-NEXT: vslideup.vi v10, v8, 5 +; ZVKB-ZVE32X-NEXT: vmv.v.v v8, v10 +; ZVKB-ZVE32X-NEXT: ret %shuffle = shufflevector <8 x i8> %v, <8 x i8> poison, <8 x i32> ret <8 x i8> %shuffle } @@ -357,19 +357,19 @@ define <8 x i8> @shuffle_v8i8_as_i64_32(<8 x i8> %v) { ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret ; -; ZVBB-V-LABEL: shuffle_v8i8_as_i64_32: -; ZVBB-V: # %bb.0: -; ZVBB-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma -; ZVBB-V-NEXT: vror.vi v8, v8, 32 -; ZVBB-V-NEXT: ret -; -; ZVBB-ZVE32X-LABEL: shuffle_v8i8_as_i64_32: -; ZVBB-ZVE32X: # %bb.0: -; ZVBB-ZVE32X-NEXT: vsetivli zero, 8, e8, m2, ta, ma -; ZVBB-ZVE32X-NEXT: vslidedown.vi v10, v8, 4 -; ZVBB-ZVE32X-NEXT: vslideup.vi v10, v8, 4 -; ZVBB-ZVE32X-NEXT: vmv.v.v v8, v10 -; ZVBB-ZVE32X-NEXT: ret +; ZVKB-V-LABEL: shuffle_v8i8_as_i64_32: +; ZVKB-V: # %bb.0: +; ZVKB-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma +; ZVKB-V-NEXT: vror.vi v8, v8, 32 +; ZVKB-V-NEXT: ret +; +; ZVKB-ZVE32X-LABEL: shuffle_v8i8_as_i64_32: +; ZVKB-ZVE32X: # %bb.0: +; ZVKB-ZVE32X-NEXT: vsetivli zero, 8, e8, m2, ta, ma +; ZVKB-ZVE32X-NEXT: vslidedown.vi v10, v8, 4 +; ZVKB-ZVE32X-NEXT: vslideup.vi v10, v8, 4 +; ZVKB-ZVE32X-NEXT: vmv.v.v v8, v10 +; ZVKB-ZVE32X-NEXT: ret %shuffle = shufflevector <8 x i8> %v, <8 x i8> poison, <8 x i32> ret <8 x i8> %shuffle } @@ -383,19 +383,19 @@ define <8 x i8> @shuffle_v8i8_as_i64_40(<8 x i8> %v) { ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret ; -; ZVBB-V-LABEL: shuffle_v8i8_as_i64_40: -; ZVBB-V: # %bb.0: -; ZVBB-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma -; ZVBB-V-NEXT: vror.vi v8, v8, 40 -; ZVBB-V-NEXT: ret -; -; ZVBB-ZVE32X-LABEL: shuffle_v8i8_as_i64_40: -; ZVBB-ZVE32X: # %bb.0: -; ZVBB-ZVE32X-NEXT: vsetivli zero, 8, e8, m2, ta, ma -; ZVBB-ZVE32X-NEXT: vslidedown.vi v10, v8, 5 -; ZVBB-ZVE32X-NEXT: vslideup.vi v10, v8, 3 -; ZVBB-ZVE32X-NEXT: vmv.v.v v8, v10 -; ZVBB-ZVE32X-NEXT: ret +; ZVKB-V-LABEL: shuffle_v8i8_as_i64_40: +; ZVKB-V: # %bb.0: +; ZVKB-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma +; ZVKB-V-NEXT: vror.vi v8, v8, 40 +; ZVKB-V-NEXT: ret +; +; ZVKB-ZVE32X-LABEL: shuffle_v8i8_as_i64_40: +; ZVKB-ZVE32X: # %bb.0: +; ZVKB-ZVE32X-NEXT: vsetivli zero, 8, e8, m2, ta, ma +; ZVKB-ZVE32X-NEXT: vslidedown.vi v10, v8, 5 +; ZVKB-ZVE32X-NEXT: vslideup.vi v10, v8, 3 +; ZVKB-ZVE32X-NEXT: vmv.v.v v8, v10 +; ZVKB-ZVE32X-NEXT: ret %shuffle = shufflevector <8 x i8> %v, <8 x i8> poison, <8 x i32> ret <8 x i8> %shuffle } @@ -409,19 +409,19 @@ define <8 x i8> @shuffle_v8i8_as_i64_48(<8 x i8> %v) { ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret ; -; ZVBB-V-LABEL: shuffle_v8i8_as_i64_48: -; ZVBB-V: # %bb.0: -; ZVBB-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma -; ZVBB-V-NEXT: vror.vi v8, v8, 48 -; ZVBB-V-NEXT: ret -; -; ZVBB-ZVE32X-LABEL: shuffle_v8i8_as_i64_48: -; ZVBB-ZVE32X: # %bb.0: -; ZVBB-ZVE32X-NEXT: vsetivli zero, 8, e8, m2, ta, ma -; ZVBB-ZVE32X-NEXT: vslidedown.vi v10, v8, 6 -; ZVBB-ZVE32X-NEXT: vslideup.vi v10, v8, 2 -; ZVBB-ZVE32X-NEXT: vmv.v.v v8, v10 -; ZVBB-ZVE32X-NEXT: ret +; ZVKB-V-LABEL: shuffle_v8i8_as_i64_48: +; ZVKB-V: # %bb.0: +; ZVKB-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma +; ZVKB-V-NEXT: vror.vi v8, v8, 48 +; ZVKB-V-NEXT: ret +; +; ZVKB-ZVE32X-LABEL: shuffle_v8i8_as_i64_48: +; ZVKB-ZVE32X: # %bb.0: +; ZVKB-ZVE32X-NEXT: vsetivli zero, 8, e8, m2, ta, ma +; ZVKB-ZVE32X-NEXT: vslidedown.vi v10, v8, 6 +; ZVKB-ZVE32X-NEXT: vslideup.vi v10, v8, 2 +; ZVKB-ZVE32X-NEXT: vmv.v.v v8, v10 +; ZVKB-ZVE32X-NEXT: ret %shuffle = shufflevector <8 x i8> %v, <8 x i8> poison, <8 x i32> ret <8 x i8> %shuffle } @@ -435,19 +435,19 @@ define <8 x i8> @shuffle_v8i8_as_i64_56(<8 x i8> %v) { ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret ; -; ZVBB-V-LABEL: shuffle_v8i8_as_i64_56: -; ZVBB-V: # %bb.0: -; ZVBB-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma -; ZVBB-V-NEXT: vror.vi v8, v8, 56 -; ZVBB-V-NEXT: ret -; -; ZVBB-ZVE32X-LABEL: shuffle_v8i8_as_i64_56: -; ZVBB-ZVE32X: # %bb.0: -; ZVBB-ZVE32X-NEXT: vsetivli zero, 8, e8, m2, ta, ma -; ZVBB-ZVE32X-NEXT: vslidedown.vi v10, v8, 7 -; ZVBB-ZVE32X-NEXT: vslideup.vi v10, v8, 1 -; ZVBB-ZVE32X-NEXT: vmv.v.v v8, v10 -; ZVBB-ZVE32X-NEXT: ret +; ZVKB-V-LABEL: shuffle_v8i8_as_i64_56: +; ZVKB-V: # %bb.0: +; ZVKB-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma +; ZVKB-V-NEXT: vror.vi v8, v8, 56 +; ZVKB-V-NEXT: ret +; +; ZVKB-ZVE32X-LABEL: shuffle_v8i8_as_i64_56: +; ZVKB-ZVE32X: # %bb.0: +; ZVKB-ZVE32X-NEXT: vsetivli zero, 8, e8, m2, ta, ma +; ZVKB-ZVE32X-NEXT: vslidedown.vi v10, v8, 7 +; ZVKB-ZVE32X-NEXT: vslideup.vi v10, v8, 1 +; ZVKB-ZVE32X-NEXT: vmv.v.v v8, v10 +; ZVKB-ZVE32X-NEXT: ret %shuffle = shufflevector <8 x i8> %v, <8 x i8> poison, <8 x i32> ret <8 x i8> %shuffle } @@ -461,17 +461,17 @@ define <8 x i16> @shuffle_v8i16_as_i32(<8 x i16> %v) { ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret ; -; ZVBB-V-LABEL: shuffle_v8i16_as_i32: -; ZVBB-V: # %bb.0: -; ZVBB-V-NEXT: vsetivli zero, 4, e32, m1, ta, ma -; ZVBB-V-NEXT: vror.vi v8, v8, 16 -; ZVBB-V-NEXT: ret -; -; ZVBB-ZVE32X-LABEL: shuffle_v8i16_as_i32: -; ZVBB-ZVE32X: # %bb.0: -; ZVBB-ZVE32X-NEXT: vsetivli zero, 4, e32, m4, ta, ma -; ZVBB-ZVE32X-NEXT: vror.vi v8, v8, 16 -; ZVBB-ZVE32X-NEXT: ret +; ZVKB-V-LABEL: shuffle_v8i16_as_i32: +; ZVKB-V: # %bb.0: +; ZVKB-V-NEXT: vsetivli zero, 4, e32, m1, ta, ma +; ZVKB-V-NEXT: vror.vi v8, v8, 16 +; ZVKB-V-NEXT: ret +; +; ZVKB-ZVE32X-LABEL: shuffle_v8i16_as_i32: +; ZVKB-ZVE32X: # %bb.0: +; ZVKB-ZVE32X-NEXT: vsetivli zero, 4, e32, m4, ta, ma +; ZVKB-ZVE32X-NEXT: vror.vi v8, v8, 16 +; ZVKB-ZVE32X-NEXT: ret %shuffle = shufflevector <8 x i16> %v, <8 x i16> poison, <8 x i32> ret <8 x i16> %shuffle } @@ -500,22 +500,22 @@ define <8 x i16> @shuffle_v8i16_as_i64_16(<8 x i16> %v) { ; RV64-NEXT: vor.vv v8, v9, v8 ; RV64-NEXT: ret ; -; ZVBB-V-LABEL: shuffle_v8i16_as_i64_16: -; ZVBB-V: # %bb.0: -; ZVBB-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma -; ZVBB-V-NEXT: vror.vi v8, v8, 16 -; ZVBB-V-NEXT: ret -; -; ZVBB-ZVE32X-LABEL: shuffle_v8i16_as_i64_16: -; ZVBB-ZVE32X: # %bb.0: -; ZVBB-ZVE32X-NEXT: lui a0, %hi(.LCPI19_0) -; ZVBB-ZVE32X-NEXT: addi a0, a0, %lo(.LCPI19_0) -; ZVBB-ZVE32X-NEXT: vsetivli zero, 8, e16, m4, ta, ma -; ZVBB-ZVE32X-NEXT: vle8.v v12, (a0) -; ZVBB-ZVE32X-NEXT: vsext.vf2 v16, v12 -; ZVBB-ZVE32X-NEXT: vrgather.vv v12, v8, v16 -; ZVBB-ZVE32X-NEXT: vmv.v.v v8, v12 -; ZVBB-ZVE32X-NEXT: ret +; ZVKB-V-LABEL: shuffle_v8i16_as_i64_16: +; ZVKB-V: # %bb.0: +; ZVKB-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma +; ZVKB-V-NEXT: vror.vi v8, v8, 16 +; ZVKB-V-NEXT: ret +; +; ZVKB-ZVE32X-LABEL: shuffle_v8i16_as_i64_16: +; ZVKB-ZVE32X: # %bb.0: +; ZVKB-ZVE32X-NEXT: lui a0, %hi(.LCPI19_0) +; ZVKB-ZVE32X-NEXT: addi a0, a0, %lo(.LCPI19_0) +; ZVKB-ZVE32X-NEXT: vsetivli zero, 8, e16, m4, ta, ma +; ZVKB-ZVE32X-NEXT: vle8.v v12, (a0) +; ZVKB-ZVE32X-NEXT: vsext.vf2 v16, v12 +; ZVKB-ZVE32X-NEXT: vrgather.vv v12, v8, v16 +; ZVKB-ZVE32X-NEXT: vmv.v.v v8, v12 +; ZVKB-ZVE32X-NEXT: ret %shuffle = shufflevector <8 x i16> %v, <8 x i16> poison, <8 x i32> ret <8 x i16> %shuffle } @@ -544,22 +544,22 @@ define <8 x i16> @shuffle_v8i16_as_i64_32(<8 x i16> %v) { ; RV64-NEXT: vor.vv v8, v8, v9 ; RV64-NEXT: ret ; -; ZVBB-V-LABEL: shuffle_v8i16_as_i64_32: -; ZVBB-V: # %bb.0: -; ZVBB-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma -; ZVBB-V-NEXT: vror.vi v8, v8, 32 -; ZVBB-V-NEXT: ret -; -; ZVBB-ZVE32X-LABEL: shuffle_v8i16_as_i64_32: -; ZVBB-ZVE32X: # %bb.0: -; ZVBB-ZVE32X-NEXT: lui a0, %hi(.LCPI20_0) -; ZVBB-ZVE32X-NEXT: addi a0, a0, %lo(.LCPI20_0) -; ZVBB-ZVE32X-NEXT: vsetivli zero, 8, e16, m4, ta, ma -; ZVBB-ZVE32X-NEXT: vle8.v v12, (a0) -; ZVBB-ZVE32X-NEXT: vsext.vf2 v16, v12 -; ZVBB-ZVE32X-NEXT: vrgather.vv v12, v8, v16 -; ZVBB-ZVE32X-NEXT: vmv.v.v v8, v12 -; ZVBB-ZVE32X-NEXT: ret +; ZVKB-V-LABEL: shuffle_v8i16_as_i64_32: +; ZVKB-V: # %bb.0: +; ZVKB-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma +; ZVKB-V-NEXT: vror.vi v8, v8, 32 +; ZVKB-V-NEXT: ret +; +; ZVKB-ZVE32X-LABEL: shuffle_v8i16_as_i64_32: +; ZVKB-ZVE32X: # %bb.0: +; ZVKB-ZVE32X-NEXT: lui a0, %hi(.LCPI20_0) +; ZVKB-ZVE32X-NEXT: addi a0, a0, %lo(.LCPI20_0) +; ZVKB-ZVE32X-NEXT: vsetivli zero, 8, e16, m4, ta, ma +; ZVKB-ZVE32X-NEXT: vle8.v v12, (a0) +; ZVKB-ZVE32X-NEXT: vsext.vf2 v16, v12 +; ZVKB-ZVE32X-NEXT: vrgather.vv v12, v8, v16 +; ZVKB-ZVE32X-NEXT: vmv.v.v v8, v12 +; ZVKB-ZVE32X-NEXT: ret %shuffle = shufflevector <8 x i16> %v, <8 x i16> poison, <8 x i32> ret <8 x i16> %shuffle } @@ -588,22 +588,22 @@ define <8 x i16> @shuffle_v8i16_as_i64_48(<8 x i16> %v) { ; RV64-NEXT: vor.vv v8, v8, v9 ; RV64-NEXT: ret ; -; ZVBB-V-LABEL: shuffle_v8i16_as_i64_48: -; ZVBB-V: # %bb.0: -; ZVBB-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma -; ZVBB-V-NEXT: vror.vi v8, v8, 48 -; ZVBB-V-NEXT: ret -; -; ZVBB-ZVE32X-LABEL: shuffle_v8i16_as_i64_48: -; ZVBB-ZVE32X: # %bb.0: -; ZVBB-ZVE32X-NEXT: lui a0, %hi(.LCPI21_0) -; ZVBB-ZVE32X-NEXT: addi a0, a0, %lo(.LCPI21_0) -; ZVBB-ZVE32X-NEXT: vsetivli zero, 8, e16, m4, ta, ma -; ZVBB-ZVE32X-NEXT: vle8.v v12, (a0) -; ZVBB-ZVE32X-NEXT: vsext.vf2 v16, v12 -; ZVBB-ZVE32X-NEXT: vrgather.vv v12, v8, v16 -; ZVBB-ZVE32X-NEXT: vmv.v.v v8, v12 -; ZVBB-ZVE32X-NEXT: ret +; ZVKB-V-LABEL: shuffle_v8i16_as_i64_48: +; ZVKB-V: # %bb.0: +; ZVKB-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma +; ZVKB-V-NEXT: vror.vi v8, v8, 48 +; ZVKB-V-NEXT: ret +; +; ZVKB-ZVE32X-LABEL: shuffle_v8i16_as_i64_48: +; ZVKB-ZVE32X: # %bb.0: +; ZVKB-ZVE32X-NEXT: lui a0, %hi(.LCPI21_0) +; ZVKB-ZVE32X-NEXT: addi a0, a0, %lo(.LCPI21_0) +; ZVKB-ZVE32X-NEXT: vsetivli zero, 8, e16, m4, ta, ma +; ZVKB-ZVE32X-NEXT: vle8.v v12, (a0) +; ZVKB-ZVE32X-NEXT: vsext.vf2 v16, v12 +; ZVKB-ZVE32X-NEXT: vrgather.vv v12, v8, v16 +; ZVKB-ZVE32X-NEXT: vmv.v.v v8, v12 +; ZVKB-ZVE32X-NEXT: ret %shuffle = shufflevector <8 x i16> %v, <8 x i16> poison, <8 x i32> ret <8 x i16> %shuffle } @@ -632,23 +632,23 @@ define <8 x i32> @shuffle_v8i32_as_i64(<8 x i32> %v) { ; RV64-NEXT: vor.vv v8, v8, v10 ; RV64-NEXT: ret ; -; ZVBB-V-LABEL: shuffle_v8i32_as_i64: -; ZVBB-V: # %bb.0: -; ZVBB-V-NEXT: vsetivli zero, 4, e64, m2, ta, ma -; ZVBB-V-NEXT: vror.vi v8, v8, 32 -; ZVBB-V-NEXT: ret -; -; ZVBB-ZVE32X-LABEL: shuffle_v8i32_as_i64: -; ZVBB-ZVE32X: # %bb.0: -; ZVBB-ZVE32X-NEXT: lui a0, %hi(.LCPI22_0) -; ZVBB-ZVE32X-NEXT: addi a0, a0, %lo(.LCPI22_0) -; ZVBB-ZVE32X-NEXT: vsetivli zero, 8, e16, m4, ta, ma -; ZVBB-ZVE32X-NEXT: vle8.v v16, (a0) -; ZVBB-ZVE32X-NEXT: vsext.vf2 v24, v16 -; ZVBB-ZVE32X-NEXT: vsetvli zero, zero, e32, m8, ta, ma -; ZVBB-ZVE32X-NEXT: vrgatherei16.vv v16, v8, v24 -; ZVBB-ZVE32X-NEXT: vmv.v.v v8, v16 -; ZVBB-ZVE32X-NEXT: ret +; ZVKB-V-LABEL: shuffle_v8i32_as_i64: +; ZVKB-V: # %bb.0: +; ZVKB-V-NEXT: vsetivli zero, 4, e64, m2, ta, ma +; ZVKB-V-NEXT: vror.vi v8, v8, 32 +; ZVKB-V-NEXT: ret +; +; ZVKB-ZVE32X-LABEL: shuffle_v8i32_as_i64: +; ZVKB-ZVE32X: # %bb.0: +; ZVKB-ZVE32X-NEXT: lui a0, %hi(.LCPI22_0) +; ZVKB-ZVE32X-NEXT: addi a0, a0, %lo(.LCPI22_0) +; ZVKB-ZVE32X-NEXT: vsetivli zero, 8, e16, m4, ta, ma +; ZVKB-ZVE32X-NEXT: vle8.v v16, (a0) +; ZVKB-ZVE32X-NEXT: vsext.vf2 v24, v16 +; ZVKB-ZVE32X-NEXT: vsetvli zero, zero, e32, m8, ta, ma +; ZVKB-ZVE32X-NEXT: vrgatherei16.vv v16, v8, v24 +; ZVKB-ZVE32X-NEXT: vmv.v.v v8, v16 +; ZVKB-ZVE32X-NEXT: ret %shuffle = shufflevector <8 x i32> %v, <8 x i32> poison, <8 x i32> ret <8 x i32> %shuffle } @@ -662,17 +662,17 @@ define <8 x half> @shuffle_v8f16_as_i32(<8 x half> %v) { ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret ; -; ZVBB-V-LABEL: shuffle_v8f16_as_i32: -; ZVBB-V: # %bb.0: -; ZVBB-V-NEXT: vsetivli zero, 4, e32, m1, ta, ma -; ZVBB-V-NEXT: vror.vi v8, v8, 16 -; ZVBB-V-NEXT: ret -; -; ZVBB-ZVE32X-LABEL: shuffle_v8f16_as_i32: -; ZVBB-ZVE32X: # %bb.0: -; ZVBB-ZVE32X-NEXT: vsetivli zero, 4, e32, m4, ta, ma -; ZVBB-ZVE32X-NEXT: vror.vi v8, v8, 16 -; ZVBB-ZVE32X-NEXT: ret +; ZVKB-V-LABEL: shuffle_v8f16_as_i32: +; ZVKB-V: # %bb.0: +; ZVKB-V-NEXT: vsetivli zero, 4, e32, m1, ta, ma +; ZVKB-V-NEXT: vror.vi v8, v8, 16 +; ZVKB-V-NEXT: ret +; +; ZVKB-ZVE32X-LABEL: shuffle_v8f16_as_i32: +; ZVKB-ZVE32X: # %bb.0: +; ZVKB-ZVE32X-NEXT: vsetivli zero, 4, e32, m4, ta, ma +; ZVKB-ZVE32X-NEXT: vror.vi v8, v8, 16 +; ZVKB-ZVE32X-NEXT: ret %shuffle = shufflevector <8 x half> %v, <8 x half> poison, <8 x i32> ret <8 x half> %shuffle } @@ -701,22 +701,22 @@ define <8 x half> @shuffle_v8f16_as_i64_16(<8 x half> %v) { ; RV64-NEXT: vor.vv v8, v9, v8 ; RV64-NEXT: ret ; -; ZVBB-V-LABEL: shuffle_v8f16_as_i64_16: -; ZVBB-V: # %bb.0: -; ZVBB-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma -; ZVBB-V-NEXT: vror.vi v8, v8, 16 -; ZVBB-V-NEXT: ret -; -; ZVBB-ZVE32X-LABEL: shuffle_v8f16_as_i64_16: -; ZVBB-ZVE32X: # %bb.0: -; ZVBB-ZVE32X-NEXT: lui a0, %hi(.LCPI24_0) -; ZVBB-ZVE32X-NEXT: addi a0, a0, %lo(.LCPI24_0) -; ZVBB-ZVE32X-NEXT: vsetivli zero, 8, e16, m4, ta, ma -; ZVBB-ZVE32X-NEXT: vle8.v v12, (a0) -; ZVBB-ZVE32X-NEXT: vsext.vf2 v16, v12 -; ZVBB-ZVE32X-NEXT: vrgather.vv v12, v8, v16 -; ZVBB-ZVE32X-NEXT: vmv.v.v v8, v12 -; ZVBB-ZVE32X-NEXT: ret +; ZVKB-V-LABEL: shuffle_v8f16_as_i64_16: +; ZVKB-V: # %bb.0: +; ZVKB-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma +; ZVKB-V-NEXT: vror.vi v8, v8, 16 +; ZVKB-V-NEXT: ret +; +; ZVKB-ZVE32X-LABEL: shuffle_v8f16_as_i64_16: +; ZVKB-ZVE32X: # %bb.0: +; ZVKB-ZVE32X-NEXT: lui a0, %hi(.LCPI24_0) +; ZVKB-ZVE32X-NEXT: addi a0, a0, %lo(.LCPI24_0) +; ZVKB-ZVE32X-NEXT: vsetivli zero, 8, e16, m4, ta, ma +; ZVKB-ZVE32X-NEXT: vle8.v v12, (a0) +; ZVKB-ZVE32X-NEXT: vsext.vf2 v16, v12 +; ZVKB-ZVE32X-NEXT: vrgather.vv v12, v8, v16 +; ZVKB-ZVE32X-NEXT: vmv.v.v v8, v12 +; ZVKB-ZVE32X-NEXT: ret %shuffle = shufflevector <8 x half> %v, <8 x half> poison, <8 x i32> ret <8 x half> %shuffle } @@ -745,22 +745,22 @@ define <8 x half> @shuffle_v8f16_as_i64_32(<8 x half> %v) { ; RV64-NEXT: vor.vv v8, v8, v9 ; RV64-NEXT: ret ; -; ZVBB-V-LABEL: shuffle_v8f16_as_i64_32: -; ZVBB-V: # %bb.0: -; ZVBB-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma -; ZVBB-V-NEXT: vror.vi v8, v8, 32 -; ZVBB-V-NEXT: ret -; -; ZVBB-ZVE32X-LABEL: shuffle_v8f16_as_i64_32: -; ZVBB-ZVE32X: # %bb.0: -; ZVBB-ZVE32X-NEXT: lui a0, %hi(.LCPI25_0) -; ZVBB-ZVE32X-NEXT: addi a0, a0, %lo(.LCPI25_0) -; ZVBB-ZVE32X-NEXT: vsetivli zero, 8, e16, m4, ta, ma -; ZVBB-ZVE32X-NEXT: vle8.v v12, (a0) -; ZVBB-ZVE32X-NEXT: vsext.vf2 v16, v12 -; ZVBB-ZVE32X-NEXT: vrgather.vv v12, v8, v16 -; ZVBB-ZVE32X-NEXT: vmv.v.v v8, v12 -; ZVBB-ZVE32X-NEXT: ret +; ZVKB-V-LABEL: shuffle_v8f16_as_i64_32: +; ZVKB-V: # %bb.0: +; ZVKB-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma +; ZVKB-V-NEXT: vror.vi v8, v8, 32 +; ZVKB-V-NEXT: ret +; +; ZVKB-ZVE32X-LABEL: shuffle_v8f16_as_i64_32: +; ZVKB-ZVE32X: # %bb.0: +; ZVKB-ZVE32X-NEXT: lui a0, %hi(.LCPI25_0) +; ZVKB-ZVE32X-NEXT: addi a0, a0, %lo(.LCPI25_0) +; ZVKB-ZVE32X-NEXT: vsetivli zero, 8, e16, m4, ta, ma +; ZVKB-ZVE32X-NEXT: vle8.v v12, (a0) +; ZVKB-ZVE32X-NEXT: vsext.vf2 v16, v12 +; ZVKB-ZVE32X-NEXT: vrgather.vv v12, v8, v16 +; ZVKB-ZVE32X-NEXT: vmv.v.v v8, v12 +; ZVKB-ZVE32X-NEXT: ret %shuffle = shufflevector <8 x half> %v, <8 x half> poison, <8 x i32> ret <8 x half> %shuffle } @@ -789,22 +789,22 @@ define <8 x half> @shuffle_v8f16_as_i64_48(<8 x half> %v) { ; RV64-NEXT: vor.vv v8, v8, v9 ; RV64-NEXT: ret ; -; ZVBB-V-LABEL: shuffle_v8f16_as_i64_48: -; ZVBB-V: # %bb.0: -; ZVBB-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma -; ZVBB-V-NEXT: vror.vi v8, v8, 48 -; ZVBB-V-NEXT: ret -; -; ZVBB-ZVE32X-LABEL: shuffle_v8f16_as_i64_48: -; ZVBB-ZVE32X: # %bb.0: -; ZVBB-ZVE32X-NEXT: lui a0, %hi(.LCPI26_0) -; ZVBB-ZVE32X-NEXT: addi a0, a0, %lo(.LCPI26_0) -; ZVBB-ZVE32X-NEXT: vsetivli zero, 8, e16, m4, ta, ma -; ZVBB-ZVE32X-NEXT: vle8.v v12, (a0) -; ZVBB-ZVE32X-NEXT: vsext.vf2 v16, v12 -; ZVBB-ZVE32X-NEXT: vrgather.vv v12, v8, v16 -; ZVBB-ZVE32X-NEXT: vmv.v.v v8, v12 -; ZVBB-ZVE32X-NEXT: ret +; ZVKB-V-LABEL: shuffle_v8f16_as_i64_48: +; ZVKB-V: # %bb.0: +; ZVKB-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma +; ZVKB-V-NEXT: vror.vi v8, v8, 48 +; ZVKB-V-NEXT: ret +; +; ZVKB-ZVE32X-LABEL: shuffle_v8f16_as_i64_48: +; ZVKB-ZVE32X: # %bb.0: +; ZVKB-ZVE32X-NEXT: lui a0, %hi(.LCPI26_0) +; ZVKB-ZVE32X-NEXT: addi a0, a0, %lo(.LCPI26_0) +; ZVKB-ZVE32X-NEXT: vsetivli zero, 8, e16, m4, ta, ma +; ZVKB-ZVE32X-NEXT: vle8.v v12, (a0) +; ZVKB-ZVE32X-NEXT: vsext.vf2 v16, v12 +; ZVKB-ZVE32X-NEXT: vrgather.vv v12, v8, v16 +; ZVKB-ZVE32X-NEXT: vmv.v.v v8, v12 +; ZVKB-ZVE32X-NEXT: ret %shuffle = shufflevector <8 x half> %v, <8 x half> poison, <8 x i32> ret <8 x half> %shuffle } @@ -833,23 +833,23 @@ define <8 x float> @shuffle_v8f32_as_i64(<8 x float> %v) { ; RV64-NEXT: vor.vv v8, v8, v10 ; RV64-NEXT: ret ; -; ZVBB-V-LABEL: shuffle_v8f32_as_i64: -; ZVBB-V: # %bb.0: -; ZVBB-V-NEXT: vsetivli zero, 4, e64, m2, ta, ma -; ZVBB-V-NEXT: vror.vi v8, v8, 32 -; ZVBB-V-NEXT: ret -; -; ZVBB-ZVE32X-LABEL: shuffle_v8f32_as_i64: -; ZVBB-ZVE32X: # %bb.0: -; ZVBB-ZVE32X-NEXT: lui a0, %hi(.LCPI27_0) -; ZVBB-ZVE32X-NEXT: addi a0, a0, %lo(.LCPI27_0) -; ZVBB-ZVE32X-NEXT: vsetivli zero, 8, e16, m4, ta, ma -; ZVBB-ZVE32X-NEXT: vle8.v v16, (a0) -; ZVBB-ZVE32X-NEXT: vsext.vf2 v24, v16 -; ZVBB-ZVE32X-NEXT: vsetvli zero, zero, e32, m8, ta, ma -; ZVBB-ZVE32X-NEXT: vrgatherei16.vv v16, v8, v24 -; ZVBB-ZVE32X-NEXT: vmv.v.v v8, v16 -; ZVBB-ZVE32X-NEXT: ret +; ZVKB-V-LABEL: shuffle_v8f32_as_i64: +; ZVKB-V: # %bb.0: +; ZVKB-V-NEXT: vsetivli zero, 4, e64, m2, ta, ma +; ZVKB-V-NEXT: vror.vi v8, v8, 32 +; ZVKB-V-NEXT: ret +; +; ZVKB-ZVE32X-LABEL: shuffle_v8f32_as_i64: +; ZVKB-ZVE32X: # %bb.0: +; ZVKB-ZVE32X-NEXT: lui a0, %hi(.LCPI27_0) +; ZVKB-ZVE32X-NEXT: addi a0, a0, %lo(.LCPI27_0) +; ZVKB-ZVE32X-NEXT: vsetivli zero, 8, e16, m4, ta, ma +; ZVKB-ZVE32X-NEXT: vle8.v v16, (a0) +; ZVKB-ZVE32X-NEXT: vsext.vf2 v24, v16 +; ZVKB-ZVE32X-NEXT: vsetvli zero, zero, e32, m8, ta, ma +; ZVKB-ZVE32X-NEXT: vrgatherei16.vv v16, v8, v24 +; ZVKB-ZVE32X-NEXT: vmv.v.v v8, v16 +; ZVKB-ZVE32X-NEXT: ret %shuffle = shufflevector <8 x float> %v, <8 x float> poison, <8 x i32> ret <8 x float> %shuffle } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrol.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrol.ll index 53957586a8c62..99a933985a351 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrol.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrol.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 -; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV32 -; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV64 -; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB -; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB +; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB +; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB declare <1 x i8> @llvm.fshl.v1i8(<1 x i8>, <1 x i8>, <1 x i8>) @@ -18,11 +18,11 @@ define <1 x i8> @vrol_vv_v1i8(<1 x i8> %a, <1 x i8> %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vv_v1i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 1, e8, mf8, ta, ma -; CHECK-ZVBB-NEXT: vrol.vv v8, v8, v9 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vv_v1i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 1, e8, mf8, ta, ma +; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v9 +; CHECK-ZVKB-NEXT: ret %x = call <1 x i8> @llvm.fshl.v1i8(<1 x i8> %a, <1 x i8> %a, <1 x i8> %b) ret <1 x i8> %x } @@ -40,11 +40,11 @@ define <1 x i8> @vrol_vx_v1i8(<1 x i8> %a, i8 %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vx_v1i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 1, e8, mf8, ta, ma -; CHECK-ZVBB-NEXT: vrol.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vx_v1i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 1, e8, mf8, ta, ma +; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement <1 x i8> poison, i8 %b, i32 0 %b.splat = shufflevector <1 x i8> %b.head, <1 x i8> poison, <1 x i32> zeroinitializer %x = call <1 x i8> @llvm.fshl.v1i8(<1 x i8> %a, <1 x i8> %a, <1 x i8> %b.splat) @@ -65,11 +65,11 @@ define <2 x i8> @vrol_vv_v2i8(<2 x i8> %a, <2 x i8> %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vv_v2i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 2, e8, mf8, ta, ma -; CHECK-ZVBB-NEXT: vrol.vv v8, v8, v9 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vv_v2i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 2, e8, mf8, ta, ma +; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v9 +; CHECK-ZVKB-NEXT: ret %x = call <2 x i8> @llvm.fshl.v2i8(<2 x i8> %a, <2 x i8> %a, <2 x i8> %b) ret <2 x i8> %x } @@ -87,11 +87,11 @@ define <2 x i8> @vrol_vx_v2i8(<2 x i8> %a, i8 %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vx_v2i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 2, e8, mf8, ta, ma -; CHECK-ZVBB-NEXT: vrol.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vx_v2i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 2, e8, mf8, ta, ma +; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement <2 x i8> poison, i8 %b, i32 0 %b.splat = shufflevector <2 x i8> %b.head, <2 x i8> poison, <2 x i32> zeroinitializer %x = call <2 x i8> @llvm.fshl.v2i8(<2 x i8> %a, <2 x i8> %a, <2 x i8> %b.splat) @@ -112,11 +112,11 @@ define <4 x i8> @vrol_vv_v4i8(<4 x i8> %a, <4 x i8> %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vv_v4i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 4, e8, mf4, ta, ma -; CHECK-ZVBB-NEXT: vrol.vv v8, v8, v9 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vv_v4i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 4, e8, mf4, ta, ma +; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v9 +; CHECK-ZVKB-NEXT: ret %x = call <4 x i8> @llvm.fshl.v4i8(<4 x i8> %a, <4 x i8> %a, <4 x i8> %b) ret <4 x i8> %x } @@ -134,11 +134,11 @@ define <4 x i8> @vrol_vx_v4i8(<4 x i8> %a, i8 %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vx_v4i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 4, e8, mf4, ta, ma -; CHECK-ZVBB-NEXT: vrol.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vx_v4i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 4, e8, mf4, ta, ma +; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement <4 x i8> poison, i8 %b, i32 0 %b.splat = shufflevector <4 x i8> %b.head, <4 x i8> poison, <4 x i32> zeroinitializer %x = call <4 x i8> @llvm.fshl.v4i8(<4 x i8> %a, <4 x i8> %a, <4 x i8> %b.splat) @@ -159,11 +159,11 @@ define <8 x i8> @vrol_vv_v8i8(<8 x i8> %a, <8 x i8> %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vv_v8i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 8, e8, mf2, ta, ma -; CHECK-ZVBB-NEXT: vrol.vv v8, v8, v9 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vv_v8i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 8, e8, mf2, ta, ma +; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v9 +; CHECK-ZVKB-NEXT: ret %x = call <8 x i8> @llvm.fshl.v8i8(<8 x i8> %a, <8 x i8> %a, <8 x i8> %b) ret <8 x i8> %x } @@ -181,11 +181,11 @@ define <8 x i8> @vrol_vx_v8i8(<8 x i8> %a, i8 %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vx_v8i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 8, e8, mf2, ta, ma -; CHECK-ZVBB-NEXT: vrol.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vx_v8i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 8, e8, mf2, ta, ma +; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement <8 x i8> poison, i8 %b, i32 0 %b.splat = shufflevector <8 x i8> %b.head, <8 x i8> poison, <8 x i32> zeroinitializer %x = call <8 x i8> @llvm.fshl.v8i8(<8 x i8> %a, <8 x i8> %a, <8 x i8> %b.splat) @@ -206,11 +206,11 @@ define <16 x i8> @vrol_vv_v16i8(<16 x i8> %a, <16 x i8> %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vv_v16i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 16, e8, m1, ta, ma -; CHECK-ZVBB-NEXT: vrol.vv v8, v8, v9 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vv_v16i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 16, e8, m1, ta, ma +; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v9 +; CHECK-ZVKB-NEXT: ret %x = call <16 x i8> @llvm.fshl.v16i8(<16 x i8> %a, <16 x i8> %a, <16 x i8> %b) ret <16 x i8> %x } @@ -228,11 +228,11 @@ define <16 x i8> @vrol_vx_v16i8(<16 x i8> %a, i8 %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vx_v16i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 16, e8, m1, ta, ma -; CHECK-ZVBB-NEXT: vrol.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vx_v16i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 16, e8, m1, ta, ma +; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement <16 x i8> poison, i8 %b, i32 0 %b.splat = shufflevector <16 x i8> %b.head, <16 x i8> poison, <16 x i32> zeroinitializer %x = call <16 x i8> @llvm.fshl.v16i8(<16 x i8> %a, <16 x i8> %a, <16 x i8> %b.splat) @@ -254,12 +254,12 @@ define <32 x i8> @vrol_vv_v32i8(<32 x i8> %a, <32 x i8> %b) { ; CHECK-NEXT: vor.vv v8, v12, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vv_v32i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: li a0, 32 -; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m2, ta, ma -; CHECK-ZVBB-NEXT: vrol.vv v8, v8, v10 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vv_v32i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: li a0, 32 +; CHECK-ZVKB-NEXT: vsetvli zero, a0, e8, m2, ta, ma +; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v10 +; CHECK-ZVKB-NEXT: ret %x = call <32 x i8> @llvm.fshl.v32i8(<32 x i8> %a, <32 x i8> %a, <32 x i8> %b) ret <32 x i8> %x } @@ -278,12 +278,12 @@ define <32 x i8> @vrol_vx_v32i8(<32 x i8> %a, i8 %b) { ; CHECK-NEXT: vor.vv v8, v12, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vx_v32i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: li a1, 32 -; CHECK-ZVBB-NEXT: vsetvli zero, a1, e8, m2, ta, ma -; CHECK-ZVBB-NEXT: vrol.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vx_v32i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: li a1, 32 +; CHECK-ZVKB-NEXT: vsetvli zero, a1, e8, m2, ta, ma +; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement <32 x i8> poison, i8 %b, i32 0 %b.splat = shufflevector <32 x i8> %b.head, <32 x i8> poison, <32 x i32> zeroinitializer %x = call <32 x i8> @llvm.fshl.v32i8(<32 x i8> %a, <32 x i8> %a, <32 x i8> %b.splat) @@ -305,12 +305,12 @@ define <64 x i8> @vrol_vv_v64i8(<64 x i8> %a, <64 x i8> %b) { ; CHECK-NEXT: vor.vv v8, v16, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vv_v64i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: li a0, 64 -; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m4, ta, ma -; CHECK-ZVBB-NEXT: vrol.vv v8, v8, v12 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vv_v64i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: li a0, 64 +; CHECK-ZVKB-NEXT: vsetvli zero, a0, e8, m4, ta, ma +; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v12 +; CHECK-ZVKB-NEXT: ret %x = call <64 x i8> @llvm.fshl.v64i8(<64 x i8> %a, <64 x i8> %a, <64 x i8> %b) ret <64 x i8> %x } @@ -329,12 +329,12 @@ define <64 x i8> @vrol_vx_v64i8(<64 x i8> %a, i8 %b) { ; CHECK-NEXT: vor.vv v8, v16, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vx_v64i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: li a1, 64 -; CHECK-ZVBB-NEXT: vsetvli zero, a1, e8, m4, ta, ma -; CHECK-ZVBB-NEXT: vrol.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vx_v64i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: li a1, 64 +; CHECK-ZVKB-NEXT: vsetvli zero, a1, e8, m4, ta, ma +; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement <64 x i8> poison, i8 %b, i32 0 %b.splat = shufflevector <64 x i8> %b.head, <64 x i8> poison, <64 x i32> zeroinitializer %x = call <64 x i8> @llvm.fshl.v64i8(<64 x i8> %a, <64 x i8> %a, <64 x i8> %b.splat) @@ -355,11 +355,11 @@ define <1 x i16> @vrol_vv_v1i16(<1 x i16> %a, <1 x i16> %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vv_v1i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 1, e16, mf4, ta, ma -; CHECK-ZVBB-NEXT: vrol.vv v8, v8, v9 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vv_v1i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 1, e16, mf4, ta, ma +; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v9 +; CHECK-ZVKB-NEXT: ret %x = call <1 x i16> @llvm.fshl.v1i16(<1 x i16> %a, <1 x i16> %a, <1 x i16> %b) ret <1 x i16> %x } @@ -377,11 +377,11 @@ define <1 x i16> @vrol_vx_v1i16(<1 x i16> %a, i16 %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vx_v1i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 1, e16, mf4, ta, ma -; CHECK-ZVBB-NEXT: vrol.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vx_v1i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 1, e16, mf4, ta, ma +; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement <1 x i16> poison, i16 %b, i32 0 %b.splat = shufflevector <1 x i16> %b.head, <1 x i16> poison, <1 x i32> zeroinitializer %x = call <1 x i16> @llvm.fshl.v1i16(<1 x i16> %a, <1 x i16> %a, <1 x i16> %b.splat) @@ -402,11 +402,11 @@ define <2 x i16> @vrol_vv_v2i16(<2 x i16> %a, <2 x i16> %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vv_v2i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 2, e16, mf4, ta, ma -; CHECK-ZVBB-NEXT: vrol.vv v8, v8, v9 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vv_v2i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 2, e16, mf4, ta, ma +; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v9 +; CHECK-ZVKB-NEXT: ret %x = call <2 x i16> @llvm.fshl.v2i16(<2 x i16> %a, <2 x i16> %a, <2 x i16> %b) ret <2 x i16> %x } @@ -424,11 +424,11 @@ define <2 x i16> @vrol_vx_v2i16(<2 x i16> %a, i16 %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vx_v2i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 2, e16, mf4, ta, ma -; CHECK-ZVBB-NEXT: vrol.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vx_v2i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 2, e16, mf4, ta, ma +; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement <2 x i16> poison, i16 %b, i32 0 %b.splat = shufflevector <2 x i16> %b.head, <2 x i16> poison, <2 x i32> zeroinitializer %x = call <2 x i16> @llvm.fshl.v2i16(<2 x i16> %a, <2 x i16> %a, <2 x i16> %b.splat) @@ -449,11 +449,11 @@ define <4 x i16> @vrol_vv_v4i16(<4 x i16> %a, <4 x i16> %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vv_v4i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma -; CHECK-ZVBB-NEXT: vrol.vv v8, v8, v9 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vv_v4i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma +; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v9 +; CHECK-ZVKB-NEXT: ret %x = call <4 x i16> @llvm.fshl.v4i16(<4 x i16> %a, <4 x i16> %a, <4 x i16> %b) ret <4 x i16> %x } @@ -471,11 +471,11 @@ define <4 x i16> @vrol_vx_v4i16(<4 x i16> %a, i16 %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vx_v4i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma -; CHECK-ZVBB-NEXT: vrol.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vx_v4i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma +; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement <4 x i16> poison, i16 %b, i32 0 %b.splat = shufflevector <4 x i16> %b.head, <4 x i16> poison, <4 x i32> zeroinitializer %x = call <4 x i16> @llvm.fshl.v4i16(<4 x i16> %a, <4 x i16> %a, <4 x i16> %b.splat) @@ -496,11 +496,11 @@ define <8 x i16> @vrol_vv_v8i16(<8 x i16> %a, <8 x i16> %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vv_v8i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma -; CHECK-ZVBB-NEXT: vrol.vv v8, v8, v9 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vv_v8i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 8, e16, m1, ta, ma +; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v9 +; CHECK-ZVKB-NEXT: ret %x = call <8 x i16> @llvm.fshl.v8i16(<8 x i16> %a, <8 x i16> %a, <8 x i16> %b) ret <8 x i16> %x } @@ -518,11 +518,11 @@ define <8 x i16> @vrol_vx_v8i16(<8 x i16> %a, i16 %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vx_v8i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma -; CHECK-ZVBB-NEXT: vrol.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vx_v8i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 8, e16, m1, ta, ma +; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement <8 x i16> poison, i16 %b, i32 0 %b.splat = shufflevector <8 x i16> %b.head, <8 x i16> poison, <8 x i32> zeroinitializer %x = call <8 x i16> @llvm.fshl.v8i16(<8 x i16> %a, <8 x i16> %a, <8 x i16> %b.splat) @@ -543,11 +543,11 @@ define <16 x i16> @vrol_vv_v16i16(<16 x i16> %a, <16 x i16> %b) { ; CHECK-NEXT: vor.vv v8, v12, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vv_v16i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 16, e16, m2, ta, ma -; CHECK-ZVBB-NEXT: vrol.vv v8, v8, v10 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vv_v16i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 16, e16, m2, ta, ma +; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v10 +; CHECK-ZVKB-NEXT: ret %x = call <16 x i16> @llvm.fshl.v16i16(<16 x i16> %a, <16 x i16> %a, <16 x i16> %b) ret <16 x i16> %x } @@ -565,11 +565,11 @@ define <16 x i16> @vrol_vx_v16i16(<16 x i16> %a, i16 %b) { ; CHECK-NEXT: vor.vv v8, v12, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vx_v16i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 16, e16, m2, ta, ma -; CHECK-ZVBB-NEXT: vrol.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vx_v16i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 16, e16, m2, ta, ma +; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement <16 x i16> poison, i16 %b, i32 0 %b.splat = shufflevector <16 x i16> %b.head, <16 x i16> poison, <16 x i32> zeroinitializer %x = call <16 x i16> @llvm.fshl.v16i16(<16 x i16> %a, <16 x i16> %a, <16 x i16> %b.splat) @@ -591,12 +591,12 @@ define <32 x i16> @vrol_vv_v32i16(<32 x i16> %a, <32 x i16> %b) { ; CHECK-NEXT: vor.vv v8, v16, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vv_v32i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: li a0, 32 -; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-ZVBB-NEXT: vrol.vv v8, v8, v12 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vv_v32i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: li a0, 32 +; CHECK-ZVKB-NEXT: vsetvli zero, a0, e16, m4, ta, ma +; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v12 +; CHECK-ZVKB-NEXT: ret %x = call <32 x i16> @llvm.fshl.v32i16(<32 x i16> %a, <32 x i16> %a, <32 x i16> %b) ret <32 x i16> %x } @@ -615,12 +615,12 @@ define <32 x i16> @vrol_vx_v32i16(<32 x i16> %a, i16 %b) { ; CHECK-NEXT: vor.vv v8, v16, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vx_v32i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: li a1, 32 -; CHECK-ZVBB-NEXT: vsetvli zero, a1, e16, m4, ta, ma -; CHECK-ZVBB-NEXT: vrol.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vx_v32i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: li a1, 32 +; CHECK-ZVKB-NEXT: vsetvli zero, a1, e16, m4, ta, ma +; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement <32 x i16> poison, i16 %b, i32 0 %b.splat = shufflevector <32 x i16> %b.head, <32 x i16> poison, <32 x i32> zeroinitializer %x = call <32 x i16> @llvm.fshl.v32i16(<32 x i16> %a, <32 x i16> %a, <32 x i16> %b.splat) @@ -642,11 +642,11 @@ define <1 x i32> @vrol_vv_v1i32(<1 x i32> %a, <1 x i32> %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vv_v1i32: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 1, e32, mf2, ta, ma -; CHECK-ZVBB-NEXT: vrol.vv v8, v8, v9 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vv_v1i32: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 1, e32, mf2, ta, ma +; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v9 +; CHECK-ZVKB-NEXT: ret %x = call <1 x i32> @llvm.fshl.v1i32(<1 x i32> %a, <1 x i32> %a, <1 x i32> %b) ret <1 x i32> %x } @@ -665,11 +665,11 @@ define <1 x i32> @vrol_vx_v1i32(<1 x i32> %a, i32 %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vx_v1i32: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 1, e32, mf2, ta, ma -; CHECK-ZVBB-NEXT: vrol.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vx_v1i32: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 1, e32, mf2, ta, ma +; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement <1 x i32> poison, i32 %b, i32 0 %b.splat = shufflevector <1 x i32> %b.head, <1 x i32> poison, <1 x i32> zeroinitializer %x = call <1 x i32> @llvm.fshl.v1i32(<1 x i32> %a, <1 x i32> %a, <1 x i32> %b.splat) @@ -691,11 +691,11 @@ define <2 x i32> @vrol_vv_v2i32(<2 x i32> %a, <2 x i32> %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vv_v2i32: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma -; CHECK-ZVBB-NEXT: vrol.vv v8, v8, v9 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vv_v2i32: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma +; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v9 +; CHECK-ZVKB-NEXT: ret %x = call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %a, <2 x i32> %a, <2 x i32> %b) ret <2 x i32> %x } @@ -714,11 +714,11 @@ define <2 x i32> @vrol_vx_v2i32(<2 x i32> %a, i32 %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vx_v2i32: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma -; CHECK-ZVBB-NEXT: vrol.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vx_v2i32: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma +; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement <2 x i32> poison, i32 %b, i32 0 %b.splat = shufflevector <2 x i32> %b.head, <2 x i32> poison, <2 x i32> zeroinitializer %x = call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %a, <2 x i32> %a, <2 x i32> %b.splat) @@ -740,11 +740,11 @@ define <4 x i32> @vrol_vv_v4i32(<4 x i32> %a, <4 x i32> %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vv_v4i32: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma -; CHECK-ZVBB-NEXT: vrol.vv v8, v8, v9 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vv_v4i32: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 4, e32, m1, ta, ma +; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v9 +; CHECK-ZVKB-NEXT: ret %x = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %a, <4 x i32> %a, <4 x i32> %b) ret <4 x i32> %x } @@ -763,11 +763,11 @@ define <4 x i32> @vrol_vx_v4i32(<4 x i32> %a, i32 %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vx_v4i32: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma -; CHECK-ZVBB-NEXT: vrol.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vx_v4i32: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 4, e32, m1, ta, ma +; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement <4 x i32> poison, i32 %b, i32 0 %b.splat = shufflevector <4 x i32> %b.head, <4 x i32> poison, <4 x i32> zeroinitializer %x = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %a, <4 x i32> %a, <4 x i32> %b.splat) @@ -789,11 +789,11 @@ define <8 x i32> @vrol_vv_v8i32(<8 x i32> %a, <8 x i32> %b) { ; CHECK-NEXT: vor.vv v8, v12, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vv_v8i32: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 8, e32, m2, ta, ma -; CHECK-ZVBB-NEXT: vrol.vv v8, v8, v10 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vv_v8i32: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 8, e32, m2, ta, ma +; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v10 +; CHECK-ZVKB-NEXT: ret %x = call <8 x i32> @llvm.fshl.v8i32(<8 x i32> %a, <8 x i32> %a, <8 x i32> %b) ret <8 x i32> %x } @@ -812,11 +812,11 @@ define <8 x i32> @vrol_vx_v8i32(<8 x i32> %a, i32 %b) { ; CHECK-NEXT: vor.vv v8, v12, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vx_v8i32: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 8, e32, m2, ta, ma -; CHECK-ZVBB-NEXT: vrol.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vx_v8i32: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 8, e32, m2, ta, ma +; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement <8 x i32> poison, i32 %b, i32 0 %b.splat = shufflevector <8 x i32> %b.head, <8 x i32> poison, <8 x i32> zeroinitializer %x = call <8 x i32> @llvm.fshl.v8i32(<8 x i32> %a, <8 x i32> %a, <8 x i32> %b.splat) @@ -838,11 +838,11 @@ define <16 x i32> @vrol_vv_v16i32(<16 x i32> %a, <16 x i32> %b) { ; CHECK-NEXT: vor.vv v8, v16, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vv_v16i32: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 16, e32, m4, ta, ma -; CHECK-ZVBB-NEXT: vrol.vv v8, v8, v12 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vv_v16i32: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 16, e32, m4, ta, ma +; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v12 +; CHECK-ZVKB-NEXT: ret %x = call <16 x i32> @llvm.fshl.v16i32(<16 x i32> %a, <16 x i32> %a, <16 x i32> %b) ret <16 x i32> %x } @@ -861,11 +861,11 @@ define <16 x i32> @vrol_vx_v16i32(<16 x i32> %a, i32 %b) { ; CHECK-NEXT: vor.vv v8, v16, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vx_v16i32: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 16, e32, m4, ta, ma -; CHECK-ZVBB-NEXT: vrol.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vx_v16i32: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 16, e32, m4, ta, ma +; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement <16 x i32> poison, i32 %b, i32 0 %b.splat = shufflevector <16 x i32> %b.head, <16 x i32> poison, <16 x i32> zeroinitializer %x = call <16 x i32> @llvm.fshl.v16i32(<16 x i32> %a, <16 x i32> %a, <16 x i32> %b.splat) @@ -887,11 +887,11 @@ define <1 x i64> @vrol_vv_v1i64(<1 x i64> %a, <1 x i64> %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vv_v1i64: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 1, e64, m1, ta, ma -; CHECK-ZVBB-NEXT: vrol.vv v8, v8, v9 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vv_v1i64: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 1, e64, m1, ta, ma +; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v9 +; CHECK-ZVKB-NEXT: ret %x = call <1 x i64> @llvm.fshl.v1i64(<1 x i64> %a, <1 x i64> %a, <1 x i64> %b) ret <1 x i64> %x } @@ -910,11 +910,11 @@ define <1 x i64> @vrol_vx_v1i64(<1 x i64> %a, i64 %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vx_v1i64: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 1, e64, m1, ta, ma -; CHECK-ZVBB-NEXT: vrol.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vx_v1i64: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 1, e64, m1, ta, ma +; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement <1 x i64> poison, i64 %b, i32 0 %b.splat = shufflevector <1 x i64> %b.head, <1 x i64> poison, <1 x i32> zeroinitializer %x = call <1 x i64> @llvm.fshl.v1i64(<1 x i64> %a, <1 x i64> %a, <1 x i64> %b.splat) @@ -936,11 +936,11 @@ define <2 x i64> @vrol_vv_v2i64(<2 x i64> %a, <2 x i64> %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vv_v2i64: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 2, e64, m1, ta, ma -; CHECK-ZVBB-NEXT: vrol.vv v8, v8, v9 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vv_v2i64: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 2, e64, m1, ta, ma +; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v9 +; CHECK-ZVKB-NEXT: ret %x = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> %a, <2 x i64> %a, <2 x i64> %b) ret <2 x i64> %x } @@ -959,11 +959,11 @@ define <2 x i64> @vrol_vx_v2i64(<2 x i64> %a, i64 %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vx_v2i64: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 2, e64, m1, ta, ma -; CHECK-ZVBB-NEXT: vrol.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vx_v2i64: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 2, e64, m1, ta, ma +; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement <2 x i64> poison, i64 %b, i32 0 %b.splat = shufflevector <2 x i64> %b.head, <2 x i64> poison, <2 x i32> zeroinitializer %x = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> %a, <2 x i64> %a, <2 x i64> %b.splat) @@ -985,11 +985,11 @@ define <4 x i64> @vrol_vv_v4i64(<4 x i64> %a, <4 x i64> %b) { ; CHECK-NEXT: vor.vv v8, v12, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vv_v4i64: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 4, e64, m2, ta, ma -; CHECK-ZVBB-NEXT: vrol.vv v8, v8, v10 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vv_v4i64: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 4, e64, m2, ta, ma +; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v10 +; CHECK-ZVKB-NEXT: ret %x = call <4 x i64> @llvm.fshl.v4i64(<4 x i64> %a, <4 x i64> %a, <4 x i64> %b) ret <4 x i64> %x } @@ -1008,11 +1008,11 @@ define <4 x i64> @vrol_vx_v4i64(<4 x i64> %a, i64 %b) { ; CHECK-NEXT: vor.vv v8, v12, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vx_v4i64: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 4, e64, m2, ta, ma -; CHECK-ZVBB-NEXT: vrol.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vx_v4i64: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 4, e64, m2, ta, ma +; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement <4 x i64> poison, i64 %b, i32 0 %b.splat = shufflevector <4 x i64> %b.head, <4 x i64> poison, <4 x i32> zeroinitializer %x = call <4 x i64> @llvm.fshl.v4i64(<4 x i64> %a, <4 x i64> %a, <4 x i64> %b.splat) @@ -1034,11 +1034,11 @@ define <8 x i64> @vrol_vv_v8i64(<8 x i64> %a, <8 x i64> %b) { ; CHECK-NEXT: vor.vv v8, v16, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vv_v8i64: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 8, e64, m4, ta, ma -; CHECK-ZVBB-NEXT: vrol.vv v8, v8, v12 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vv_v8i64: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 8, e64, m4, ta, ma +; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v12 +; CHECK-ZVKB-NEXT: ret %x = call <8 x i64> @llvm.fshl.v8i64(<8 x i64> %a, <8 x i64> %a, <8 x i64> %b) ret <8 x i64> %x } @@ -1057,16 +1057,13 @@ define <8 x i64> @vrol_vx_v8i64(<8 x i64> %a, i64 %b) { ; CHECK-NEXT: vor.vv v8, v16, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vx_v8i64: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 8, e64, m4, ta, ma -; CHECK-ZVBB-NEXT: vrol.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vx_v8i64: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 8, e64, m4, ta, ma +; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement <8 x i64> poison, i64 %b, i32 0 %b.splat = shufflevector <8 x i64> %b.head, <8 x i64> poison, <8 x i32> zeroinitializer %x = call <8 x i64> @llvm.fshl.v8i64(<8 x i64> %a, <8 x i64> %a, <8 x i64> %b.splat) ret <8 x i64> %x } -;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: -; CHECK-RV32: {{.*}} -; CHECK-RV64: {{.*}} diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vror.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vror.ll index 8de463af78d6f..aa63013eec120 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vror.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vror.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 ; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV32 ; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV64 -; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB -; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB +; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB +; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB declare <1 x i8> @llvm.fshr.v1i8(<1 x i8>, <1 x i8>, <1 x i8>) declare <1 x i8> @llvm.fshl.v1i8(<1 x i8>, <1 x i8>, <1 x i8>) @@ -19,11 +19,11 @@ define <1 x i8> @vror_vv_v1i8(<1 x i8> %a, <1 x i8> %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vv_v1i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 1, e8, mf8, ta, ma -; CHECK-ZVBB-NEXT: vror.vv v8, v8, v9 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vv_v1i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 1, e8, mf8, ta, ma +; CHECK-ZVKB-NEXT: vror.vv v8, v8, v9 +; CHECK-ZVKB-NEXT: ret %x = call <1 x i8> @llvm.fshr.v1i8(<1 x i8> %a, <1 x i8> %a, <1 x i8> %b) ret <1 x i8> %x } @@ -41,11 +41,11 @@ define <1 x i8> @vror_vx_v1i8(<1 x i8> %a, i8 %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vx_v1i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 1, e8, mf8, ta, ma -; CHECK-ZVBB-NEXT: vror.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vx_v1i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 1, e8, mf8, ta, ma +; CHECK-ZVKB-NEXT: vror.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement <1 x i8> poison, i8 %b, i32 0 %b.splat = shufflevector <1 x i8> %b.head, <1 x i8> poison, <1 x i32> zeroinitializer %x = call <1 x i8> @llvm.fshr.v1i8(<1 x i8> %a, <1 x i8> %a, <1 x i8> %b.splat) @@ -61,11 +61,11 @@ define <1 x i8> @vror_vi_v1i8(<1 x i8> %a) { ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_v1i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 1, e8, mf8, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 1 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_v1i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 1, e8, mf8, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1 +; CHECK-ZVKB-NEXT: ret %x = call <1 x i8> @llvm.fshr.v1i8(<1 x i8> %a, <1 x i8> %a, <1 x i8> shufflevector(<1 x i8> insertelement(<1 x i8> poison, i8 1, i32 0), <1 x i8> poison, <1 x i32> zeroinitializer)) ret <1 x i8> %x } @@ -79,11 +79,11 @@ define <1 x i8> @vror_vi_rotl_v1i8(<1 x i8> %a) { ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_rotl_v1i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 1, e8, mf8, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 7 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_rotl_v1i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 1, e8, mf8, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 7 +; CHECK-ZVKB-NEXT: ret %x = call <1 x i8> @llvm.fshl.v1i8(<1 x i8> %a, <1 x i8> %a, <1 x i8> shufflevector(<1 x i8> insertelement(<1 x i8> poison, i8 1, i32 0), <1 x i8> poison, <1 x i32> zeroinitializer)) ret <1 x i8> %x } @@ -103,11 +103,11 @@ define <2 x i8> @vror_vv_v2i8(<2 x i8> %a, <2 x i8> %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vv_v2i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 2, e8, mf8, ta, ma -; CHECK-ZVBB-NEXT: vror.vv v8, v8, v9 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vv_v2i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 2, e8, mf8, ta, ma +; CHECK-ZVKB-NEXT: vror.vv v8, v8, v9 +; CHECK-ZVKB-NEXT: ret %x = call <2 x i8> @llvm.fshr.v2i8(<2 x i8> %a, <2 x i8> %a, <2 x i8> %b) ret <2 x i8> %x } @@ -125,11 +125,11 @@ define <2 x i8> @vror_vx_v2i8(<2 x i8> %a, i8 %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vx_v2i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 2, e8, mf8, ta, ma -; CHECK-ZVBB-NEXT: vror.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vx_v2i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 2, e8, mf8, ta, ma +; CHECK-ZVKB-NEXT: vror.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement <2 x i8> poison, i8 %b, i32 0 %b.splat = shufflevector <2 x i8> %b.head, <2 x i8> poison, <2 x i32> zeroinitializer %x = call <2 x i8> @llvm.fshr.v2i8(<2 x i8> %a, <2 x i8> %a, <2 x i8> %b.splat) @@ -145,11 +145,11 @@ define <2 x i8> @vror_vi_v2i8(<2 x i8> %a) { ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_v2i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 2, e8, mf8, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 1 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_v2i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 2, e8, mf8, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1 +; CHECK-ZVKB-NEXT: ret %x = call <2 x i8> @llvm.fshr.v2i8(<2 x i8> %a, <2 x i8> %a, <2 x i8> shufflevector(<2 x i8> insertelement(<2 x i8> poison, i8 1, i32 0), <2 x i8> poison, <2 x i32> zeroinitializer)) ret <2 x i8> %x } @@ -163,11 +163,11 @@ define <2 x i8> @vror_vi_rotl_v2i8(<2 x i8> %a) { ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_rotl_v2i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 2, e8, mf8, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 7 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_rotl_v2i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 2, e8, mf8, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 7 +; CHECK-ZVKB-NEXT: ret %x = call <2 x i8> @llvm.fshl.v2i8(<2 x i8> %a, <2 x i8> %a, <2 x i8> shufflevector(<2 x i8> insertelement(<2 x i8> poison, i8 1, i32 0), <2 x i8> poison, <2 x i32> zeroinitializer)) ret <2 x i8> %x } @@ -187,11 +187,11 @@ define <4 x i8> @vror_vv_v4i8(<4 x i8> %a, <4 x i8> %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vv_v4i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 4, e8, mf4, ta, ma -; CHECK-ZVBB-NEXT: vror.vv v8, v8, v9 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vv_v4i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 4, e8, mf4, ta, ma +; CHECK-ZVKB-NEXT: vror.vv v8, v8, v9 +; CHECK-ZVKB-NEXT: ret %x = call <4 x i8> @llvm.fshr.v4i8(<4 x i8> %a, <4 x i8> %a, <4 x i8> %b) ret <4 x i8> %x } @@ -209,11 +209,11 @@ define <4 x i8> @vror_vx_v4i8(<4 x i8> %a, i8 %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vx_v4i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 4, e8, mf4, ta, ma -; CHECK-ZVBB-NEXT: vror.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vx_v4i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 4, e8, mf4, ta, ma +; CHECK-ZVKB-NEXT: vror.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement <4 x i8> poison, i8 %b, i32 0 %b.splat = shufflevector <4 x i8> %b.head, <4 x i8> poison, <4 x i32> zeroinitializer %x = call <4 x i8> @llvm.fshr.v4i8(<4 x i8> %a, <4 x i8> %a, <4 x i8> %b.splat) @@ -229,11 +229,11 @@ define <4 x i8> @vror_vi_v4i8(<4 x i8> %a) { ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_v4i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 4, e8, mf4, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 1 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_v4i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 4, e8, mf4, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1 +; CHECK-ZVKB-NEXT: ret %x = call <4 x i8> @llvm.fshr.v4i8(<4 x i8> %a, <4 x i8> %a, <4 x i8> shufflevector(<4 x i8> insertelement(<4 x i8> poison, i8 1, i32 0), <4 x i8> poison, <4 x i32> zeroinitializer)) ret <4 x i8> %x } @@ -247,11 +247,11 @@ define <4 x i8> @vror_vi_rotl_v4i8(<4 x i8> %a) { ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_rotl_v4i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 4, e8, mf4, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 7 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_rotl_v4i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 4, e8, mf4, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 7 +; CHECK-ZVKB-NEXT: ret %x = call <4 x i8> @llvm.fshl.v4i8(<4 x i8> %a, <4 x i8> %a, <4 x i8> shufflevector(<4 x i8> insertelement(<4 x i8> poison, i8 1, i32 0), <4 x i8> poison, <4 x i32> zeroinitializer)) ret <4 x i8> %x } @@ -271,11 +271,11 @@ define <8 x i8> @vror_vv_v8i8(<8 x i8> %a, <8 x i8> %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vv_v8i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 8, e8, mf2, ta, ma -; CHECK-ZVBB-NEXT: vror.vv v8, v8, v9 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vv_v8i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 8, e8, mf2, ta, ma +; CHECK-ZVKB-NEXT: vror.vv v8, v8, v9 +; CHECK-ZVKB-NEXT: ret %x = call <8 x i8> @llvm.fshr.v8i8(<8 x i8> %a, <8 x i8> %a, <8 x i8> %b) ret <8 x i8> %x } @@ -293,11 +293,11 @@ define <8 x i8> @vror_vx_v8i8(<8 x i8> %a, i8 %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vx_v8i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 8, e8, mf2, ta, ma -; CHECK-ZVBB-NEXT: vror.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vx_v8i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 8, e8, mf2, ta, ma +; CHECK-ZVKB-NEXT: vror.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement <8 x i8> poison, i8 %b, i32 0 %b.splat = shufflevector <8 x i8> %b.head, <8 x i8> poison, <8 x i32> zeroinitializer %x = call <8 x i8> @llvm.fshr.v8i8(<8 x i8> %a, <8 x i8> %a, <8 x i8> %b.splat) @@ -313,11 +313,11 @@ define <8 x i8> @vror_vi_v8i8(<8 x i8> %a) { ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_v8i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 8, e8, mf2, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 1 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_v8i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 8, e8, mf2, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1 +; CHECK-ZVKB-NEXT: ret %x = call <8 x i8> @llvm.fshr.v8i8(<8 x i8> %a, <8 x i8> %a, <8 x i8> shufflevector(<8 x i8> insertelement(<8 x i8> poison, i8 1, i32 0), <8 x i8> poison, <8 x i32> zeroinitializer)) ret <8 x i8> %x } @@ -331,11 +331,11 @@ define <8 x i8> @vror_vi_rotl_v8i8(<8 x i8> %a) { ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_rotl_v8i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 8, e8, mf2, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 7 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_rotl_v8i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 8, e8, mf2, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 7 +; CHECK-ZVKB-NEXT: ret %x = call <8 x i8> @llvm.fshl.v8i8(<8 x i8> %a, <8 x i8> %a, <8 x i8> shufflevector(<8 x i8> insertelement(<8 x i8> poison, i8 1, i32 0), <8 x i8> poison, <8 x i32> zeroinitializer)) ret <8 x i8> %x } @@ -355,11 +355,11 @@ define <16 x i8> @vror_vv_v16i8(<16 x i8> %a, <16 x i8> %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vv_v16i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 16, e8, m1, ta, ma -; CHECK-ZVBB-NEXT: vror.vv v8, v8, v9 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vv_v16i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 16, e8, m1, ta, ma +; CHECK-ZVKB-NEXT: vror.vv v8, v8, v9 +; CHECK-ZVKB-NEXT: ret %x = call <16 x i8> @llvm.fshr.v16i8(<16 x i8> %a, <16 x i8> %a, <16 x i8> %b) ret <16 x i8> %x } @@ -377,11 +377,11 @@ define <16 x i8> @vror_vx_v16i8(<16 x i8> %a, i8 %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vx_v16i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 16, e8, m1, ta, ma -; CHECK-ZVBB-NEXT: vror.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vx_v16i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 16, e8, m1, ta, ma +; CHECK-ZVKB-NEXT: vror.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement <16 x i8> poison, i8 %b, i32 0 %b.splat = shufflevector <16 x i8> %b.head, <16 x i8> poison, <16 x i32> zeroinitializer %x = call <16 x i8> @llvm.fshr.v16i8(<16 x i8> %a, <16 x i8> %a, <16 x i8> %b.splat) @@ -397,11 +397,11 @@ define <16 x i8> @vror_vi_v16i8(<16 x i8> %a) { ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_v16i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 16, e8, m1, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 1 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_v16i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 16, e8, m1, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1 +; CHECK-ZVKB-NEXT: ret %x = call <16 x i8> @llvm.fshr.v16i8(<16 x i8> %a, <16 x i8> %a, <16 x i8> shufflevector(<16 x i8> insertelement(<16 x i8> poison, i8 1, i32 0), <16 x i8> poison, <16 x i32> zeroinitializer)) ret <16 x i8> %x } @@ -415,11 +415,11 @@ define <16 x i8> @vror_vi_rotl_v16i8(<16 x i8> %a) { ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_rotl_v16i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 16, e8, m1, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 7 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_rotl_v16i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 16, e8, m1, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 7 +; CHECK-ZVKB-NEXT: ret %x = call <16 x i8> @llvm.fshl.v16i8(<16 x i8> %a, <16 x i8> %a, <16 x i8> shufflevector(<16 x i8> insertelement(<16 x i8> poison, i8 1, i32 0), <16 x i8> poison, <16 x i32> zeroinitializer)) ret <16 x i8> %x } @@ -440,12 +440,12 @@ define <32 x i8> @vror_vv_v32i8(<32 x i8> %a, <32 x i8> %b) { ; CHECK-NEXT: vor.vv v8, v12, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vv_v32i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: li a0, 32 -; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m2, ta, ma -; CHECK-ZVBB-NEXT: vror.vv v8, v8, v10 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vv_v32i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: li a0, 32 +; CHECK-ZVKB-NEXT: vsetvli zero, a0, e8, m2, ta, ma +; CHECK-ZVKB-NEXT: vror.vv v8, v8, v10 +; CHECK-ZVKB-NEXT: ret %x = call <32 x i8> @llvm.fshr.v32i8(<32 x i8> %a, <32 x i8> %a, <32 x i8> %b) ret <32 x i8> %x } @@ -464,12 +464,12 @@ define <32 x i8> @vror_vx_v32i8(<32 x i8> %a, i8 %b) { ; CHECK-NEXT: vor.vv v8, v12, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vx_v32i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: li a1, 32 -; CHECK-ZVBB-NEXT: vsetvli zero, a1, e8, m2, ta, ma -; CHECK-ZVBB-NEXT: vror.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vx_v32i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: li a1, 32 +; CHECK-ZVKB-NEXT: vsetvli zero, a1, e8, m2, ta, ma +; CHECK-ZVKB-NEXT: vror.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement <32 x i8> poison, i8 %b, i32 0 %b.splat = shufflevector <32 x i8> %b.head, <32 x i8> poison, <32 x i32> zeroinitializer %x = call <32 x i8> @llvm.fshr.v32i8(<32 x i8> %a, <32 x i8> %a, <32 x i8> %b.splat) @@ -486,12 +486,12 @@ define <32 x i8> @vror_vi_v32i8(<32 x i8> %a) { ; CHECK-NEXT: vor.vv v8, v8, v10 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_v32i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: li a0, 32 -; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m2, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 1 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_v32i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: li a0, 32 +; CHECK-ZVKB-NEXT: vsetvli zero, a0, e8, m2, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1 +; CHECK-ZVKB-NEXT: ret %x = call <32 x i8> @llvm.fshr.v32i8(<32 x i8> %a, <32 x i8> %a, <32 x i8> shufflevector(<32 x i8> insertelement(<32 x i8> poison, i8 1, i32 0), <32 x i8> poison, <32 x i32> zeroinitializer)) ret <32 x i8> %x } @@ -506,12 +506,12 @@ define <32 x i8> @vror_vi_rotl_v32i8(<32 x i8> %a) { ; CHECK-NEXT: vor.vv v8, v8, v10 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_rotl_v32i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: li a0, 32 -; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m2, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 7 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_rotl_v32i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: li a0, 32 +; CHECK-ZVKB-NEXT: vsetvli zero, a0, e8, m2, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 7 +; CHECK-ZVKB-NEXT: ret %x = call <32 x i8> @llvm.fshl.v32i8(<32 x i8> %a, <32 x i8> %a, <32 x i8> shufflevector(<32 x i8> insertelement(<32 x i8> poison, i8 1, i32 0), <32 x i8> poison, <32 x i32> zeroinitializer)) ret <32 x i8> %x } @@ -532,12 +532,12 @@ define <64 x i8> @vror_vv_v64i8(<64 x i8> %a, <64 x i8> %b) { ; CHECK-NEXT: vor.vv v8, v16, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vv_v64i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: li a0, 64 -; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m4, ta, ma -; CHECK-ZVBB-NEXT: vror.vv v8, v8, v12 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vv_v64i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: li a0, 64 +; CHECK-ZVKB-NEXT: vsetvli zero, a0, e8, m4, ta, ma +; CHECK-ZVKB-NEXT: vror.vv v8, v8, v12 +; CHECK-ZVKB-NEXT: ret %x = call <64 x i8> @llvm.fshr.v64i8(<64 x i8> %a, <64 x i8> %a, <64 x i8> %b) ret <64 x i8> %x } @@ -556,12 +556,12 @@ define <64 x i8> @vror_vx_v64i8(<64 x i8> %a, i8 %b) { ; CHECK-NEXT: vor.vv v8, v16, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vx_v64i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: li a1, 64 -; CHECK-ZVBB-NEXT: vsetvli zero, a1, e8, m4, ta, ma -; CHECK-ZVBB-NEXT: vror.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vx_v64i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: li a1, 64 +; CHECK-ZVKB-NEXT: vsetvli zero, a1, e8, m4, ta, ma +; CHECK-ZVKB-NEXT: vror.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement <64 x i8> poison, i8 %b, i32 0 %b.splat = shufflevector <64 x i8> %b.head, <64 x i8> poison, <64 x i32> zeroinitializer %x = call <64 x i8> @llvm.fshr.v64i8(<64 x i8> %a, <64 x i8> %a, <64 x i8> %b.splat) @@ -578,12 +578,12 @@ define <64 x i8> @vror_vi_v64i8(<64 x i8> %a) { ; CHECK-NEXT: vor.vv v8, v8, v12 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_v64i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: li a0, 64 -; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m4, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 1 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_v64i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: li a0, 64 +; CHECK-ZVKB-NEXT: vsetvli zero, a0, e8, m4, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1 +; CHECK-ZVKB-NEXT: ret %x = call <64 x i8> @llvm.fshr.v64i8(<64 x i8> %a, <64 x i8> %a, <64 x i8> shufflevector(<64 x i8> insertelement(<64 x i8> poison, i8 1, i32 0), <64 x i8> poison, <64 x i32> zeroinitializer)) ret <64 x i8> %x } @@ -598,12 +598,12 @@ define <64 x i8> @vror_vi_rotl_v64i8(<64 x i8> %a) { ; CHECK-NEXT: vor.vv v8, v8, v12 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_rotl_v64i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: li a0, 64 -; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m4, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 7 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_rotl_v64i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: li a0, 64 +; CHECK-ZVKB-NEXT: vsetvli zero, a0, e8, m4, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 7 +; CHECK-ZVKB-NEXT: ret %x = call <64 x i8> @llvm.fshl.v64i8(<64 x i8> %a, <64 x i8> %a, <64 x i8> shufflevector(<64 x i8> insertelement(<64 x i8> poison, i8 1, i32 0), <64 x i8> poison, <64 x i32> zeroinitializer)) ret <64 x i8> %x } @@ -623,11 +623,11 @@ define <1 x i16> @vror_vv_v1i16(<1 x i16> %a, <1 x i16> %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vv_v1i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 1, e16, mf4, ta, ma -; CHECK-ZVBB-NEXT: vror.vv v8, v8, v9 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vv_v1i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 1, e16, mf4, ta, ma +; CHECK-ZVKB-NEXT: vror.vv v8, v8, v9 +; CHECK-ZVKB-NEXT: ret %x = call <1 x i16> @llvm.fshr.v1i16(<1 x i16> %a, <1 x i16> %a, <1 x i16> %b) ret <1 x i16> %x } @@ -645,11 +645,11 @@ define <1 x i16> @vror_vx_v1i16(<1 x i16> %a, i16 %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vx_v1i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 1, e16, mf4, ta, ma -; CHECK-ZVBB-NEXT: vror.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vx_v1i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 1, e16, mf4, ta, ma +; CHECK-ZVKB-NEXT: vror.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement <1 x i16> poison, i16 %b, i32 0 %b.splat = shufflevector <1 x i16> %b.head, <1 x i16> poison, <1 x i32> zeroinitializer %x = call <1 x i16> @llvm.fshr.v1i16(<1 x i16> %a, <1 x i16> %a, <1 x i16> %b.splat) @@ -665,11 +665,11 @@ define <1 x i16> @vror_vi_v1i16(<1 x i16> %a) { ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_v1i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 1, e16, mf4, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 1 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_v1i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 1, e16, mf4, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1 +; CHECK-ZVKB-NEXT: ret %x = call <1 x i16> @llvm.fshr.v1i16(<1 x i16> %a, <1 x i16> %a, <1 x i16> shufflevector(<1 x i16> insertelement(<1 x i16> poison, i16 1, i32 0), <1 x i16> poison, <1 x i32> zeroinitializer)) ret <1 x i16> %x } @@ -683,11 +683,11 @@ define <1 x i16> @vror_vi_rotl_v1i16(<1 x i16> %a) { ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_rotl_v1i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 1, e16, mf4, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 15 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_rotl_v1i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 1, e16, mf4, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 15 +; CHECK-ZVKB-NEXT: ret %x = call <1 x i16> @llvm.fshl.v1i16(<1 x i16> %a, <1 x i16> %a, <1 x i16> shufflevector(<1 x i16> insertelement(<1 x i16> poison, i16 1, i32 0), <1 x i16> poison, <1 x i32> zeroinitializer)) ret <1 x i16> %x } @@ -707,11 +707,11 @@ define <2 x i16> @vror_vv_v2i16(<2 x i16> %a, <2 x i16> %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vv_v2i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 2, e16, mf4, ta, ma -; CHECK-ZVBB-NEXT: vror.vv v8, v8, v9 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vv_v2i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 2, e16, mf4, ta, ma +; CHECK-ZVKB-NEXT: vror.vv v8, v8, v9 +; CHECK-ZVKB-NEXT: ret %x = call <2 x i16> @llvm.fshr.v2i16(<2 x i16> %a, <2 x i16> %a, <2 x i16> %b) ret <2 x i16> %x } @@ -729,11 +729,11 @@ define <2 x i16> @vror_vx_v2i16(<2 x i16> %a, i16 %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vx_v2i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 2, e16, mf4, ta, ma -; CHECK-ZVBB-NEXT: vror.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vx_v2i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 2, e16, mf4, ta, ma +; CHECK-ZVKB-NEXT: vror.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement <2 x i16> poison, i16 %b, i32 0 %b.splat = shufflevector <2 x i16> %b.head, <2 x i16> poison, <2 x i32> zeroinitializer %x = call <2 x i16> @llvm.fshr.v2i16(<2 x i16> %a, <2 x i16> %a, <2 x i16> %b.splat) @@ -749,11 +749,11 @@ define <2 x i16> @vror_vi_v2i16(<2 x i16> %a) { ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_v2i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 2, e16, mf4, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 1 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_v2i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 2, e16, mf4, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1 +; CHECK-ZVKB-NEXT: ret %x = call <2 x i16> @llvm.fshr.v2i16(<2 x i16> %a, <2 x i16> %a, <2 x i16> shufflevector(<2 x i16> insertelement(<2 x i16> poison, i16 1, i32 0), <2 x i16> poison, <2 x i32> zeroinitializer)) ret <2 x i16> %x } @@ -767,11 +767,11 @@ define <2 x i16> @vror_vi_rotl_v2i16(<2 x i16> %a) { ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_rotl_v2i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 2, e16, mf4, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 15 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_rotl_v2i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 2, e16, mf4, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 15 +; CHECK-ZVKB-NEXT: ret %x = call <2 x i16> @llvm.fshl.v2i16(<2 x i16> %a, <2 x i16> %a, <2 x i16> shufflevector(<2 x i16> insertelement(<2 x i16> poison, i16 1, i32 0), <2 x i16> poison, <2 x i32> zeroinitializer)) ret <2 x i16> %x } @@ -791,11 +791,11 @@ define <4 x i16> @vror_vv_v4i16(<4 x i16> %a, <4 x i16> %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vv_v4i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma -; CHECK-ZVBB-NEXT: vror.vv v8, v8, v9 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vv_v4i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma +; CHECK-ZVKB-NEXT: vror.vv v8, v8, v9 +; CHECK-ZVKB-NEXT: ret %x = call <4 x i16> @llvm.fshr.v4i16(<4 x i16> %a, <4 x i16> %a, <4 x i16> %b) ret <4 x i16> %x } @@ -813,11 +813,11 @@ define <4 x i16> @vror_vx_v4i16(<4 x i16> %a, i16 %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vx_v4i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma -; CHECK-ZVBB-NEXT: vror.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vx_v4i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma +; CHECK-ZVKB-NEXT: vror.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement <4 x i16> poison, i16 %b, i32 0 %b.splat = shufflevector <4 x i16> %b.head, <4 x i16> poison, <4 x i32> zeroinitializer %x = call <4 x i16> @llvm.fshr.v4i16(<4 x i16> %a, <4 x i16> %a, <4 x i16> %b.splat) @@ -833,11 +833,11 @@ define <4 x i16> @vror_vi_v4i16(<4 x i16> %a) { ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_v4i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 1 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_v4i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1 +; CHECK-ZVKB-NEXT: ret %x = call <4 x i16> @llvm.fshr.v4i16(<4 x i16> %a, <4 x i16> %a, <4 x i16> shufflevector(<4 x i16> insertelement(<4 x i16> poison, i16 1, i32 0), <4 x i16> poison, <4 x i32> zeroinitializer)) ret <4 x i16> %x } @@ -851,11 +851,11 @@ define <4 x i16> @vror_vi_rotl_v4i16(<4 x i16> %a) { ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_rotl_v4i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 15 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_rotl_v4i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 15 +; CHECK-ZVKB-NEXT: ret %x = call <4 x i16> @llvm.fshl.v4i16(<4 x i16> %a, <4 x i16> %a, <4 x i16> shufflevector(<4 x i16> insertelement(<4 x i16> poison, i16 1, i32 0), <4 x i16> poison, <4 x i32> zeroinitializer)) ret <4 x i16> %x } @@ -875,11 +875,11 @@ define <8 x i16> @vror_vv_v8i16(<8 x i16> %a, <8 x i16> %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vv_v8i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma -; CHECK-ZVBB-NEXT: vror.vv v8, v8, v9 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vv_v8i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 8, e16, m1, ta, ma +; CHECK-ZVKB-NEXT: vror.vv v8, v8, v9 +; CHECK-ZVKB-NEXT: ret %x = call <8 x i16> @llvm.fshr.v8i16(<8 x i16> %a, <8 x i16> %a, <8 x i16> %b) ret <8 x i16> %x } @@ -897,11 +897,11 @@ define <8 x i16> @vror_vx_v8i16(<8 x i16> %a, i16 %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vx_v8i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma -; CHECK-ZVBB-NEXT: vror.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vx_v8i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 8, e16, m1, ta, ma +; CHECK-ZVKB-NEXT: vror.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement <8 x i16> poison, i16 %b, i32 0 %b.splat = shufflevector <8 x i16> %b.head, <8 x i16> poison, <8 x i32> zeroinitializer %x = call <8 x i16> @llvm.fshr.v8i16(<8 x i16> %a, <8 x i16> %a, <8 x i16> %b.splat) @@ -917,11 +917,11 @@ define <8 x i16> @vror_vi_v8i16(<8 x i16> %a) { ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_v8i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 1 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_v8i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 8, e16, m1, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1 +; CHECK-ZVKB-NEXT: ret %x = call <8 x i16> @llvm.fshr.v8i16(<8 x i16> %a, <8 x i16> %a, <8 x i16> shufflevector(<8 x i16> insertelement(<8 x i16> poison, i16 1, i32 0), <8 x i16> poison, <8 x i32> zeroinitializer)) ret <8 x i16> %x } @@ -935,11 +935,11 @@ define <8 x i16> @vror_vi_rotl_v8i16(<8 x i16> %a) { ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_rotl_v8i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 15 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_rotl_v8i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 8, e16, m1, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 15 +; CHECK-ZVKB-NEXT: ret %x = call <8 x i16> @llvm.fshl.v8i16(<8 x i16> %a, <8 x i16> %a, <8 x i16> shufflevector(<8 x i16> insertelement(<8 x i16> poison, i16 1, i32 0), <8 x i16> poison, <8 x i32> zeroinitializer)) ret <8 x i16> %x } @@ -959,11 +959,11 @@ define <16 x i16> @vror_vv_v16i16(<16 x i16> %a, <16 x i16> %b) { ; CHECK-NEXT: vor.vv v8, v12, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vv_v16i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 16, e16, m2, ta, ma -; CHECK-ZVBB-NEXT: vror.vv v8, v8, v10 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vv_v16i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 16, e16, m2, ta, ma +; CHECK-ZVKB-NEXT: vror.vv v8, v8, v10 +; CHECK-ZVKB-NEXT: ret %x = call <16 x i16> @llvm.fshr.v16i16(<16 x i16> %a, <16 x i16> %a, <16 x i16> %b) ret <16 x i16> %x } @@ -981,11 +981,11 @@ define <16 x i16> @vror_vx_v16i16(<16 x i16> %a, i16 %b) { ; CHECK-NEXT: vor.vv v8, v12, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vx_v16i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 16, e16, m2, ta, ma -; CHECK-ZVBB-NEXT: vror.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vx_v16i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 16, e16, m2, ta, ma +; CHECK-ZVKB-NEXT: vror.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement <16 x i16> poison, i16 %b, i32 0 %b.splat = shufflevector <16 x i16> %b.head, <16 x i16> poison, <16 x i32> zeroinitializer %x = call <16 x i16> @llvm.fshr.v16i16(<16 x i16> %a, <16 x i16> %a, <16 x i16> %b.splat) @@ -1001,11 +1001,11 @@ define <16 x i16> @vror_vi_v16i16(<16 x i16> %a) { ; CHECK-NEXT: vor.vv v8, v8, v10 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_v16i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 16, e16, m2, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 1 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_v16i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 16, e16, m2, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1 +; CHECK-ZVKB-NEXT: ret %x = call <16 x i16> @llvm.fshr.v16i16(<16 x i16> %a, <16 x i16> %a, <16 x i16> shufflevector(<16 x i16> insertelement(<16 x i16> poison, i16 1, i32 0), <16 x i16> poison, <16 x i32> zeroinitializer)) ret <16 x i16> %x } @@ -1019,11 +1019,11 @@ define <16 x i16> @vror_vi_rotl_v16i16(<16 x i16> %a) { ; CHECK-NEXT: vor.vv v8, v8, v10 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_rotl_v16i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 16, e16, m2, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 15 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_rotl_v16i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 16, e16, m2, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 15 +; CHECK-ZVKB-NEXT: ret %x = call <16 x i16> @llvm.fshl.v16i16(<16 x i16> %a, <16 x i16> %a, <16 x i16> shufflevector(<16 x i16> insertelement(<16 x i16> poison, i16 1, i32 0), <16 x i16> poison, <16 x i32> zeroinitializer)) ret <16 x i16> %x } @@ -1044,12 +1044,12 @@ define <32 x i16> @vror_vv_v32i16(<32 x i16> %a, <32 x i16> %b) { ; CHECK-NEXT: vor.vv v8, v16, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vv_v32i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: li a0, 32 -; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-ZVBB-NEXT: vror.vv v8, v8, v12 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vv_v32i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: li a0, 32 +; CHECK-ZVKB-NEXT: vsetvli zero, a0, e16, m4, ta, ma +; CHECK-ZVKB-NEXT: vror.vv v8, v8, v12 +; CHECK-ZVKB-NEXT: ret %x = call <32 x i16> @llvm.fshr.v32i16(<32 x i16> %a, <32 x i16> %a, <32 x i16> %b) ret <32 x i16> %x } @@ -1068,12 +1068,12 @@ define <32 x i16> @vror_vx_v32i16(<32 x i16> %a, i16 %b) { ; CHECK-NEXT: vor.vv v8, v16, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vx_v32i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: li a1, 32 -; CHECK-ZVBB-NEXT: vsetvli zero, a1, e16, m4, ta, ma -; CHECK-ZVBB-NEXT: vror.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vx_v32i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: li a1, 32 +; CHECK-ZVKB-NEXT: vsetvli zero, a1, e16, m4, ta, ma +; CHECK-ZVKB-NEXT: vror.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement <32 x i16> poison, i16 %b, i32 0 %b.splat = shufflevector <32 x i16> %b.head, <32 x i16> poison, <32 x i32> zeroinitializer %x = call <32 x i16> @llvm.fshr.v32i16(<32 x i16> %a, <32 x i16> %a, <32 x i16> %b.splat) @@ -1090,12 +1090,12 @@ define <32 x i16> @vror_vi_v32i16(<32 x i16> %a) { ; CHECK-NEXT: vor.vv v8, v8, v12 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_v32i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: li a0, 32 -; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 1 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_v32i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: li a0, 32 +; CHECK-ZVKB-NEXT: vsetvli zero, a0, e16, m4, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1 +; CHECK-ZVKB-NEXT: ret %x = call <32 x i16> @llvm.fshr.v32i16(<32 x i16> %a, <32 x i16> %a, <32 x i16> shufflevector(<32 x i16> insertelement(<32 x i16> poison, i16 1, i32 0), <32 x i16> poison, <32 x i32> zeroinitializer)) ret <32 x i16> %x } @@ -1110,12 +1110,12 @@ define <32 x i16> @vror_vi_rotl_v32i16(<32 x i16> %a) { ; CHECK-NEXT: vor.vv v8, v8, v12 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_rotl_v32i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: li a0, 32 -; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 15 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_rotl_v32i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: li a0, 32 +; CHECK-ZVKB-NEXT: vsetvli zero, a0, e16, m4, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 15 +; CHECK-ZVKB-NEXT: ret %x = call <32 x i16> @llvm.fshl.v32i16(<32 x i16> %a, <32 x i16> %a, <32 x i16> shufflevector(<32 x i16> insertelement(<32 x i16> poison, i16 1, i32 0), <32 x i16> poison, <32 x i32> zeroinitializer)) ret <32 x i16> %x } @@ -1136,11 +1136,11 @@ define <1 x i32> @vror_vv_v1i32(<1 x i32> %a, <1 x i32> %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vv_v1i32: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 1, e32, mf2, ta, ma -; CHECK-ZVBB-NEXT: vror.vv v8, v8, v9 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vv_v1i32: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 1, e32, mf2, ta, ma +; CHECK-ZVKB-NEXT: vror.vv v8, v8, v9 +; CHECK-ZVKB-NEXT: ret %x = call <1 x i32> @llvm.fshr.v1i32(<1 x i32> %a, <1 x i32> %a, <1 x i32> %b) ret <1 x i32> %x } @@ -1159,11 +1159,11 @@ define <1 x i32> @vror_vx_v1i32(<1 x i32> %a, i32 %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vx_v1i32: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 1, e32, mf2, ta, ma -; CHECK-ZVBB-NEXT: vror.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vx_v1i32: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 1, e32, mf2, ta, ma +; CHECK-ZVKB-NEXT: vror.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement <1 x i32> poison, i32 %b, i32 0 %b.splat = shufflevector <1 x i32> %b.head, <1 x i32> poison, <1 x i32> zeroinitializer %x = call <1 x i32> @llvm.fshr.v1i32(<1 x i32> %a, <1 x i32> %a, <1 x i32> %b.splat) @@ -1179,11 +1179,11 @@ define <1 x i32> @vror_vi_v1i32(<1 x i32> %a) { ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_v1i32: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 1, e32, mf2, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 1 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_v1i32: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 1, e32, mf2, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1 +; CHECK-ZVKB-NEXT: ret %x = call <1 x i32> @llvm.fshr.v1i32(<1 x i32> %a, <1 x i32> %a, <1 x i32> shufflevector(<1 x i32> insertelement(<1 x i32> poison, i32 1, i32 0), <1 x i32> poison, <1 x i32> zeroinitializer)) ret <1 x i32> %x } @@ -1197,11 +1197,11 @@ define <1 x i32> @vror_vi_rotl_v1i32(<1 x i32> %a) { ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_rotl_v1i32: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 1, e32, mf2, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 31 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_rotl_v1i32: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 1, e32, mf2, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 31 +; CHECK-ZVKB-NEXT: ret %x = call <1 x i32> @llvm.fshl.v1i32(<1 x i32> %a, <1 x i32> %a, <1 x i32> shufflevector(<1 x i32> insertelement(<1 x i32> poison, i32 1, i32 0), <1 x i32> poison, <1 x i32> zeroinitializer)) ret <1 x i32> %x } @@ -1222,11 +1222,11 @@ define <2 x i32> @vror_vv_v2i32(<2 x i32> %a, <2 x i32> %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vv_v2i32: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma -; CHECK-ZVBB-NEXT: vror.vv v8, v8, v9 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vv_v2i32: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma +; CHECK-ZVKB-NEXT: vror.vv v8, v8, v9 +; CHECK-ZVKB-NEXT: ret %x = call <2 x i32> @llvm.fshr.v2i32(<2 x i32> %a, <2 x i32> %a, <2 x i32> %b) ret <2 x i32> %x } @@ -1245,11 +1245,11 @@ define <2 x i32> @vror_vx_v2i32(<2 x i32> %a, i32 %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vx_v2i32: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma -; CHECK-ZVBB-NEXT: vror.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vx_v2i32: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma +; CHECK-ZVKB-NEXT: vror.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement <2 x i32> poison, i32 %b, i32 0 %b.splat = shufflevector <2 x i32> %b.head, <2 x i32> poison, <2 x i32> zeroinitializer %x = call <2 x i32> @llvm.fshr.v2i32(<2 x i32> %a, <2 x i32> %a, <2 x i32> %b.splat) @@ -1265,11 +1265,11 @@ define <2 x i32> @vror_vi_v2i32(<2 x i32> %a) { ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_v2i32: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 1 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_v2i32: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1 +; CHECK-ZVKB-NEXT: ret %x = call <2 x i32> @llvm.fshr.v2i32(<2 x i32> %a, <2 x i32> %a, <2 x i32> shufflevector(<2 x i32> insertelement(<2 x i32> poison, i32 1, i32 0), <2 x i32> poison, <2 x i32> zeroinitializer)) ret <2 x i32> %x } @@ -1283,11 +1283,11 @@ define <2 x i32> @vror_vi_rotl_v2i32(<2 x i32> %a) { ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_rotl_v2i32: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 31 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_rotl_v2i32: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 31 +; CHECK-ZVKB-NEXT: ret %x = call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %a, <2 x i32> %a, <2 x i32> shufflevector(<2 x i32> insertelement(<2 x i32> poison, i32 1, i32 0), <2 x i32> poison, <2 x i32> zeroinitializer)) ret <2 x i32> %x } @@ -1308,11 +1308,11 @@ define <4 x i32> @vror_vv_v4i32(<4 x i32> %a, <4 x i32> %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vv_v4i32: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma -; CHECK-ZVBB-NEXT: vror.vv v8, v8, v9 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vv_v4i32: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 4, e32, m1, ta, ma +; CHECK-ZVKB-NEXT: vror.vv v8, v8, v9 +; CHECK-ZVKB-NEXT: ret %x = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %a, <4 x i32> %a, <4 x i32> %b) ret <4 x i32> %x } @@ -1331,11 +1331,11 @@ define <4 x i32> @vror_vx_v4i32(<4 x i32> %a, i32 %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vx_v4i32: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma -; CHECK-ZVBB-NEXT: vror.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vx_v4i32: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 4, e32, m1, ta, ma +; CHECK-ZVKB-NEXT: vror.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement <4 x i32> poison, i32 %b, i32 0 %b.splat = shufflevector <4 x i32> %b.head, <4 x i32> poison, <4 x i32> zeroinitializer %x = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %a, <4 x i32> %a, <4 x i32> %b.splat) @@ -1351,11 +1351,11 @@ define <4 x i32> @vror_vi_v4i32(<4 x i32> %a) { ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_v4i32: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 1 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_v4i32: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 4, e32, m1, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1 +; CHECK-ZVKB-NEXT: ret %x = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %a, <4 x i32> %a, <4 x i32> shufflevector(<4 x i32> insertelement(<4 x i32> poison, i32 1, i32 0), <4 x i32> poison, <4 x i32> zeroinitializer)) ret <4 x i32> %x } @@ -1369,11 +1369,11 @@ define <4 x i32> @vror_vi_rotl_v4i32(<4 x i32> %a) { ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_rotl_v4i32: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 31 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_rotl_v4i32: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 4, e32, m1, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 31 +; CHECK-ZVKB-NEXT: ret %x = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %a, <4 x i32> %a, <4 x i32> shufflevector(<4 x i32> insertelement(<4 x i32> poison, i32 1, i32 0), <4 x i32> poison, <4 x i32> zeroinitializer)) ret <4 x i32> %x } @@ -1394,11 +1394,11 @@ define <8 x i32> @vror_vv_v8i32(<8 x i32> %a, <8 x i32> %b) { ; CHECK-NEXT: vor.vv v8, v12, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vv_v8i32: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 8, e32, m2, ta, ma -; CHECK-ZVBB-NEXT: vror.vv v8, v8, v10 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vv_v8i32: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 8, e32, m2, ta, ma +; CHECK-ZVKB-NEXT: vror.vv v8, v8, v10 +; CHECK-ZVKB-NEXT: ret %x = call <8 x i32> @llvm.fshr.v8i32(<8 x i32> %a, <8 x i32> %a, <8 x i32> %b) ret <8 x i32> %x } @@ -1417,11 +1417,11 @@ define <8 x i32> @vror_vx_v8i32(<8 x i32> %a, i32 %b) { ; CHECK-NEXT: vor.vv v8, v12, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vx_v8i32: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 8, e32, m2, ta, ma -; CHECK-ZVBB-NEXT: vror.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vx_v8i32: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 8, e32, m2, ta, ma +; CHECK-ZVKB-NEXT: vror.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement <8 x i32> poison, i32 %b, i32 0 %b.splat = shufflevector <8 x i32> %b.head, <8 x i32> poison, <8 x i32> zeroinitializer %x = call <8 x i32> @llvm.fshr.v8i32(<8 x i32> %a, <8 x i32> %a, <8 x i32> %b.splat) @@ -1437,11 +1437,11 @@ define <8 x i32> @vror_vi_v8i32(<8 x i32> %a) { ; CHECK-NEXT: vor.vv v8, v8, v10 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_v8i32: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 8, e32, m2, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 1 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_v8i32: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 8, e32, m2, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1 +; CHECK-ZVKB-NEXT: ret %x = call <8 x i32> @llvm.fshr.v8i32(<8 x i32> %a, <8 x i32> %a, <8 x i32> shufflevector(<8 x i32> insertelement(<8 x i32> poison, i32 1, i32 0), <8 x i32> poison, <8 x i32> zeroinitializer)) ret <8 x i32> %x } @@ -1455,11 +1455,11 @@ define <8 x i32> @vror_vi_rotl_v8i32(<8 x i32> %a) { ; CHECK-NEXT: vor.vv v8, v8, v10 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_rotl_v8i32: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 8, e32, m2, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 31 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_rotl_v8i32: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 8, e32, m2, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 31 +; CHECK-ZVKB-NEXT: ret %x = call <8 x i32> @llvm.fshl.v8i32(<8 x i32> %a, <8 x i32> %a, <8 x i32> shufflevector(<8 x i32> insertelement(<8 x i32> poison, i32 1, i32 0), <8 x i32> poison, <8 x i32> zeroinitializer)) ret <8 x i32> %x } @@ -1480,11 +1480,11 @@ define <16 x i32> @vror_vv_v16i32(<16 x i32> %a, <16 x i32> %b) { ; CHECK-NEXT: vor.vv v8, v16, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vv_v16i32: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 16, e32, m4, ta, ma -; CHECK-ZVBB-NEXT: vror.vv v8, v8, v12 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vv_v16i32: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 16, e32, m4, ta, ma +; CHECK-ZVKB-NEXT: vror.vv v8, v8, v12 +; CHECK-ZVKB-NEXT: ret %x = call <16 x i32> @llvm.fshr.v16i32(<16 x i32> %a, <16 x i32> %a, <16 x i32> %b) ret <16 x i32> %x } @@ -1503,11 +1503,11 @@ define <16 x i32> @vror_vx_v16i32(<16 x i32> %a, i32 %b) { ; CHECK-NEXT: vor.vv v8, v16, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vx_v16i32: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 16, e32, m4, ta, ma -; CHECK-ZVBB-NEXT: vror.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vx_v16i32: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 16, e32, m4, ta, ma +; CHECK-ZVKB-NEXT: vror.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement <16 x i32> poison, i32 %b, i32 0 %b.splat = shufflevector <16 x i32> %b.head, <16 x i32> poison, <16 x i32> zeroinitializer %x = call <16 x i32> @llvm.fshr.v16i32(<16 x i32> %a, <16 x i32> %a, <16 x i32> %b.splat) @@ -1523,11 +1523,11 @@ define <16 x i32> @vror_vi_v16i32(<16 x i32> %a) { ; CHECK-NEXT: vor.vv v8, v8, v12 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_v16i32: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 16, e32, m4, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 1 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_v16i32: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 16, e32, m4, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1 +; CHECK-ZVKB-NEXT: ret %x = call <16 x i32> @llvm.fshr.v16i32(<16 x i32> %a, <16 x i32> %a, <16 x i32> shufflevector(<16 x i32> insertelement(<16 x i32> poison, i32 1, i32 0), <16 x i32> poison, <16 x i32> zeroinitializer)) ret <16 x i32> %x } @@ -1541,11 +1541,11 @@ define <16 x i32> @vror_vi_rotl_v16i32(<16 x i32> %a) { ; CHECK-NEXT: vor.vv v8, v8, v12 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_rotl_v16i32: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 16, e32, m4, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 31 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_rotl_v16i32: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 16, e32, m4, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 31 +; CHECK-ZVKB-NEXT: ret %x = call <16 x i32> @llvm.fshl.v16i32(<16 x i32> %a, <16 x i32> %a, <16 x i32> shufflevector(<16 x i32> insertelement(<16 x i32> poison, i32 1, i32 0), <16 x i32> poison, <16 x i32> zeroinitializer)) ret <16 x i32> %x } @@ -1566,11 +1566,11 @@ define <1 x i64> @vror_vv_v1i64(<1 x i64> %a, <1 x i64> %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vv_v1i64: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 1, e64, m1, ta, ma -; CHECK-ZVBB-NEXT: vror.vv v8, v8, v9 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vv_v1i64: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 1, e64, m1, ta, ma +; CHECK-ZVKB-NEXT: vror.vv v8, v8, v9 +; CHECK-ZVKB-NEXT: ret %x = call <1 x i64> @llvm.fshr.v1i64(<1 x i64> %a, <1 x i64> %a, <1 x i64> %b) ret <1 x i64> %x } @@ -1589,11 +1589,11 @@ define <1 x i64> @vror_vx_v1i64(<1 x i64> %a, i64 %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vx_v1i64: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 1, e64, m1, ta, ma -; CHECK-ZVBB-NEXT: vror.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vx_v1i64: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 1, e64, m1, ta, ma +; CHECK-ZVKB-NEXT: vror.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement <1 x i64> poison, i64 %b, i32 0 %b.splat = shufflevector <1 x i64> %b.head, <1 x i64> poison, <1 x i32> zeroinitializer %x = call <1 x i64> @llvm.fshr.v1i64(<1 x i64> %a, <1 x i64> %a, <1 x i64> %b.splat) @@ -1624,11 +1624,11 @@ define <1 x i64> @vror_vi_v1i64(<1 x i64> %a) { ; CHECK-RV64-NEXT: vor.vv v8, v8, v9 ; CHECK-RV64-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_v1i64: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 1, e64, m1, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 1 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_v1i64: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 1, e64, m1, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1 +; CHECK-ZVKB-NEXT: ret %x = call <1 x i64> @llvm.fshr.v1i64(<1 x i64> %a, <1 x i64> %a, <1 x i64> shufflevector(<1 x i64> insertelement(<1 x i64> poison, i64 1, i32 0), <1 x i64> poison, <1 x i32> zeroinitializer)) ret <1 x i64> %x } @@ -1657,11 +1657,11 @@ define <1 x i64> @vror_vi_rotl_v1i64(<1 x i64> %a) { ; CHECK-RV64-NEXT: vor.vv v8, v8, v9 ; CHECK-RV64-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_rotl_v1i64: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 1, e64, m1, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 63 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_rotl_v1i64: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 1, e64, m1, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 63 +; CHECK-ZVKB-NEXT: ret %x = call <1 x i64> @llvm.fshl.v1i64(<1 x i64> %a, <1 x i64> %a, <1 x i64> shufflevector(<1 x i64> insertelement(<1 x i64> poison, i64 1, i32 0), <1 x i64> poison, <1 x i32> zeroinitializer)) ret <1 x i64> %x } @@ -1682,11 +1682,11 @@ define <2 x i64> @vror_vv_v2i64(<2 x i64> %a, <2 x i64> %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vv_v2i64: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 2, e64, m1, ta, ma -; CHECK-ZVBB-NEXT: vror.vv v8, v8, v9 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vv_v2i64: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 2, e64, m1, ta, ma +; CHECK-ZVKB-NEXT: vror.vv v8, v8, v9 +; CHECK-ZVKB-NEXT: ret %x = call <2 x i64> @llvm.fshr.v2i64(<2 x i64> %a, <2 x i64> %a, <2 x i64> %b) ret <2 x i64> %x } @@ -1705,11 +1705,11 @@ define <2 x i64> @vror_vx_v2i64(<2 x i64> %a, i64 %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vx_v2i64: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 2, e64, m1, ta, ma -; CHECK-ZVBB-NEXT: vror.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vx_v2i64: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 2, e64, m1, ta, ma +; CHECK-ZVKB-NEXT: vror.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement <2 x i64> poison, i64 %b, i32 0 %b.splat = shufflevector <2 x i64> %b.head, <2 x i64> poison, <2 x i32> zeroinitializer %x = call <2 x i64> @llvm.fshr.v2i64(<2 x i64> %a, <2 x i64> %a, <2 x i64> %b.splat) @@ -1740,11 +1740,11 @@ define <2 x i64> @vror_vi_v2i64(<2 x i64> %a) { ; CHECK-RV64-NEXT: vor.vv v8, v8, v9 ; CHECK-RV64-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_v2i64: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 2, e64, m1, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 1 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_v2i64: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 2, e64, m1, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1 +; CHECK-ZVKB-NEXT: ret %x = call <2 x i64> @llvm.fshr.v2i64(<2 x i64> %a, <2 x i64> %a, <2 x i64> shufflevector(<2 x i64> insertelement(<2 x i64> poison, i64 1, i32 0), <2 x i64> poison, <2 x i32> zeroinitializer)) ret <2 x i64> %x } @@ -1773,11 +1773,11 @@ define <2 x i64> @vror_vi_rotl_v2i64(<2 x i64> %a) { ; CHECK-RV64-NEXT: vor.vv v8, v8, v9 ; CHECK-RV64-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_rotl_v2i64: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 2, e64, m1, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 63 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_rotl_v2i64: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 2, e64, m1, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 63 +; CHECK-ZVKB-NEXT: ret %x = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> %a, <2 x i64> %a, <2 x i64> shufflevector(<2 x i64> insertelement(<2 x i64> poison, i64 1, i32 0), <2 x i64> poison, <2 x i32> zeroinitializer)) ret <2 x i64> %x } @@ -1798,11 +1798,11 @@ define <4 x i64> @vror_vv_v4i64(<4 x i64> %a, <4 x i64> %b) { ; CHECK-NEXT: vor.vv v8, v12, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vv_v4i64: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 4, e64, m2, ta, ma -; CHECK-ZVBB-NEXT: vror.vv v8, v8, v10 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vv_v4i64: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 4, e64, m2, ta, ma +; CHECK-ZVKB-NEXT: vror.vv v8, v8, v10 +; CHECK-ZVKB-NEXT: ret %x = call <4 x i64> @llvm.fshr.v4i64(<4 x i64> %a, <4 x i64> %a, <4 x i64> %b) ret <4 x i64> %x } @@ -1821,11 +1821,11 @@ define <4 x i64> @vror_vx_v4i64(<4 x i64> %a, i64 %b) { ; CHECK-NEXT: vor.vv v8, v12, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vx_v4i64: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 4, e64, m2, ta, ma -; CHECK-ZVBB-NEXT: vror.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vx_v4i64: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 4, e64, m2, ta, ma +; CHECK-ZVKB-NEXT: vror.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement <4 x i64> poison, i64 %b, i32 0 %b.splat = shufflevector <4 x i64> %b.head, <4 x i64> poison, <4 x i32> zeroinitializer %x = call <4 x i64> @llvm.fshr.v4i64(<4 x i64> %a, <4 x i64> %a, <4 x i64> %b.splat) @@ -1856,11 +1856,11 @@ define <4 x i64> @vror_vi_v4i64(<4 x i64> %a) { ; CHECK-RV64-NEXT: vor.vv v8, v8, v10 ; CHECK-RV64-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_v4i64: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 4, e64, m2, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 1 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_v4i64: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 4, e64, m2, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1 +; CHECK-ZVKB-NEXT: ret %x = call <4 x i64> @llvm.fshr.v4i64(<4 x i64> %a, <4 x i64> %a, <4 x i64> shufflevector(<4 x i64> insertelement(<4 x i64> poison, i64 1, i32 0), <4 x i64> poison, <4 x i32> zeroinitializer)) ret <4 x i64> %x } @@ -1889,11 +1889,11 @@ define <4 x i64> @vror_vi_rotl_v4i64(<4 x i64> %a) { ; CHECK-RV64-NEXT: vor.vv v8, v8, v10 ; CHECK-RV64-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_rotl_v4i64: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 4, e64, m2, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 63 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_rotl_v4i64: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 4, e64, m2, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 63 +; CHECK-ZVKB-NEXT: ret %x = call <4 x i64> @llvm.fshl.v4i64(<4 x i64> %a, <4 x i64> %a, <4 x i64> shufflevector(<4 x i64> insertelement(<4 x i64> poison, i64 1, i32 0), <4 x i64> poison, <4 x i32> zeroinitializer)) ret <4 x i64> %x } @@ -1914,11 +1914,11 @@ define <8 x i64> @vror_vv_v8i64(<8 x i64> %a, <8 x i64> %b) { ; CHECK-NEXT: vor.vv v8, v16, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vv_v8i64: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 8, e64, m4, ta, ma -; CHECK-ZVBB-NEXT: vror.vv v8, v8, v12 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vv_v8i64: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 8, e64, m4, ta, ma +; CHECK-ZVKB-NEXT: vror.vv v8, v8, v12 +; CHECK-ZVKB-NEXT: ret %x = call <8 x i64> @llvm.fshr.v8i64(<8 x i64> %a, <8 x i64> %a, <8 x i64> %b) ret <8 x i64> %x } @@ -1937,11 +1937,11 @@ define <8 x i64> @vror_vx_v8i64(<8 x i64> %a, i64 %b) { ; CHECK-NEXT: vor.vv v8, v16, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vx_v8i64: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 8, e64, m4, ta, ma -; CHECK-ZVBB-NEXT: vror.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vx_v8i64: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 8, e64, m4, ta, ma +; CHECK-ZVKB-NEXT: vror.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement <8 x i64> poison, i64 %b, i32 0 %b.splat = shufflevector <8 x i64> %b.head, <8 x i64> poison, <8 x i32> zeroinitializer %x = call <8 x i64> @llvm.fshr.v8i64(<8 x i64> %a, <8 x i64> %a, <8 x i64> %b.splat) @@ -1972,11 +1972,11 @@ define <8 x i64> @vror_vi_v8i64(<8 x i64> %a) { ; CHECK-RV64-NEXT: vor.vv v8, v8, v12 ; CHECK-RV64-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_v8i64: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 8, e64, m4, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 1 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_v8i64: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 8, e64, m4, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1 +; CHECK-ZVKB-NEXT: ret %x = call <8 x i64> @llvm.fshr.v8i64(<8 x i64> %a, <8 x i64> %a, <8 x i64> shufflevector(<8 x i64> insertelement(<8 x i64> poison, i64 1, i32 0), <8 x i64> poison, <8 x i32> zeroinitializer)) ret <8 x i64> %x } @@ -2005,11 +2005,11 @@ define <8 x i64> @vror_vi_rotl_v8i64(<8 x i64> %a) { ; CHECK-RV64-NEXT: vor.vv v8, v8, v12 ; CHECK-RV64-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_rotl_v8i64: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 8, e64, m4, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 63 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_rotl_v8i64: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetivli zero, 8, e64, m4, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 63 +; CHECK-ZVKB-NEXT: ret %x = call <8 x i64> @llvm.fshl.v8i64(<8 x i64> %a, <8 x i64> %a, <8 x i64> shufflevector(<8 x i64> insertelement(<8 x i64> poison, i64 1, i32 0), <8 x i64> poison, <8 x i32> zeroinitializer)) ret <8 x i64> %x } diff --git a/llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll index adcd676d3e058..f716984599e3f 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3 ; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV32 ; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV64 -; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB,CHECK-ZVBB32 -; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB,CHECK-ZVBB64 +; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB,CHECK-ZVKB32 +; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB,CHECK-ZVKB64 define @vandn_vv_nxv1i8( %x, %y) { ; CHECK-LABEL: vandn_vv_nxv1i8: @@ -12,11 +12,11 @@ define @vandn_vv_nxv1i8( %x, poison, i8 -1, i32 0 %splat = shufflevector %head, poison, zeroinitializer %a = xor %x, %splat @@ -32,11 +32,11 @@ define @vandn_vv_swapped_nxv1i8( %x, poison, i8 -1, i32 0 %splat = shufflevector %head, poison, zeroinitializer %a = xor %x, %splat @@ -52,11 +52,11 @@ define @vandn_vx_nxv1i8(i8 %x, %y) { ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vandn_vx_nxv1i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e8, mf8, ta, ma -; CHECK-ZVBB-NEXT: vandn.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vandn_vx_nxv1i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e8, mf8, ta, ma +; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %a = xor i8 %x, -1 %head = insertelement poison, i8 %a, i32 0 %splat = shufflevector %head, poison, zeroinitializer @@ -72,11 +72,11 @@ define @vandn_vx_swapped_nxv1i8(i8 %x, %y) { ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vandn_vx_swapped_nxv1i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e8, mf8, ta, ma -; CHECK-ZVBB-NEXT: vandn.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vandn_vx_swapped_nxv1i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e8, mf8, ta, ma +; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %a = xor i8 %x, -1 %head = insertelement poison, i8 %a, i32 0 %splat = shufflevector %head, poison, zeroinitializer @@ -92,11 +92,11 @@ define @vandn_vv_nxv2i8( %x, poison, i8 -1, i32 0 %splat = shufflevector %head, poison, zeroinitializer %a = xor %x, %splat @@ -112,11 +112,11 @@ define @vandn_vv_swapped_nxv2i8( %x, poison, i8 -1, i32 0 %splat = shufflevector %head, poison, zeroinitializer %a = xor %x, %splat @@ -132,11 +132,11 @@ define @vandn_vx_nxv2i8(i8 %x, %y) { ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vandn_vx_nxv2i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e8, mf4, ta, ma -; CHECK-ZVBB-NEXT: vandn.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vandn_vx_nxv2i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e8, mf4, ta, ma +; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %a = xor i8 %x, -1 %head = insertelement poison, i8 %a, i32 0 %splat = shufflevector %head, poison, zeroinitializer @@ -152,11 +152,11 @@ define @vandn_vx_swapped_nxv2i8(i8 %x, %y) { ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vandn_vx_swapped_nxv2i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e8, mf4, ta, ma -; CHECK-ZVBB-NEXT: vandn.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vandn_vx_swapped_nxv2i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e8, mf4, ta, ma +; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %a = xor i8 %x, -1 %head = insertelement poison, i8 %a, i32 0 %splat = shufflevector %head, poison, zeroinitializer @@ -172,11 +172,11 @@ define @vandn_vv_nxv4i8( %x, poison, i8 -1, i32 0 %splat = shufflevector %head, poison, zeroinitializer %a = xor %x, %splat @@ -192,11 +192,11 @@ define @vandn_vv_swapped_nxv4i8( %x, poison, i8 -1, i32 0 %splat = shufflevector %head, poison, zeroinitializer %a = xor %x, %splat @@ -212,11 +212,11 @@ define @vandn_vx_nxv4i8(i8 %x, %y) { ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vandn_vx_nxv4i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e8, mf2, ta, ma -; CHECK-ZVBB-NEXT: vandn.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vandn_vx_nxv4i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e8, mf2, ta, ma +; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %a = xor i8 %x, -1 %head = insertelement poison, i8 %a, i32 0 %splat = shufflevector %head, poison, zeroinitializer @@ -232,11 +232,11 @@ define @vandn_vx_swapped_nxv4i8(i8 %x, %y) { ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vandn_vx_swapped_nxv4i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e8, mf2, ta, ma -; CHECK-ZVBB-NEXT: vandn.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vandn_vx_swapped_nxv4i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e8, mf2, ta, ma +; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %a = xor i8 %x, -1 %head = insertelement poison, i8 %a, i32 0 %splat = shufflevector %head, poison, zeroinitializer @@ -252,11 +252,11 @@ define @vandn_vv_nxv8i8( %x, poison, i8 -1, i32 0 %splat = shufflevector %head, poison, zeroinitializer %a = xor %x, %splat @@ -272,11 +272,11 @@ define @vandn_vv_swapped_nxv8i8( %x, poison, i8 -1, i32 0 %splat = shufflevector %head, poison, zeroinitializer %a = xor %x, %splat @@ -292,11 +292,11 @@ define @vandn_vx_nxv8i8(i8 %x, %y) { ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vandn_vx_nxv8i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e8, m1, ta, ma -; CHECK-ZVBB-NEXT: vandn.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vandn_vx_nxv8i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e8, m1, ta, ma +; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %a = xor i8 %x, -1 %head = insertelement poison, i8 %a, i32 0 %splat = shufflevector %head, poison, zeroinitializer @@ -312,11 +312,11 @@ define @vandn_vx_swapped_nxv8i8(i8 %x, %y) { ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vandn_vx_swapped_nxv8i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e8, m1, ta, ma -; CHECK-ZVBB-NEXT: vandn.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vandn_vx_swapped_nxv8i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e8, m1, ta, ma +; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %a = xor i8 %x, -1 %head = insertelement poison, i8 %a, i32 0 %splat = shufflevector %head, poison, zeroinitializer @@ -332,11 +332,11 @@ define @vandn_vv_nxv16i8( %x, poison, i8 -1, i32 0 %splat = shufflevector %head, poison, zeroinitializer %a = xor %x, %splat @@ -352,11 +352,11 @@ define @vandn_vv_swapped_nxv16i8( %x, poison, i8 -1, i32 0 %splat = shufflevector %head, poison, zeroinitializer %a = xor %x, %splat @@ -372,11 +372,11 @@ define @vandn_vx_nxv16i8(i8 %x, %y) { ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vandn_vx_nxv16i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e8, m2, ta, ma -; CHECK-ZVBB-NEXT: vandn.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vandn_vx_nxv16i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e8, m2, ta, ma +; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %a = xor i8 %x, -1 %head = insertelement poison, i8 %a, i32 0 %splat = shufflevector %head, poison, zeroinitializer @@ -392,11 +392,11 @@ define @vandn_vx_swapped_nxv16i8(i8 %x, %y ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vandn_vx_swapped_nxv16i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e8, m2, ta, ma -; CHECK-ZVBB-NEXT: vandn.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vandn_vx_swapped_nxv16i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e8, m2, ta, ma +; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %a = xor i8 %x, -1 %head = insertelement poison, i8 %a, i32 0 %splat = shufflevector %head, poison, zeroinitializer @@ -412,11 +412,11 @@ define @vandn_vv_nxv32i8( %x, poison, i8 -1, i32 0 %splat = shufflevector %head, poison, zeroinitializer %a = xor %x, %splat @@ -432,11 +432,11 @@ define @vandn_vv_swapped_nxv32i8( %x, poison, i8 -1, i32 0 %splat = shufflevector %head, poison, zeroinitializer %a = xor %x, %splat @@ -452,11 +452,11 @@ define @vandn_vx_nxv32i8(i8 %x, %y) { ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vandn_vx_nxv32i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e8, m4, ta, ma -; CHECK-ZVBB-NEXT: vandn.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vandn_vx_nxv32i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e8, m4, ta, ma +; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %a = xor i8 %x, -1 %head = insertelement poison, i8 %a, i32 0 %splat = shufflevector %head, poison, zeroinitializer @@ -472,11 +472,11 @@ define @vandn_vx_swapped_nxv32i8(i8 %x, %y ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vandn_vx_swapped_nxv32i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e8, m4, ta, ma -; CHECK-ZVBB-NEXT: vandn.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vandn_vx_swapped_nxv32i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e8, m4, ta, ma +; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %a = xor i8 %x, -1 %head = insertelement poison, i8 %a, i32 0 %splat = shufflevector %head, poison, zeroinitializer @@ -492,11 +492,11 @@ define @vandn_vv_nxv64i8( %x, poison, i8 -1, i32 0 %splat = shufflevector %head, poison, zeroinitializer %a = xor %x, %splat @@ -512,11 +512,11 @@ define @vandn_vv_swapped_nxv64i8( %x, poison, i8 -1, i32 0 %splat = shufflevector %head, poison, zeroinitializer %a = xor %x, %splat @@ -532,11 +532,11 @@ define @vandn_vx_nxv64i8(i8 %x, %y) { ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vandn_vx_nxv64i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e8, m8, ta, ma -; CHECK-ZVBB-NEXT: vandn.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vandn_vx_nxv64i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e8, m8, ta, ma +; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %a = xor i8 %x, -1 %head = insertelement poison, i8 %a, i32 0 %splat = shufflevector %head, poison, zeroinitializer @@ -552,11 +552,11 @@ define @vandn_vx_swapped_nxv64i8(i8 %x, %y ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vandn_vx_swapped_nxv64i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e8, m8, ta, ma -; CHECK-ZVBB-NEXT: vandn.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vandn_vx_swapped_nxv64i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e8, m8, ta, ma +; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %a = xor i8 %x, -1 %head = insertelement poison, i8 %a, i32 0 %splat = shufflevector %head, poison, zeroinitializer @@ -572,11 +572,11 @@ define @vandn_vv_nxv1i16( %x, poison, i16 -1, i32 0 %splat = shufflevector %head, poison, zeroinitializer %a = xor %x, %splat @@ -592,11 +592,11 @@ define @vandn_vv_swapped_nxv1i16( %x, poison, i16 -1, i32 0 %splat = shufflevector %head, poison, zeroinitializer %a = xor %x, %splat @@ -612,11 +612,11 @@ define @vandn_vx_nxv1i16(i16 %x, %y) { ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vandn_vx_nxv1i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e16, mf4, ta, ma -; CHECK-ZVBB-NEXT: vandn.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vandn_vx_nxv1i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %a = xor i16 %x, -1 %head = insertelement poison, i16 %a, i32 0 %splat = shufflevector %head, poison, zeroinitializer @@ -632,11 +632,11 @@ define @vandn_vx_swapped_nxv1i16(i16 %x, % ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vandn_vx_swapped_nxv1i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e16, mf4, ta, ma -; CHECK-ZVBB-NEXT: vandn.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vandn_vx_swapped_nxv1i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %a = xor i16 %x, -1 %head = insertelement poison, i16 %a, i32 0 %splat = shufflevector %head, poison, zeroinitializer @@ -652,11 +652,11 @@ define @vandn_vv_nxv2i16( %x, poison, i16 -1, i32 0 %splat = shufflevector %head, poison, zeroinitializer %a = xor %x, %splat @@ -672,11 +672,11 @@ define @vandn_vv_swapped_nxv2i16( %x, poison, i16 -1, i32 0 %splat = shufflevector %head, poison, zeroinitializer %a = xor %x, %splat @@ -692,11 +692,11 @@ define @vandn_vx_nxv2i16(i16 %x, %y) { ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vandn_vx_nxv2i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e16, mf2, ta, ma -; CHECK-ZVBB-NEXT: vandn.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vandn_vx_nxv2i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %a = xor i16 %x, -1 %head = insertelement poison, i16 %a, i32 0 %splat = shufflevector %head, poison, zeroinitializer @@ -712,11 +712,11 @@ define @vandn_vx_swapped_nxv2i16(i16 %x, % ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vandn_vx_swapped_nxv2i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e16, mf2, ta, ma -; CHECK-ZVBB-NEXT: vandn.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vandn_vx_swapped_nxv2i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %a = xor i16 %x, -1 %head = insertelement poison, i16 %a, i32 0 %splat = shufflevector %head, poison, zeroinitializer @@ -732,11 +732,11 @@ define @vandn_vv_nxv4i16( %x, poison, i16 -1, i32 0 %splat = shufflevector %head, poison, zeroinitializer %a = xor %x, %splat @@ -752,11 +752,11 @@ define @vandn_vv_swapped_nxv4i16( %x, poison, i16 -1, i32 0 %splat = shufflevector %head, poison, zeroinitializer %a = xor %x, %splat @@ -772,11 +772,11 @@ define @vandn_vx_nxv4i16(i16 %x, %y) { ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vandn_vx_nxv4i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e16, m1, ta, ma -; CHECK-ZVBB-NEXT: vandn.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vandn_vx_nxv4i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e16, m1, ta, ma +; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %a = xor i16 %x, -1 %head = insertelement poison, i16 %a, i32 0 %splat = shufflevector %head, poison, zeroinitializer @@ -792,11 +792,11 @@ define @vandn_vx_swapped_nxv4i16(i16 %x, % ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vandn_vx_swapped_nxv4i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e16, m1, ta, ma -; CHECK-ZVBB-NEXT: vandn.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vandn_vx_swapped_nxv4i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e16, m1, ta, ma +; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %a = xor i16 %x, -1 %head = insertelement poison, i16 %a, i32 0 %splat = shufflevector %head, poison, zeroinitializer @@ -812,11 +812,11 @@ define @vandn_vv_nxv8i16( %x, poison, i16 -1, i32 0 %splat = shufflevector %head, poison, zeroinitializer %a = xor %x, %splat @@ -832,11 +832,11 @@ define @vandn_vv_swapped_nxv8i16( %x, poison, i16 -1, i32 0 %splat = shufflevector %head, poison, zeroinitializer %a = xor %x, %splat @@ -852,11 +852,11 @@ define @vandn_vx_nxv8i16(i16 %x, %y) { ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vandn_vx_nxv8i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e16, m2, ta, ma -; CHECK-ZVBB-NEXT: vandn.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vandn_vx_nxv8i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %a = xor i16 %x, -1 %head = insertelement poison, i16 %a, i32 0 %splat = shufflevector %head, poison, zeroinitializer @@ -872,11 +872,11 @@ define @vandn_vx_swapped_nxv8i16(i16 %x, % ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vandn_vx_swapped_nxv8i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e16, m2, ta, ma -; CHECK-ZVBB-NEXT: vandn.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vandn_vx_swapped_nxv8i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %a = xor i16 %x, -1 %head = insertelement poison, i16 %a, i32 0 %splat = shufflevector %head, poison, zeroinitializer @@ -892,11 +892,11 @@ define @vandn_vv_nxv16i16( %x, poison, i16 -1, i32 0 %splat = shufflevector %head, poison, zeroinitializer %a = xor %x, %splat @@ -912,11 +912,11 @@ define @vandn_vv_swapped_nxv16i16( %x, poison, i16 -1, i32 0 %splat = shufflevector %head, poison, zeroinitializer %a = xor %x, %splat @@ -932,11 +932,11 @@ define @vandn_vx_nxv16i16(i16 %x, %y) { ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vandn_vx_nxv16i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e16, m4, ta, ma -; CHECK-ZVBB-NEXT: vandn.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vandn_vx_nxv16i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %a = xor i16 %x, -1 %head = insertelement poison, i16 %a, i32 0 %splat = shufflevector %head, poison, zeroinitializer @@ -952,11 +952,11 @@ define @vandn_vx_swapped_nxv16i16(i16 %x, poison, i16 %a, i32 0 %splat = shufflevector %head, poison, zeroinitializer @@ -972,11 +972,11 @@ define @vandn_vv_nxv32i16( %x, poison, i16 -1, i32 0 %splat = shufflevector %head, poison, zeroinitializer %a = xor %x, %splat @@ -992,11 +992,11 @@ define @vandn_vv_swapped_nxv32i16( %x, poison, i16 -1, i32 0 %splat = shufflevector %head, poison, zeroinitializer %a = xor %x, %splat @@ -1012,11 +1012,11 @@ define @vandn_vx_nxv32i16(i16 %x, %y) { ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vandn_vx_nxv32i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e16, m8, ta, ma -; CHECK-ZVBB-NEXT: vandn.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vandn_vx_nxv32i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e16, m8, ta, ma +; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %a = xor i16 %x, -1 %head = insertelement poison, i16 %a, i32 0 %splat = shufflevector %head, poison, zeroinitializer @@ -1032,11 +1032,11 @@ define @vandn_vx_swapped_nxv32i16(i16 %x, poison, i16 %a, i32 0 %splat = shufflevector %head, poison, zeroinitializer @@ -1052,11 +1052,11 @@ define @vandn_vv_nxv1i32( %x, poison, i32 -1, i32 0 %splat = shufflevector %head, poison, zeroinitializer %a = xor %x, %splat @@ -1072,11 +1072,11 @@ define @vandn_vv_swapped_nxv1i32( %x, poison, i32 -1, i32 0 %splat = shufflevector %head, poison, zeroinitializer %a = xor %x, %splat @@ -1092,11 +1092,11 @@ define @vandn_vx_nxv1i32(i32 %x, %y) { ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vandn_vx_nxv1i32: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e32, mf2, ta, ma -; CHECK-ZVBB-NEXT: vandn.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vandn_vx_nxv1i32: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e32, mf2, ta, ma +; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %a = xor i32 %x, -1 %head = insertelement poison, i32 %a, i32 0 %splat = shufflevector %head, poison, zeroinitializer @@ -1112,11 +1112,11 @@ define @vandn_vx_swapped_nxv1i32(i32 %x, % ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vandn_vx_swapped_nxv1i32: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e32, mf2, ta, ma -; CHECK-ZVBB-NEXT: vandn.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vandn_vx_swapped_nxv1i32: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e32, mf2, ta, ma +; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %a = xor i32 %x, -1 %head = insertelement poison, i32 %a, i32 0 %splat = shufflevector %head, poison, zeroinitializer @@ -1132,11 +1132,11 @@ define @vandn_vv_nxv2i32( %x, poison, i32 -1, i32 0 %splat = shufflevector %head, poison, zeroinitializer %a = xor %x, %splat @@ -1152,11 +1152,11 @@ define @vandn_vv_swapped_nxv2i32( %x, poison, i32 -1, i32 0 %splat = shufflevector %head, poison, zeroinitializer %a = xor %x, %splat @@ -1172,11 +1172,11 @@ define @vandn_vx_nxv2i32(i32 %x, %y) { ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vandn_vx_nxv2i32: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e32, m1, ta, ma -; CHECK-ZVBB-NEXT: vandn.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vandn_vx_nxv2i32: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e32, m1, ta, ma +; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %a = xor i32 %x, -1 %head = insertelement poison, i32 %a, i32 0 %splat = shufflevector %head, poison, zeroinitializer @@ -1192,11 +1192,11 @@ define @vandn_vx_swapped_nxv2i32(i32 %x, % ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vandn_vx_swapped_nxv2i32: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e32, m1, ta, ma -; CHECK-ZVBB-NEXT: vandn.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vandn_vx_swapped_nxv2i32: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e32, m1, ta, ma +; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %a = xor i32 %x, -1 %head = insertelement poison, i32 %a, i32 0 %splat = shufflevector %head, poison, zeroinitializer @@ -1212,11 +1212,11 @@ define @vandn_vv_nxv4i32( %x, poison, i32 -1, i32 0 %splat = shufflevector %head, poison, zeroinitializer %a = xor %x, %splat @@ -1232,11 +1232,11 @@ define @vandn_vv_swapped_nxv4i32( %x, poison, i32 -1, i32 0 %splat = shufflevector %head, poison, zeroinitializer %a = xor %x, %splat @@ -1252,11 +1252,11 @@ define @vandn_vx_nxv4i32(i32 %x, %y) { ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vandn_vx_nxv4i32: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e32, m2, ta, ma -; CHECK-ZVBB-NEXT: vandn.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vandn_vx_nxv4i32: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e32, m2, ta, ma +; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %a = xor i32 %x, -1 %head = insertelement poison, i32 %a, i32 0 %splat = shufflevector %head, poison, zeroinitializer @@ -1272,11 +1272,11 @@ define @vandn_vx_swapped_nxv4i32(i32 %x, % ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vandn_vx_swapped_nxv4i32: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e32, m2, ta, ma -; CHECK-ZVBB-NEXT: vandn.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vandn_vx_swapped_nxv4i32: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e32, m2, ta, ma +; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %a = xor i32 %x, -1 %head = insertelement poison, i32 %a, i32 0 %splat = shufflevector %head, poison, zeroinitializer @@ -1292,11 +1292,11 @@ define @vandn_vv_nxv8i32( %x, poison, i32 -1, i32 0 %splat = shufflevector %head, poison, zeroinitializer %a = xor %x, %splat @@ -1312,11 +1312,11 @@ define @vandn_vv_swapped_nxv8i32( %x, poison, i32 -1, i32 0 %splat = shufflevector %head, poison, zeroinitializer %a = xor %x, %splat @@ -1332,11 +1332,11 @@ define @vandn_vx_nxv8i32(i32 %x, %y) { ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vandn_vx_nxv8i32: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e32, m4, ta, ma -; CHECK-ZVBB-NEXT: vandn.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vandn_vx_nxv8i32: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e32, m4, ta, ma +; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %a = xor i32 %x, -1 %head = insertelement poison, i32 %a, i32 0 %splat = shufflevector %head, poison, zeroinitializer @@ -1352,11 +1352,11 @@ define @vandn_vx_swapped_nxv8i32(i32 %x, % ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vandn_vx_swapped_nxv8i32: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e32, m4, ta, ma -; CHECK-ZVBB-NEXT: vandn.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vandn_vx_swapped_nxv8i32: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e32, m4, ta, ma +; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %a = xor i32 %x, -1 %head = insertelement poison, i32 %a, i32 0 %splat = shufflevector %head, poison, zeroinitializer @@ -1372,11 +1372,11 @@ define @vandn_vv_nxv16i32( %x, poison, i32 -1, i32 0 %splat = shufflevector %head, poison, zeroinitializer %a = xor %x, %splat @@ -1392,11 +1392,11 @@ define @vandn_vv_swapped_nxv16i32( %x, poison, i32 -1, i32 0 %splat = shufflevector %head, poison, zeroinitializer %a = xor %x, %splat @@ -1412,11 +1412,11 @@ define @vandn_vx_nxv16i32(i32 %x, %y) { ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vandn_vx_nxv16i32: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e32, m8, ta, ma -; CHECK-ZVBB-NEXT: vandn.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vandn_vx_nxv16i32: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e32, m8, ta, ma +; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %a = xor i32 %x, -1 %head = insertelement poison, i32 %a, i32 0 %splat = shufflevector %head, poison, zeroinitializer @@ -1432,11 +1432,11 @@ define @vandn_vx_swapped_nxv16i32(i32 %x, poison, i32 %a, i32 0 %splat = shufflevector %head, poison, zeroinitializer @@ -1452,11 +1452,11 @@ define @vandn_vv_nxv1i64( %x, poison, i64 -1, i32 0 %splat = shufflevector %head, poison, zeroinitializer %a = xor %x, %splat @@ -1472,11 +1472,11 @@ define @vandn_vv_swapped_nxv1i64( %x, poison, i64 -1, i32 0 %splat = shufflevector %head, poison, zeroinitializer %a = xor %x, %splat @@ -1507,26 +1507,26 @@ define @vandn_vx_nxv1i64(i64 %x, %y) { ; CHECK-RV64-NEXT: vand.vx v8, v8, a0 ; CHECK-RV64-NEXT: ret ; -; CHECK-ZVBB32-LABEL: vandn_vx_nxv1i64: -; CHECK-ZVBB32: # %bb.0: -; CHECK-ZVBB32-NEXT: addi sp, sp, -16 -; CHECK-ZVBB32-NEXT: .cfi_def_cfa_offset 16 -; CHECK-ZVBB32-NEXT: not a0, a0 -; CHECK-ZVBB32-NEXT: not a1, a1 -; CHECK-ZVBB32-NEXT: sw a1, 12(sp) -; CHECK-ZVBB32-NEXT: sw a0, 8(sp) -; CHECK-ZVBB32-NEXT: addi a0, sp, 8 -; CHECK-ZVBB32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; CHECK-ZVBB32-NEXT: vlse64.v v9, (a0), zero -; CHECK-ZVBB32-NEXT: vand.vv v8, v9, v8 -; CHECK-ZVBB32-NEXT: addi sp, sp, 16 -; CHECK-ZVBB32-NEXT: ret -; -; CHECK-ZVBB64-LABEL: vandn_vx_nxv1i64: -; CHECK-ZVBB64: # %bb.0: -; CHECK-ZVBB64-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; CHECK-ZVBB64-NEXT: vandn.vx v8, v8, a0 -; CHECK-ZVBB64-NEXT: ret +; CHECK-ZVKB32-LABEL: vandn_vx_nxv1i64: +; CHECK-ZVKB32: # %bb.0: +; CHECK-ZVKB32-NEXT: addi sp, sp, -16 +; CHECK-ZVKB32-NEXT: .cfi_def_cfa_offset 16 +; CHECK-ZVKB32-NEXT: not a0, a0 +; CHECK-ZVKB32-NEXT: not a1, a1 +; CHECK-ZVKB32-NEXT: sw a1, 12(sp) +; CHECK-ZVKB32-NEXT: sw a0, 8(sp) +; CHECK-ZVKB32-NEXT: addi a0, sp, 8 +; CHECK-ZVKB32-NEXT: vsetvli a1, zero, e64, m1, ta, ma +; CHECK-ZVKB32-NEXT: vlse64.v v9, (a0), zero +; CHECK-ZVKB32-NEXT: vand.vv v8, v9, v8 +; CHECK-ZVKB32-NEXT: addi sp, sp, 16 +; CHECK-ZVKB32-NEXT: ret +; +; CHECK-ZVKB64-LABEL: vandn_vx_nxv1i64: +; CHECK-ZVKB64: # %bb.0: +; CHECK-ZVKB64-NEXT: vsetvli a1, zero, e64, m1, ta, ma +; CHECK-ZVKB64-NEXT: vandn.vx v8, v8, a0 +; CHECK-ZVKB64-NEXT: ret %a = xor i64 %x, -1 %head = insertelement poison, i64 %a, i32 0 %splat = shufflevector %head, poison, zeroinitializer @@ -1557,26 +1557,26 @@ define @vandn_vx_swapped_nxv1i64(i64 %x, % ; CHECK-RV64-NEXT: vand.vx v8, v8, a0 ; CHECK-RV64-NEXT: ret ; -; CHECK-ZVBB32-LABEL: vandn_vx_swapped_nxv1i64: -; CHECK-ZVBB32: # %bb.0: -; CHECK-ZVBB32-NEXT: addi sp, sp, -16 -; CHECK-ZVBB32-NEXT: .cfi_def_cfa_offset 16 -; CHECK-ZVBB32-NEXT: not a0, a0 -; CHECK-ZVBB32-NEXT: not a1, a1 -; CHECK-ZVBB32-NEXT: sw a1, 12(sp) -; CHECK-ZVBB32-NEXT: sw a0, 8(sp) -; CHECK-ZVBB32-NEXT: addi a0, sp, 8 -; CHECK-ZVBB32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; CHECK-ZVBB32-NEXT: vlse64.v v9, (a0), zero -; CHECK-ZVBB32-NEXT: vand.vv v8, v9, v8 -; CHECK-ZVBB32-NEXT: addi sp, sp, 16 -; CHECK-ZVBB32-NEXT: ret -; -; CHECK-ZVBB64-LABEL: vandn_vx_swapped_nxv1i64: -; CHECK-ZVBB64: # %bb.0: -; CHECK-ZVBB64-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; CHECK-ZVBB64-NEXT: vandn.vx v8, v8, a0 -; CHECK-ZVBB64-NEXT: ret +; CHECK-ZVKB32-LABEL: vandn_vx_swapped_nxv1i64: +; CHECK-ZVKB32: # %bb.0: +; CHECK-ZVKB32-NEXT: addi sp, sp, -16 +; CHECK-ZVKB32-NEXT: .cfi_def_cfa_offset 16 +; CHECK-ZVKB32-NEXT: not a0, a0 +; CHECK-ZVKB32-NEXT: not a1, a1 +; CHECK-ZVKB32-NEXT: sw a1, 12(sp) +; CHECK-ZVKB32-NEXT: sw a0, 8(sp) +; CHECK-ZVKB32-NEXT: addi a0, sp, 8 +; CHECK-ZVKB32-NEXT: vsetvli a1, zero, e64, m1, ta, ma +; CHECK-ZVKB32-NEXT: vlse64.v v9, (a0), zero +; CHECK-ZVKB32-NEXT: vand.vv v8, v9, v8 +; CHECK-ZVKB32-NEXT: addi sp, sp, 16 +; CHECK-ZVKB32-NEXT: ret +; +; CHECK-ZVKB64-LABEL: vandn_vx_swapped_nxv1i64: +; CHECK-ZVKB64: # %bb.0: +; CHECK-ZVKB64-NEXT: vsetvli a1, zero, e64, m1, ta, ma +; CHECK-ZVKB64-NEXT: vandn.vx v8, v8, a0 +; CHECK-ZVKB64-NEXT: ret %a = xor i64 %x, -1 %head = insertelement poison, i64 %a, i32 0 %splat = shufflevector %head, poison, zeroinitializer @@ -1592,11 +1592,11 @@ define @vandn_vv_nxv2i64( %x, poison, i64 -1, i32 0 %splat = shufflevector %head, poison, zeroinitializer %a = xor %x, %splat @@ -1612,11 +1612,11 @@ define @vandn_vv_swapped_nxv2i64( %x, poison, i64 -1, i32 0 %splat = shufflevector %head, poison, zeroinitializer %a = xor %x, %splat @@ -1647,26 +1647,26 @@ define @vandn_vx_nxv2i64(i64 %x, %y) { ; CHECK-RV64-NEXT: vand.vx v8, v8, a0 ; CHECK-RV64-NEXT: ret ; -; CHECK-ZVBB32-LABEL: vandn_vx_nxv2i64: -; CHECK-ZVBB32: # %bb.0: -; CHECK-ZVBB32-NEXT: addi sp, sp, -16 -; CHECK-ZVBB32-NEXT: .cfi_def_cfa_offset 16 -; CHECK-ZVBB32-NEXT: not a0, a0 -; CHECK-ZVBB32-NEXT: not a1, a1 -; CHECK-ZVBB32-NEXT: sw a1, 12(sp) -; CHECK-ZVBB32-NEXT: sw a0, 8(sp) -; CHECK-ZVBB32-NEXT: addi a0, sp, 8 -; CHECK-ZVBB32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; CHECK-ZVBB32-NEXT: vlse64.v v10, (a0), zero -; CHECK-ZVBB32-NEXT: vand.vv v8, v10, v8 -; CHECK-ZVBB32-NEXT: addi sp, sp, 16 -; CHECK-ZVBB32-NEXT: ret -; -; CHECK-ZVBB64-LABEL: vandn_vx_nxv2i64: -; CHECK-ZVBB64: # %bb.0: -; CHECK-ZVBB64-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; CHECK-ZVBB64-NEXT: vandn.vx v8, v8, a0 -; CHECK-ZVBB64-NEXT: ret +; CHECK-ZVKB32-LABEL: vandn_vx_nxv2i64: +; CHECK-ZVKB32: # %bb.0: +; CHECK-ZVKB32-NEXT: addi sp, sp, -16 +; CHECK-ZVKB32-NEXT: .cfi_def_cfa_offset 16 +; CHECK-ZVKB32-NEXT: not a0, a0 +; CHECK-ZVKB32-NEXT: not a1, a1 +; CHECK-ZVKB32-NEXT: sw a1, 12(sp) +; CHECK-ZVKB32-NEXT: sw a0, 8(sp) +; CHECK-ZVKB32-NEXT: addi a0, sp, 8 +; CHECK-ZVKB32-NEXT: vsetvli a1, zero, e64, m2, ta, ma +; CHECK-ZVKB32-NEXT: vlse64.v v10, (a0), zero +; CHECK-ZVKB32-NEXT: vand.vv v8, v10, v8 +; CHECK-ZVKB32-NEXT: addi sp, sp, 16 +; CHECK-ZVKB32-NEXT: ret +; +; CHECK-ZVKB64-LABEL: vandn_vx_nxv2i64: +; CHECK-ZVKB64: # %bb.0: +; CHECK-ZVKB64-NEXT: vsetvli a1, zero, e64, m2, ta, ma +; CHECK-ZVKB64-NEXT: vandn.vx v8, v8, a0 +; CHECK-ZVKB64-NEXT: ret %a = xor i64 %x, -1 %head = insertelement poison, i64 %a, i32 0 %splat = shufflevector %head, poison, zeroinitializer @@ -1697,26 +1697,26 @@ define @vandn_vx_swapped_nxv2i64(i64 %x, % ; CHECK-RV64-NEXT: vand.vx v8, v8, a0 ; CHECK-RV64-NEXT: ret ; -; CHECK-ZVBB32-LABEL: vandn_vx_swapped_nxv2i64: -; CHECK-ZVBB32: # %bb.0: -; CHECK-ZVBB32-NEXT: addi sp, sp, -16 -; CHECK-ZVBB32-NEXT: .cfi_def_cfa_offset 16 -; CHECK-ZVBB32-NEXT: not a0, a0 -; CHECK-ZVBB32-NEXT: not a1, a1 -; CHECK-ZVBB32-NEXT: sw a1, 12(sp) -; CHECK-ZVBB32-NEXT: sw a0, 8(sp) -; CHECK-ZVBB32-NEXT: addi a0, sp, 8 -; CHECK-ZVBB32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; CHECK-ZVBB32-NEXT: vlse64.v v10, (a0), zero -; CHECK-ZVBB32-NEXT: vand.vv v8, v10, v8 -; CHECK-ZVBB32-NEXT: addi sp, sp, 16 -; CHECK-ZVBB32-NEXT: ret -; -; CHECK-ZVBB64-LABEL: vandn_vx_swapped_nxv2i64: -; CHECK-ZVBB64: # %bb.0: -; CHECK-ZVBB64-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; CHECK-ZVBB64-NEXT: vandn.vx v8, v8, a0 -; CHECK-ZVBB64-NEXT: ret +; CHECK-ZVKB32-LABEL: vandn_vx_swapped_nxv2i64: +; CHECK-ZVKB32: # %bb.0: +; CHECK-ZVKB32-NEXT: addi sp, sp, -16 +; CHECK-ZVKB32-NEXT: .cfi_def_cfa_offset 16 +; CHECK-ZVKB32-NEXT: not a0, a0 +; CHECK-ZVKB32-NEXT: not a1, a1 +; CHECK-ZVKB32-NEXT: sw a1, 12(sp) +; CHECK-ZVKB32-NEXT: sw a0, 8(sp) +; CHECK-ZVKB32-NEXT: addi a0, sp, 8 +; CHECK-ZVKB32-NEXT: vsetvli a1, zero, e64, m2, ta, ma +; CHECK-ZVKB32-NEXT: vlse64.v v10, (a0), zero +; CHECK-ZVKB32-NEXT: vand.vv v8, v10, v8 +; CHECK-ZVKB32-NEXT: addi sp, sp, 16 +; CHECK-ZVKB32-NEXT: ret +; +; CHECK-ZVKB64-LABEL: vandn_vx_swapped_nxv2i64: +; CHECK-ZVKB64: # %bb.0: +; CHECK-ZVKB64-NEXT: vsetvli a1, zero, e64, m2, ta, ma +; CHECK-ZVKB64-NEXT: vandn.vx v8, v8, a0 +; CHECK-ZVKB64-NEXT: ret %a = xor i64 %x, -1 %head = insertelement poison, i64 %a, i32 0 %splat = shufflevector %head, poison, zeroinitializer @@ -1732,11 +1732,11 @@ define @vandn_vv_nxv4i64( %x, poison, i64 -1, i32 0 %splat = shufflevector %head, poison, zeroinitializer %a = xor %x, %splat @@ -1752,11 +1752,11 @@ define @vandn_vv_swapped_nxv4i64( %x, poison, i64 -1, i32 0 %splat = shufflevector %head, poison, zeroinitializer %a = xor %x, %splat @@ -1787,26 +1787,26 @@ define @vandn_vx_nxv4i64(i64 %x, %y) { ; CHECK-RV64-NEXT: vand.vx v8, v8, a0 ; CHECK-RV64-NEXT: ret ; -; CHECK-ZVBB32-LABEL: vandn_vx_nxv4i64: -; CHECK-ZVBB32: # %bb.0: -; CHECK-ZVBB32-NEXT: addi sp, sp, -16 -; CHECK-ZVBB32-NEXT: .cfi_def_cfa_offset 16 -; CHECK-ZVBB32-NEXT: not a0, a0 -; CHECK-ZVBB32-NEXT: not a1, a1 -; CHECK-ZVBB32-NEXT: sw a1, 12(sp) -; CHECK-ZVBB32-NEXT: sw a0, 8(sp) -; CHECK-ZVBB32-NEXT: addi a0, sp, 8 -; CHECK-ZVBB32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; CHECK-ZVBB32-NEXT: vlse64.v v12, (a0), zero -; CHECK-ZVBB32-NEXT: vand.vv v8, v12, v8 -; CHECK-ZVBB32-NEXT: addi sp, sp, 16 -; CHECK-ZVBB32-NEXT: ret -; -; CHECK-ZVBB64-LABEL: vandn_vx_nxv4i64: -; CHECK-ZVBB64: # %bb.0: -; CHECK-ZVBB64-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; CHECK-ZVBB64-NEXT: vandn.vx v8, v8, a0 -; CHECK-ZVBB64-NEXT: ret +; CHECK-ZVKB32-LABEL: vandn_vx_nxv4i64: +; CHECK-ZVKB32: # %bb.0: +; CHECK-ZVKB32-NEXT: addi sp, sp, -16 +; CHECK-ZVKB32-NEXT: .cfi_def_cfa_offset 16 +; CHECK-ZVKB32-NEXT: not a0, a0 +; CHECK-ZVKB32-NEXT: not a1, a1 +; CHECK-ZVKB32-NEXT: sw a1, 12(sp) +; CHECK-ZVKB32-NEXT: sw a0, 8(sp) +; CHECK-ZVKB32-NEXT: addi a0, sp, 8 +; CHECK-ZVKB32-NEXT: vsetvli a1, zero, e64, m4, ta, ma +; CHECK-ZVKB32-NEXT: vlse64.v v12, (a0), zero +; CHECK-ZVKB32-NEXT: vand.vv v8, v12, v8 +; CHECK-ZVKB32-NEXT: addi sp, sp, 16 +; CHECK-ZVKB32-NEXT: ret +; +; CHECK-ZVKB64-LABEL: vandn_vx_nxv4i64: +; CHECK-ZVKB64: # %bb.0: +; CHECK-ZVKB64-NEXT: vsetvli a1, zero, e64, m4, ta, ma +; CHECK-ZVKB64-NEXT: vandn.vx v8, v8, a0 +; CHECK-ZVKB64-NEXT: ret %a = xor i64 %x, -1 %head = insertelement poison, i64 %a, i32 0 %splat = shufflevector %head, poison, zeroinitializer @@ -1837,26 +1837,26 @@ define @vandn_vx_swapped_nxv4i64(i64 %x, % ; CHECK-RV64-NEXT: vand.vx v8, v8, a0 ; CHECK-RV64-NEXT: ret ; -; CHECK-ZVBB32-LABEL: vandn_vx_swapped_nxv4i64: -; CHECK-ZVBB32: # %bb.0: -; CHECK-ZVBB32-NEXT: addi sp, sp, -16 -; CHECK-ZVBB32-NEXT: .cfi_def_cfa_offset 16 -; CHECK-ZVBB32-NEXT: not a0, a0 -; CHECK-ZVBB32-NEXT: not a1, a1 -; CHECK-ZVBB32-NEXT: sw a1, 12(sp) -; CHECK-ZVBB32-NEXT: sw a0, 8(sp) -; CHECK-ZVBB32-NEXT: addi a0, sp, 8 -; CHECK-ZVBB32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; CHECK-ZVBB32-NEXT: vlse64.v v12, (a0), zero -; CHECK-ZVBB32-NEXT: vand.vv v8, v12, v8 -; CHECK-ZVBB32-NEXT: addi sp, sp, 16 -; CHECK-ZVBB32-NEXT: ret -; -; CHECK-ZVBB64-LABEL: vandn_vx_swapped_nxv4i64: -; CHECK-ZVBB64: # %bb.0: -; CHECK-ZVBB64-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; CHECK-ZVBB64-NEXT: vandn.vx v8, v8, a0 -; CHECK-ZVBB64-NEXT: ret +; CHECK-ZVKB32-LABEL: vandn_vx_swapped_nxv4i64: +; CHECK-ZVKB32: # %bb.0: +; CHECK-ZVKB32-NEXT: addi sp, sp, -16 +; CHECK-ZVKB32-NEXT: .cfi_def_cfa_offset 16 +; CHECK-ZVKB32-NEXT: not a0, a0 +; CHECK-ZVKB32-NEXT: not a1, a1 +; CHECK-ZVKB32-NEXT: sw a1, 12(sp) +; CHECK-ZVKB32-NEXT: sw a0, 8(sp) +; CHECK-ZVKB32-NEXT: addi a0, sp, 8 +; CHECK-ZVKB32-NEXT: vsetvli a1, zero, e64, m4, ta, ma +; CHECK-ZVKB32-NEXT: vlse64.v v12, (a0), zero +; CHECK-ZVKB32-NEXT: vand.vv v8, v12, v8 +; CHECK-ZVKB32-NEXT: addi sp, sp, 16 +; CHECK-ZVKB32-NEXT: ret +; +; CHECK-ZVKB64-LABEL: vandn_vx_swapped_nxv4i64: +; CHECK-ZVKB64: # %bb.0: +; CHECK-ZVKB64-NEXT: vsetvli a1, zero, e64, m4, ta, ma +; CHECK-ZVKB64-NEXT: vandn.vx v8, v8, a0 +; CHECK-ZVKB64-NEXT: ret %a = xor i64 %x, -1 %head = insertelement poison, i64 %a, i32 0 %splat = shufflevector %head, poison, zeroinitializer @@ -1872,11 +1872,11 @@ define @vandn_vv_nxv8i64( %x, poison, i64 -1, i32 0 %splat = shufflevector %head, poison, zeroinitializer %a = xor %x, %splat @@ -1892,11 +1892,11 @@ define @vandn_vv_swapped_nxv8i64( %x, poison, i64 -1, i32 0 %splat = shufflevector %head, poison, zeroinitializer %a = xor %x, %splat @@ -1927,26 +1927,26 @@ define @vandn_vx_nxv8i64(i64 %x, %y) { ; CHECK-RV64-NEXT: vand.vx v8, v8, a0 ; CHECK-RV64-NEXT: ret ; -; CHECK-ZVBB32-LABEL: vandn_vx_nxv8i64: -; CHECK-ZVBB32: # %bb.0: -; CHECK-ZVBB32-NEXT: addi sp, sp, -16 -; CHECK-ZVBB32-NEXT: .cfi_def_cfa_offset 16 -; CHECK-ZVBB32-NEXT: not a0, a0 -; CHECK-ZVBB32-NEXT: not a1, a1 -; CHECK-ZVBB32-NEXT: sw a1, 12(sp) -; CHECK-ZVBB32-NEXT: sw a0, 8(sp) -; CHECK-ZVBB32-NEXT: addi a0, sp, 8 -; CHECK-ZVBB32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; CHECK-ZVBB32-NEXT: vlse64.v v16, (a0), zero -; CHECK-ZVBB32-NEXT: vand.vv v8, v16, v8 -; CHECK-ZVBB32-NEXT: addi sp, sp, 16 -; CHECK-ZVBB32-NEXT: ret -; -; CHECK-ZVBB64-LABEL: vandn_vx_nxv8i64: -; CHECK-ZVBB64: # %bb.0: -; CHECK-ZVBB64-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; CHECK-ZVBB64-NEXT: vandn.vx v8, v8, a0 -; CHECK-ZVBB64-NEXT: ret +; CHECK-ZVKB32-LABEL: vandn_vx_nxv8i64: +; CHECK-ZVKB32: # %bb.0: +; CHECK-ZVKB32-NEXT: addi sp, sp, -16 +; CHECK-ZVKB32-NEXT: .cfi_def_cfa_offset 16 +; CHECK-ZVKB32-NEXT: not a0, a0 +; CHECK-ZVKB32-NEXT: not a1, a1 +; CHECK-ZVKB32-NEXT: sw a1, 12(sp) +; CHECK-ZVKB32-NEXT: sw a0, 8(sp) +; CHECK-ZVKB32-NEXT: addi a0, sp, 8 +; CHECK-ZVKB32-NEXT: vsetvli a1, zero, e64, m8, ta, ma +; CHECK-ZVKB32-NEXT: vlse64.v v16, (a0), zero +; CHECK-ZVKB32-NEXT: vand.vv v8, v16, v8 +; CHECK-ZVKB32-NEXT: addi sp, sp, 16 +; CHECK-ZVKB32-NEXT: ret +; +; CHECK-ZVKB64-LABEL: vandn_vx_nxv8i64: +; CHECK-ZVKB64: # %bb.0: +; CHECK-ZVKB64-NEXT: vsetvli a1, zero, e64, m8, ta, ma +; CHECK-ZVKB64-NEXT: vandn.vx v8, v8, a0 +; CHECK-ZVKB64-NEXT: ret %a = xor i64 %x, -1 %head = insertelement poison, i64 %a, i32 0 %splat = shufflevector %head, poison, zeroinitializer @@ -1977,26 +1977,26 @@ define @vandn_vx_swapped_nxv8i64(i64 %x, % ; CHECK-RV64-NEXT: vand.vx v8, v8, a0 ; CHECK-RV64-NEXT: ret ; -; CHECK-ZVBB32-LABEL: vandn_vx_swapped_nxv8i64: -; CHECK-ZVBB32: # %bb.0: -; CHECK-ZVBB32-NEXT: addi sp, sp, -16 -; CHECK-ZVBB32-NEXT: .cfi_def_cfa_offset 16 -; CHECK-ZVBB32-NEXT: not a0, a0 -; CHECK-ZVBB32-NEXT: not a1, a1 -; CHECK-ZVBB32-NEXT: sw a1, 12(sp) -; CHECK-ZVBB32-NEXT: sw a0, 8(sp) -; CHECK-ZVBB32-NEXT: addi a0, sp, 8 -; CHECK-ZVBB32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; CHECK-ZVBB32-NEXT: vlse64.v v16, (a0), zero -; CHECK-ZVBB32-NEXT: vand.vv v8, v16, v8 -; CHECK-ZVBB32-NEXT: addi sp, sp, 16 -; CHECK-ZVBB32-NEXT: ret -; -; CHECK-ZVBB64-LABEL: vandn_vx_swapped_nxv8i64: -; CHECK-ZVBB64: # %bb.0: -; CHECK-ZVBB64-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; CHECK-ZVBB64-NEXT: vandn.vx v8, v8, a0 -; CHECK-ZVBB64-NEXT: ret +; CHECK-ZVKB32-LABEL: vandn_vx_swapped_nxv8i64: +; CHECK-ZVKB32: # %bb.0: +; CHECK-ZVKB32-NEXT: addi sp, sp, -16 +; CHECK-ZVKB32-NEXT: .cfi_def_cfa_offset 16 +; CHECK-ZVKB32-NEXT: not a0, a0 +; CHECK-ZVKB32-NEXT: not a1, a1 +; CHECK-ZVKB32-NEXT: sw a1, 12(sp) +; CHECK-ZVKB32-NEXT: sw a0, 8(sp) +; CHECK-ZVKB32-NEXT: addi a0, sp, 8 +; CHECK-ZVKB32-NEXT: vsetvli a1, zero, e64, m8, ta, ma +; CHECK-ZVKB32-NEXT: vlse64.v v16, (a0), zero +; CHECK-ZVKB32-NEXT: vand.vv v8, v16, v8 +; CHECK-ZVKB32-NEXT: addi sp, sp, 16 +; CHECK-ZVKB32-NEXT: ret +; +; CHECK-ZVKB64-LABEL: vandn_vx_swapped_nxv8i64: +; CHECK-ZVKB64: # %bb.0: +; CHECK-ZVKB64-NEXT: vsetvli a1, zero, e64, m8, ta, ma +; CHECK-ZVKB64-NEXT: vandn.vx v8, v8, a0 +; CHECK-ZVKB64-NEXT: ret %a = xor i64 %x, -1 %head = insertelement poison, i64 %a, i32 0 %splat = shufflevector %head, poison, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vandn-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vandn-vp.ll index d0e23f236b2f7..c1e85802d3732 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vandn-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vandn-vp.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 ; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV32 ; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV64 -; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB,CHECK-ZVBB32 -; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB,CHECK-ZVBB64 +; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB,CHECK-ZVKB32 +; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB,CHECK-ZVKB64 declare @llvm.vp.and.nxv1i8(, , , i32) declare @llvm.vp.xor.nxv1i8(, , , i32) @@ -15,11 +15,11 @@ define @vandn_vv_vp_nxv1i8( %a, @llvm.vp.xor.nxv1i8( %a, shufflevector( insertelement( poison, i8 -1, i32 0), poison, zeroinitializer), %mask, i32 %evl) %x = call @llvm.vp.and.nxv1i8( %not.a, %b, %mask, i32 %evl) ret %x @@ -33,11 +33,11 @@ define @vandn_vv_vp_swapped_nxv1i8( %a, @llvm.vp.xor.nxv1i8( %a, shufflevector( insertelement( poison, i8 -1, i32 0), poison, zeroinitializer), %mask, i32 %evl) %x = call @llvm.vp.and.nxv1i8( %b, %not.a, %mask, i32 %evl) ret %x @@ -51,11 +51,11 @@ define @vandn_vx_vp_nxv1i8(i8 %a, %b, poison, i8 %not.a, i32 0 %splat.not.a = shufflevector %head.not.a, poison, zeroinitializer @@ -74,11 +74,11 @@ define @vandn_vv_vp_nxv2i8( %a, @llvm.vp.xor.nxv2i8( %a, shufflevector( insertelement( poison, i8 -1, i32 0), poison, zeroinitializer), %mask, i32 %evl) %x = call @llvm.vp.and.nxv2i8( %not.a, %b, %mask, i32 %evl) ret %x @@ -92,11 +92,11 @@ define @vandn_vv_vp_swapped_nxv2i8( %a, @llvm.vp.xor.nxv2i8( %a, shufflevector( insertelement( poison, i8 -1, i32 0), poison, zeroinitializer), %mask, i32 %evl) %x = call @llvm.vp.and.nxv2i8( %b, %not.a, %mask, i32 %evl) ret %x @@ -110,11 +110,11 @@ define @vandn_vx_vp_nxv2i8(i8 %a, %b, poison, i8 %not.a, i32 0 %splat.not.a = shufflevector %head.not.a, poison, zeroinitializer @@ -133,11 +133,11 @@ define @vandn_vv_vp_nxv4i8( %a, @llvm.vp.xor.nxv4i8( %a, shufflevector( insertelement( poison, i8 -1, i32 0), poison, zeroinitializer), %mask, i32 %evl) %x = call @llvm.vp.and.nxv4i8( %not.a, %b, %mask, i32 %evl) ret %x @@ -151,11 +151,11 @@ define @vandn_vv_vp_swapped_nxv4i8( %a, @llvm.vp.xor.nxv4i8( %a, shufflevector( insertelement( poison, i8 -1, i32 0), poison, zeroinitializer), %mask, i32 %evl) %x = call @llvm.vp.and.nxv4i8( %b, %not.a, %mask, i32 %evl) ret %x @@ -169,11 +169,11 @@ define @vandn_vx_vp_nxv4i8(i8 %a, %b, poison, i8 %not.a, i32 0 %splat.not.a = shufflevector %head.not.a, poison, zeroinitializer @@ -192,11 +192,11 @@ define @vandn_vv_vp_nxv8i8( %a, @llvm.vp.xor.nxv8i8( %a, shufflevector( insertelement( poison, i8 -1, i32 0), poison, zeroinitializer), %mask, i32 %evl) %x = call @llvm.vp.and.nxv8i8( %not.a, %b, %mask, i32 %evl) ret %x @@ -210,11 +210,11 @@ define @vandn_vv_vp_swapped_nxv8i8( %a, @llvm.vp.xor.nxv8i8( %a, shufflevector( insertelement( poison, i8 -1, i32 0), poison, zeroinitializer), %mask, i32 %evl) %x = call @llvm.vp.and.nxv8i8( %b, %not.a, %mask, i32 %evl) ret %x @@ -228,11 +228,11 @@ define @vandn_vx_vp_nxv8i8(i8 %a, %b, poison, i8 %not.a, i32 0 %splat.not.a = shufflevector %head.not.a, poison, zeroinitializer @@ -251,11 +251,11 @@ define @vandn_vv_vp_nxv16i8( %a, @llvm.vp.xor.nxv16i8( %a, shufflevector( insertelement( poison, i8 -1, i32 0), poison, zeroinitializer), %mask, i32 %evl) %x = call @llvm.vp.and.nxv16i8( %not.a, %b, %mask, i32 %evl) ret %x @@ -269,11 +269,11 @@ define @vandn_vv_vp_swapped_nxv16i8( %a, @llvm.vp.xor.nxv16i8( %a, shufflevector( insertelement( poison, i8 -1, i32 0), poison, zeroinitializer), %mask, i32 %evl) %x = call @llvm.vp.and.nxv16i8( %b, %not.a, %mask, i32 %evl) ret %x @@ -287,11 +287,11 @@ define @vandn_vx_vp_nxv16i8(i8 %a, %b, poison, i8 %not.a, i32 0 %splat.not.a = shufflevector %head.not.a, poison, zeroinitializer @@ -310,11 +310,11 @@ define @vandn_vv_vp_nxv32i8( %a, @llvm.vp.xor.nxv32i8( %a, shufflevector( insertelement( poison, i8 -1, i32 0), poison, zeroinitializer), %mask, i32 %evl) %x = call @llvm.vp.and.nxv32i8( %not.a, %b, %mask, i32 %evl) ret %x @@ -328,11 +328,11 @@ define @vandn_vv_vp_swapped_nxv32i8( %a, @llvm.vp.xor.nxv32i8( %a, shufflevector( insertelement( poison, i8 -1, i32 0), poison, zeroinitializer), %mask, i32 %evl) %x = call @llvm.vp.and.nxv32i8( %b, %not.a, %mask, i32 %evl) ret %x @@ -346,11 +346,11 @@ define @vandn_vx_vp_nxv32i8(i8 %a, %b, poison, i8 %not.a, i32 0 %splat.not.a = shufflevector %head.not.a, poison, zeroinitializer @@ -369,11 +369,11 @@ define @vandn_vv_vp_nxv64i8( %a, @llvm.vp.xor.nxv64i8( %a, shufflevector( insertelement( poison, i8 -1, i32 0), poison, zeroinitializer), %mask, i32 %evl) %x = call @llvm.vp.and.nxv64i8( %not.a, %b, %mask, i32 %evl) ret %x @@ -387,11 +387,11 @@ define @vandn_vv_vp_swapped_nxv64i8( %a, @llvm.vp.xor.nxv64i8( %a, shufflevector( insertelement( poison, i8 -1, i32 0), poison, zeroinitializer), %mask, i32 %evl) %x = call @llvm.vp.and.nxv64i8( %b, %not.a, %mask, i32 %evl) ret %x @@ -405,11 +405,11 @@ define @vandn_vx_vp_nxv64i8(i8 %a, %b, poison, i8 %not.a, i32 0 %splat.not.a = shufflevector %head.not.a, poison, zeroinitializer @@ -428,11 +428,11 @@ define @vandn_vv_vp_nxv1i16( %a, @llvm.vp.xor.nxv1i16( %a, shufflevector( insertelement( poison, i16 -1, i32 0), poison, zeroinitializer), %mask, i32 %evl) %x = call @llvm.vp.and.nxv1i16( %not.a, %b, %mask, i32 %evl) ret %x @@ -446,11 +446,11 @@ define @vandn_vv_vp_swapped_nxv1i16( %a, @llvm.vp.xor.nxv1i16( %a, shufflevector( insertelement( poison, i16 -1, i32 0), poison, zeroinitializer), %mask, i32 %evl) %x = call @llvm.vp.and.nxv1i16( %b, %not.a, %mask, i32 %evl) ret %x @@ -464,11 +464,11 @@ define @vandn_vx_vp_nxv1i16(i16 %a, %b, poison, i16 %not.a, i32 0 %splat.not.a = shufflevector %head.not.a, poison, zeroinitializer @@ -487,11 +487,11 @@ define @vandn_vv_vp_nxv2i16( %a, @llvm.vp.xor.nxv2i16( %a, shufflevector( insertelement( poison, i16 -1, i32 0), poison, zeroinitializer), %mask, i32 %evl) %x = call @llvm.vp.and.nxv2i16( %not.a, %b, %mask, i32 %evl) ret %x @@ -505,11 +505,11 @@ define @vandn_vv_vp_swapped_nxv2i16( %a, @llvm.vp.xor.nxv2i16( %a, shufflevector( insertelement( poison, i16 -1, i32 0), poison, zeroinitializer), %mask, i32 %evl) %x = call @llvm.vp.and.nxv2i16( %b, %not.a, %mask, i32 %evl) ret %x @@ -523,11 +523,11 @@ define @vandn_vx_vp_nxv2i16(i16 %a, %b, poison, i16 %not.a, i32 0 %splat.not.a = shufflevector %head.not.a, poison, zeroinitializer @@ -546,11 +546,11 @@ define @vandn_vv_vp_nxv4i16( %a, @llvm.vp.xor.nxv4i16( %a, shufflevector( insertelement( poison, i16 -1, i32 0), poison, zeroinitializer), %mask, i32 %evl) %x = call @llvm.vp.and.nxv4i16( %not.a, %b, %mask, i32 %evl) ret %x @@ -564,11 +564,11 @@ define @vandn_vv_vp_swapped_nxv4i16( %a, @llvm.vp.xor.nxv4i16( %a, shufflevector( insertelement( poison, i16 -1, i32 0), poison, zeroinitializer), %mask, i32 %evl) %x = call @llvm.vp.and.nxv4i16( %b, %not.a, %mask, i32 %evl) ret %x @@ -582,11 +582,11 @@ define @vandn_vx_vp_nxv4i16(i16 %a, %b, poison, i16 %not.a, i32 0 %splat.not.a = shufflevector %head.not.a, poison, zeroinitializer @@ -605,11 +605,11 @@ define @vandn_vv_vp_nxv8i16( %a, @llvm.vp.xor.nxv8i16( %a, shufflevector( insertelement( poison, i16 -1, i32 0), poison, zeroinitializer), %mask, i32 %evl) %x = call @llvm.vp.and.nxv8i16( %not.a, %b, %mask, i32 %evl) ret %x @@ -623,11 +623,11 @@ define @vandn_vv_vp_swapped_nxv8i16( %a, @llvm.vp.xor.nxv8i16( %a, shufflevector( insertelement( poison, i16 -1, i32 0), poison, zeroinitializer), %mask, i32 %evl) %x = call @llvm.vp.and.nxv8i16( %b, %not.a, %mask, i32 %evl) ret %x @@ -641,11 +641,11 @@ define @vandn_vx_vp_nxv8i16(i16 %a, %b, poison, i16 %not.a, i32 0 %splat.not.a = shufflevector %head.not.a, poison, zeroinitializer @@ -664,11 +664,11 @@ define @vandn_vv_vp_nxv16i16( %a, @llvm.vp.xor.nxv16i16( %a, shufflevector( insertelement( poison, i16 -1, i32 0), poison, zeroinitializer), %mask, i32 %evl) %x = call @llvm.vp.and.nxv16i16( %not.a, %b, %mask, i32 %evl) ret %x @@ -682,11 +682,11 @@ define @vandn_vv_vp_swapped_nxv16i16( %a, ; CHECK-NEXT: vand.vv v8, v12, v8, v0.t ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vandn_vv_vp_swapped_nxv16i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-ZVBB-NEXT: vandn.vv v8, v12, v8, v0.t -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vandn_vv_vp_swapped_nxv16i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli zero, a0, e16, m4, ta, ma +; CHECK-ZVKB-NEXT: vandn.vv v8, v12, v8, v0.t +; CHECK-ZVKB-NEXT: ret %not.a = call @llvm.vp.xor.nxv16i16( %a, shufflevector( insertelement( poison, i16 -1, i32 0), poison, zeroinitializer), %mask, i32 %evl) %x = call @llvm.vp.and.nxv16i16( %b, %not.a, %mask, i32 %evl) ret %x @@ -700,11 +700,11 @@ define @vandn_vx_vp_nxv16i16(i16 %a, %b, ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vandn_vx_vp_nxv16i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli zero, a1, e16, m4, ta, ma -; CHECK-ZVBB-NEXT: vandn.vx v8, v8, a0, v0.t -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vandn_vx_vp_nxv16i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli zero, a1, e16, m4, ta, ma +; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a0, v0.t +; CHECK-ZVKB-NEXT: ret %not.a = xor i16 %a, -1 %head.not.a = insertelement poison, i16 %not.a, i32 0 %splat.not.a = shufflevector %head.not.a, poison, zeroinitializer @@ -723,11 +723,11 @@ define @vandn_vv_vp_nxv32i16( %a, @llvm.vp.xor.nxv32i16( %a, shufflevector( insertelement( poison, i16 -1, i32 0), poison, zeroinitializer), %mask, i32 %evl) %x = call @llvm.vp.and.nxv32i16( %not.a, %b, %mask, i32 %evl) ret %x @@ -741,11 +741,11 @@ define @vandn_vv_vp_swapped_nxv32i16( %a, ; CHECK-NEXT: vand.vv v8, v16, v8, v0.t ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vandn_vv_vp_swapped_nxv32i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m8, ta, ma -; CHECK-ZVBB-NEXT: vandn.vv v8, v16, v8, v0.t -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vandn_vv_vp_swapped_nxv32i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli zero, a0, e16, m8, ta, ma +; CHECK-ZVKB-NEXT: vandn.vv v8, v16, v8, v0.t +; CHECK-ZVKB-NEXT: ret %not.a = call @llvm.vp.xor.nxv32i16( %a, shufflevector( insertelement( poison, i16 -1, i32 0), poison, zeroinitializer), %mask, i32 %evl) %x = call @llvm.vp.and.nxv32i16( %b, %not.a, %mask, i32 %evl) ret %x @@ -759,11 +759,11 @@ define @vandn_vx_vp_nxv32i16(i16 %a, %b, ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vandn_vx_vp_nxv32i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli zero, a1, e16, m8, ta, ma -; CHECK-ZVBB-NEXT: vandn.vx v8, v8, a0, v0.t -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vandn_vx_vp_nxv32i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli zero, a1, e16, m8, ta, ma +; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a0, v0.t +; CHECK-ZVKB-NEXT: ret %not.a = xor i16 %a, -1 %head.not.a = insertelement poison, i16 %not.a, i32 0 %splat.not.a = shufflevector %head.not.a, poison, zeroinitializer @@ -782,11 +782,11 @@ define @vandn_vv_vp_nxv1i32( %a, @llvm.vp.xor.nxv1i32( %a, shufflevector( insertelement( poison, i32 -1, i32 0), poison, zeroinitializer), %mask, i32 %evl) %x = call @llvm.vp.and.nxv1i32( %not.a, %b, %mask, i32 %evl) ret %x @@ -800,11 +800,11 @@ define @vandn_vv_vp_swapped_nxv1i32( %a, @llvm.vp.xor.nxv1i32( %a, shufflevector( insertelement( poison, i32 -1, i32 0), poison, zeroinitializer), %mask, i32 %evl) %x = call @llvm.vp.and.nxv1i32( %b, %not.a, %mask, i32 %evl) ret %x @@ -818,11 +818,11 @@ define @vandn_vx_vp_nxv1i32(i32 %a, %b, poison, i32 %not.a, i32 0 %splat.not.a = shufflevector %head.not.a, poison, zeroinitializer @@ -841,11 +841,11 @@ define @vandn_vv_vp_nxv2i32( %a, @llvm.vp.xor.nxv2i32( %a, shufflevector( insertelement( poison, i32 -1, i32 0), poison, zeroinitializer), %mask, i32 %evl) %x = call @llvm.vp.and.nxv2i32( %not.a, %b, %mask, i32 %evl) ret %x @@ -859,11 +859,11 @@ define @vandn_vv_vp_swapped_nxv2i32( %a, @llvm.vp.xor.nxv2i32( %a, shufflevector( insertelement( poison, i32 -1, i32 0), poison, zeroinitializer), %mask, i32 %evl) %x = call @llvm.vp.and.nxv2i32( %b, %not.a, %mask, i32 %evl) ret %x @@ -877,11 +877,11 @@ define @vandn_vx_vp_nxv2i32(i32 %a, %b, poison, i32 %not.a, i32 0 %splat.not.a = shufflevector %head.not.a, poison, zeroinitializer @@ -900,11 +900,11 @@ define @vandn_vv_vp_nxv4i32( %a, @llvm.vp.xor.nxv4i32( %a, shufflevector( insertelement( poison, i32 -1, i32 0), poison, zeroinitializer), %mask, i32 %evl) %x = call @llvm.vp.and.nxv4i32( %not.a, %b, %mask, i32 %evl) ret %x @@ -918,11 +918,11 @@ define @vandn_vv_vp_swapped_nxv4i32( %a, @llvm.vp.xor.nxv4i32( %a, shufflevector( insertelement( poison, i32 -1, i32 0), poison, zeroinitializer), %mask, i32 %evl) %x = call @llvm.vp.and.nxv4i32( %b, %not.a, %mask, i32 %evl) ret %x @@ -936,11 +936,11 @@ define @vandn_vx_vp_nxv4i32(i32 %a, %b, poison, i32 %not.a, i32 0 %splat.not.a = shufflevector %head.not.a, poison, zeroinitializer @@ -959,11 +959,11 @@ define @vandn_vv_vp_nxv8i32( %a, @llvm.vp.xor.nxv8i32( %a, shufflevector( insertelement( poison, i32 -1, i32 0), poison, zeroinitializer), %mask, i32 %evl) %x = call @llvm.vp.and.nxv8i32( %not.a, %b, %mask, i32 %evl) ret %x @@ -977,11 +977,11 @@ define @vandn_vv_vp_swapped_nxv8i32( %a, @llvm.vp.xor.nxv8i32( %a, shufflevector( insertelement( poison, i32 -1, i32 0), poison, zeroinitializer), %mask, i32 %evl) %x = call @llvm.vp.and.nxv8i32( %b, %not.a, %mask, i32 %evl) ret %x @@ -995,11 +995,11 @@ define @vandn_vx_vp_nxv8i32(i32 %a, %b, poison, i32 %not.a, i32 0 %splat.not.a = shufflevector %head.not.a, poison, zeroinitializer @@ -1018,11 +1018,11 @@ define @vandn_vv_vp_nxv16i32( %a, @llvm.vp.xor.nxv16i32( %a, shufflevector( insertelement( poison, i32 -1, i32 0), poison, zeroinitializer), %mask, i32 %evl) %x = call @llvm.vp.and.nxv16i32( %not.a, %b, %mask, i32 %evl) ret %x @@ -1036,11 +1036,11 @@ define @vandn_vv_vp_swapped_nxv16i32( %a, ; CHECK-NEXT: vand.vv v8, v16, v8, v0.t ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vandn_vv_vp_swapped_nxv16i32: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m8, ta, ma -; CHECK-ZVBB-NEXT: vandn.vv v8, v16, v8, v0.t -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vandn_vv_vp_swapped_nxv16i32: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; CHECK-ZVKB-NEXT: vandn.vv v8, v16, v8, v0.t +; CHECK-ZVKB-NEXT: ret %not.a = call @llvm.vp.xor.nxv16i32( %a, shufflevector( insertelement( poison, i32 -1, i32 0), poison, zeroinitializer), %mask, i32 %evl) %x = call @llvm.vp.and.nxv16i32( %b, %not.a, %mask, i32 %evl) ret %x @@ -1054,11 +1054,11 @@ define @vandn_vx_vp_nxv16i32(i32 %a, %b, ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vandn_vx_vp_nxv16i32: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli zero, a1, e32, m8, ta, ma -; CHECK-ZVBB-NEXT: vandn.vx v8, v8, a0, v0.t -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vandn_vx_vp_nxv16i32: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli zero, a1, e32, m8, ta, ma +; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a0, v0.t +; CHECK-ZVKB-NEXT: ret %not.a = xor i32 %a, -1 %head.not.a = insertelement poison, i32 %not.a, i32 0 %splat.not.a = shufflevector %head.not.a, poison, zeroinitializer @@ -1077,11 +1077,11 @@ define @vandn_vv_vp_nxv1i64( %a, @llvm.vp.xor.nxv1i64( %a, shufflevector( insertelement( poison, i64 -1, i32 0), poison, zeroinitializer), %mask, i32 %evl) %x = call @llvm.vp.and.nxv1i64( %not.a, %b, %mask, i32 %evl) ret %x @@ -1095,11 +1095,11 @@ define @vandn_vv_vp_swapped_nxv1i64( %a, @llvm.vp.xor.nxv1i64( %a, shufflevector( insertelement( poison, i64 -1, i32 0), poison, zeroinitializer), %mask, i32 %evl) %x = call @llvm.vp.and.nxv1i64( %b, %not.a, %mask, i32 %evl) ret %x @@ -1129,27 +1129,27 @@ define @vandn_vx_vp_nxv1i64(i64 %a, %b, poison, i64 %not.a, i32 0 %splat.not.a = shufflevector %head.not.a, poison, zeroinitializer @@ -1168,11 +1168,11 @@ define @vandn_vv_vp_nxv2i64( %a, @llvm.vp.xor.nxv2i64( %a, shufflevector( insertelement( poison, i64 -1, i32 0), poison, zeroinitializer), %mask, i32 %evl) %x = call @llvm.vp.and.nxv2i64( %not.a, %b, %mask, i32 %evl) ret %x @@ -1186,11 +1186,11 @@ define @vandn_vv_vp_swapped_nxv2i64( %a, @llvm.vp.xor.nxv2i64( %a, shufflevector( insertelement( poison, i64 -1, i32 0), poison, zeroinitializer), %mask, i32 %evl) %x = call @llvm.vp.and.nxv2i64( %b, %not.a, %mask, i32 %evl) ret %x @@ -1220,27 +1220,27 @@ define @vandn_vx_vp_nxv2i64(i64 %a, %b, poison, i64 %not.a, i32 0 %splat.not.a = shufflevector %head.not.a, poison, zeroinitializer @@ -1259,11 +1259,11 @@ define @vandn_vv_vp_nxv4i64( %a, @llvm.vp.xor.nxv4i64( %a, shufflevector( insertelement( poison, i64 -1, i32 0), poison, zeroinitializer), %mask, i32 %evl) %x = call @llvm.vp.and.nxv4i64( %not.a, %b, %mask, i32 %evl) ret %x @@ -1277,11 +1277,11 @@ define @vandn_vv_vp_swapped_nxv4i64( %a, @llvm.vp.xor.nxv4i64( %a, shufflevector( insertelement( poison, i64 -1, i32 0), poison, zeroinitializer), %mask, i32 %evl) %x = call @llvm.vp.and.nxv4i64( %b, %not.a, %mask, i32 %evl) ret %x @@ -1311,27 +1311,27 @@ define @vandn_vx_vp_nxv4i64(i64 %a, %b, poison, i64 %not.a, i32 0 %splat.not.a = shufflevector %head.not.a, poison, zeroinitializer @@ -1350,11 +1350,11 @@ define @vandn_vv_vp_nxv8i64( %a, @llvm.vp.xor.nxv8i64( %a, shufflevector( insertelement( poison, i64 -1, i32 0), poison, zeroinitializer), %mask, i32 %evl) %x = call @llvm.vp.and.nxv8i64( %not.a, %b, %mask, i32 %evl) ret %x @@ -1368,11 +1368,11 @@ define @vandn_vv_vp_swapped_nxv8i64( %a, @llvm.vp.xor.nxv8i64( %a, shufflevector( insertelement( poison, i64 -1, i32 0), poison, zeroinitializer), %mask, i32 %evl) %x = call @llvm.vp.and.nxv8i64( %b, %not.a, %mask, i32 %evl) ret %x @@ -1402,27 +1402,27 @@ define @vandn_vx_vp_nxv8i64(i64 %a, %b, poison, i64 %not.a, i32 0 %splat.not.a = shufflevector %head.not.a, poison, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vrol-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vrol-sdnode.ll index 394435f55cf20..2d8b3647163ea 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vrol-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vrol-sdnode.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 ; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV32 ; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV64 -; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-ZVBB -; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-ZVBB +; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-ZVKB +; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-ZVKB declare @llvm.fshl.nxv1i8(, , ) @@ -18,11 +18,11 @@ define @vrol_vv_nxv1i8( %a, ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vv_nxv1i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf8, ta, ma -; CHECK-ZVBB-NEXT: vrol.vv v8, v8, v9 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vv_nxv1i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, mf8, ta, ma +; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v9 +; CHECK-ZVKB-NEXT: ret %x = call @llvm.fshl.nxv1i8( %a, %a, %b) ret %x } @@ -40,11 +40,11 @@ define @vrol_vx_nxv1i8( %a, i8 %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vx_nxv1i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e8, mf8, ta, ma -; CHECK-ZVBB-NEXT: vrol.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vx_nxv1i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e8, mf8, ta, ma +; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement poison, i8 %b, i32 0 %b.splat = shufflevector %b.head, poison, zeroinitializer %x = call @llvm.fshl.nxv1i8( %a, %a, %b.splat) @@ -65,11 +65,11 @@ define @vrol_vv_nxv2i8( %a, ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vv_nxv2i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf4, ta, ma -; CHECK-ZVBB-NEXT: vrol.vv v8, v8, v9 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vv_nxv2i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, mf4, ta, ma +; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v9 +; CHECK-ZVKB-NEXT: ret %x = call @llvm.fshl.nxv2i8( %a, %a, %b) ret %x } @@ -87,11 +87,11 @@ define @vrol_vx_nxv2i8( %a, i8 %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vx_nxv2i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e8, mf4, ta, ma -; CHECK-ZVBB-NEXT: vrol.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vx_nxv2i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e8, mf4, ta, ma +; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement poison, i8 %b, i32 0 %b.splat = shufflevector %b.head, poison, zeroinitializer %x = call @llvm.fshl.nxv2i8( %a, %a, %b.splat) @@ -112,11 +112,11 @@ define @vrol_vv_nxv4i8( %a, ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vv_nxv4i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf2, ta, ma -; CHECK-ZVBB-NEXT: vrol.vv v8, v8, v9 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vv_nxv4i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, mf2, ta, ma +; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v9 +; CHECK-ZVKB-NEXT: ret %x = call @llvm.fshl.nxv4i8( %a, %a, %b) ret %x } @@ -134,11 +134,11 @@ define @vrol_vx_nxv4i8( %a, i8 %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vx_nxv4i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e8, mf2, ta, ma -; CHECK-ZVBB-NEXT: vrol.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vx_nxv4i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e8, mf2, ta, ma +; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement poison, i8 %b, i32 0 %b.splat = shufflevector %b.head, poison, zeroinitializer %x = call @llvm.fshl.nxv4i8( %a, %a, %b.splat) @@ -159,11 +159,11 @@ define @vrol_vv_nxv8i8( %a, ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vv_nxv8i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m1, ta, ma -; CHECK-ZVBB-NEXT: vrol.vv v8, v8, v9 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vv_nxv8i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, m1, ta, ma +; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v9 +; CHECK-ZVKB-NEXT: ret %x = call @llvm.fshl.nxv8i8( %a, %a, %b) ret %x } @@ -181,11 +181,11 @@ define @vrol_vx_nxv8i8( %a, i8 %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vx_nxv8i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e8, m1, ta, ma -; CHECK-ZVBB-NEXT: vrol.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vx_nxv8i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e8, m1, ta, ma +; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement poison, i8 %b, i32 0 %b.splat = shufflevector %b.head, poison, zeroinitializer %x = call @llvm.fshl.nxv8i8( %a, %a, %b.splat) @@ -206,11 +206,11 @@ define @vrol_vv_nxv16i8( %a, @llvm.fshl.nxv16i8( %a, %a, %b) ret %x } @@ -228,11 +228,11 @@ define @vrol_vx_nxv16i8( %a, i8 %b) { ; CHECK-NEXT: vor.vv v8, v12, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vx_nxv16i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e8, m2, ta, ma -; CHECK-ZVBB-NEXT: vrol.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vx_nxv16i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e8, m2, ta, ma +; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement poison, i8 %b, i32 0 %b.splat = shufflevector %b.head, poison, zeroinitializer %x = call @llvm.fshl.nxv16i8( %a, %a, %b.splat) @@ -253,11 +253,11 @@ define @vrol_vv_nxv32i8( %a, @llvm.fshl.nxv32i8( %a, %a, %b) ret %x } @@ -275,11 +275,11 @@ define @vrol_vx_nxv32i8( %a, i8 %b) { ; CHECK-NEXT: vor.vv v8, v16, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vx_nxv32i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e8, m4, ta, ma -; CHECK-ZVBB-NEXT: vrol.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vx_nxv32i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e8, m4, ta, ma +; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement poison, i8 %b, i32 0 %b.splat = shufflevector %b.head, poison, zeroinitializer %x = call @llvm.fshl.nxv32i8( %a, %a, %b.splat) @@ -300,11 +300,11 @@ define @vrol_vv_nxv64i8( %a, @llvm.fshl.nxv64i8( %a, %a, %b) ret %x } @@ -322,11 +322,11 @@ define @vrol_vx_nxv64i8( %a, i8 %b) { ; CHECK-NEXT: vor.vv v8, v24, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vx_nxv64i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e8, m8, ta, ma -; CHECK-ZVBB-NEXT: vrol.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vx_nxv64i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e8, m8, ta, ma +; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement poison, i8 %b, i32 0 %b.splat = shufflevector %b.head, poison, zeroinitializer %x = call @llvm.fshl.nxv64i8( %a, %a, %b.splat) @@ -347,11 +347,11 @@ define @vrol_vv_nxv1i16( %a, @llvm.fshl.nxv1i16( %a, %a, %b) ret %x } @@ -369,11 +369,11 @@ define @vrol_vx_nxv1i16( %a, i16 %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vx_nxv1i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e16, mf4, ta, ma -; CHECK-ZVBB-NEXT: vrol.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vx_nxv1i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement poison, i16 %b, i32 0 %b.splat = shufflevector %b.head, poison, zeroinitializer %x = call @llvm.fshl.nxv1i16( %a, %a, %b.splat) @@ -394,11 +394,11 @@ define @vrol_vv_nxv2i16( %a, @llvm.fshl.nxv2i16( %a, %a, %b) ret %x } @@ -416,11 +416,11 @@ define @vrol_vx_nxv2i16( %a, i16 %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vx_nxv2i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e16, mf2, ta, ma -; CHECK-ZVBB-NEXT: vrol.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vx_nxv2i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement poison, i16 %b, i32 0 %b.splat = shufflevector %b.head, poison, zeroinitializer %x = call @llvm.fshl.nxv2i16( %a, %a, %b.splat) @@ -441,11 +441,11 @@ define @vrol_vv_nxv4i16( %a, @llvm.fshl.nxv4i16( %a, %a, %b) ret %x } @@ -463,11 +463,11 @@ define @vrol_vx_nxv4i16( %a, i16 %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vx_nxv4i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e16, m1, ta, ma -; CHECK-ZVBB-NEXT: vrol.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vx_nxv4i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e16, m1, ta, ma +; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement poison, i16 %b, i32 0 %b.splat = shufflevector %b.head, poison, zeroinitializer %x = call @llvm.fshl.nxv4i16( %a, %a, %b.splat) @@ -488,11 +488,11 @@ define @vrol_vv_nxv8i16( %a, @llvm.fshl.nxv8i16( %a, %a, %b) ret %x } @@ -510,11 +510,11 @@ define @vrol_vx_nxv8i16( %a, i16 %b) { ; CHECK-NEXT: vor.vv v8, v12, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vx_nxv8i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e16, m2, ta, ma -; CHECK-ZVBB-NEXT: vrol.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vx_nxv8i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement poison, i16 %b, i32 0 %b.splat = shufflevector %b.head, poison, zeroinitializer %x = call @llvm.fshl.nxv8i16( %a, %a, %b.splat) @@ -535,11 +535,11 @@ define @vrol_vv_nxv16i16( %a, @llvm.fshl.nxv16i16( %a, %a, %b) ret %x } @@ -557,11 +557,11 @@ define @vrol_vx_nxv16i16( %a, i16 %b) { ; CHECK-NEXT: vor.vv v8, v16, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vx_nxv16i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e16, m4, ta, ma -; CHECK-ZVBB-NEXT: vrol.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vx_nxv16i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement poison, i16 %b, i32 0 %b.splat = shufflevector %b.head, poison, zeroinitializer %x = call @llvm.fshl.nxv16i16( %a, %a, %b.splat) @@ -582,11 +582,11 @@ define @vrol_vv_nxv32i16( %a, @llvm.fshl.nxv32i16( %a, %a, %b) ret %x } @@ -604,11 +604,11 @@ define @vrol_vx_nxv32i16( %a, i16 %b) { ; CHECK-NEXT: vor.vv v8, v24, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vx_nxv32i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e16, m8, ta, ma -; CHECK-ZVBB-NEXT: vrol.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vx_nxv32i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e16, m8, ta, ma +; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement poison, i16 %b, i32 0 %b.splat = shufflevector %b.head, poison, zeroinitializer %x = call @llvm.fshl.nxv32i16( %a, %a, %b.splat) @@ -630,11 +630,11 @@ define @vrol_vv_nxv1i32( %a, @llvm.fshl.nxv1i32( %a, %a, %b) ret %x } @@ -664,11 +664,11 @@ define @vrol_vx_nxv1i32( %a, i32 %b) { ; CHECK-RV64-NEXT: vor.vv v8, v10, v8 ; CHECK-RV64-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vx_nxv1i32: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e32, mf2, ta, ma -; CHECK-ZVBB-NEXT: vrol.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vx_nxv1i32: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e32, mf2, ta, ma +; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement poison, i32 %b, i32 0 %b.splat = shufflevector %b.head, poison, zeroinitializer %x = call @llvm.fshl.nxv1i32( %a, %a, %b.splat) @@ -690,11 +690,11 @@ define @vrol_vv_nxv2i32( %a, @llvm.fshl.nxv2i32( %a, %a, %b) ret %x } @@ -724,11 +724,11 @@ define @vrol_vx_nxv2i32( %a, i32 %b) { ; CHECK-RV64-NEXT: vor.vv v8, v10, v8 ; CHECK-RV64-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vx_nxv2i32: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e32, m1, ta, ma -; CHECK-ZVBB-NEXT: vrol.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vx_nxv2i32: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e32, m1, ta, ma +; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement poison, i32 %b, i32 0 %b.splat = shufflevector %b.head, poison, zeroinitializer %x = call @llvm.fshl.nxv2i32( %a, %a, %b.splat) @@ -750,11 +750,11 @@ define @vrol_vv_nxv4i32( %a, @llvm.fshl.nxv4i32( %a, %a, %b) ret %x } @@ -784,11 +784,11 @@ define @vrol_vx_nxv4i32( %a, i32 %b) { ; CHECK-RV64-NEXT: vor.vv v8, v12, v8 ; CHECK-RV64-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vx_nxv4i32: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e32, m2, ta, ma -; CHECK-ZVBB-NEXT: vrol.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vx_nxv4i32: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e32, m2, ta, ma +; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement poison, i32 %b, i32 0 %b.splat = shufflevector %b.head, poison, zeroinitializer %x = call @llvm.fshl.nxv4i32( %a, %a, %b.splat) @@ -810,11 +810,11 @@ define @vrol_vv_nxv8i32( %a, @llvm.fshl.nxv8i32( %a, %a, %b) ret %x } @@ -844,11 +844,11 @@ define @vrol_vx_nxv8i32( %a, i32 %b) { ; CHECK-RV64-NEXT: vor.vv v8, v16, v8 ; CHECK-RV64-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vx_nxv8i32: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e32, m4, ta, ma -; CHECK-ZVBB-NEXT: vrol.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vx_nxv8i32: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e32, m4, ta, ma +; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement poison, i32 %b, i32 0 %b.splat = shufflevector %b.head, poison, zeroinitializer %x = call @llvm.fshl.nxv8i32( %a, %a, %b.splat) @@ -870,11 +870,11 @@ define @vrol_vv_nxv16i32( %a, @llvm.fshl.nxv16i32( %a, %a, %b) ret %x } @@ -904,11 +904,11 @@ define @vrol_vx_nxv16i32( %a, i32 %b) { ; CHECK-RV64-NEXT: vor.vv v8, v24, v8 ; CHECK-RV64-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vx_nxv16i32: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e32, m8, ta, ma -; CHECK-ZVBB-NEXT: vrol.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vx_nxv16i32: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e32, m8, ta, ma +; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement poison, i32 %b, i32 0 %b.splat = shufflevector %b.head, poison, zeroinitializer %x = call @llvm.fshl.nxv16i32( %a, %a, %b.splat) @@ -930,11 +930,11 @@ define @vrol_vv_nxv1i64( %a, @llvm.fshl.nxv1i64( %a, %a, %b) ret %x } @@ -964,11 +964,11 @@ define @vrol_vx_nxv1i64( %a, i64 %b) { ; CHECK-RV64-NEXT: vor.vv v8, v9, v8 ; CHECK-RV64-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vx_nxv1i64: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; CHECK-ZVBB-NEXT: vrol.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vx_nxv1i64: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e64, m1, ta, ma +; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement poison, i64 %b, i32 0 %b.splat = shufflevector %b.head, poison, zeroinitializer %x = call @llvm.fshl.nxv1i64( %a, %a, %b.splat) @@ -990,11 +990,11 @@ define @vrol_vv_nxv2i64( %a, @llvm.fshl.nxv2i64( %a, %a, %b) ret %x } @@ -1024,11 +1024,11 @@ define @vrol_vx_nxv2i64( %a, i64 %b) { ; CHECK-RV64-NEXT: vor.vv v8, v10, v8 ; CHECK-RV64-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vx_nxv2i64: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; CHECK-ZVBB-NEXT: vrol.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vx_nxv2i64: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e64, m2, ta, ma +; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement poison, i64 %b, i32 0 %b.splat = shufflevector %b.head, poison, zeroinitializer %x = call @llvm.fshl.nxv2i64( %a, %a, %b.splat) @@ -1050,11 +1050,11 @@ define @vrol_vv_nxv4i64( %a, @llvm.fshl.nxv4i64( %a, %a, %b) ret %x } @@ -1084,11 +1084,11 @@ define @vrol_vx_nxv4i64( %a, i64 %b) { ; CHECK-RV64-NEXT: vor.vv v8, v12, v8 ; CHECK-RV64-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vx_nxv4i64: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; CHECK-ZVBB-NEXT: vrol.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vx_nxv4i64: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e64, m4, ta, ma +; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement poison, i64 %b, i32 0 %b.splat = shufflevector %b.head, poison, zeroinitializer %x = call @llvm.fshl.nxv4i64( %a, %a, %b.splat) @@ -1110,11 +1110,11 @@ define @vrol_vv_nxv8i64( %a, @llvm.fshl.nxv8i64( %a, %a, %b) ret %x } @@ -1144,11 +1144,11 @@ define @vrol_vx_nxv8i64( %a, i64 %b) { ; CHECK-RV64-NEXT: vor.vv v8, v16, v8 ; CHECK-RV64-NEXT: ret ; -; CHECK-ZVBB-LABEL: vrol_vx_nxv8i64: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; CHECK-ZVBB-NEXT: vrol.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vrol_vx_nxv8i64: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e64, m8, ta, ma +; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement poison, i64 %b, i32 0 %b.splat = shufflevector %b.head, poison, zeroinitializer %x = call @llvm.fshl.nxv8i64( %a, %a, %b.splat) diff --git a/llvm/test/CodeGen/RISCV/rvv/vror-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vror-sdnode.ll index 0f13efde7e12a..f8c1bb5194f11 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vror-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vror-sdnode.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 ; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV32 ; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV64 -; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-ZVBB -; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-ZVBB +; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-ZVKB +; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-ZVKB declare @llvm.fshr.nxv1i8(, , ) declare @llvm.fshl.nxv1i8(, , ) @@ -19,11 +19,11 @@ define @vror_vv_nxv1i8( %a, ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vv_nxv1i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf8, ta, ma -; CHECK-ZVBB-NEXT: vror.vv v8, v8, v9 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vv_nxv1i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, mf8, ta, ma +; CHECK-ZVKB-NEXT: vror.vv v8, v8, v9 +; CHECK-ZVKB-NEXT: ret %x = call @llvm.fshr.nxv1i8( %a, %a, %b) ret %x } @@ -41,11 +41,11 @@ define @vror_vx_nxv1i8( %a, i8 %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vx_nxv1i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e8, mf8, ta, ma -; CHECK-ZVBB-NEXT: vror.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vx_nxv1i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e8, mf8, ta, ma +; CHECK-ZVKB-NEXT: vror.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement poison, i8 %b, i32 0 %b.splat = shufflevector %b.head, poison, zeroinitializer %x = call @llvm.fshr.nxv1i8( %a, %a, %b.splat) @@ -61,11 +61,11 @@ define @vror_vi_nxv1i8( %a) { ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_nxv1i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf8, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 1 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_nxv1i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, mf8, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1 +; CHECK-ZVKB-NEXT: ret %x = call @llvm.fshr.nxv1i8( %a, %a, shufflevector( insertelement( poison, i8 1, i32 0), poison, zeroinitializer)) ret %x } @@ -79,11 +79,11 @@ define @vror_vi_rotl_nxv1i8( %a) { ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_rotl_nxv1i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf8, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 7 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_rotl_nxv1i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, mf8, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 7 +; CHECK-ZVKB-NEXT: ret %x = call @llvm.fshl.nxv1i8( %a, %a, shufflevector( insertelement( poison, i8 1, i32 0), poison, zeroinitializer)) ret %x } @@ -103,11 +103,11 @@ define @vror_vv_nxv2i8( %a, ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vv_nxv2i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf4, ta, ma -; CHECK-ZVBB-NEXT: vror.vv v8, v8, v9 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vv_nxv2i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, mf4, ta, ma +; CHECK-ZVKB-NEXT: vror.vv v8, v8, v9 +; CHECK-ZVKB-NEXT: ret %x = call @llvm.fshr.nxv2i8( %a, %a, %b) ret %x } @@ -125,11 +125,11 @@ define @vror_vx_nxv2i8( %a, i8 %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vx_nxv2i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e8, mf4, ta, ma -; CHECK-ZVBB-NEXT: vror.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vx_nxv2i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e8, mf4, ta, ma +; CHECK-ZVKB-NEXT: vror.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement poison, i8 %b, i32 0 %b.splat = shufflevector %b.head, poison, zeroinitializer %x = call @llvm.fshr.nxv2i8( %a, %a, %b.splat) @@ -145,11 +145,11 @@ define @vror_vi_nxv2i8( %a) { ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_nxv2i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf4, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 1 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_nxv2i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, mf4, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1 +; CHECK-ZVKB-NEXT: ret %x = call @llvm.fshr.nxv2i8( %a, %a, shufflevector( insertelement( poison, i8 1, i32 0), poison, zeroinitializer)) ret %x } @@ -163,11 +163,11 @@ define @vror_vi_rotl_nxv2i8( %a) { ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_rotl_nxv2i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf4, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 7 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_rotl_nxv2i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, mf4, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 7 +; CHECK-ZVKB-NEXT: ret %x = call @llvm.fshl.nxv2i8( %a, %a, shufflevector( insertelement( poison, i8 1, i32 0), poison, zeroinitializer)) ret %x } @@ -187,11 +187,11 @@ define @vror_vv_nxv4i8( %a, ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vv_nxv4i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf2, ta, ma -; CHECK-ZVBB-NEXT: vror.vv v8, v8, v9 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vv_nxv4i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, mf2, ta, ma +; CHECK-ZVKB-NEXT: vror.vv v8, v8, v9 +; CHECK-ZVKB-NEXT: ret %x = call @llvm.fshr.nxv4i8( %a, %a, %b) ret %x } @@ -209,11 +209,11 @@ define @vror_vx_nxv4i8( %a, i8 %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vx_nxv4i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e8, mf2, ta, ma -; CHECK-ZVBB-NEXT: vror.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vx_nxv4i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e8, mf2, ta, ma +; CHECK-ZVKB-NEXT: vror.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement poison, i8 %b, i32 0 %b.splat = shufflevector %b.head, poison, zeroinitializer %x = call @llvm.fshr.nxv4i8( %a, %a, %b.splat) @@ -229,11 +229,11 @@ define @vror_vi_nxv4i8( %a) { ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_nxv4i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf2, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 1 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_nxv4i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, mf2, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1 +; CHECK-ZVKB-NEXT: ret %x = call @llvm.fshr.nxv4i8( %a, %a, shufflevector( insertelement( poison, i8 1, i32 0), poison, zeroinitializer)) ret %x } @@ -247,11 +247,11 @@ define @vror_vi_rotl_nxv4i8( %a) { ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_rotl_nxv4i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf2, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 7 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_rotl_nxv4i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, mf2, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 7 +; CHECK-ZVKB-NEXT: ret %x = call @llvm.fshl.nxv4i8( %a, %a, shufflevector( insertelement( poison, i8 1, i32 0), poison, zeroinitializer)) ret %x } @@ -271,11 +271,11 @@ define @vror_vv_nxv8i8( %a, ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vv_nxv8i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m1, ta, ma -; CHECK-ZVBB-NEXT: vror.vv v8, v8, v9 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vv_nxv8i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, m1, ta, ma +; CHECK-ZVKB-NEXT: vror.vv v8, v8, v9 +; CHECK-ZVKB-NEXT: ret %x = call @llvm.fshr.nxv8i8( %a, %a, %b) ret %x } @@ -293,11 +293,11 @@ define @vror_vx_nxv8i8( %a, i8 %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vx_nxv8i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e8, m1, ta, ma -; CHECK-ZVBB-NEXT: vror.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vx_nxv8i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e8, m1, ta, ma +; CHECK-ZVKB-NEXT: vror.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement poison, i8 %b, i32 0 %b.splat = shufflevector %b.head, poison, zeroinitializer %x = call @llvm.fshr.nxv8i8( %a, %a, %b.splat) @@ -313,11 +313,11 @@ define @vror_vi_nxv8i8( %a) { ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_nxv8i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m1, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 1 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_nxv8i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, m1, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1 +; CHECK-ZVKB-NEXT: ret %x = call @llvm.fshr.nxv8i8( %a, %a, shufflevector( insertelement( poison, i8 1, i32 0), poison, zeroinitializer)) ret %x } @@ -331,11 +331,11 @@ define @vror_vi_rotl_nxv8i8( %a) { ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_rotl_nxv8i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m1, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 7 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_rotl_nxv8i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, m1, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 7 +; CHECK-ZVKB-NEXT: ret %x = call @llvm.fshl.nxv8i8( %a, %a, shufflevector( insertelement( poison, i8 1, i32 0), poison, zeroinitializer)) ret %x } @@ -355,11 +355,11 @@ define @vror_vv_nxv16i8( %a, @llvm.fshr.nxv16i8( %a, %a, %b) ret %x } @@ -377,11 +377,11 @@ define @vror_vx_nxv16i8( %a, i8 %b) { ; CHECK-NEXT: vor.vv v8, v12, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vx_nxv16i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e8, m2, ta, ma -; CHECK-ZVBB-NEXT: vror.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vx_nxv16i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e8, m2, ta, ma +; CHECK-ZVKB-NEXT: vror.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement poison, i8 %b, i32 0 %b.splat = shufflevector %b.head, poison, zeroinitializer %x = call @llvm.fshr.nxv16i8( %a, %a, %b.splat) @@ -397,11 +397,11 @@ define @vror_vi_nxv16i8( %a) { ; CHECK-NEXT: vor.vv v8, v8, v10 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_nxv16i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m2, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 1 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_nxv16i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, m2, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1 +; CHECK-ZVKB-NEXT: ret %x = call @llvm.fshr.nxv16i8( %a, %a, shufflevector( insertelement( poison, i8 1, i32 0), poison, zeroinitializer)) ret %x } @@ -415,11 +415,11 @@ define @vror_vi_rotl_nxv16i8( %a) { ; CHECK-NEXT: vor.vv v8, v8, v10 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_rotl_nxv16i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m2, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 7 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_rotl_nxv16i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, m2, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 7 +; CHECK-ZVKB-NEXT: ret %x = call @llvm.fshl.nxv16i8( %a, %a, shufflevector( insertelement( poison, i8 1, i32 0), poison, zeroinitializer)) ret %x } @@ -439,11 +439,11 @@ define @vror_vv_nxv32i8( %a, @llvm.fshr.nxv32i8( %a, %a, %b) ret %x } @@ -461,11 +461,11 @@ define @vror_vx_nxv32i8( %a, i8 %b) { ; CHECK-NEXT: vor.vv v8, v16, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vx_nxv32i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e8, m4, ta, ma -; CHECK-ZVBB-NEXT: vror.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vx_nxv32i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e8, m4, ta, ma +; CHECK-ZVKB-NEXT: vror.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement poison, i8 %b, i32 0 %b.splat = shufflevector %b.head, poison, zeroinitializer %x = call @llvm.fshr.nxv32i8( %a, %a, %b.splat) @@ -481,11 +481,11 @@ define @vror_vi_nxv32i8( %a) { ; CHECK-NEXT: vor.vv v8, v8, v12 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_nxv32i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m4, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 1 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_nxv32i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, m4, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1 +; CHECK-ZVKB-NEXT: ret %x = call @llvm.fshr.nxv32i8( %a, %a, shufflevector( insertelement( poison, i8 1, i32 0), poison, zeroinitializer)) ret %x } @@ -499,11 +499,11 @@ define @vror_vi_rotl_nxv32i8( %a) { ; CHECK-NEXT: vor.vv v8, v8, v12 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_rotl_nxv32i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m4, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 7 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_rotl_nxv32i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, m4, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 7 +; CHECK-ZVKB-NEXT: ret %x = call @llvm.fshl.nxv32i8( %a, %a, shufflevector( insertelement( poison, i8 1, i32 0), poison, zeroinitializer)) ret %x } @@ -523,11 +523,11 @@ define @vror_vv_nxv64i8( %a, @llvm.fshr.nxv64i8( %a, %a, %b) ret %x } @@ -545,11 +545,11 @@ define @vror_vx_nxv64i8( %a, i8 %b) { ; CHECK-NEXT: vor.vv v8, v24, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vx_nxv64i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e8, m8, ta, ma -; CHECK-ZVBB-NEXT: vror.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vx_nxv64i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e8, m8, ta, ma +; CHECK-ZVKB-NEXT: vror.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement poison, i8 %b, i32 0 %b.splat = shufflevector %b.head, poison, zeroinitializer %x = call @llvm.fshr.nxv64i8( %a, %a, %b.splat) @@ -565,11 +565,11 @@ define @vror_vi_nxv64i8( %a) { ; CHECK-NEXT: vor.vv v8, v8, v16 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_nxv64i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m8, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 1 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_nxv64i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, m8, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1 +; CHECK-ZVKB-NEXT: ret %x = call @llvm.fshr.nxv64i8( %a, %a, shufflevector( insertelement( poison, i8 1, i32 0), poison, zeroinitializer)) ret %x } @@ -583,11 +583,11 @@ define @vror_vi_rotl_nxv64i8( %a) { ; CHECK-NEXT: vor.vv v8, v8, v16 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_rotl_nxv64i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m8, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 7 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_rotl_nxv64i8: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, m8, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 7 +; CHECK-ZVKB-NEXT: ret %x = call @llvm.fshl.nxv64i8( %a, %a, shufflevector( insertelement( poison, i8 1, i32 0), poison, zeroinitializer)) ret %x } @@ -607,11 +607,11 @@ define @vror_vv_nxv1i16( %a, @llvm.fshr.nxv1i16( %a, %a, %b) ret %x } @@ -629,11 +629,11 @@ define @vror_vx_nxv1i16( %a, i16 %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vx_nxv1i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e16, mf4, ta, ma -; CHECK-ZVBB-NEXT: vror.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vx_nxv1i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; CHECK-ZVKB-NEXT: vror.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement poison, i16 %b, i32 0 %b.splat = shufflevector %b.head, poison, zeroinitializer %x = call @llvm.fshr.nxv1i16( %a, %a, %b.splat) @@ -649,11 +649,11 @@ define @vror_vi_nxv1i16( %a) { ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_nxv1i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, mf4, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 1 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_nxv1i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, mf4, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1 +; CHECK-ZVKB-NEXT: ret %x = call @llvm.fshr.nxv1i16( %a, %a, shufflevector( insertelement( poison, i16 1, i32 0), poison, zeroinitializer)) ret %x } @@ -667,11 +667,11 @@ define @vror_vi_rotl_nxv1i16( %a) { ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_rotl_nxv1i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, mf4, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 15 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_rotl_nxv1i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, mf4, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 15 +; CHECK-ZVKB-NEXT: ret %x = call @llvm.fshl.nxv1i16( %a, %a, shufflevector( insertelement( poison, i16 1, i32 0), poison, zeroinitializer)) ret %x } @@ -691,11 +691,11 @@ define @vror_vv_nxv2i16( %a, @llvm.fshr.nxv2i16( %a, %a, %b) ret %x } @@ -713,11 +713,11 @@ define @vror_vx_nxv2i16( %a, i16 %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vx_nxv2i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e16, mf2, ta, ma -; CHECK-ZVBB-NEXT: vror.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vx_nxv2i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; CHECK-ZVKB-NEXT: vror.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement poison, i16 %b, i32 0 %b.splat = shufflevector %b.head, poison, zeroinitializer %x = call @llvm.fshr.nxv2i16( %a, %a, %b.splat) @@ -733,11 +733,11 @@ define @vror_vi_nxv2i16( %a) { ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_nxv2i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, mf2, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 1 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_nxv2i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, mf2, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1 +; CHECK-ZVKB-NEXT: ret %x = call @llvm.fshr.nxv2i16( %a, %a, shufflevector( insertelement( poison, i16 1, i32 0), poison, zeroinitializer)) ret %x } @@ -751,11 +751,11 @@ define @vror_vi_rotl_nxv2i16( %a) { ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_rotl_nxv2i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, mf2, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 15 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_rotl_nxv2i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, mf2, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 15 +; CHECK-ZVKB-NEXT: ret %x = call @llvm.fshl.nxv2i16( %a, %a, shufflevector( insertelement( poison, i16 1, i32 0), poison, zeroinitializer)) ret %x } @@ -775,11 +775,11 @@ define @vror_vv_nxv4i16( %a, @llvm.fshr.nxv4i16( %a, %a, %b) ret %x } @@ -797,11 +797,11 @@ define @vror_vx_nxv4i16( %a, i16 %b) { ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vx_nxv4i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e16, m1, ta, ma -; CHECK-ZVBB-NEXT: vror.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vx_nxv4i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e16, m1, ta, ma +; CHECK-ZVKB-NEXT: vror.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement poison, i16 %b, i32 0 %b.splat = shufflevector %b.head, poison, zeroinitializer %x = call @llvm.fshr.nxv4i16( %a, %a, %b.splat) @@ -817,11 +817,11 @@ define @vror_vi_nxv4i16( %a) { ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_nxv4i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m1, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 1 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_nxv4i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, m1, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1 +; CHECK-ZVKB-NEXT: ret %x = call @llvm.fshr.nxv4i16( %a, %a, shufflevector( insertelement( poison, i16 1, i32 0), poison, zeroinitializer)) ret %x } @@ -835,11 +835,11 @@ define @vror_vi_rotl_nxv4i16( %a) { ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_rotl_nxv4i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m1, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 15 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_rotl_nxv4i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, m1, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 15 +; CHECK-ZVKB-NEXT: ret %x = call @llvm.fshl.nxv4i16( %a, %a, shufflevector( insertelement( poison, i16 1, i32 0), poison, zeroinitializer)) ret %x } @@ -859,11 +859,11 @@ define @vror_vv_nxv8i16( %a, @llvm.fshr.nxv8i16( %a, %a, %b) ret %x } @@ -881,11 +881,11 @@ define @vror_vx_nxv8i16( %a, i16 %b) { ; CHECK-NEXT: vor.vv v8, v12, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vx_nxv8i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e16, m2, ta, ma -; CHECK-ZVBB-NEXT: vror.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vx_nxv8i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; CHECK-ZVKB-NEXT: vror.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement poison, i16 %b, i32 0 %b.splat = shufflevector %b.head, poison, zeroinitializer %x = call @llvm.fshr.nxv8i16( %a, %a, %b.splat) @@ -901,11 +901,11 @@ define @vror_vi_nxv8i16( %a) { ; CHECK-NEXT: vor.vv v8, v8, v10 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_nxv8i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m2, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 1 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_nxv8i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, m2, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1 +; CHECK-ZVKB-NEXT: ret %x = call @llvm.fshr.nxv8i16( %a, %a, shufflevector( insertelement( poison, i16 1, i32 0), poison, zeroinitializer)) ret %x } @@ -919,11 +919,11 @@ define @vror_vi_rotl_nxv8i16( %a) { ; CHECK-NEXT: vor.vv v8, v8, v10 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_rotl_nxv8i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m2, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 15 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_rotl_nxv8i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, m2, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 15 +; CHECK-ZVKB-NEXT: ret %x = call @llvm.fshl.nxv8i16( %a, %a, shufflevector( insertelement( poison, i16 1, i32 0), poison, zeroinitializer)) ret %x } @@ -943,11 +943,11 @@ define @vror_vv_nxv16i16( %a, @llvm.fshr.nxv16i16( %a, %a, %b) ret %x } @@ -965,11 +965,11 @@ define @vror_vx_nxv16i16( %a, i16 %b) { ; CHECK-NEXT: vor.vv v8, v16, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vx_nxv16i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e16, m4, ta, ma -; CHECK-ZVBB-NEXT: vror.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vx_nxv16i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; CHECK-ZVKB-NEXT: vror.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement poison, i16 %b, i32 0 %b.splat = shufflevector %b.head, poison, zeroinitializer %x = call @llvm.fshr.nxv16i16( %a, %a, %b.splat) @@ -985,11 +985,11 @@ define @vror_vi_nxv16i16( %a) { ; CHECK-NEXT: vor.vv v8, v8, v12 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_nxv16i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m4, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 1 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_nxv16i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, m4, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1 +; CHECK-ZVKB-NEXT: ret %x = call @llvm.fshr.nxv16i16( %a, %a, shufflevector( insertelement( poison, i16 1, i32 0), poison, zeroinitializer)) ret %x } @@ -1003,11 +1003,11 @@ define @vror_vi_rotl_nxv16i16( %a) { ; CHECK-NEXT: vor.vv v8, v8, v12 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_rotl_nxv16i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m4, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 15 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_rotl_nxv16i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, m4, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 15 +; CHECK-ZVKB-NEXT: ret %x = call @llvm.fshl.nxv16i16( %a, %a, shufflevector( insertelement( poison, i16 1, i32 0), poison, zeroinitializer)) ret %x } @@ -1027,11 +1027,11 @@ define @vror_vv_nxv32i16( %a, @llvm.fshr.nxv32i16( %a, %a, %b) ret %x } @@ -1049,11 +1049,11 @@ define @vror_vx_nxv32i16( %a, i16 %b) { ; CHECK-NEXT: vor.vv v8, v24, v8 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vx_nxv32i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e16, m8, ta, ma -; CHECK-ZVBB-NEXT: vror.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vx_nxv32i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e16, m8, ta, ma +; CHECK-ZVKB-NEXT: vror.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement poison, i16 %b, i32 0 %b.splat = shufflevector %b.head, poison, zeroinitializer %x = call @llvm.fshr.nxv32i16( %a, %a, %b.splat) @@ -1069,11 +1069,11 @@ define @vror_vi_nxv32i16( %a) { ; CHECK-NEXT: vor.vv v8, v8, v16 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_nxv32i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m8, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 1 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_nxv32i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, m8, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1 +; CHECK-ZVKB-NEXT: ret %x = call @llvm.fshr.nxv32i16( %a, %a, shufflevector( insertelement( poison, i16 1, i32 0), poison, zeroinitializer)) ret %x } @@ -1087,11 +1087,11 @@ define @vror_vi_rotl_nxv32i16( %a) { ; CHECK-NEXT: vor.vv v8, v8, v16 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_rotl_nxv32i16: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m8, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 15 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_rotl_nxv32i16: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, m8, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 15 +; CHECK-ZVKB-NEXT: ret %x = call @llvm.fshl.nxv32i16( %a, %a, shufflevector( insertelement( poison, i16 1, i32 0), poison, zeroinitializer)) ret %x } @@ -1112,11 +1112,11 @@ define @vror_vv_nxv1i32( %a, @llvm.fshr.nxv1i32( %a, %a, %b) ret %x } @@ -1146,11 +1146,11 @@ define @vror_vx_nxv1i32( %a, i32 %b) { ; CHECK-RV64-NEXT: vor.vv v8, v10, v8 ; CHECK-RV64-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vx_nxv1i32: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e32, mf2, ta, ma -; CHECK-ZVBB-NEXT: vror.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vx_nxv1i32: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e32, mf2, ta, ma +; CHECK-ZVKB-NEXT: vror.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement poison, i32 %b, i32 0 %b.splat = shufflevector %b.head, poison, zeroinitializer %x = call @llvm.fshr.nxv1i32( %a, %a, %b.splat) @@ -1166,11 +1166,11 @@ define @vror_vi_nxv1i32( %a) { ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_nxv1i32: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, mf2, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 1 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_nxv1i32: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a0, zero, e32, mf2, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1 +; CHECK-ZVKB-NEXT: ret %x = call @llvm.fshr.nxv1i32( %a, %a, shufflevector( insertelement( poison, i32 1, i32 0), poison, zeroinitializer)) ret %x } @@ -1184,11 +1184,11 @@ define @vror_vi_rotl_nxv1i32( %a) { ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_rotl_nxv1i32: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, mf2, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 31 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_rotl_nxv1i32: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a0, zero, e32, mf2, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 31 +; CHECK-ZVKB-NEXT: ret %x = call @llvm.fshl.nxv1i32( %a, %a, shufflevector( insertelement( poison, i32 1, i32 0), poison, zeroinitializer)) ret %x } @@ -1209,11 +1209,11 @@ define @vror_vv_nxv2i32( %a, @llvm.fshr.nxv2i32( %a, %a, %b) ret %x } @@ -1243,11 +1243,11 @@ define @vror_vx_nxv2i32( %a, i32 %b) { ; CHECK-RV64-NEXT: vor.vv v8, v10, v8 ; CHECK-RV64-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vx_nxv2i32: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e32, m1, ta, ma -; CHECK-ZVBB-NEXT: vror.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vx_nxv2i32: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e32, m1, ta, ma +; CHECK-ZVKB-NEXT: vror.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement poison, i32 %b, i32 0 %b.splat = shufflevector %b.head, poison, zeroinitializer %x = call @llvm.fshr.nxv2i32( %a, %a, %b.splat) @@ -1263,11 +1263,11 @@ define @vror_vi_nxv2i32( %a) { ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_nxv2i32: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m1, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 1 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_nxv2i32: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a0, zero, e32, m1, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1 +; CHECK-ZVKB-NEXT: ret %x = call @llvm.fshr.nxv2i32( %a, %a, shufflevector( insertelement( poison, i32 1, i32 0), poison, zeroinitializer)) ret %x } @@ -1281,11 +1281,11 @@ define @vror_vi_rotl_nxv2i32( %a) { ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_rotl_nxv2i32: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m1, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 31 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_rotl_nxv2i32: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a0, zero, e32, m1, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 31 +; CHECK-ZVKB-NEXT: ret %x = call @llvm.fshl.nxv2i32( %a, %a, shufflevector( insertelement( poison, i32 1, i32 0), poison, zeroinitializer)) ret %x } @@ -1306,11 +1306,11 @@ define @vror_vv_nxv4i32( %a, @llvm.fshr.nxv4i32( %a, %a, %b) ret %x } @@ -1340,11 +1340,11 @@ define @vror_vx_nxv4i32( %a, i32 %b) { ; CHECK-RV64-NEXT: vor.vv v8, v12, v8 ; CHECK-RV64-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vx_nxv4i32: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e32, m2, ta, ma -; CHECK-ZVBB-NEXT: vror.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vx_nxv4i32: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e32, m2, ta, ma +; CHECK-ZVKB-NEXT: vror.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement poison, i32 %b, i32 0 %b.splat = shufflevector %b.head, poison, zeroinitializer %x = call @llvm.fshr.nxv4i32( %a, %a, %b.splat) @@ -1360,11 +1360,11 @@ define @vror_vi_nxv4i32( %a) { ; CHECK-NEXT: vor.vv v8, v8, v10 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_nxv4i32: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m2, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 1 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_nxv4i32: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a0, zero, e32, m2, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1 +; CHECK-ZVKB-NEXT: ret %x = call @llvm.fshr.nxv4i32( %a, %a, shufflevector( insertelement( poison, i32 1, i32 0), poison, zeroinitializer)) ret %x } @@ -1378,11 +1378,11 @@ define @vror_vi_rotl_nxv4i32( %a) { ; CHECK-NEXT: vor.vv v8, v8, v10 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_rotl_nxv4i32: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m2, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 31 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_rotl_nxv4i32: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a0, zero, e32, m2, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 31 +; CHECK-ZVKB-NEXT: ret %x = call @llvm.fshl.nxv4i32( %a, %a, shufflevector( insertelement( poison, i32 1, i32 0), poison, zeroinitializer)) ret %x } @@ -1403,11 +1403,11 @@ define @vror_vv_nxv8i32( %a, @llvm.fshr.nxv8i32( %a, %a, %b) ret %x } @@ -1437,11 +1437,11 @@ define @vror_vx_nxv8i32( %a, i32 %b) { ; CHECK-RV64-NEXT: vor.vv v8, v16, v8 ; CHECK-RV64-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vx_nxv8i32: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e32, m4, ta, ma -; CHECK-ZVBB-NEXT: vror.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vx_nxv8i32: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e32, m4, ta, ma +; CHECK-ZVKB-NEXT: vror.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement poison, i32 %b, i32 0 %b.splat = shufflevector %b.head, poison, zeroinitializer %x = call @llvm.fshr.nxv8i32( %a, %a, %b.splat) @@ -1457,11 +1457,11 @@ define @vror_vi_nxv8i32( %a) { ; CHECK-NEXT: vor.vv v8, v8, v12 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_nxv8i32: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 1 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_nxv8i32: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a0, zero, e32, m4, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1 +; CHECK-ZVKB-NEXT: ret %x = call @llvm.fshr.nxv8i32( %a, %a, shufflevector( insertelement( poison, i32 1, i32 0), poison, zeroinitializer)) ret %x } @@ -1475,11 +1475,11 @@ define @vror_vi_rotl_nxv8i32( %a) { ; CHECK-NEXT: vor.vv v8, v8, v12 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_rotl_nxv8i32: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 31 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_rotl_nxv8i32: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a0, zero, e32, m4, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 31 +; CHECK-ZVKB-NEXT: ret %x = call @llvm.fshl.nxv8i32( %a, %a, shufflevector( insertelement( poison, i32 1, i32 0), poison, zeroinitializer)) ret %x } @@ -1500,11 +1500,11 @@ define @vror_vv_nxv16i32( %a, @llvm.fshr.nxv16i32( %a, %a, %b) ret %x } @@ -1534,11 +1534,11 @@ define @vror_vx_nxv16i32( %a, i32 %b) { ; CHECK-RV64-NEXT: vor.vv v8, v24, v8 ; CHECK-RV64-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vx_nxv16i32: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e32, m8, ta, ma -; CHECK-ZVBB-NEXT: vror.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vx_nxv16i32: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e32, m8, ta, ma +; CHECK-ZVKB-NEXT: vror.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement poison, i32 %b, i32 0 %b.splat = shufflevector %b.head, poison, zeroinitializer %x = call @llvm.fshr.nxv16i32( %a, %a, %b.splat) @@ -1554,11 +1554,11 @@ define @vror_vi_nxv16i32( %a) { ; CHECK-NEXT: vor.vv v8, v8, v16 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_nxv16i32: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m8, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 1 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_nxv16i32: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a0, zero, e32, m8, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1 +; CHECK-ZVKB-NEXT: ret %x = call @llvm.fshr.nxv16i32( %a, %a, shufflevector( insertelement( poison, i32 1, i32 0), poison, zeroinitializer)) ret %x } @@ -1572,11 +1572,11 @@ define @vror_vi_rotl_nxv16i32( %a) { ; CHECK-NEXT: vor.vv v8, v8, v16 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_rotl_nxv16i32: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m8, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 31 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_rotl_nxv16i32: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a0, zero, e32, m8, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 31 +; CHECK-ZVKB-NEXT: ret %x = call @llvm.fshl.nxv16i32( %a, %a, shufflevector( insertelement( poison, i32 1, i32 0), poison, zeroinitializer)) ret %x } @@ -1597,11 +1597,11 @@ define @vror_vv_nxv1i64( %a, @llvm.fshr.nxv1i64( %a, %a, %b) ret %x } @@ -1631,11 +1631,11 @@ define @vror_vx_nxv1i64( %a, i64 %b) { ; CHECK-RV64-NEXT: vor.vv v8, v9, v8 ; CHECK-RV64-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vx_nxv1i64: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; CHECK-ZVBB-NEXT: vror.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vx_nxv1i64: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e64, m1, ta, ma +; CHECK-ZVKB-NEXT: vror.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement poison, i64 %b, i32 0 %b.splat = shufflevector %b.head, poison, zeroinitializer %x = call @llvm.fshr.nxv1i64( %a, %a, %b.splat) @@ -1652,11 +1652,11 @@ define @vror_vi_nxv1i64( %a) { ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_nxv1i64: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m1, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 1 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_nxv1i64: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a0, zero, e64, m1, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1 +; CHECK-ZVKB-NEXT: ret %x = call @llvm.fshr.nxv1i64( %a, %a, shufflevector( insertelement( poison, i64 1, i32 0), poison, zeroinitializer)) ret %x } @@ -1671,11 +1671,11 @@ define @vror_vi_rotl_nxv1i64( %a) { ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_rotl_nxv1i64: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m1, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 63 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_rotl_nxv1i64: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a0, zero, e64, m1, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 63 +; CHECK-ZVKB-NEXT: ret %x = call @llvm.fshl.nxv1i64( %a, %a, shufflevector( insertelement( poison, i64 1, i32 0), poison, zeroinitializer)) ret %x } @@ -1696,11 +1696,11 @@ define @vror_vv_nxv2i64( %a, @llvm.fshr.nxv2i64( %a, %a, %b) ret %x } @@ -1730,11 +1730,11 @@ define @vror_vx_nxv2i64( %a, i64 %b) { ; CHECK-RV64-NEXT: vor.vv v8, v10, v8 ; CHECK-RV64-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vx_nxv2i64: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; CHECK-ZVBB-NEXT: vror.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vx_nxv2i64: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e64, m2, ta, ma +; CHECK-ZVKB-NEXT: vror.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement poison, i64 %b, i32 0 %b.splat = shufflevector %b.head, poison, zeroinitializer %x = call @llvm.fshr.nxv2i64( %a, %a, %b.splat) @@ -1751,11 +1751,11 @@ define @vror_vi_nxv2i64( %a) { ; CHECK-NEXT: vor.vv v8, v8, v10 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_nxv2i64: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m2, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 1 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_nxv2i64: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a0, zero, e64, m2, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1 +; CHECK-ZVKB-NEXT: ret %x = call @llvm.fshr.nxv2i64( %a, %a, shufflevector( insertelement( poison, i64 1, i32 0), poison, zeroinitializer)) ret %x } @@ -1770,11 +1770,11 @@ define @vror_vi_rotl_nxv2i64( %a) { ; CHECK-NEXT: vor.vv v8, v8, v10 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_rotl_nxv2i64: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m2, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 63 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_rotl_nxv2i64: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a0, zero, e64, m2, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 63 +; CHECK-ZVKB-NEXT: ret %x = call @llvm.fshl.nxv2i64( %a, %a, shufflevector( insertelement( poison, i64 1, i32 0), poison, zeroinitializer)) ret %x } @@ -1795,11 +1795,11 @@ define @vror_vv_nxv4i64( %a, @llvm.fshr.nxv4i64( %a, %a, %b) ret %x } @@ -1829,11 +1829,11 @@ define @vror_vx_nxv4i64( %a, i64 %b) { ; CHECK-RV64-NEXT: vor.vv v8, v12, v8 ; CHECK-RV64-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vx_nxv4i64: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; CHECK-ZVBB-NEXT: vror.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vx_nxv4i64: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e64, m4, ta, ma +; CHECK-ZVKB-NEXT: vror.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement poison, i64 %b, i32 0 %b.splat = shufflevector %b.head, poison, zeroinitializer %x = call @llvm.fshr.nxv4i64( %a, %a, %b.splat) @@ -1850,11 +1850,11 @@ define @vror_vi_nxv4i64( %a) { ; CHECK-NEXT: vor.vv v8, v8, v12 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_nxv4i64: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m4, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 1 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_nxv4i64: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a0, zero, e64, m4, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1 +; CHECK-ZVKB-NEXT: ret %x = call @llvm.fshr.nxv4i64( %a, %a, shufflevector( insertelement( poison, i64 1, i32 0), poison, zeroinitializer)) ret %x } @@ -1869,11 +1869,11 @@ define @vror_vi_rotl_nxv4i64( %a) { ; CHECK-NEXT: vor.vv v8, v8, v12 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_rotl_nxv4i64: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m4, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 63 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_rotl_nxv4i64: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a0, zero, e64, m4, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 63 +; CHECK-ZVKB-NEXT: ret %x = call @llvm.fshl.nxv4i64( %a, %a, shufflevector( insertelement( poison, i64 1, i32 0), poison, zeroinitializer)) ret %x } @@ -1894,11 +1894,11 @@ define @vror_vv_nxv8i64( %a, @llvm.fshr.nxv8i64( %a, %a, %b) ret %x } @@ -1928,11 +1928,11 @@ define @vror_vx_nxv8i64( %a, i64 %b) { ; CHECK-RV64-NEXT: vor.vv v8, v16, v8 ; CHECK-RV64-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vx_nxv8i64: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; CHECK-ZVBB-NEXT: vror.vx v8, v8, a0 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vx_nxv8i64: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a1, zero, e64, m8, ta, ma +; CHECK-ZVKB-NEXT: vror.vx v8, v8, a0 +; CHECK-ZVKB-NEXT: ret %b.head = insertelement poison, i64 %b, i32 0 %b.splat = shufflevector %b.head, poison, zeroinitializer %x = call @llvm.fshr.nxv8i64( %a, %a, %b.splat) @@ -1949,11 +1949,11 @@ define @vror_vi_nxv8i64( %a) { ; CHECK-NEXT: vor.vv v8, v8, v16 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_nxv8i64: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m8, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 1 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_nxv8i64: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a0, zero, e64, m8, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1 +; CHECK-ZVKB-NEXT: ret %x = call @llvm.fshr.nxv8i64( %a, %a, shufflevector( insertelement( poison, i64 1, i32 0), poison, zeroinitializer)) ret %x } @@ -1968,11 +1968,11 @@ define @vror_vi_rotl_nxv8i64( %a) { ; CHECK-NEXT: vor.vv v8, v8, v16 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vror_vi_rotl_nxv8i64: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m8, ta, ma -; CHECK-ZVBB-NEXT: vror.vi v8, v8, 63 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVKB-LABEL: vror_vi_rotl_nxv8i64: +; CHECK-ZVKB: # %bb.0: +; CHECK-ZVKB-NEXT: vsetvli a0, zero, e64, m8, ta, ma +; CHECK-ZVKB-NEXT: vror.vi v8, v8, 63 +; CHECK-ZVKB-NEXT: ret %x = call @llvm.fshl.nxv8i64( %a, %a, shufflevector( insertelement( poison, i64 1, i32 0), poison, zeroinitializer)) ret %x }