diff --git a/clang/include/clang/Basic/riscv_vector.td b/clang/include/clang/Basic/riscv_vector.td index e7d78b03511fe..8bde081052505 100644 --- a/clang/include/clang/Basic/riscv_vector.td +++ b/clang/include/clang/Basic/riscv_vector.td @@ -117,7 +117,7 @@ multiclass RVVIndexedLoad { defvar eew = eew_list[0]; defvar eew_type = eew_list[1]; let Name = op # eew # "_v", IRName = op, MaskedIRName = op # "_mask", - RequiredFeatures = !if(!eq(type, "x"), ["ZvfhminOrZvfh"], + RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin"], []) in { def: RVVOutOp1Builtin<"v", "vPCe" # eew_type # "Uv", type>; if !not(IsFloat.val) then { @@ -128,7 +128,7 @@ multiclass RVVIndexedLoad { defvar eew64 = "64"; defvar eew64_type = "(Log2EEW:6)"; let Name = op # eew64 # "_v", IRName = op, MaskedIRName = op # "_mask", - RequiredFeatures = !if(!eq(type, "x"), ["ZvfhminOrZvfh", "RV64"], + RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin", "RV64"], ["RV64"]) in { def: RVVOutOp1Builtin<"v", "vPCe" # eew64_type # "Uv", type>; if !not(IsFloat.val) then { @@ -222,7 +222,7 @@ multiclass RVVIndexedStore { defvar eew = eew_list[0]; defvar eew_type = eew_list[1]; let Name = op # eew # "_v", IRName = op, MaskedIRName = op # "_mask", - RequiredFeatures = !if(!eq(type, "x"), ["ZvfhminOrZvfh"], + RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin"], []) in { def : RVVBuiltin<"v", "0Pe" # eew_type # "Uvv", type>; if !not(IsFloat.val) then { @@ -233,7 +233,7 @@ multiclass RVVIndexedStore { defvar eew64 = "64"; defvar eew64_type = "(Log2EEW:6)"; let Name = op # eew64 # "_v", IRName = op, MaskedIRName = op # "_mask", - RequiredFeatures = !if(!eq(type, "x"), ["ZvfhminOrZvfh", "RV64"], + RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin", "RV64"], ["RV64"]) in { def : RVVBuiltin<"v", "0Pe" # eew64_type # "Uvv", type>; if !not(IsFloat.val) then { @@ -681,7 +681,7 @@ let HasBuiltinAlias = false, def vlm: RVVVLEMaskBuiltin; defm vle8: RVVVLEBuiltin<["c"]>; defm vle16: RVVVLEBuiltin<["s"]>; -let Name = "vle16_v", RequiredFeatures = ["ZvfhminOrZvfh"] in +let Name = "vle16_v", RequiredFeatures = ["Zvfhmin"] in defm vle16_h: RVVVLEBuiltin<["x"]>; defm vle32: RVVVLEBuiltin<["i","f"]>; defm vle64: RVVVLEBuiltin<["l","d"]>; @@ -689,7 +689,7 @@ defm vle64: RVVVLEBuiltin<["l","d"]>; def vsm : RVVVSEMaskBuiltin; defm vse8 : RVVVSEBuiltin<["c"]>; defm vse16: RVVVSEBuiltin<["s"]>; -let Name = "vse16_v", RequiredFeatures = ["ZvfhminOrZvfh"] in +let Name = "vse16_v", RequiredFeatures = ["Zvfhmin"] in defm vse16_h: RVVVSEBuiltin<["x"]>; defm vse32: RVVVSEBuiltin<["i","f"]>; defm vse64: RVVVSEBuiltin<["l","d"]>; @@ -697,14 +697,14 @@ defm vse64: RVVVSEBuiltin<["l","d"]>; // 7.5. Vector Strided Instructions defm vlse8: RVVVLSEBuiltin<["c"]>; defm vlse16: RVVVLSEBuiltin<["s"]>; -let Name = "vlse16_v", RequiredFeatures = ["ZvfhminOrZvfh"] in +let Name = "vlse16_v", RequiredFeatures = ["Zvfhmin"] in defm vlse16_h: RVVVLSEBuiltin<["x"]>; defm vlse32: RVVVLSEBuiltin<["i","f"]>; defm vlse64: RVVVLSEBuiltin<["l","d"]>; defm vsse8 : RVVVSSEBuiltin<["c"]>; defm vsse16: RVVVSSEBuiltin<["s"]>; -let Name = "vsse16_v", RequiredFeatures = ["ZvfhminOrZvfh"] in +let Name = "vsse16_v", RequiredFeatures = ["Zvfhmin"] in defm vsse16_h: RVVVSSEBuiltin<["x"]>; defm vsse32: RVVVSSEBuiltin<["i","f"]>; defm vsse64: RVVVSSEBuiltin<["l","d"]>; @@ -719,7 +719,7 @@ defm : RVVIndexedStore<"vsoxei">; // 7.7. Unit-stride Fault-Only-First Loads defm vle8ff: RVVVLEFFBuiltin<["c"]>; defm vle16ff: RVVVLEFFBuiltin<["s"]>; -let Name = "vle16ff_v", RequiredFeatures = ["ZvfhminOrZvfh"] in +let Name = "vle16ff_v", RequiredFeatures = ["Zvfhmin"] in defm vle16ff: RVVVLEFFBuiltin<["x"]>; defm vle32ff: RVVVLEFFBuiltin<["i", "f"]>; defm vle64ff: RVVVLEFFBuiltin<["l", "d"]>; @@ -738,7 +738,7 @@ multiclass RVVUnitStridedSegLoadTuple { IRName = op # nf, MaskedIRName = op # nf # "_mask", NF = nf, - RequiredFeatures = !if(!eq(type, "x"), ["ZvfhminOrZvfh"], + RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin"], []), ManualCodegen = [{ { @@ -800,7 +800,7 @@ multiclass RVVUnitStridedSegStoreTuple { MaskedIRName = op # nf # "_mask", NF = nf, HasMaskedOffOperand = false, - RequiredFeatures = !if(!eq(type, "x"), ["ZvfhminOrZvfh"], + RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin"], []), ManualCodegen = [{ { @@ -852,7 +852,7 @@ multiclass RVVUnitStridedSegLoadFFTuple { IRName = op # nf # "ff", MaskedIRName = op # nf # "ff_mask", NF = nf, - RequiredFeatures = !if(!eq(type, "x"), ["ZvfhminOrZvfh"], + RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin"], []), ManualCodegen = [{ { @@ -927,7 +927,7 @@ multiclass RVVStridedSegLoadTuple { IRName = op # nf, MaskedIRName = op # nf # "_mask", NF = nf, - RequiredFeatures = !if(!eq(type, "x"), ["ZvfhminOrZvfh"], + RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin"], []), ManualCodegen = [{ { @@ -991,7 +991,7 @@ multiclass RVVStridedSegStoreTuple { NF = nf, HasMaskedOffOperand = false, MaskedPolicyScheme = NonePolicy, - RequiredFeatures = !if(!eq(type, "x"), ["ZvfhminOrZvfh"], + RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin"], []), ManualCodegen = [{ { @@ -1040,7 +1040,7 @@ multiclass RVVIndexedSegLoadTuple { IRName = op # nf, MaskedIRName = op # nf # "_mask", NF = nf, - RequiredFeatures = !if(!eq(type, "x"), ["ZvfhminOrZvfh"], + RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin"], []), ManualCodegen = [{ { @@ -1103,7 +1103,7 @@ multiclass RVVIndexedSegStoreTuple { NF = nf, HasMaskedOffOperand = false, MaskedPolicyScheme = NonePolicy, - RequiredFeatures = !if(!eq(type, "x"), ["ZvfhminOrZvfh"], + RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin"], []), ManualCodegen = [{ { @@ -1345,7 +1345,7 @@ let HasMasked = false, [["v", "Uv", "UvUv"]]>; defm vmv_v : RVVOutBuiltinSet<"vmv_v_v", "csilfd", [["v", "v", "vv"]]>; - let RequiredFeatures = ["ZvfhminOrZvfh"] in + let RequiredFeatures = ["Zvfhmin"] in defm vmv_v : RVVOutBuiltinSet<"vmv_v_v", "x", [["v", "v", "vv"]]>; let SupportOverloading = false in @@ -1841,7 +1841,7 @@ let HasMasked = false, }] in { defm vmerge : RVVOutOp1BuiltinSet<"vmerge", "fd", [["vvm", "v", "vvvm"]]>; - let RequiredFeatures = ["ZvfhminOrZvfh"] in + let RequiredFeatures = ["Zvfhmin"] in defm vmerge : RVVOutOp1BuiltinSet<"vmerge", "x", [["vvm", "v", "vvvm"]]>; defm vfmerge : RVVOutOp1BuiltinSet<"vfmerge", "xfd", @@ -1869,7 +1869,7 @@ let Log2LMUL = [-3, -2, -1, 0, 1, 2] in { def vfwcvt_f_xu_v : RVVConvBuiltin<"Fw", "FwUv", "csi", "vfwcvt_f">; def vfwcvt_f_x_v : RVVConvBuiltin<"Fw", "Fwv", "csi", "vfwcvt_f">; def vfwcvt_f_f_v : RVVConvBuiltin<"w", "wv", "f", "vfwcvt_f">; - let RequiredFeatures = ["ZvfhminOrZvfh"] in + let RequiredFeatures = ["Zvfhmin"] in def vfwcvt_f_f_v_fp16 : RVVConvBuiltin<"w", "wv", "x", "vfwcvt_f"> { let Name = "vfwcvt_f_f_v"; let IRName = "vfwcvt_f_f_v"; @@ -1966,7 +1966,7 @@ let ManualCodegen = [{ } let OverloadedName = "vfncvt_f" in { defm : RVVConvBuiltinSet<"vfncvt_f_f_w", "f", [["v", "vwu"]]>; - let RequiredFeatures = ["ZvfhminOrZvfh"] in + let RequiredFeatures = ["Zvfhmin"] in defm : RVVConvBuiltinSet<"vfncvt_f_f_w", "x", [["v", "vwu"]]>; } } @@ -2011,7 +2011,7 @@ let ManualCodegen = [{ } let OverloadedName = "vfncvt_f" in { defm : RVVConvBuiltinSet<"vfncvt_f_f_w", "f", [["v", "vw"]]>; - let RequiredFeatures = ["ZvfhminOrZvfh"] in + let RequiredFeatures = ["Zvfhmin"] in defm : RVVConvBuiltinSet<"vfncvt_f_f_w", "x", [["v", "vw"]]>; } } @@ -2271,7 +2271,7 @@ let HasMasked = false, HasVL = false, IRName = "" in { def vreinterpret_u_f : RVVBuiltin<"FvUv", "UvFv", "il", "Uv">; def vreinterpret_f_i : RVVBuiltin<"vFv", "Fvv", "il", "Fv">; def vreinterpret_f_u : RVVBuiltin<"UvFv", "FvUv", "il", "Fv">; - let RequiredFeatures = ["ZvfhminOrZvfh"] in { + let RequiredFeatures = ["Zvfhmin"] in { def vreinterpret_i_h : RVVBuiltin<"Fvv", "vFv", "s", "v">; def vreinterpret_u_h : RVVBuiltin<"FvUv", "UvFv", "s", "Uv">; def vreinterpret_h_i : RVVBuiltin<"vFv", "Fvv", "s", "Fv">; diff --git a/clang/include/clang/Support/RISCVVIntrinsicUtils.h b/clang/include/clang/Support/RISCVVIntrinsicUtils.h index c525d3443331e..05a5e02e13900 100644 --- a/clang/include/clang/Support/RISCVVIntrinsicUtils.h +++ b/clang/include/clang/Support/RISCVVIntrinsicUtils.h @@ -488,7 +488,7 @@ class RVVIntrinsic { enum RVVRequire : uint32_t { RVV_REQ_None = 0, RVV_REQ_RV64 = 1 << 0, - RVV_REQ_ZvfhminOrZvfh = 1 << 1, + RVV_REQ_Zvfhmin = 1 << 1, RVV_REQ_Xsfvcp = 1 << 2, RVV_REQ_Xsfvfnrclipxfqf = 1 << 3, RVV_REQ_Xsfvfwmaccqqq = 1 << 4, diff --git a/clang/lib/Sema/SemaRISCVVectorLookup.cpp b/clang/lib/Sema/SemaRISCVVectorLookup.cpp index 3ed3e61954418..00a5ea65f3f4e 100644 --- a/clang/lib/Sema/SemaRISCVVectorLookup.cpp +++ b/clang/lib/Sema/SemaRISCVVectorLookup.cpp @@ -274,9 +274,8 @@ void RISCVIntrinsicManagerImpl::ConstructRVVIntrinsics( continue; if (BaseType == BasicType::Float16) { - if ((Record.RequiredExtensions & RVV_REQ_ZvfhminOrZvfh) == - RVV_REQ_ZvfhminOrZvfh) { - if (!TI.hasFeature("zvfh") && !TI.hasFeature("zvfhmin")) + if ((Record.RequiredExtensions & RVV_REQ_Zvfhmin) == RVV_REQ_Zvfhmin) { + if (!TI.hasFeature("zvfhmin")) continue; } else if (!TI.hasFeature("zvfh")) { continue; diff --git a/clang/utils/TableGen/RISCVVEmitter.cpp b/clang/utils/TableGen/RISCVVEmitter.cpp index d570bcae8d863..2ca47f1ba59f3 100644 --- a/clang/utils/TableGen/RISCVVEmitter.cpp +++ b/clang/utils/TableGen/RISCVVEmitter.cpp @@ -656,7 +656,7 @@ void RVVEmitter::createRVVIntrinsics( RVVRequire RequireExt = StringSwitch(RequiredFeature) .Case("RV64", RVV_REQ_RV64) - .Case("ZvfhminOrZvfh", RVV_REQ_ZvfhminOrZvfh) + .Case("Zvfhmin", RVV_REQ_Zvfhmin) .Case("Xsfvcp", RVV_REQ_Xsfvcp) .Case("Xsfvfnrclipxfqf", RVV_REQ_Xsfvfnrclipxfqf) .Case("Xsfvfwmaccqqq", RVV_REQ_Xsfvfwmaccqqq)