diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 0cbf7bd9bd479..de909cc107956 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -6054,10 +6054,6 @@ static SDValue foldAndOrOfSETCC(SDNode *LogicOp, SelectionDAG &DAG) {
       TLI.isOperationLegal(ISD::SMAX, OpVT) &&
       TLI.isOperationLegal(ISD::UMIN, OpVT) &&
       TLI.isOperationLegal(ISD::SMIN, OpVT)) {
-    SDValue CommonValue;
-    SDValue Operand1;
-    SDValue Operand2;
-    ISD::CondCode CC = ISD::SETCC_INVALID;
     if (LHS->getOpcode() == ISD::SETCC && RHS->getOpcode() == ISD::SETCC &&
         LHS->hasOneUse() && RHS->hasOneUse() &&
         // The two comparisons should have either the same predicate or the
@@ -6065,6 +6061,8 @@ static SDValue foldAndOrOfSETCC(SDNode *LogicOp, SelectionDAG &DAG) {
         (CCL == CCR || CCL == ISD::getSetCCSwappedOperands(CCR)) &&
         // The optimization does not work for `==` or `!=` .
         !ISD::isIntEqualitySetCC(CCL) && !ISD::isIntEqualitySetCC(CCR)) {
+      SDValue CommonValue, Operand1, Operand2;
+      ISD::CondCode CC = ISD::SETCC_INVALID;
       if (CCL == CCR) {
         if (LHS0 == RHS0) {
           CommonValue = LHS0;
@@ -6077,7 +6075,8 @@ static SDValue foldAndOrOfSETCC(SDNode *LogicOp, SelectionDAG &DAG) {
           Operand2 = RHS0;
           CC = CCL;
         }
-      } else if (CCL == ISD::getSetCCSwappedOperands(CCR)) {
+      } else {
+        assert(CCL == ISD::getSetCCSwappedOperands(CCR) && "Unexpected CC");
         if (LHS0 == RHS1) {
           CommonValue = LHS0;
           Operand1 = LHS1;