diff --git a/llvm/test/CodeGen/AArch64/replace-intrinsics-with-veclib-armpl.ll b/llvm/test/CodeGen/AArch64/replace-intrinsics-with-veclib-armpl.ll index a38d4a53407c5..18431ae021f97 100644 --- a/llvm/test/CodeGen/AArch64/replace-intrinsics-with-veclib-armpl.ll +++ b/llvm/test/CodeGen/AArch64/replace-intrinsics-with-veclib-armpl.ll @@ -15,7 +15,7 @@ declare @llvm.cos.nxv2f64() declare @llvm.cos.nxv4f32() ;. -; CHECK: @[[LLVM_COMPILER_USED:[a-zA-Z0-9_$"\\.-]+]] = appending global [16 x ptr] [ptr @armpl_vcosq_f64, ptr @armpl_vcosq_f32, ptr @armpl_vsinq_f64, ptr @armpl_vsinq_f32, ptr @armpl_vexpq_f64, ptr @armpl_vexpq_f32, ptr @armpl_vexp2q_f64, ptr @armpl_vexp2q_f32, ptr @armpl_vexp10q_f64, ptr @armpl_vexp10q_f32, ptr @armpl_vlogq_f64, ptr @armpl_vlogq_f32, ptr @armpl_vlog2q_f64, ptr @armpl_vlog2q_f32, ptr @armpl_vlog10q_f64, ptr @armpl_vlog10q_f32], section "llvm.metadata" +; CHECK: @llvm.compiler.used = appending global [16 x ptr] [ptr @armpl_vcosq_f64, ptr @armpl_vcosq_f32, ptr @armpl_vsinq_f64, ptr @armpl_vsinq_f32, ptr @armpl_vexpq_f64, ptr @armpl_vexpq_f32, ptr @armpl_vexp2q_f64, ptr @armpl_vexp2q_f32, ptr @armpl_vexp10q_f64, ptr @armpl_vexp10q_f32, ptr @armpl_vlogq_f64, ptr @armpl_vlogq_f32, ptr @armpl_vlog2q_f64, ptr @armpl_vlog2q_f32, ptr @armpl_vlog10q_f64, ptr @armpl_vlog10q_f32], section "llvm.metadata" ;. define <2 x double> @llvm_cos_f64(<2 x double> %in) { ; CHECK-LABEL: define <2 x double> @llvm_cos_f64 diff --git a/llvm/test/CodeGen/AArch64/replace-intrinsics-with-veclib-sleef.ll b/llvm/test/CodeGen/AArch64/replace-intrinsics-with-veclib-sleef.ll index cedb7dd85149d..be247de368056 100644 --- a/llvm/test/CodeGen/AArch64/replace-intrinsics-with-veclib-sleef.ll +++ b/llvm/test/CodeGen/AArch64/replace-intrinsics-with-veclib-sleef.ll @@ -4,7 +4,7 @@ target triple = "aarch64-unknown-linux-gnu" ;. -; CHECK: @[[LLVM_COMPILER_USED:[a-zA-Z0-9_$"\\.-]+]] = appending global [16 x ptr] [ptr @_ZGVnN2v_cos, ptr @_ZGVnN4v_cosf, ptr @_ZGVnN2v_exp, ptr @_ZGVnN4v_expf, ptr @_ZGVnN2v_exp2, ptr @_ZGVnN4v_exp2f, ptr @_ZGVnN2v_exp10, ptr @_ZGVnN4v_exp10f, ptr @_ZGVnN2v_log, ptr @_ZGVnN4v_logf, ptr @_ZGVnN2v_log10, ptr @_ZGVnN4v_log10f, ptr @_ZGVnN2v_log2, ptr @_ZGVnN4v_log2f, ptr @_ZGVnN2v_sin, ptr @_ZGVnN4v_sinf], section "llvm.metadata" +; CHECK: @llvm.compiler.used = appending global [16 x ptr] [ptr @_ZGVnN2v_cos, ptr @_ZGVnN4v_cosf, ptr @_ZGVnN2v_exp, ptr @_ZGVnN4v_expf, ptr @_ZGVnN2v_exp2, ptr @_ZGVnN4v_exp2f, ptr @_ZGVnN2v_exp10, ptr @_ZGVnN4v_exp10f, ptr @_ZGVnN2v_log, ptr @_ZGVnN4v_logf, ptr @_ZGVnN2v_log10, ptr @_ZGVnN4v_log10f, ptr @_ZGVnN2v_log2, ptr @_ZGVnN4v_log2f, ptr @_ZGVnN2v_sin, ptr @_ZGVnN4v_sinf], section "llvm.metadata" ;. define <2 x double> @llvm_ceil_f64(<2 x double> %in) { ; CHECK-LABEL: @llvm_ceil_f64( diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/armpl-intrinsics.ll b/llvm/test/Transforms/LoopVectorize/AArch64/armpl-intrinsics.ll index 03d959c928577..07b1402b4697f 100644 --- a/llvm/test/Transforms/LoopVectorize/AArch64/armpl-intrinsics.ll +++ b/llvm/test/Transforms/LoopVectorize/AArch64/armpl-intrinsics.ll @@ -1,10 +1,9 @@ -; RUN: opt -vector-library=ArmPL -passes=inject-tli-mappings,loop-vectorize -S < %s | FileCheck %s --check-prefixes=CHECK,NEON -; RUN: opt -mattr=+sve -vector-library=ArmPL -passes=inject-tli-mappings,loop-vectorize -S < %s | FileCheck %s --check-prefixes=CHECK,SVE +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --filter "(\.|_v|_sv)(ceil|copysign|cos|exp\.|expf?\(|exp2|exp10|fabs|floor|fma|log|m..num|pow|nearbyint|rint|round|sin|sqrt|trunc)|(ret)" --version 2 +; RUN: opt -vector-library=ArmPL -passes=inject-tli-mappings,loop-vectorize -prefer-predicate-over-epilogue=predicate-dont-vectorize -S < %s | FileCheck %s --check-prefixes=NEON +; RUN: opt -mattr=+sve -vector-library=ArmPL -passes=inject-tli-mappings,loop-vectorize -prefer-predicate-over-epilogue=predicate-dont-vectorize -S < %s | FileCheck %s --check-prefixes=SVE -target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" target triple = "aarch64-unknown-linux-gnu" - ; Tests are checking if LV can vectorize loops with llvm math intrinsics ; using mappings from TLI for scalable and fixed width vectorization. @@ -12,10 +11,18 @@ declare double @llvm.cos.f64(double) declare float @llvm.cos.f32(float) define void @cos_f64(ptr nocapture %in.ptr, ptr %out.ptr) { -; CHECK-LABEL: @cos_f64( -; NEON: [[TMP5:%.*]] = call <2 x double> @armpl_vcosq_f64(<2 x double> [[TMP4:%.*]]) -; SVE: [[TMP5:%.*]] = call @armpl_svcos_f64_x( [[TMP4:%.*]], {{.*}}) -; CHECK: ret void +; +; NEON-LABEL: define void @cos_f64 +; NEON-SAME: (ptr nocapture [[IN_PTR:%.*]], ptr [[OUT_PTR:%.*]]) { +; NEON: [[TMP4:%.*]] = call <2 x double> @armpl_vcosq_f64(<2 x double> [[WIDE_LOAD:%.*]]) +; NEON: [[CALL:%.*]] = tail call double @llvm.cos.f64(double [[IN:%.*]]) #[[ATTR1:[0-9]+]] +; NEON: ret void +; +; SVE-LABEL: define void @cos_f64 +; SVE-SAME: (ptr nocapture [[IN_PTR:%.*]], ptr [[OUT_PTR:%.*]]) #[[ATTR1:[0-9]+]] { +; SVE: [[TMP17:%.*]] = call @armpl_svcos_f64_x( [[WIDE_MASKED_LOAD:%.*]], [[ACTIVE_LANE_MASK:%.*]]) +; SVE: [[CALL:%.*]] = tail call double @llvm.cos.f64(double [[IN:%.*]]) #[[ATTR5:[0-9]+]] +; SVE: ret void ; entry: br label %for.body @@ -36,10 +43,17 @@ define void @cos_f64(ptr nocapture %in.ptr, ptr %out.ptr) { } define void @cos_f32(ptr nocapture %in.ptr, ptr %out.ptr) { -; CHECK-LABEL: @cos_f32( -; NEON: [[TMP5:%.*]] = call <4 x float> @armpl_vcosq_f32(<4 x float> [[TMP4:%.*]]) -; SVE: [[TMP5:%.*]] = call @armpl_svcos_f32_x( [[TMP4:%.*]], {{.*}}) -; CHECK: ret void +; NEON-LABEL: define void @cos_f32 +; NEON-SAME: (ptr nocapture [[IN_PTR:%.*]], ptr [[OUT_PTR:%.*]]) { +; NEON: [[TMP4:%.*]] = call <4 x float> @armpl_vcosq_f32(<4 x float> [[WIDE_LOAD:%.*]]) +; NEON: [[CALL:%.*]] = tail call float @llvm.cos.f32(float [[IN:%.*]]) #[[ATTR2:[0-9]+]] +; NEON: ret void +; +; SVE-LABEL: define void @cos_f32 +; SVE-SAME: (ptr nocapture [[IN_PTR:%.*]], ptr [[OUT_PTR:%.*]]) #[[ATTR1]] { +; SVE: [[TMP17:%.*]] = call @armpl_svcos_f32_x( [[WIDE_MASKED_LOAD:%.*]], [[ACTIVE_LANE_MASK:%.*]]) +; SVE: [[CALL:%.*]] = tail call float @llvm.cos.f32(float [[IN:%.*]]) #[[ATTR6:[0-9]+]] +; SVE: ret void ; entry: br label %for.body @@ -63,10 +77,15 @@ declare double @llvm.exp.f64(double) declare float @llvm.exp.f32(float) define void @exp_f64(ptr nocapture %in.ptr, ptr %out.ptr) { -; CHECK-LABEL: @exp_f64( -; NEON: [[TMP5:%.*]] = call <2 x double> @armpl_vexpq_f64(<2 x double> [[TMP4:%.*]]) -; SVE: [[TMP5:%.*]] = call @armpl_svexp_f64_x( [[TMP4:%.*]], {{.*}}) -; CHECK: ret void +; NEON-LABEL: define void @exp_f64 +; NEON-SAME: (ptr nocapture [[IN_PTR:%.*]], ptr [[OUT_PTR:%.*]]) { +; NEON: [[CALL:%.*]] = tail call double @llvm.exp.f64(double [[IN:%.*]]) #[[ATTR3:[0-9]+]] +; NEON: ret void +; +; SVE-LABEL: define void @exp_f64 +; SVE-SAME: (ptr nocapture [[IN_PTR:%.*]], ptr [[OUT_PTR:%.*]]) #[[ATTR1]] { +; SVE: [[CALL:%.*]] = tail call double @llvm.exp.f64(double [[IN:%.*]]) #[[ATTR7:[0-9]+]] +; SVE: ret void ; entry: br label %for.body @@ -87,10 +106,15 @@ define void @exp_f64(ptr nocapture %in.ptr, ptr %out.ptr) { } define void @exp_f32(ptr nocapture %in.ptr, ptr %out.ptr) { -; CHECK-LABEL: @exp_f32( -; NEON: [[TMP5:%.*]] = call <4 x float> @armpl_vexpq_f32(<4 x float> [[TMP4:%.*]]) -; SVE: [[TMP5:%.*]] = call @armpl_svexp_f32_x( [[TMP4:%.*]], {{.*}}) -; CHECK: ret void +; NEON-LABEL: define void @exp_f32 +; NEON-SAME: (ptr nocapture [[IN_PTR:%.*]], ptr [[OUT_PTR:%.*]]) { +; NEON: [[CALL:%.*]] = tail call float @llvm.exp.f32(float [[IN:%.*]]) #[[ATTR4:[0-9]+]] +; NEON: ret void +; +; SVE-LABEL: define void @exp_f32 +; SVE-SAME: (ptr nocapture [[IN_PTR:%.*]], ptr [[OUT_PTR:%.*]]) #[[ATTR1]] { +; SVE: [[CALL:%.*]] = tail call float @llvm.exp.f32(float [[IN:%.*]]) #[[ATTR8:[0-9]+]] +; SVE: ret void ; entry: br label %for.body @@ -114,10 +138,17 @@ declare double @llvm.exp2.f64(double) declare float @llvm.exp2.f32(float) define void @exp2_f64(ptr nocapture %in.ptr, ptr %out.ptr) { -; CHECK-LABEL: @exp2_f64( -; NEON: [[TMP5:%.*]] = call <2 x double> @armpl_vexp2q_f64(<2 x double> [[TMP4:%.*]]) -; SVE: [[TMP5:%.*]] = call @armpl_svexp2_f64_x( [[TMP4:%.*]], {{.*}}) -; CHECK: ret void +; NEON-LABEL: define void @exp2_f64 +; NEON-SAME: (ptr nocapture [[IN_PTR:%.*]], ptr [[OUT_PTR:%.*]]) { +; NEON: [[TMP4:%.*]] = call <2 x double> @armpl_vexp2q_f64(<2 x double> [[WIDE_LOAD:%.*]]) +; NEON: [[CALL:%.*]] = tail call double @llvm.exp2.f64(double [[IN:%.*]]) #[[ATTR5:[0-9]+]] +; NEON: ret void +; +; SVE-LABEL: define void @exp2_f64 +; SVE-SAME: (ptr nocapture [[IN_PTR:%.*]], ptr [[OUT_PTR:%.*]]) #[[ATTR1]] { +; SVE: [[TMP17:%.*]] = call @armpl_svexp2_f64_x( [[WIDE_MASKED_LOAD:%.*]], [[ACTIVE_LANE_MASK:%.*]]) +; SVE: [[CALL:%.*]] = tail call double @llvm.exp2.f64(double [[IN:%.*]]) #[[ATTR9:[0-9]+]] +; SVE: ret void ; entry: br label %for.body @@ -138,10 +169,17 @@ define void @exp2_f64(ptr nocapture %in.ptr, ptr %out.ptr) { } define void @exp2_f32(ptr nocapture %in.ptr, ptr %out.ptr) { -; CHECK-LABEL: @exp2_f32( -; NEON: [[TMP5:%.*]] = call <4 x float> @armpl_vexp2q_f32(<4 x float> [[TMP4:%.*]]) -; SVE: [[TMP5:%.*]] = call @armpl_svexp2_f32_x( [[TMP4:%.*]], {{.*}}) -; CHECK: ret void +; NEON-LABEL: define void @exp2_f32 +; NEON-SAME: (ptr nocapture [[IN_PTR:%.*]], ptr [[OUT_PTR:%.*]]) { +; NEON: [[TMP4:%.*]] = call <4 x float> @armpl_vexp2q_f32(<4 x float> [[WIDE_LOAD:%.*]]) +; NEON: [[CALL:%.*]] = tail call float @llvm.exp2.f32(float [[IN:%.*]]) #[[ATTR6:[0-9]+]] +; NEON: ret void +; +; SVE-LABEL: define void @exp2_f32 +; SVE-SAME: (ptr nocapture [[IN_PTR:%.*]], ptr [[OUT_PTR:%.*]]) #[[ATTR1]] { +; SVE: [[TMP17:%.*]] = call @armpl_svexp2_f32_x( [[WIDE_MASKED_LOAD:%.*]], [[ACTIVE_LANE_MASK:%.*]]) +; SVE: [[CALL:%.*]] = tail call float @llvm.exp2.f32(float [[IN:%.*]]) #[[ATTR10:[0-9]+]] +; SVE: ret void ; entry: br label %for.body @@ -165,10 +203,17 @@ declare double @llvm.exp10.f64(double) declare float @llvm.exp10.f32(float) define void @exp10_f64(ptr nocapture %in.ptr, ptr %out.ptr) { -; CHECK-LABEL: @exp10_f64( -; NEON: [[TMP5:%.*]] = call <2 x double> @armpl_vexp10q_f64(<2 x double> [[TMP4:%.*]]) -; SVE: [[TMP5:%.*]] = call @armpl_svexp10_f64_x( [[TMP4:%.*]], {{.*}}) -; CHECK: ret void +; NEON-LABEL: define void @exp10_f64 +; NEON-SAME: (ptr nocapture [[IN_PTR:%.*]], ptr [[OUT_PTR:%.*]]) { +; NEON: [[TMP4:%.*]] = call <2 x double> @armpl_vexp10q_f64(<2 x double> [[WIDE_LOAD:%.*]]) +; NEON: [[CALL:%.*]] = tail call double @llvm.exp10.f64(double [[IN:%.*]]) #[[ATTR7:[0-9]+]] +; NEON: ret void +; +; SVE-LABEL: define void @exp10_f64 +; SVE-SAME: (ptr nocapture [[IN_PTR:%.*]], ptr [[OUT_PTR:%.*]]) #[[ATTR1]] { +; SVE: [[TMP17:%.*]] = call @armpl_svexp10_f64_x( [[WIDE_MASKED_LOAD:%.*]], [[ACTIVE_LANE_MASK:%.*]]) +; SVE: [[CALL:%.*]] = tail call double @llvm.exp10.f64(double [[IN:%.*]]) #[[ATTR11:[0-9]+]] +; SVE: ret void ; entry: br label %for.body @@ -189,10 +234,17 @@ define void @exp10_f64(ptr nocapture %in.ptr, ptr %out.ptr) { } define void @exp10_f32(ptr nocapture %in.ptr, ptr %out.ptr) { -; CHECK-LABEL: @exp10_f32( -; NEON: [[TMP5:%.*]] = call <4 x float> @armpl_vexp10q_f32(<4 x float> [[TMP4:%.*]]) -; SVE: [[TMP5:%.*]] = call @armpl_svexp10_f32_x( [[TMP4:%.*]], {{.*}}) -; CHECK: ret void +; NEON-LABEL: define void @exp10_f32 +; NEON-SAME: (ptr nocapture [[IN_PTR:%.*]], ptr [[OUT_PTR:%.*]]) { +; NEON: [[TMP4:%.*]] = call <4 x float> @armpl_vexp10q_f32(<4 x float> [[WIDE_LOAD:%.*]]) +; NEON: [[CALL:%.*]] = tail call float @llvm.exp10.f32(float [[IN:%.*]]) #[[ATTR8:[0-9]+]] +; NEON: ret void +; +; SVE-LABEL: define void @exp10_f32 +; SVE-SAME: (ptr nocapture [[IN_PTR:%.*]], ptr [[OUT_PTR:%.*]]) #[[ATTR1]] { +; SVE: [[TMP17:%.*]] = call @armpl_svexp10_f32_x( [[WIDE_MASKED_LOAD:%.*]], [[ACTIVE_LANE_MASK:%.*]]) +; SVE: [[CALL:%.*]] = tail call float @llvm.exp10.f32(float [[IN:%.*]]) #[[ATTR12:[0-9]+]] +; SVE: ret void ; entry: br label %for.body @@ -216,10 +268,17 @@ declare double @llvm.log.f64(double) declare float @llvm.log.f32(float) define void @log_f64(ptr nocapture %in.ptr, ptr %out.ptr) { -; CHECK-LABEL: @log_f64( -; NEON: [[TMP5:%.*]] = call <2 x double> @armpl_vlogq_f64(<2 x double> [[TMP4:%.*]]) -; SVE: [[TMP5:%.*]] = call @armpl_svlog_f64_x( [[TMP4:%.*]], {{.*}}) -; CHECK: ret void +; NEON-LABEL: define void @log_f64 +; NEON-SAME: (ptr nocapture [[IN_PTR:%.*]], ptr [[OUT_PTR:%.*]]) { +; NEON: [[TMP4:%.*]] = call <2 x double> @armpl_vlogq_f64(<2 x double> [[WIDE_LOAD:%.*]]) +; NEON: [[CALL:%.*]] = tail call double @llvm.log.f64(double [[IN:%.*]]) #[[ATTR9:[0-9]+]] +; NEON: ret void +; +; SVE-LABEL: define void @log_f64 +; SVE-SAME: (ptr nocapture [[IN_PTR:%.*]], ptr [[OUT_PTR:%.*]]) #[[ATTR1]] { +; SVE: [[TMP17:%.*]] = call @armpl_svlog_f64_x( [[WIDE_MASKED_LOAD:%.*]], [[ACTIVE_LANE_MASK:%.*]]) +; SVE: [[CALL:%.*]] = tail call double @llvm.log.f64(double [[IN:%.*]]) #[[ATTR13:[0-9]+]] +; SVE: ret void ; entry: br label %for.body @@ -240,10 +299,17 @@ define void @log_f64(ptr nocapture %in.ptr, ptr %out.ptr) { } define void @log_f32(ptr nocapture %in.ptr, ptr %out.ptr) { -; CHECK-LABEL: @log_f32( -; NEON: [[TMP5:%.*]] = call <4 x float> @armpl_vlogq_f32(<4 x float> [[TMP4:%.*]]) -; SVE: [[TMP5:%.*]] = call @armpl_svlog_f32_x( [[TMP4:%.*]], {{.*}}) -; CHECK: ret void +; NEON-LABEL: define void @log_f32 +; NEON-SAME: (ptr nocapture [[IN_PTR:%.*]], ptr [[OUT_PTR:%.*]]) { +; NEON: [[TMP4:%.*]] = call <4 x float> @armpl_vlogq_f32(<4 x float> [[WIDE_LOAD:%.*]]) +; NEON: [[CALL:%.*]] = tail call float @llvm.log.f32(float [[IN:%.*]]) #[[ATTR10:[0-9]+]] +; NEON: ret void +; +; SVE-LABEL: define void @log_f32 +; SVE-SAME: (ptr nocapture [[IN_PTR:%.*]], ptr [[OUT_PTR:%.*]]) #[[ATTR1]] { +; SVE: [[TMP17:%.*]] = call @armpl_svlog_f32_x( [[WIDE_MASKED_LOAD:%.*]], [[ACTIVE_LANE_MASK:%.*]]) +; SVE: [[CALL:%.*]] = tail call float @llvm.log.f32(float [[IN:%.*]]) #[[ATTR14:[0-9]+]] +; SVE: ret void ; entry: br label %for.body @@ -267,10 +333,17 @@ declare double @llvm.log2.f64(double) declare float @llvm.log2.f32(float) define void @log2_f64(ptr nocapture %in.ptr, ptr %out.ptr) { -; CHECK-LABEL: @log2_f64( -; NEON: [[TMP5:%.*]] = call <2 x double> @armpl_vlog2q_f64(<2 x double> [[TMP4:%.*]]) -; SVE: [[TMP5:%.*]] = call @armpl_svlog2_f64_x( [[TMP4:%.*]], {{.*}}) -; CHECK: ret void +; NEON-LABEL: define void @log2_f64 +; NEON-SAME: (ptr nocapture [[IN_PTR:%.*]], ptr [[OUT_PTR:%.*]]) { +; NEON: [[TMP4:%.*]] = call <2 x double> @armpl_vlog2q_f64(<2 x double> [[WIDE_LOAD:%.*]]) +; NEON: [[CALL:%.*]] = tail call double @llvm.log2.f64(double [[IN:%.*]]) #[[ATTR11:[0-9]+]] +; NEON: ret void +; +; SVE-LABEL: define void @log2_f64 +; SVE-SAME: (ptr nocapture [[IN_PTR:%.*]], ptr [[OUT_PTR:%.*]]) #[[ATTR1]] { +; SVE: [[TMP17:%.*]] = call @armpl_svlog2_f64_x( [[WIDE_MASKED_LOAD:%.*]], [[ACTIVE_LANE_MASK:%.*]]) +; SVE: [[CALL:%.*]] = tail call double @llvm.log2.f64(double [[IN:%.*]]) #[[ATTR15:[0-9]+]] +; SVE: ret void ; entry: br label %for.body @@ -291,10 +364,17 @@ define void @log2_f64(ptr nocapture %in.ptr, ptr %out.ptr) { } define void @log2_f32(ptr nocapture %in.ptr, ptr %out.ptr) { -; CHECK-LABEL: @log2_f32( -; NEON: [[TMP5:%.*]] = call <4 x float> @armpl_vlog2q_f32(<4 x float> [[TMP4:%.*]]) -; SVE: [[TMP5:%.*]] = call @armpl_svlog2_f32_x( [[TMP4:%.*]], {{.*}}) -; CHECK: ret void +; NEON-LABEL: define void @log2_f32 +; NEON-SAME: (ptr nocapture [[IN_PTR:%.*]], ptr [[OUT_PTR:%.*]]) { +; NEON: [[TMP4:%.*]] = call <4 x float> @armpl_vlog2q_f32(<4 x float> [[WIDE_LOAD:%.*]]) +; NEON: [[CALL:%.*]] = tail call float @llvm.log2.f32(float [[IN:%.*]]) #[[ATTR12:[0-9]+]] +; NEON: ret void +; +; SVE-LABEL: define void @log2_f32 +; SVE-SAME: (ptr nocapture [[IN_PTR:%.*]], ptr [[OUT_PTR:%.*]]) #[[ATTR1]] { +; SVE: [[TMP17:%.*]] = call @armpl_svlog2_f32_x( [[WIDE_MASKED_LOAD:%.*]], [[ACTIVE_LANE_MASK:%.*]]) +; SVE: [[CALL:%.*]] = tail call float @llvm.log2.f32(float [[IN:%.*]]) #[[ATTR16:[0-9]+]] +; SVE: ret void ; entry: br label %for.body @@ -318,10 +398,17 @@ declare double @llvm.log10.f64(double) declare float @llvm.log10.f32(float) define void @log10_f64(ptr nocapture %in.ptr, ptr %out.ptr) { -; CHECK-LABEL: @log10_f64( -; NEON: [[TMP5:%.*]] = call <2 x double> @armpl_vlog10q_f64(<2 x double> [[TMP4:%.*]]) -; SVE: [[TMP5:%.*]] = call @armpl_svlog10_f64_x( [[TMP4:%.*]], {{.*}}) -; CHECK: ret void +; NEON-LABEL: define void @log10_f64 +; NEON-SAME: (ptr nocapture [[IN_PTR:%.*]], ptr [[OUT_PTR:%.*]]) { +; NEON: [[TMP4:%.*]] = call <2 x double> @armpl_vlog10q_f64(<2 x double> [[WIDE_LOAD:%.*]]) +; NEON: [[CALL:%.*]] = tail call double @llvm.log10.f64(double [[IN:%.*]]) #[[ATTR13:[0-9]+]] +; NEON: ret void +; +; SVE-LABEL: define void @log10_f64 +; SVE-SAME: (ptr nocapture [[IN_PTR:%.*]], ptr [[OUT_PTR:%.*]]) #[[ATTR1]] { +; SVE: [[TMP17:%.*]] = call @armpl_svlog10_f64_x( [[WIDE_MASKED_LOAD:%.*]], [[ACTIVE_LANE_MASK:%.*]]) +; SVE: [[CALL:%.*]] = tail call double @llvm.log10.f64(double [[IN:%.*]]) #[[ATTR17:[0-9]+]] +; SVE: ret void ; entry: br label %for.body @@ -342,10 +429,17 @@ define void @log10_f64(ptr nocapture %in.ptr, ptr %out.ptr) { } define void @log10_f32(ptr nocapture %in.ptr, ptr %out.ptr) { -; CHECK-LABEL: @log10_f32( -; NEON: [[TMP5:%.*]] = call <4 x float> @armpl_vlog10q_f32(<4 x float> [[TMP4:%.*]]) -; SVE: [[TMP5:%.*]] = call @armpl_svlog10_f32_x( [[TMP4:%.*]], {{.*}}) -; CHECK: ret void +; NEON-LABEL: define void @log10_f32 +; NEON-SAME: (ptr nocapture [[IN_PTR:%.*]], ptr [[OUT_PTR:%.*]]) { +; NEON: [[TMP4:%.*]] = call <4 x float> @armpl_vlog10q_f32(<4 x float> [[WIDE_LOAD:%.*]]) +; NEON: [[CALL:%.*]] = tail call float @llvm.log10.f32(float [[IN:%.*]]) #[[ATTR14:[0-9]+]] +; NEON: ret void +; +; SVE-LABEL: define void @log10_f32 +; SVE-SAME: (ptr nocapture [[IN_PTR:%.*]], ptr [[OUT_PTR:%.*]]) #[[ATTR1]] { +; SVE: [[TMP17:%.*]] = call @armpl_svlog10_f32_x( [[WIDE_MASKED_LOAD:%.*]], [[ACTIVE_LANE_MASK:%.*]]) +; SVE: [[CALL:%.*]] = tail call float @llvm.log10.f32(float [[IN:%.*]]) #[[ATTR18:[0-9]+]] +; SVE: ret void ; entry: br label %for.body @@ -369,10 +463,17 @@ declare double @llvm.sin.f64(double) declare float @llvm.sin.f32(float) define void @sin_f64(ptr nocapture %in.ptr, ptr %out.ptr) { -; CHECK-LABEL: @sin_f64( -; NEON: [[TMP5:%.*]] = call <2 x double> @armpl_vsinq_f64(<2 x double> [[TMP4:%.*]]) -; SVE: [[TMP5:%.*]] = call @armpl_svsin_f64_x( [[TMP4:%.*]], {{.*}}) -; CHECK: ret void +; NEON-LABEL: define void @sin_f64 +; NEON-SAME: (ptr nocapture [[IN_PTR:%.*]], ptr [[OUT_PTR:%.*]]) { +; NEON: [[TMP4:%.*]] = call <2 x double> @armpl_vsinq_f64(<2 x double> [[WIDE_LOAD:%.*]]) +; NEON: [[CALL:%.*]] = tail call double @llvm.sin.f64(double [[IN:%.*]]) #[[ATTR15:[0-9]+]] +; NEON: ret void +; +; SVE-LABEL: define void @sin_f64 +; SVE-SAME: (ptr nocapture [[IN_PTR:%.*]], ptr [[OUT_PTR:%.*]]) #[[ATTR1]] { +; SVE: [[TMP17:%.*]] = call @armpl_svsin_f64_x( [[WIDE_MASKED_LOAD:%.*]], [[ACTIVE_LANE_MASK:%.*]]) +; SVE: [[CALL:%.*]] = tail call double @llvm.sin.f64(double [[IN:%.*]]) #[[ATTR19:[0-9]+]] +; SVE: ret void ; entry: br label %for.body @@ -393,10 +494,17 @@ define void @sin_f64(ptr nocapture %in.ptr, ptr %out.ptr) { } define void @sin_f32(ptr nocapture %in.ptr, ptr %out.ptr) { -; CHECK-LABEL: @sin_f32( -; NEON: [[TMP5:%.*]] = call <4 x float> @armpl_vsinq_f32(<4 x float> [[TMP4:%.*]]) -; SVE: [[TMP5:%.*]] = call @armpl_svsin_f32_x( [[TMP4:%.*]], {{.*}}) -; CHECK: ret void +; NEON-LABEL: define void @sin_f32 +; NEON-SAME: (ptr nocapture [[IN_PTR:%.*]], ptr [[OUT_PTR:%.*]]) { +; NEON: [[TMP4:%.*]] = call <4 x float> @armpl_vsinq_f32(<4 x float> [[WIDE_LOAD:%.*]]) +; NEON: [[CALL:%.*]] = tail call float @llvm.sin.f32(float [[IN:%.*]]) #[[ATTR16:[0-9]+]] +; NEON: ret void +; +; SVE-LABEL: define void @sin_f32 +; SVE-SAME: (ptr nocapture [[IN_PTR:%.*]], ptr [[OUT_PTR:%.*]]) #[[ATTR1]] { +; SVE: [[TMP17:%.*]] = call @armpl_svsin_f32_x( [[WIDE_MASKED_LOAD:%.*]], [[ACTIVE_LANE_MASK:%.*]]) +; SVE: [[CALL:%.*]] = tail call float @llvm.sin.f32(float [[IN:%.*]]) #[[ATTR20:[0-9]+]] +; SVE: ret void ; entry: br label %for.body @@ -420,10 +528,17 @@ declare double @llvm.pow.f64(double, double) declare float @llvm.pow.f32(float, float) define void @pow_f64(ptr nocapture %in.ptr, ptr %out.ptr) { -; CHECK-LABEL: @pow_f64( -; NEON: [[TMP5:%.*]] = call <2 x double> @armpl_vpowq_f64(<2 x double> [[TMP4:%.*]], <2 x double> [[TMP4:%.*]]) -; SVE: [[TMP5:%.*]] = call @armpl_svpow_f64_x( [[TMP4:%.*]], [[TMP4:%.*]], {{.*}}) -; CHECK: ret void +; NEON-LABEL: define void @pow_f64 +; NEON-SAME: (ptr nocapture [[IN_PTR:%.*]], ptr [[OUT_PTR:%.*]]) { +; NEON: [[TMP4:%.*]] = call <2 x double> @armpl_vpowq_f64(<2 x double> [[WIDE_LOAD:%.*]], <2 x double> [[WIDE_LOAD]]) +; NEON: [[CALL:%.*]] = tail call double @llvm.pow.f64(double [[IN:%.*]], double [[IN]]) #[[ATTR17:[0-9]+]] +; NEON: ret void +; +; SVE-LABEL: define void @pow_f64 +; SVE-SAME: (ptr nocapture [[IN_PTR:%.*]], ptr [[OUT_PTR:%.*]]) #[[ATTR1]] { +; SVE: [[TMP17:%.*]] = call @armpl_svpow_f64_x( [[WIDE_MASKED_LOAD:%.*]], [[WIDE_MASKED_LOAD]], [[ACTIVE_LANE_MASK:%.*]]) +; SVE: [[CALL:%.*]] = tail call double @llvm.pow.f64(double [[IN:%.*]], double [[IN]]) #[[ATTR21:[0-9]+]] +; SVE: ret void ; entry: br label %for.body @@ -444,10 +559,17 @@ define void @pow_f64(ptr nocapture %in.ptr, ptr %out.ptr) { } define void @pow_f32(ptr nocapture %in.ptr, ptr %out.ptr) { -; CHECK-LABEL: @pow_f32( -; NEON: [[TMP5:%.*]] = call <4 x float> @armpl_vpowq_f32(<4 x float> [[TMP4:%.*]], <4 x float> [[TMP4:%.*]]) -; SVE: [[TMP5:%.*]] = call @armpl_svpow_f32_x( [[TMP4:%.*]], [[TMP4:%.*]], {{.*}}) -; CHECK: ret void +; NEON-LABEL: define void @pow_f32 +; NEON-SAME: (ptr nocapture [[IN_PTR:%.*]], ptr [[OUT_PTR:%.*]]) { +; NEON: [[TMP4:%.*]] = call <4 x float> @armpl_vpowq_f32(<4 x float> [[WIDE_LOAD:%.*]], <4 x float> [[WIDE_LOAD]]) +; NEON: [[CALL:%.*]] = tail call float @llvm.pow.f32(float [[IN:%.*]], float [[IN]]) #[[ATTR18:[0-9]+]] +; NEON: ret void +; +; SVE-LABEL: define void @pow_f32 +; SVE-SAME: (ptr nocapture [[IN_PTR:%.*]], ptr [[OUT_PTR:%.*]]) #[[ATTR1]] { +; SVE: [[TMP17:%.*]] = call @armpl_svpow_f32_x( [[WIDE_MASKED_LOAD:%.*]], [[WIDE_MASKED_LOAD]], [[ACTIVE_LANE_MASK:%.*]]) +; SVE: [[CALL:%.*]] = tail call float @llvm.pow.f32(float [[IN:%.*]], float [[IN]]) #[[ATTR22:[0-9]+]] +; SVE: ret void ; entry: br label %for.body @@ -466,4 +588,3 @@ define void @pow_f32(ptr nocapture %in.ptr, ptr %out.ptr) { for.end: ret void } - diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/sleef-intrinsic-calls-aarch64.ll b/llvm/test/Transforms/LoopVectorize/AArch64/sleef-intrinsic-calls-aarch64.ll index 01ce3657835a4..2b95a861c358b 100644 --- a/llvm/test/Transforms/LoopVectorize/AArch64/sleef-intrinsic-calls-aarch64.ll +++ b/llvm/test/Transforms/LoopVectorize/AArch64/sleef-intrinsic-calls-aarch64.ll @@ -1,11 +1,9 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --filter "(\.|_)(ceil|copysign|cos|exp\.|expf?\(|exp2|exp10|fabs|floor|fma|log|m..num|pow|.*int|round|sin|sqrt|trunc)|(ret)" --version 2 -; RUN: opt -vector-library=sleefgnuabi -passes=inject-tli-mappings,loop-vectorize -force-vector-interleave=1 -S < %s | FileCheck %s --check-prefix=NEON -; RUN: opt -mattr=+sve -vector-library=sleefgnuabi -passes=inject-tli-mappings,loop-vectorize -force-vector-interleave=1 -S < %s | FileCheck %s --check-prefix=SVE +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --filter "(\.|_)(ceil|copysign|cos|exp\.|expf?\(|exp2|exp10|fabs|floor|fma|log|m..num|pow|nearbyint|rint|round|sin|sqrt|trunc)|(ret)" --version 2 +; RUN: opt -vector-library=sleefgnuabi -passes=inject-tli-mappings,loop-vectorize -force-vector-interleave=1 -prefer-predicate-over-epilogue=predicate-dont-vectorize -S < %s | FileCheck %s --check-prefix=NEON +; RUN: opt -mattr=+sve -vector-library=sleefgnuabi -passes=inject-tli-mappings,loop-vectorize -force-vector-interleave=1 -prefer-predicate-over-epilogue=predicate-dont-vectorize -S < %s | FileCheck %s --check-prefix=SVE -target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" target triple = "aarch64-unknown-linux-gnu" - ; Tests are checking if LV can vectorize loops with llvm math intrinsics using mappings ; from TLI (if such mappings exist) for scalable and fixed width vectors. @@ -21,7 +19,7 @@ define void @llvm_ceil_f64(double* nocapture %varray) { ; ; SVE-LABEL: define void @llvm_ceil_f64 ; SVE-SAME: (ptr nocapture [[VARRAY:%.*]]) #[[ATTR1:[0-9]+]] { -; SVE: [[TMP12:%.*]] = call @llvm.ceil.nxv2f64( [[TMP11:%.*]]) +; SVE: [[TMP18:%.*]] = call @llvm.ceil.nxv2f64( [[TMP17:%.*]]) ; SVE: [[CALL:%.*]] = tail call double @llvm.ceil.f64(double [[CONV:%.*]]) ; SVE: ret void ; @@ -52,7 +50,7 @@ define void @llvm_ceil_f32(float* nocapture %varray) { ; ; SVE-LABEL: define void @llvm_ceil_f32 ; SVE-SAME: (ptr nocapture [[VARRAY:%.*]]) #[[ATTR1]] { -; SVE: [[TMP12:%.*]] = call @llvm.ceil.nxv4f32( [[TMP11:%.*]]) +; SVE: [[TMP18:%.*]] = call @llvm.ceil.nxv4f32( [[TMP17:%.*]]) ; SVE: [[CALL:%.*]] = tail call float @llvm.ceil.f32(float [[CONV:%.*]]) ; SVE: ret void ; @@ -86,7 +84,7 @@ define void @llvm_copysign_f64(double* nocapture %varray) { ; ; SVE-LABEL: define void @llvm_copysign_f64 ; SVE-SAME: (ptr nocapture [[VARRAY:%.*]]) #[[ATTR1]] { -; SVE: [[TMP12:%.*]] = call @llvm.copysign.nxv2f64( [[TMP11:%.*]], [[TMP11]]) +; SVE: [[TMP18:%.*]] = call @llvm.copysign.nxv2f64( [[TMP17:%.*]], [[TMP17]]) ; SVE: [[CALL:%.*]] = tail call double @llvm.copysign.f64(double [[CONV:%.*]], double [[CONV]]) ; SVE: ret void ; @@ -117,7 +115,7 @@ define void @llvm_copysign_f32(float* nocapture %varray) { ; ; SVE-LABEL: define void @llvm_copysign_f32 ; SVE-SAME: (ptr nocapture [[VARRAY:%.*]]) #[[ATTR1]] { -; SVE: [[TMP12:%.*]] = call @llvm.copysign.nxv4f32( [[TMP11:%.*]], [[TMP11]]) +; SVE: [[TMP18:%.*]] = call @llvm.copysign.nxv4f32( [[TMP17:%.*]], [[TMP17]]) ; SVE: [[CALL:%.*]] = tail call float @llvm.copysign.f32(float [[CONV:%.*]], float [[CONV]]) ; SVE: ret void ; @@ -151,8 +149,8 @@ define void @llvm_cos_f64(double* nocapture %varray) { ; ; SVE-LABEL: define void @llvm_cos_f64 ; SVE-SAME: (ptr nocapture [[VARRAY:%.*]]) #[[ATTR1]] { -; SVE: [[TMP12:%.*]] = call @_ZGVsMxv_cos( [[TMP11:%.*]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer)) -; SVE: [[CALL:%.*]] = tail call double @llvm.cos.f64(double [[CONV:%.*]]) #[[ATTR4:[0-9]+]] +; SVE: [[TMP18:%.*]] = call @_ZGVsMxv_cos( [[TMP17:%.*]], [[ACTIVE_LANE_MASK:%.*]]) +; SVE: [[CALL:%.*]] = tail call double @llvm.cos.f64(double [[CONV:%.*]]) #[[ATTR5:[0-9]+]] ; SVE: ret void ; entry: @@ -182,8 +180,8 @@ define void @llvm_cos_f32(float* nocapture %varray) { ; ; SVE-LABEL: define void @llvm_cos_f32 ; SVE-SAME: (ptr nocapture [[VARRAY:%.*]]) #[[ATTR1]] { -; SVE: [[TMP12:%.*]] = call @_ZGVsMxv_cosf( [[TMP11:%.*]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer)) -; SVE: [[CALL:%.*]] = tail call float @llvm.cos.f32(float [[CONV:%.*]]) #[[ATTR5:[0-9]+]] +; SVE: [[TMP18:%.*]] = call @_ZGVsMxv_cosf( [[TMP17:%.*]], [[ACTIVE_LANE_MASK:%.*]]) +; SVE: [[CALL:%.*]] = tail call float @llvm.cos.f32(float [[CONV:%.*]]) #[[ATTR6:[0-9]+]] ; SVE: ret void ; entry: @@ -216,8 +214,8 @@ define void @llvm_exp_f64(double* nocapture %varray) { ; ; SVE-LABEL: define void @llvm_exp_f64 ; SVE-SAME: (ptr nocapture [[VARRAY:%.*]]) #[[ATTR1]] { -; SVE: [[TMP12:%.*]] = call @_ZGVsMxv_exp( [[TMP11:%.*]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer)) -; SVE: [[CALL:%.*]] = tail call double @llvm.exp.f64(double [[CONV:%.*]]) #[[ATTR6:[0-9]+]] +; SVE: [[TMP18:%.*]] = call @_ZGVsMxv_exp( [[TMP17:%.*]], [[ACTIVE_LANE_MASK:%.*]]) +; SVE: [[CALL:%.*]] = tail call double @llvm.exp.f64(double [[CONV:%.*]]) #[[ATTR7:[0-9]+]] ; SVE: ret void ; entry: @@ -247,8 +245,8 @@ define void @llvm_exp_f32(float* nocapture %varray) { ; ; SVE-LABEL: define void @llvm_exp_f32 ; SVE-SAME: (ptr nocapture [[VARRAY:%.*]]) #[[ATTR1]] { -; SVE: [[TMP12:%.*]] = call @_ZGVsMxv_expf( [[TMP11:%.*]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer)) -; SVE: [[CALL:%.*]] = tail call float @llvm.exp.f32(float [[CONV:%.*]]) #[[ATTR7:[0-9]+]] +; SVE: [[TMP18:%.*]] = call @_ZGVsMxv_expf( [[TMP17:%.*]], [[ACTIVE_LANE_MASK:%.*]]) +; SVE: [[CALL:%.*]] = tail call float @llvm.exp.f32(float [[CONV:%.*]]) #[[ATTR8:[0-9]+]] ; SVE: ret void ; entry: @@ -281,8 +279,8 @@ define void @llvm_exp2_f64(double* nocapture %varray) { ; ; SVE-LABEL: define void @llvm_exp2_f64 ; SVE-SAME: (ptr nocapture [[VARRAY:%.*]]) #[[ATTR1]] { -; SVE: [[TMP12:%.*]] = call @_ZGVsMxv_exp2( [[TMP11:%.*]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer)) -; SVE: [[CALL:%.*]] = tail call double @llvm.exp2.f64(double [[CONV:%.*]]) #[[ATTR8:[0-9]+]] +; SVE: [[TMP18:%.*]] = call @_ZGVsMxv_exp2( [[TMP17:%.*]], [[ACTIVE_LANE_MASK:%.*]]) +; SVE: [[CALL:%.*]] = tail call double @llvm.exp2.f64(double [[CONV:%.*]]) #[[ATTR9:[0-9]+]] ; SVE: ret void ; entry: @@ -312,8 +310,8 @@ define void @llvm_exp2_f32(float* nocapture %varray) { ; ; SVE-LABEL: define void @llvm_exp2_f32 ; SVE-SAME: (ptr nocapture [[VARRAY:%.*]]) #[[ATTR1]] { -; SVE: [[TMP12:%.*]] = call @_ZGVsMxv_exp2f( [[TMP11:%.*]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer)) -; SVE: [[CALL:%.*]] = tail call float @llvm.exp2.f32(float [[CONV:%.*]]) #[[ATTR9:[0-9]+]] +; SVE: [[TMP18:%.*]] = call @_ZGVsMxv_exp2f( [[TMP17:%.*]], [[ACTIVE_LANE_MASK:%.*]]) +; SVE: [[CALL:%.*]] = tail call float @llvm.exp2.f32(float [[CONV:%.*]]) #[[ATTR10:[0-9]+]] ; SVE: ret void ; entry: @@ -346,8 +344,8 @@ define void @llvm_exp10_f64(double* nocapture %varray) { ; ; SVE-LABEL: define void @llvm_exp10_f64 ; SVE-SAME: (ptr nocapture [[VARRAY:%.*]]) #[[ATTR1]] { -; SVE: [[TMP12:%.*]] = call @_ZGVsMxv_exp10( [[TMP11:%.*]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer)) -; SVE: [[CALL:%.*]] = tail call double @llvm.exp10.f64(double [[CONV:%.*]]) #[[ATTR10:[0-9]+]] +; SVE: [[TMP18:%.*]] = call @_ZGVsMxv_exp10( [[TMP17:%.*]], [[ACTIVE_LANE_MASK:%.*]]) +; SVE: [[CALL:%.*]] = tail call double @llvm.exp10.f64(double [[CONV:%.*]]) #[[ATTR11:[0-9]+]] ; SVE: ret void ; entry: @@ -377,8 +375,8 @@ define void @llvm_exp10_f32(float* nocapture %varray) { ; ; SVE-LABEL: define void @llvm_exp10_f32 ; SVE-SAME: (ptr nocapture [[VARRAY:%.*]]) #[[ATTR1]] { -; SVE: [[TMP12:%.*]] = call @_ZGVsMxv_exp10f( [[TMP11:%.*]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer)) -; SVE: [[CALL:%.*]] = tail call float @llvm.exp10.f32(float [[CONV:%.*]]) #[[ATTR11:[0-9]+]] +; SVE: [[TMP18:%.*]] = call @_ZGVsMxv_exp10f( [[TMP17:%.*]], [[ACTIVE_LANE_MASK:%.*]]) +; SVE: [[CALL:%.*]] = tail call float @llvm.exp10.f32(float [[CONV:%.*]]) #[[ATTR12:[0-9]+]] ; SVE: ret void ; entry: @@ -411,7 +409,7 @@ define void @llvm_fabs_f64(double* nocapture %varray) { ; ; SVE-LABEL: define void @llvm_fabs_f64 ; SVE-SAME: (ptr nocapture [[VARRAY:%.*]]) #[[ATTR1]] { -; SVE: [[TMP12:%.*]] = call @llvm.fabs.nxv2f64( [[TMP11:%.*]]) +; SVE: [[TMP18:%.*]] = call @llvm.fabs.nxv2f64( [[TMP17:%.*]]) ; SVE: [[CALL:%.*]] = tail call double @llvm.fabs.f64(double [[CONV:%.*]]) ; SVE: ret void ; @@ -443,7 +441,7 @@ define void @llvm_fabs_f32(float* nocapture %varray) { ; ; SVE-LABEL: define void @llvm_fabs_f32 ; SVE-SAME: (ptr nocapture [[VARRAY:%.*]]) #[[ATTR1]] { -; SVE: [[TMP12:%.*]] = call @llvm.fabs.nxv4f32( [[TMP11:%.*]]) +; SVE: [[TMP18:%.*]] = call @llvm.fabs.nxv4f32( [[TMP17:%.*]]) ; SVE: [[CALL:%.*]] = tail call float @llvm.fabs.f32(float [[CONV:%.*]]) ; SVE: ret void ; @@ -477,7 +475,7 @@ define void @llvm_floor_f64(double* nocapture %varray) { ; ; SVE-LABEL: define void @llvm_floor_f64 ; SVE-SAME: (ptr nocapture [[VARRAY:%.*]]) #[[ATTR1]] { -; SVE: [[TMP12:%.*]] = call @llvm.floor.nxv2f64( [[TMP11:%.*]]) +; SVE: [[TMP18:%.*]] = call @llvm.floor.nxv2f64( [[TMP17:%.*]]) ; SVE: [[CALL:%.*]] = tail call double @llvm.floor.f64(double [[CONV:%.*]]) ; SVE: ret void ; @@ -508,7 +506,7 @@ define void @llvm_floor_f32(float* nocapture %varray) { ; ; SVE-LABEL: define void @llvm_floor_f32 ; SVE-SAME: (ptr nocapture [[VARRAY:%.*]]) #[[ATTR1]] { -; SVE: [[TMP12:%.*]] = call @llvm.floor.nxv4f32( [[TMP11:%.*]]) +; SVE: [[TMP18:%.*]] = call @llvm.floor.nxv4f32( [[TMP17:%.*]]) ; SVE: [[CALL:%.*]] = tail call float @llvm.floor.f32(float [[CONV:%.*]]) ; SVE: ret void ; @@ -542,7 +540,7 @@ define void @llvm_fma_f64(double* nocapture %varray) { ; ; SVE-LABEL: define void @llvm_fma_f64 ; SVE-SAME: (ptr nocapture [[VARRAY:%.*]]) #[[ATTR1]] { -; SVE: [[TMP12:%.*]] = call @llvm.fma.nxv2f64( [[TMP11:%.*]], [[TMP11]], [[TMP11]]) +; SVE: [[TMP18:%.*]] = call @llvm.fma.nxv2f64( [[TMP17:%.*]], [[TMP17]], [[TMP17]]) ; SVE: [[CALL:%.*]] = tail call double @llvm.fma.f64(double [[CONV:%.*]], double [[CONV]], double [[CONV]]) ; SVE: ret void ; @@ -573,7 +571,7 @@ define void @llvm_fma_f32(float* nocapture %varray) { ; ; SVE-LABEL: define void @llvm_fma_f32 ; SVE-SAME: (ptr nocapture [[VARRAY:%.*]]) #[[ATTR1]] { -; SVE: [[TMP12:%.*]] = call @llvm.fma.nxv4f32( [[TMP11:%.*]], [[TMP11]], [[TMP11]]) +; SVE: [[TMP18:%.*]] = call @llvm.fma.nxv4f32( [[TMP17:%.*]], [[TMP17]], [[TMP17]]) ; SVE: [[CALL:%.*]] = tail call float @llvm.fma.f32(float [[CONV:%.*]], float [[CONV]], float [[CONV]]) ; SVE: ret void ; @@ -607,8 +605,8 @@ define void @llvm_log_f64(double* nocapture %varray) { ; ; SVE-LABEL: define void @llvm_log_f64 ; SVE-SAME: (ptr nocapture [[VARRAY:%.*]]) #[[ATTR1]] { -; SVE: [[TMP12:%.*]] = call @_ZGVsMxv_log( [[TMP11:%.*]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer)) -; SVE: [[CALL:%.*]] = tail call double @llvm.log.f64(double [[CONV:%.*]]) #[[ATTR12:[0-9]+]] +; SVE: [[TMP18:%.*]] = call @_ZGVsMxv_log( [[TMP17:%.*]], [[ACTIVE_LANE_MASK:%.*]]) +; SVE: [[CALL:%.*]] = tail call double @llvm.log.f64(double [[CONV:%.*]]) #[[ATTR13:[0-9]+]] ; SVE: ret void ; entry: @@ -638,8 +636,8 @@ define void @llvm_log_f32(float* nocapture %varray) { ; ; SVE-LABEL: define void @llvm_log_f32 ; SVE-SAME: (ptr nocapture [[VARRAY:%.*]]) #[[ATTR1]] { -; SVE: [[TMP12:%.*]] = call @_ZGVsMxv_logf( [[TMP11:%.*]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer)) -; SVE: [[CALL:%.*]] = tail call float @llvm.log.f32(float [[CONV:%.*]]) #[[ATTR13:[0-9]+]] +; SVE: [[TMP18:%.*]] = call @_ZGVsMxv_logf( [[TMP17:%.*]], [[ACTIVE_LANE_MASK:%.*]]) +; SVE: [[CALL:%.*]] = tail call float @llvm.log.f32(float [[CONV:%.*]]) #[[ATTR14:[0-9]+]] ; SVE: ret void ; entry: @@ -672,8 +670,8 @@ define void @llvm_log10_f64(double* nocapture %varray) { ; ; SVE-LABEL: define void @llvm_log10_f64 ; SVE-SAME: (ptr nocapture [[VARRAY:%.*]]) #[[ATTR1]] { -; SVE: [[TMP12:%.*]] = call @_ZGVsMxv_log10( [[TMP11:%.*]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer)) -; SVE: [[CALL:%.*]] = tail call double @llvm.log10.f64(double [[CONV:%.*]]) #[[ATTR14:[0-9]+]] +; SVE: [[TMP18:%.*]] = call @_ZGVsMxv_log10( [[TMP17:%.*]], [[ACTIVE_LANE_MASK:%.*]]) +; SVE: [[CALL:%.*]] = tail call double @llvm.log10.f64(double [[CONV:%.*]]) #[[ATTR15:[0-9]+]] ; SVE: ret void ; entry: @@ -703,8 +701,8 @@ define void @llvm_log10_f32(float* nocapture %varray) { ; ; SVE-LABEL: define void @llvm_log10_f32 ; SVE-SAME: (ptr nocapture [[VARRAY:%.*]]) #[[ATTR1]] { -; SVE: [[TMP12:%.*]] = call @_ZGVsMxv_log10f( [[TMP11:%.*]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer)) -; SVE: [[CALL:%.*]] = tail call float @llvm.log10.f32(float [[CONV:%.*]]) #[[ATTR15:[0-9]+]] +; SVE: [[TMP18:%.*]] = call @_ZGVsMxv_log10f( [[TMP17:%.*]], [[ACTIVE_LANE_MASK:%.*]]) +; SVE: [[CALL:%.*]] = tail call float @llvm.log10.f32(float [[CONV:%.*]]) #[[ATTR16:[0-9]+]] ; SVE: ret void ; entry: @@ -737,8 +735,8 @@ define void @llvm_log2_f64(double* nocapture %varray) { ; ; SVE-LABEL: define void @llvm_log2_f64 ; SVE-SAME: (ptr nocapture [[VARRAY:%.*]]) #[[ATTR1]] { -; SVE: [[TMP12:%.*]] = call @_ZGVsMxv_log2( [[TMP11:%.*]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer)) -; SVE: [[CALL:%.*]] = tail call double @llvm.log2.f64(double [[CONV:%.*]]) #[[ATTR16:[0-9]+]] +; SVE: [[TMP18:%.*]] = call @_ZGVsMxv_log2( [[TMP17:%.*]], [[ACTIVE_LANE_MASK:%.*]]) +; SVE: [[CALL:%.*]] = tail call double @llvm.log2.f64(double [[CONV:%.*]]) #[[ATTR17:[0-9]+]] ; SVE: ret void ; entry: @@ -768,8 +766,8 @@ define void @llvm_log2_f32(float* nocapture %varray) { ; ; SVE-LABEL: define void @llvm_log2_f32 ; SVE-SAME: (ptr nocapture [[VARRAY:%.*]]) #[[ATTR1]] { -; SVE: [[TMP12:%.*]] = call @_ZGVsMxv_log2f( [[TMP11:%.*]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer)) -; SVE: [[CALL:%.*]] = tail call float @llvm.log2.f32(float [[CONV:%.*]]) #[[ATTR17:[0-9]+]] +; SVE: [[TMP18:%.*]] = call @_ZGVsMxv_log2f( [[TMP17:%.*]], [[ACTIVE_LANE_MASK:%.*]]) +; SVE: [[CALL:%.*]] = tail call float @llvm.log2.f32(float [[CONV:%.*]]) #[[ATTR18:[0-9]+]] ; SVE: ret void ; entry: @@ -802,7 +800,7 @@ define void @llvm_maxnum_f64(double* nocapture %varray) { ; ; SVE-LABEL: define void @llvm_maxnum_f64 ; SVE-SAME: (ptr nocapture [[VARRAY:%.*]]) #[[ATTR1]] { -; SVE: [[TMP12:%.*]] = call @llvm.maxnum.nxv2f64( [[TMP11:%.*]], [[TMP11]]) +; SVE: [[TMP18:%.*]] = call @llvm.maxnum.nxv2f64( [[TMP17:%.*]], [[TMP17]]) ; SVE: [[CALL:%.*]] = tail call double @llvm.maxnum.f64(double [[CONV:%.*]], double [[CONV]]) ; SVE: ret void ; @@ -833,7 +831,7 @@ define void @llvm_maxnum_f32(float* nocapture %varray) { ; ; SVE-LABEL: define void @llvm_maxnum_f32 ; SVE-SAME: (ptr nocapture [[VARRAY:%.*]]) #[[ATTR1]] { -; SVE: [[TMP12:%.*]] = call @llvm.maxnum.nxv4f32( [[TMP11:%.*]], [[TMP11]]) +; SVE: [[TMP18:%.*]] = call @llvm.maxnum.nxv4f32( [[TMP17:%.*]], [[TMP17]]) ; SVE: [[CALL:%.*]] = tail call float @llvm.maxnum.f32(float [[CONV:%.*]], float [[CONV]]) ; SVE: ret void ; @@ -867,7 +865,7 @@ define void @llvm_minnum_f64(double* nocapture %varray) { ; ; SVE-LABEL: define void @llvm_minnum_f64 ; SVE-SAME: (ptr nocapture [[VARRAY:%.*]]) #[[ATTR1]] { -; SVE: [[TMP12:%.*]] = call @llvm.minnum.nxv2f64( [[TMP11:%.*]], [[TMP11]]) +; SVE: [[TMP18:%.*]] = call @llvm.minnum.nxv2f64( [[TMP17:%.*]], [[TMP17]]) ; SVE: [[CALL:%.*]] = tail call double @llvm.minnum.f64(double [[CONV:%.*]], double [[CONV]]) ; SVE: ret void ; @@ -898,7 +896,7 @@ define void @llvm_minnum_f32(float* nocapture %varray) { ; ; SVE-LABEL: define void @llvm_minnum_f32 ; SVE-SAME: (ptr nocapture [[VARRAY:%.*]]) #[[ATTR1]] { -; SVE: [[TMP12:%.*]] = call @llvm.minnum.nxv4f32( [[TMP11:%.*]], [[TMP11]]) +; SVE: [[TMP18:%.*]] = call @llvm.minnum.nxv4f32( [[TMP17:%.*]], [[TMP17]]) ; SVE: [[CALL:%.*]] = tail call float @llvm.minnum.f32(float [[CONV:%.*]], float [[CONV]]) ; SVE: ret void ; @@ -932,7 +930,7 @@ define void @llvm_nearbyint_f64(double* nocapture %varray) { ; ; SVE-LABEL: define void @llvm_nearbyint_f64 ; SVE-SAME: (ptr nocapture [[VARRAY:%.*]]) #[[ATTR1]] { -; SVE: [[TMP12:%.*]] = call @llvm.nearbyint.nxv2f64( [[TMP11:%.*]]) +; SVE: [[TMP18:%.*]] = call @llvm.nearbyint.nxv2f64( [[TMP17:%.*]]) ; SVE: [[CALL:%.*]] = tail call double @llvm.nearbyint.f64(double [[CONV:%.*]]) ; SVE: ret void ; @@ -963,7 +961,7 @@ define void @llvm_nearbyint_f32(float* nocapture %varray) { ; ; SVE-LABEL: define void @llvm_nearbyint_f32 ; SVE-SAME: (ptr nocapture [[VARRAY:%.*]]) #[[ATTR1]] { -; SVE: [[TMP12:%.*]] = call @llvm.nearbyint.nxv4f32( [[TMP11:%.*]]) +; SVE: [[TMP18:%.*]] = call @llvm.nearbyint.nxv4f32( [[TMP17:%.*]]) ; SVE: [[CALL:%.*]] = tail call float @llvm.nearbyint.f32(float [[CONV:%.*]]) ; SVE: ret void ; @@ -997,8 +995,8 @@ define void @llvm_pow_f64(double* nocapture %varray) { ; ; SVE-LABEL: define void @llvm_pow_f64 ; SVE-SAME: (ptr nocapture [[VARRAY:%.*]]) #[[ATTR1]] { -; SVE: [[TMP12:%.*]] = call @_ZGVsMxvv_pow( [[TMP11:%.*]], [[TMP11]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer)) -; SVE: [[CALL:%.*]] = tail call double @llvm.pow.f64(double [[CONV:%.*]], double [[CONV]]) #[[ATTR18:[0-9]+]] +; SVE: [[TMP18:%.*]] = call @_ZGVsMxvv_pow( [[TMP17:%.*]], [[TMP17]], [[ACTIVE_LANE_MASK:%.*]]) +; SVE: [[CALL:%.*]] = tail call double @llvm.pow.f64(double [[CONV:%.*]], double [[CONV]]) #[[ATTR19:[0-9]+]] ; SVE: ret void ; entry: @@ -1028,8 +1026,8 @@ define void @llvm_pow_f32(float* nocapture %varray) { ; ; SVE-LABEL: define void @llvm_pow_f32 ; SVE-SAME: (ptr nocapture [[VARRAY:%.*]]) #[[ATTR1]] { -; SVE: [[TMP12:%.*]] = call @_ZGVsMxvv_powf( [[TMP11:%.*]], [[TMP11]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer)) -; SVE: [[CALL:%.*]] = tail call float @llvm.pow.f32(float [[CONV:%.*]], float [[CONV]]) #[[ATTR19:[0-9]+]] +; SVE: [[TMP18:%.*]] = call @_ZGVsMxvv_powf( [[TMP17:%.*]], [[TMP17]], [[ACTIVE_LANE_MASK:%.*]]) +; SVE: [[CALL:%.*]] = tail call float @llvm.pow.f32(float [[CONV:%.*]], float [[CONV]]) #[[ATTR20:[0-9]+]] ; SVE: ret void ; entry: @@ -1062,7 +1060,7 @@ define void @llvm_rint_f64(double* nocapture %varray) { ; ; SVE-LABEL: define void @llvm_rint_f64 ; SVE-SAME: (ptr nocapture [[VARRAY:%.*]]) #[[ATTR1]] { -; SVE: [[TMP12:%.*]] = call @llvm.rint.nxv2f64( [[TMP11:%.*]]) +; SVE: [[TMP18:%.*]] = call @llvm.rint.nxv2f64( [[TMP17:%.*]]) ; SVE: [[CALL:%.*]] = tail call double @llvm.rint.f64(double [[CONV:%.*]]) ; SVE: ret void ; @@ -1093,7 +1091,7 @@ define void @llvm_rint_f32(float* nocapture %varray) { ; ; SVE-LABEL: define void @llvm_rint_f32 ; SVE-SAME: (ptr nocapture [[VARRAY:%.*]]) #[[ATTR1]] { -; SVE: [[TMP12:%.*]] = call @llvm.rint.nxv4f32( [[TMP11:%.*]]) +; SVE: [[TMP18:%.*]] = call @llvm.rint.nxv4f32( [[TMP17:%.*]]) ; SVE: [[CALL:%.*]] = tail call float @llvm.rint.f32(float [[CONV:%.*]]) ; SVE: ret void ; @@ -1127,7 +1125,7 @@ define void @llvm_round_f64(double* nocapture %varray) { ; ; SVE-LABEL: define void @llvm_round_f64 ; SVE-SAME: (ptr nocapture [[VARRAY:%.*]]) #[[ATTR1]] { -; SVE: [[TMP12:%.*]] = call @llvm.round.nxv2f64( [[TMP11:%.*]]) +; SVE: [[TMP18:%.*]] = call @llvm.round.nxv2f64( [[TMP17:%.*]]) ; SVE: [[CALL:%.*]] = tail call double @llvm.round.f64(double [[CONV:%.*]]) ; SVE: ret void ; @@ -1158,7 +1156,7 @@ define void @llvm_round_f32(float* nocapture %varray) { ; ; SVE-LABEL: define void @llvm_round_f32 ; SVE-SAME: (ptr nocapture [[VARRAY:%.*]]) #[[ATTR1]] { -; SVE: [[TMP12:%.*]] = call @llvm.round.nxv4f32( [[TMP11:%.*]]) +; SVE: [[TMP18:%.*]] = call @llvm.round.nxv4f32( [[TMP17:%.*]]) ; SVE: [[CALL:%.*]] = tail call float @llvm.round.f32(float [[CONV:%.*]]) ; SVE: ret void ; @@ -1192,8 +1190,8 @@ define void @llvm_sin_f64(double* nocapture %varray) { ; ; SVE-LABEL: define void @llvm_sin_f64 ; SVE-SAME: (ptr nocapture [[VARRAY:%.*]]) #[[ATTR1]] { -; SVE: [[TMP12:%.*]] = call @_ZGVsMxv_sin( [[TMP11:%.*]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer)) -; SVE: [[CALL:%.*]] = tail call double @llvm.sin.f64(double [[CONV:%.*]]) #[[ATTR20:[0-9]+]] +; SVE: [[TMP18:%.*]] = call @_ZGVsMxv_sin( [[TMP17:%.*]], [[ACTIVE_LANE_MASK:%.*]]) +; SVE: [[CALL:%.*]] = tail call double @llvm.sin.f64(double [[CONV:%.*]]) #[[ATTR21:[0-9]+]] ; SVE: ret void ; entry: @@ -1223,8 +1221,8 @@ define void @llvm_sin_f32(float* nocapture %varray) { ; ; SVE-LABEL: define void @llvm_sin_f32 ; SVE-SAME: (ptr nocapture [[VARRAY:%.*]]) #[[ATTR1]] { -; SVE: [[TMP12:%.*]] = call @_ZGVsMxv_sinf( [[TMP11:%.*]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer)) -; SVE: [[CALL:%.*]] = tail call float @llvm.sin.f32(float [[CONV:%.*]]) #[[ATTR21:[0-9]+]] +; SVE: [[TMP18:%.*]] = call @_ZGVsMxv_sinf( [[TMP17:%.*]], [[ACTIVE_LANE_MASK:%.*]]) +; SVE: [[CALL:%.*]] = tail call float @llvm.sin.f32(float [[CONV:%.*]]) #[[ATTR22:[0-9]+]] ; SVE: ret void ; entry: @@ -1257,7 +1255,7 @@ define void @llvm_sqrt_f64(double* nocapture %varray) { ; ; SVE-LABEL: define void @llvm_sqrt_f64 ; SVE-SAME: (ptr nocapture [[VARRAY:%.*]]) #[[ATTR1]] { -; SVE: [[TMP12:%.*]] = call @llvm.sqrt.nxv2f64( [[TMP11:%.*]]) +; SVE: [[TMP18:%.*]] = call @llvm.sqrt.nxv2f64( [[TMP17:%.*]]) ; SVE: [[CALL:%.*]] = tail call double @llvm.sqrt.f64(double [[CONV:%.*]]) ; SVE: ret void ; @@ -1288,7 +1286,7 @@ define void @llvm_sqrt_f32(float* nocapture %varray) { ; ; SVE-LABEL: define void @llvm_sqrt_f32 ; SVE-SAME: (ptr nocapture [[VARRAY:%.*]]) #[[ATTR1]] { -; SVE: [[TMP12:%.*]] = call @llvm.sqrt.nxv4f32( [[TMP11:%.*]]) +; SVE: [[TMP18:%.*]] = call @llvm.sqrt.nxv4f32( [[TMP17:%.*]]) ; SVE: [[CALL:%.*]] = tail call float @llvm.sqrt.f32(float [[CONV:%.*]]) ; SVE: ret void ; @@ -1322,7 +1320,7 @@ define void @llvm_trunc_f64(double* nocapture %varray) { ; ; SVE-LABEL: define void @llvm_trunc_f64 ; SVE-SAME: (ptr nocapture [[VARRAY:%.*]]) #[[ATTR1]] { -; SVE: [[TMP12:%.*]] = call @llvm.trunc.nxv2f64( [[TMP11:%.*]]) +; SVE: [[TMP18:%.*]] = call @llvm.trunc.nxv2f64( [[TMP17:%.*]]) ; SVE: [[CALL:%.*]] = tail call double @llvm.trunc.f64(double [[CONV:%.*]]) ; SVE: ret void ; @@ -1353,7 +1351,7 @@ define void @llvm_trunc_f32(float* nocapture %varray) { ; ; SVE-LABEL: define void @llvm_trunc_f32 ; SVE-SAME: (ptr nocapture [[VARRAY:%.*]]) #[[ATTR1]] { -; SVE: [[TMP12:%.*]] = call @llvm.trunc.nxv4f32( [[TMP11:%.*]]) +; SVE: [[TMP18:%.*]] = call @llvm.trunc.nxv4f32( [[TMP17:%.*]]) ; SVE: [[CALL:%.*]] = tail call float @llvm.trunc.f32(float [[CONV:%.*]]) ; SVE: ret void ;