diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 6a3bd3fa110914..8c340948780668 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -1144,6 +1144,8 @@ def : Pat<(srl (shl GPR:$rs1, (i64 32)), uimm6gt32:$shamt),
           (SRLIW GPR:$rs1, (ImmSub32 uimm6gt32:$shamt))>;
 def : Pat<(sra (sext_inreg GPR:$rs1, i32), uimm5:$shamt),
           (SRAIW GPR:$rs1, uimm5:$shamt)>;
+def : Pat<(sra (shl GPR:$rs1, (i64 32)), uimm6gt32:$shamt),
+          (SRAIW GPR:$rs1, (ImmSub32 uimm6gt32:$shamt))>;
 
 def : PatGprGpr<riscv_sllw, SLLW>;
 def : PatGprGpr<riscv_srlw, SRLW>;
diff --git a/llvm/test/CodeGen/RISCV/alu64.ll b/llvm/test/CodeGen/RISCV/alu64.ll
index 1160b4055674dd..197420d5810648 100644
--- a/llvm/test/CodeGen/RISCV/alu64.ll
+++ b/llvm/test/CodeGen/RISCV/alu64.ll
@@ -431,6 +431,23 @@ define signext i32 @sraiw(i32 %a) nounwind {
   ret i32 %1
 }
 
+define i64 @sraiw_i64(i64 %a) nounwind {
+; RV64I-LABEL: sraiw_i64:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    sraiw a0, a0, 9
+; RV64I-NEXT:    ret
+;
+; RV32I-LABEL: sraiw_i64:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    srai a2, a0, 9
+; RV32I-NEXT:    srai a1, a0, 31
+; RV32I-NEXT:    mv a0, a2
+; RV32I-NEXT:    ret
+  %1 = shl i64 %a, 32
+  %2 = ashr i64 %1, 41
+  ret i64 %2
+}
+
 define signext i32 @sextw(i32 zeroext %a) nounwind {
 ; RV64I-LABEL: sextw:
 ; RV64I:       # %bb.0: