diff --git a/llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir b/llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir
index a0be58f7fb633..6328b6f4e569b 100644
--- a/llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir
+++ b/llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir
@@ -508,3 +508,39 @@ body:             |
     STURXi killed renamable $x8, $fp, -32 :: (store 8)
     RET undef $lr
 ...
+---
+# Make sure we do not pick a register marked as undef for renaming.
+#
+# CHECK-LABEL: name: test15_undef_op
+# CHECK: bb.0:
+# CHECK-NEXT: liveins: $x0, $x1, $x8
+# CHECK:       undef renamable $x10, $x11 = LDPXi renamable $x0, 0 :: (load 8)
+# CHECK-NEXT:  renamable $x9 = LDRXui renamable $x0, 1 :: (load 8)
+# CHECK-NEXT:  STRXui renamable $x9, renamable $x0, 100 :: (store 8, align 4)
+# CHECK-NEXT:  renamable $x10 = ADDXrr $x10, $x10
+# CHECK-NEXT:  STPXi renamable $x10, killed $x11, renamable $x0, 10 :: (store 8, align 4)
+# CHECK-NEXT:  RET undef $lr
+#
+name:            test15_undef_op
+alignment:       4
+tracksRegLiveness: true
+liveins:
+  - { reg: '$x0' }
+  - { reg: '$x1' }
+  - { reg: '$x8' }
+frameInfo:
+  maxAlignment:    1
+  maxCallFrameSize: 0
+machineFunctionInfo: {}
+body:             |
+  bb.0:
+    liveins: $x0, $x1, $x8
+    renamable undef $x10, renamable $x9 = LDPXi renamable $x0, 0 :: (load 8)
+    STRXui renamable killed $x9, renamable $x0, 11 :: (store 8, align 4)
+    renamable $x9 = LDRXui renamable $x0, 1 :: (load 8)
+    STRXui renamable $x9, renamable $x0, 100 :: (store 8, align 4)
+    renamable $x10 = ADDXrr $x10, $x10
+    STRXui renamable $x10, renamable $x0, 10 :: (store 8, align 4)
+    RET undef $lr
+
+...