diff --git a/clang/test/CodeGen/PowerPC/aix-altivec-vaargs.c b/clang/test/CodeGen/PowerPC/aix-altivec-vaargs.c index 4eea05213519f1..657d83454b0fc1 100644 --- a/clang/test/CodeGen/PowerPC/aix-altivec-vaargs.c +++ b/clang/test/CodeGen/PowerPC/aix-altivec-vaargs.c @@ -1,6 +1,6 @@ // REQUIRES: powerpc-registered-target -// RUN: %clang_cc1 -no-opaque-pointers -triple powerpc-unknown-aix -emit-llvm -target-feature +altivec -target-cpu pwr7 -o - %s | FileCheck %s --check-prefixes=CHECK,AIX32 -// RUN: %clang_cc1 -no-opaque-pointers -triple powerpc64-unknown-aix -emit-llvm -target-feature +altivec -target-cpu pwr7 -o - %s | FileCheck %s --check-prefixes=CHECK,AIX64 +// RUN: %clang_cc1 -triple powerpc-unknown-aix -emit-llvm -target-feature +altivec -target-cpu pwr7 -o - %s | FileCheck %s --check-prefixes=CHECK,AIX32 +// RUN: %clang_cc1 -triple powerpc64-unknown-aix -emit-llvm -target-feature +altivec -target-cpu pwr7 -o - %s | FileCheck %s --check-prefixes=CHECK,AIX64 vector double vector_varargs(int count, ...) { __builtin_va_list arg_list; @@ -16,37 +16,33 @@ vector double vector_varargs(int count, ...) { return ret; } -// CHECK: %arg_list = alloca i8* -// CHECK: %arg_list1 = bitcast i8** %arg_list to i8* -// CHECK: call void @llvm.va_start(i8* %arg_list1) +// CHECK: %arg_list = alloca ptr +// CHECK: call void @llvm.va_start(ptr %arg_list) // AIX32: for.body: -// AIX32-NEXT: %argp.cur = load i8*, i8** %arg_list, align 4 -// AIX32-NEXT: %2 = ptrtoint i8* %argp.cur to i32 +// AIX32-NEXT: %argp.cur = load ptr, ptr %arg_list, align 4 +// AIX32-NEXT: %2 = ptrtoint ptr %argp.cur to i32 // AIX32-NEXT: %3 = add i32 %2, 15 // AIX32-NEXT: %4 = and i32 %3, -16 -// AIX32-NEXT: %argp.cur.aligned = inttoptr i32 %4 to i8* -// AIX32-NEXT: %argp.next = getelementptr inbounds i8, i8* %argp.cur.aligned, i32 16 -// AIX32-NEXT: store i8* %argp.next, i8** %arg_list, align 4 -// AIX32-NEXT: %5 = bitcast i8* %argp.cur.aligned to <2 x double>* -// AIX32-NEXT: %6 = load <2 x double>, <2 x double>* %5, align 16 -// AIX32-NEXT: store <2 x double> %6, <2 x double>* %ret, align 16 +// AIX32-NEXT: %argp.cur.aligned = inttoptr i32 %4 to ptr +// AIX32-NEXT: %argp.next = getelementptr inbounds i8, ptr %argp.cur.aligned, i32 16 +// AIX32-NEXT: store ptr %argp.next, ptr %arg_list, align 4 +// AIX32-NEXT: %5 = load <2 x double>, ptr %argp.cur.aligned, align 16 +// AIX32-NEXT: store <2 x double> %5, ptr %ret, align 16 // AIX32-NEXT: br label %for.inc // AIX64: for.body: -// AIX64-NEXT: %argp.cur = load i8*, i8** %arg_list, align 8 -// AIX64-NEXT: %2 = ptrtoint i8* %argp.cur to i64 +// AIX64-NEXT: %argp.cur = load ptr, ptr %arg_list, align 8 +// AIX64-NEXT: %2 = ptrtoint ptr %argp.cur to i64 // AIX64-NEXT: %3 = add i64 %2, 15 // AIX64-NEXT: %4 = and i64 %3, -16 -// AIX64-NEXT: %argp.cur.aligned = inttoptr i64 %4 to i8* -// AIX64-NEXT: %argp.next = getelementptr inbounds i8, i8* %argp.cur.aligned, i64 16 -// AIX64-NEXT: store i8* %argp.next, i8** %arg_list, align 8 -// AIX64-NEXT: %5 = bitcast i8* %argp.cur.aligned to <2 x double>* -// AIX64-NEXT: %6 = load <2 x double>, <2 x double>* %5, align 16 -// AIX64-NEXT: store <2 x double> %6, <2 x double>* %ret, align 16 +// AIX64-NEXT: %argp.cur.aligned = inttoptr i64 %4 to ptr +// AIX64-NEXT: %argp.next = getelementptr inbounds i8, ptr %argp.cur.aligned, i64 16 +// AIX64-NEXT: store ptr %argp.next, ptr %arg_list, align 8 +// AIX64-NEXT: %5 = load <2 x double>, ptr %argp.cur.aligned, align 16 +// AIX64-NEXT: store <2 x double> %5, ptr %ret, align 16 // AIX64-NEXT: br label %for.inc // CHECK: for.end: -// CHECK: %arg_list2 = bitcast i8** %arg_list to i8* -// CHECK: call void @llvm.va_end(i8* %arg_list2) +// CHECK: call void @llvm.va_end(ptr %arg_list) diff --git a/clang/test/CodeGen/PowerPC/aix-vaargs.c b/clang/test/CodeGen/PowerPC/aix-vaargs.c index a67498bba1d1fe..8b8417d315a504 100644 --- a/clang/test/CodeGen/PowerPC/aix-vaargs.c +++ b/clang/test/CodeGen/PowerPC/aix-vaargs.c @@ -1,7 +1,7 @@ // REQUIRES: powerpc-registered-target // REQUIRES: asserts -// RUN: %clang_cc1 -no-opaque-pointers -triple powerpc-unknown-aix -emit-llvm -o - %s | FileCheck %s --check-prefixes=CHECK,AIX32 -// RUN: %clang_cc1 -no-opaque-pointers -triple powerpc64-unknown-aix -emit-llvm -o - %s | FileCheck %s --check-prefixes=CHECK,AIX64 +// RUN: %clang_cc1 -triple powerpc-unknown-aix -emit-llvm -o - %s | FileCheck %s --check-prefixes=CHECK,AIX32 +// RUN: %clang_cc1 -triple powerpc64-unknown-aix -emit-llvm -o - %s | FileCheck %s --check-prefixes=CHECK,AIX64 struct x { double b; @@ -25,61 +25,51 @@ void testva (int n, ...) { // CHECK-NEXT: entry: // CHECK-NEXT: %n.addr = alloca i32, align 4 -// AIX32-NEXT: %ap = alloca i8*, align 4 -// AIX64-NEXT: %ap = alloca i8*, align 8 +// AIX32-NEXT: %ap = alloca ptr, align 4 +// AIX64-NEXT: %ap = alloca ptr, align 8 // CHECK-NEXT: %t = alloca %struct.x, align 8 -// AIX32-NEXT: %ap2 = alloca i8*, align 4 -// AIX64-NEXT: %ap2 = alloca i8*, align 8 +// AIX32-NEXT: %ap2 = alloca ptr, align 4 +// AIX64-NEXT: %ap2 = alloca ptr, align 8 // CHECK-NEXT: %v = alloca i32, align 4 -// CHECK-NEXT: store i32 %n, i32* %n.addr, align 4 -// CHECK-NEXT: %ap1 = bitcast i8** %ap to i8* -// CHECK-NEXT: call void @llvm.va_start(i8* %ap1) - -// AIX32-NEXT: %argp.cur = load i8*, i8** %ap, align 4 -// AIX32-NEXT: %argp.next = getelementptr inbounds i8, i8* %argp.cur, i32 16 -// AIX32-NEXT: store i8* %argp.next, i8** %ap, align 4 -// AIX64-NEXT: %argp.cur = load i8*, i8** %ap, align 8 -// AIX64-NEXT: %argp.next = getelementptr inbounds i8, i8* %argp.cur, i64 16 -// AIX64-NEXT: store i8* %argp.next, i8** %ap, align 8 - -// CHECK-NEXT: %0 = bitcast i8* %argp.cur to %struct.x* -// CHECK-NEXT: %1 = bitcast %struct.x* %t to i8* -// CHECK-NEXT: %2 = bitcast %struct.x* %0 to i8* - -// AIX32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 %1, i8* align 4 %2, i32 16, i1 false) -// AIX64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 %1, i8* align 8 %2, i64 16, i1 false) - -// CHECK-NEXT: %3 = bitcast i8** %ap2 to i8* -// CHECK-NEXT: %4 = bitcast i8** %ap to i8* -// CHECK-NEXT: call void @llvm.va_copy(i8* %3, i8* %4) - -// AIX32-NEXT: %argp.cur2 = load i8*, i8** %ap2, align 4 -// AIX32-NEXT: %argp.next3 = getelementptr inbounds i8, i8* %argp.cur2, i32 4 -// AIX32-NEXT: store i8* %argp.next3, i8** %ap2, align 4 -// AIX32-NEXT: %5 = bitcast i8* %argp.cur2 to i32* -// AIX32-NEXT: %6 = load i32, i32* %5, align 4 -// AIX32-NEXT: store i32 %6, i32* %v, align 4 -// AIX64-NEXT: %argp.cur2 = load i8*, i8** %ap2, align 8 -// AIX64-NEXT: %argp.next3 = getelementptr inbounds i8, i8* %argp.cur2, i64 8 -// AIX64-NEXT: store i8* %argp.next3, i8** %ap2, align 8 -// AIX64-NEXT: %5 = getelementptr inbounds i8, i8* %argp.cur2, i64 4 -// AIX64-NEXT: %6 = bitcast i8* %5 to i32* -// AIX64-NEXT: %7 = load i32, i32* %6, align 4 -// AIX64-NEXT: store i32 %7, i32* %v, align 4 - -// CHECK-NEXT: %ap24 = bitcast i8** %ap2 to i8* -// CHECK-NEXT: call void @llvm.va_end(i8* %ap24) -// CHECK-NEXT: %ap5 = bitcast i8** %ap to i8* -// CHECK-NEXT: call void @llvm.va_end(i8* %ap5) +// CHECK-NEXT: store i32 %n, ptr %n.addr, align 4 +// CHECK-NEXT: call void @llvm.va_start(ptr %ap) + +// AIX32-NEXT: %argp.cur = load ptr, ptr %ap, align 4 +// AIX32-NEXT: %argp.next = getelementptr inbounds i8, ptr %argp.cur, i32 16 +// AIX32-NEXT: store ptr %argp.next, ptr %ap, align 4 +// AIX64-NEXT: %argp.cur = load ptr, ptr %ap, align 8 +// AIX64-NEXT: %argp.next = getelementptr inbounds i8, ptr %argp.cur, i64 16 +// AIX64-NEXT: store ptr %argp.next, ptr %ap, align 8 + + +// AIX32-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 8 %t, ptr align 4 %argp.cur, i32 16, i1 false) +// AIX64-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 %t, ptr align 8 %argp.cur, i64 16, i1 false) + +// CHECK-NEXT: call void @llvm.va_copy(ptr %ap2, ptr %ap) + +// AIX32-NEXT: %argp.cur1 = load ptr, ptr %ap2, align 4 +// AIX32-NEXT: %argp.next2 = getelementptr inbounds i8, ptr %argp.cur1, i32 4 +// AIX32-NEXT: store ptr %argp.next2, ptr %ap2, align 4 +// AIX32-NEXT: %0 = load i32, ptr %argp.cur1, align 4 +// AIX32-NEXT: store i32 %0, ptr %v, align 4 +// AIX64-NEXT: %argp.cur1 = load ptr, ptr %ap2, align 8 +// AIX64-NEXT: %argp.next2 = getelementptr inbounds i8, ptr %argp.cur1, i64 8 +// AIX64-NEXT: store ptr %argp.next2, ptr %ap2, align 8 +// AIX64-NEXT: %0 = getelementptr inbounds i8, ptr %argp.cur1, i64 4 +// AIX64-NEXT: %1 = load i32, ptr %0, align 4 +// AIX64-NEXT: store i32 %1, ptr %v, align 4 + +// CHECK-NEXT: call void @llvm.va_end(ptr %ap2) +// CHECK-NEXT: call void @llvm.va_end(ptr %ap) // CHECK-NEXT: ret void -// CHECK: declare void @llvm.va_start(i8*) +// CHECK: declare void @llvm.va_start(ptr) -// AIX32: declare void @llvm.memcpy.p0i8.p0i8.i32(i8* noalias nocapture writeonly, i8* noalias nocapture readonly, i32, i1 immarg) -// AIX64: declare void @llvm.memcpy.p0i8.p0i8.i64(i8* noalias nocapture writeonly, i8* noalias nocapture readonly, i64, i1 immarg) +// AIX32: declare void @llvm.memcpy.p0.p0.i32(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i32, i1 immarg) +// AIX64: declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) -// CHECK: declare void @llvm.va_copy(i8*, i8*) -// CHECK: declare void @llvm.va_end(i8*) +// CHECK: declare void @llvm.va_copy(ptr, ptr) +// CHECK: declare void @llvm.va_end(ptr) diff --git a/clang/test/CodeGen/PowerPC/builtins-ppc-altivec.c b/clang/test/CodeGen/PowerPC/builtins-ppc-altivec.c index af0f6ad31cb5c2..2310082a2aac51 100644 --- a/clang/test/CodeGen/PowerPC/builtins-ppc-altivec.c +++ b/clang/test/CodeGen/PowerPC/builtins-ppc-altivec.c @@ -1,17 +1,17 @@ // REQUIRES: powerpc-registered-target -// RUN: %clang_cc1 -no-opaque-pointers -target-feature +altivec -triple powerpc-unknown-unknown -emit-llvm %s \ +// RUN: %clang_cc1 -target-feature +altivec -triple powerpc-unknown-unknown -emit-llvm %s \ // RUN: -flax-vector-conversions=none -faltivec-src-compat=mixed \ // RUN: -o - | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -target-feature +altivec -triple powerpcle-unknown-unknown -emit-llvm %s \ +// RUN: %clang_cc1 -target-feature +altivec -triple powerpcle-unknown-unknown -emit-llvm %s \ // RUN: -flax-vector-conversions=none -faltivec-src-compat=mixed \ // RUN: -o - | FileCheck %s -check-prefix=CHECK-LE -// RUN: %clang_cc1 -no-opaque-pointers -target-feature +altivec -triple powerpc64-unknown-unknown -emit-llvm %s \ +// RUN: %clang_cc1 -target-feature +altivec -triple powerpc64-unknown-unknown -emit-llvm %s \ // RUN: -flax-vector-conversions=none -faltivec-src-compat=mixed \ // RUN: -o - | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -target-feature +altivec -triple powerpc64le-unknown-unknown -emit-llvm %s \ +// RUN: %clang_cc1 -target-feature +altivec -triple powerpc64le-unknown-unknown -emit-llvm %s \ // RUN: -flax-vector-conversions=none -faltivec-src-compat=mixed \ // RUN: -o - | FileCheck %s -check-prefix=CHECK-LE -// RUN: not %clang_cc1 -no-opaque-pointers -triple powerpc64le-unknown-unknown -emit-llvm %s \ +// RUN: not %clang_cc1 -triple powerpc64le-unknown-unknown -emit-llvm %s \ // RUN: -ferror-limit 0 -DNO_ALTIVEC -o - 2>&1 \ // RUN: | FileCheck %s -check-prefix=CHECK-NOALTIVEC #ifndef NO_ALTIVEC @@ -92,14 +92,12 @@ void test1() { // CHECK-LE: @llvm.ppc.altivec.vmaxsw vf = vec_abs(vf); -// CHECK: bitcast <4 x float> %{{.*}} to <4 x i32> // CHECK: and <4 x i32> {{.*}}, -// CHECK: bitcast <4 x i32> %{{.*}} to <4 x float> -// CHECK: store <4 x float> %{{.*}}, <4 x float>* @vf +// CHECK: store <4 x float> %{{.*}}, ptr @vf // CHECK-LE: bitcast <4 x float> %{{.*}} to <4 x i32> // CHECK-LE: and <4 x i32> {{.*}}, // CHECK-LE: bitcast <4 x i32> %{{.*}} to <4 x float> -// CHECK-LE: store <4 x float> %{{.*}}, <4 x float>* @vf +// CHECK-LE: store <4 x float> %{{.*}}, ptr @vf vsc = vec_nabs(vsc); // CHECK: sub <16 x i8> zeroinitializer @@ -9376,88 +9374,88 @@ void test8() { // CHECK-LE: shufflevector <4 x float> %{{[0-9]+}}, <4 x float> %{{[0-9]+}}, <4 x i32> res_vbc = vec_revb(vbc); -// CHECK: [[T1:%.+]] = load <16 x i8>, <16 x i8>* @vbc, align 16 -// CHECK: store <16 x i8> [[T1]], <16 x i8>* [[T2:%.+]], align 16 -// CHECK: [[T3:%.+]] = load <16 x i8>, <16 x i8>* [[T2]], align 16 -// CHECK: store <16 x i8> [[T3]], <16 x i8>* @res_vbc, align 16 -// CHECK-LE: [[T1:%.+]] = load <16 x i8>, <16 x i8>* @vbc, align 16 -// CHECK-LE: store <16 x i8> [[T1]], <16 x i8>* [[T2:%.+]], align 16 -// CHECK-LE: [[T3:%.+]] = load <16 x i8>, <16 x i8>* [[T2]], align 16 -// CHECK-LE: store <16 x i8> [[T3]], <16 x i8>* @res_vbc, align 16 +// CHECK: [[T1:%.+]] = load <16 x i8>, ptr @vbc, align 16 +// CHECK: store <16 x i8> [[T1]], ptr [[T2:%.+]], align 16 +// CHECK: [[T3:%.+]] = load <16 x i8>, ptr [[T2]], align 16 +// CHECK: store <16 x i8> [[T3]], ptr @res_vbc, align 16 +// CHECK-LE: [[T1:%.+]] = load <16 x i8>, ptr @vbc, align 16 +// CHECK-LE: store <16 x i8> [[T1]], ptr [[T2:%.+]], align 16 +// CHECK-LE: [[T3:%.+]] = load <16 x i8>, ptr [[T2]], align 16 +// CHECK-LE: store <16 x i8> [[T3]], ptr @res_vbc, align 16 res_vsc = vec_revb(vsc); -// CHECK: [[T1:%.+]] = load <16 x i8>, <16 x i8>* @vsc, align 16 -// CHECK: store <16 x i8> [[T1]], <16 x i8>* [[T2:%.+]], align 16 -// CHECK: [[T3:%.+]] = load <16 x i8>, <16 x i8>* [[T2]], align 16 -// CHECK: store <16 x i8> [[T3]], <16 x i8>* @res_vsc, align 16 -// CHECK-LE: [[T1:%.+]] = load <16 x i8>, <16 x i8>* @vsc, align 16 -// CHECK-LE: store <16 x i8> [[T1]], <16 x i8>* [[T2:%.+]], align 16 -// CHECK-LE: [[T3:%.+]] = load <16 x i8>, <16 x i8>* [[T2]], align 16 -// CHECK-LE: store <16 x i8> [[T3]], <16 x i8>* @res_vsc, align 16 +// CHECK: [[T1:%.+]] = load <16 x i8>, ptr @vsc, align 16 +// CHECK: store <16 x i8> [[T1]], ptr [[T2:%.+]], align 16 +// CHECK: [[T3:%.+]] = load <16 x i8>, ptr [[T2]], align 16 +// CHECK: store <16 x i8> [[T3]], ptr @res_vsc, align 16 +// CHECK-LE: [[T1:%.+]] = load <16 x i8>, ptr @vsc, align 16 +// CHECK-LE: store <16 x i8> [[T1]], ptr [[T2:%.+]], align 16 +// CHECK-LE: [[T3:%.+]] = load <16 x i8>, ptr [[T2]], align 16 +// CHECK-LE: store <16 x i8> [[T3]], ptr @res_vsc, align 16 res_vuc = vec_revb(vuc); -// CHECK: [[T1:%.+]] = load <16 x i8>, <16 x i8>* @vuc, align 16 -// CHECK: store <16 x i8> [[T1]], <16 x i8>* [[T2:%.+]], align 16 -// CHECK: [[T3:%.+]] = load <16 x i8>, <16 x i8>* [[T2]], align 16 -// CHECK: store <16 x i8> [[T3]], <16 x i8>* @res_vuc, align 16 -// CHECK-LE: [[T1:%.+]] = load <16 x i8>, <16 x i8>* @vuc, align 16 -// CHECK-LE: store <16 x i8> [[T1]], <16 x i8>* [[T2:%.+]], align 16 -// CHECK-LE: [[T3:%.+]] = load <16 x i8>, <16 x i8>* [[T2]], align 16 -// CHECK-LE: store <16 x i8> [[T3]], <16 x i8>* @res_vuc, align 16 +// CHECK: [[T1:%.+]] = load <16 x i8>, ptr @vuc, align 16 +// CHECK: store <16 x i8> [[T1]], ptr [[T2:%.+]], align 16 +// CHECK: [[T3:%.+]] = load <16 x i8>, ptr [[T2]], align 16 +// CHECK: store <16 x i8> [[T3]], ptr @res_vuc, align 16 +// CHECK-LE: [[T1:%.+]] = load <16 x i8>, ptr @vuc, align 16 +// CHECK-LE: store <16 x i8> [[T1]], ptr [[T2:%.+]], align 16 +// CHECK-LE: [[T3:%.+]] = load <16 x i8>, ptr [[T2]], align 16 +// CHECK-LE: store <16 x i8> [[T3]], ptr @res_vuc, align 16 res_vbs = vec_revb(vbs); -// CHECK: store <16 x i8> , <16 x i8>* {{%.+}}, align 16 +// CHECK: store <16 x i8> , ptr {{%.+}}, align 16 // CHECK: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}}) -// CHECK-LE: store <16 x i8> , <16 x i8>* {{%.+}}, align 16 -// CHECK-LE: store <16 x i8> , <16 x i8>* {{%.+}}, align 16 +// CHECK-LE: store <16 x i8> , ptr {{%.+}}, align 16 +// CHECK-LE: store <16 x i8> , ptr {{%.+}}, align 16 // CHECK-LE: xor <16 x i8> // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}}) res_vs = vec_revb(vs); -// CHECK: store <16 x i8> , <16 x i8>* {{%.+}}, align 16 +// CHECK: store <16 x i8> , ptr {{%.+}}, align 16 // CHECK: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}}) -// CHECK-LE: store <16 x i8> , <16 x i8>* {{%.+}}, align 16 -// CHECK-LE: store <16 x i8> , <16 x i8>* {{%.+}}, align 16 +// CHECK-LE: store <16 x i8> , ptr {{%.+}}, align 16 +// CHECK-LE: store <16 x i8> , ptr {{%.+}}, align 16 // CHECK-LE: xor <16 x i8> // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}}) res_vus = vec_revb(vus); -// CHECK: store <16 x i8> , <16 x i8>* {{%.+}}, align 16 +// CHECK: store <16 x i8> , ptr {{%.+}}, align 16 // CHECK: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}}) -// CHECK-LE: store <16 x i8> , <16 x i8>* {{%.+}}, align 16 -// CHECK-LE: store <16 x i8> , <16 x i8>* {{%.+}}, align 16 +// CHECK-LE: store <16 x i8> , ptr {{%.+}}, align 16 +// CHECK-LE: store <16 x i8> , ptr {{%.+}}, align 16 // CHECK-LE: xor <16 x i8> // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}}) res_vbi = vec_revb(vbi); -// CHECK: store <16 x i8> , <16 x i8>* {{%.+}}, align 16 +// CHECK: store <16 x i8> , ptr {{%.+}}, align 16 // CHECK: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}}) -// CHECK-LE: store <16 x i8> , <16 x i8>* {{%.+}}, align 16 -// CHECK-LE: store <16 x i8> , <16 x i8>* {{%.+}}, align 16 +// CHECK-LE: store <16 x i8> , ptr {{%.+}}, align 16 +// CHECK-LE: store <16 x i8> , ptr {{%.+}}, align 16 // CHECK-LE: xor <16 x i8> // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}}) res_vi = vec_revb(vi); -// CHECK: store <16 x i8> , <16 x i8>* {{%.+}}, align 16 +// CHECK: store <16 x i8> , ptr {{%.+}}, align 16 // CHECK: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}}) -// CHECK-LE: store <16 x i8> , <16 x i8>* {{%.+}}, align 16 -// CHECK-LE: store <16 x i8> , <16 x i8>* {{%.+}}, align 16 +// CHECK-LE: store <16 x i8> , ptr {{%.+}}, align 16 +// CHECK-LE: store <16 x i8> , ptr {{%.+}}, align 16 // CHECK-LE: xor <16 x i8> // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}}) res_vui = vec_revb(vui); -// CHECK: store <16 x i8> , <16 x i8>* {{%.+}}, align 16 +// CHECK: store <16 x i8> , ptr {{%.+}}, align 16 // CHECK: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}}) -// CHECK-LE: store <16 x i8> , <16 x i8>* {{%.+}}, align 16 -// CHECK-LE: store <16 x i8> , <16 x i8>* {{%.+}}, align 16 +// CHECK-LE: store <16 x i8> , ptr {{%.+}}, align 16 +// CHECK-LE: store <16 x i8> , ptr {{%.+}}, align 16 // CHECK-LE: xor <16 x i8> // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}}) res_vf = vec_revb(vf); -// CHECK: store <16 x i8> , <16 x i8>* {{%.+}}, align 16 +// CHECK: store <16 x i8> , ptr {{%.+}}, align 16 // CHECK: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}}) -// CHECK-LE: store <16 x i8> , <16 x i8>* {{%.+}}, align 16 -// CHECK-LE: store <16 x i8> , <16 x i8>* {{%.+}}, align 16 +// CHECK-LE: store <16 x i8> , ptr {{%.+}}, align 16 +// CHECK-LE: store <16 x i8> , ptr {{%.+}}, align 16 // CHECK-LE: xor <16 x i8> // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}}) } @@ -9467,32 +9465,32 @@ void test9() { // CHECK-LABEL: define{{.*}} void @test9 // CHECK-LE-LABEL: define{{.*}} void @test9 res_vsc = vec_xl(param_sll, param_sc_ld); - // CHECK: load <16 x i8>, <16 x i8>* %{{[0-9]+}}, align 1 - // CHECK-LE: load <16 x i8>, <16 x i8>* %{{[0-9]+}}, align 1 + // CHECK: load <16 x i8>, ptr %{{.+}}, align 1 + // CHECK-LE: load <16 x i8>, ptr %{{.+}}, align 1 res_vuc = vec_xl(param_sll, param_uc_ld); - // CHECK: load <16 x i8>, <16 x i8>* %{{[0-9]+}}, align 1 - // CHECK-LE: load <16 x i8>, <16 x i8>* %{{[0-9]+}}, align 1 + // CHECK: load <16 x i8>, ptr %{{.+}}, align 1 + // CHECK-LE: load <16 x i8>, ptr %{{.+}}, align 1 res_vs = vec_xl(param_sll, param_s_ld); - // CHECK: load <8 x i16>, <8 x i16>* %{{[0-9]+}}, align 1 - // CHECK-LE: load <8 x i16>, <8 x i16>* %{{[0-9]+}}, align 1 + // CHECK: load <8 x i16>, ptr %{{.+}}, align 1 + // CHECK-LE: load <8 x i16>, ptr %{{.+}}, align 1 res_vus = vec_xl(param_sll, param_us_ld); - // CHECK: load <8 x i16>, <8 x i16>* %{{[0-9]+}}, align 1 - // CHECK-LE: load <8 x i16>, <8 x i16>* %{{[0-9]+}}, align 1 + // CHECK: load <8 x i16>, ptr %{{.+}}, align 1 + // CHECK-LE: load <8 x i16>, ptr %{{.+}}, align 1 res_vi = vec_xl(param_sll, param_i_ld); - // CHECK: load <4 x i32>, <4 x i32>* %{{[0-9]+}}, align 1 - // CHECK-LE: load <4 x i32>, <4 x i32>* %{{[0-9]+}}, align 1 + // CHECK: load <4 x i32>, ptr %{{.+}}, align 1 + // CHECK-LE: load <4 x i32>, ptr %{{.+}}, align 1 res_vui = vec_xl(param_sll, param_ui_ld); - // CHECK: load <4 x i32>, <4 x i32>* %{{[0-9]+}}, align 1 - // CHECK-LE: load <4 x i32>, <4 x i32>* %{{[0-9]+}}, align 1 + // CHECK: load <4 x i32>, ptr %{{.+}}, align 1 + // CHECK-LE: load <4 x i32>, ptr %{{.+}}, align 1 res_vf = vec_xl(param_sll, param_f_ld); - // CHECK: load <4 x float>, <4 x float>* %{{[0-9]+}}, align 1 - // CHECK-LE: load <4 x float>, <4 x float>* %{{[0-9]+}}, align 1 + // CHECK: load <4 x float>, ptr %{{.+}}, align 1 + // CHECK-LE: load <4 x float>, ptr %{{.+}}, align 1 } /* ------------------------------ vec_xst ----------------------------------- */ @@ -9500,32 +9498,32 @@ void test10() { // CHECK-LABEL: define{{.*}} void @test10 // CHECK-LE-LABEL: define{{.*}} void @test10 vec_xst(vsc, param_sll, ¶m_sc); - // CHECK: store <16 x i8> %{{[0-9]+}}, <16 x i8>* %{{[0-9]+}}, align 1 - // CHECK-LE: store <16 x i8> %{{[0-9]+}}, <16 x i8>* %{{[0-9]+}}, align 1 + // CHECK: store <16 x i8> %{{[0-9]+}}, ptr %{{.+}}, align 1 + // CHECK-LE: store <16 x i8> %{{[0-9]+}}, ptr %{{.+}}, align 1 vec_xst(vuc, param_sll, ¶m_uc); - // CHECK: store <16 x i8> %{{[0-9]+}}, <16 x i8>* %{{[0-9]+}}, align 1 - // CHECK-LE: store <16 x i8> %{{[0-9]+}}, <16 x i8>* %{{[0-9]+}}, align 1 + // CHECK: store <16 x i8> %{{[0-9]+}}, ptr %{{.+}}, align 1 + // CHECK-LE: store <16 x i8> %{{[0-9]+}}, ptr %{{.+}}, align 1 vec_xst(vs, param_sll, ¶m_s); - // CHECK: store <8 x i16> %{{[0-9]+}}, <8 x i16>* %{{[0-9]+}}, align 1 - // CHECK-LE: store <8 x i16> %{{[0-9]+}}, <8 x i16>* %{{[0-9]+}}, align 1 + // CHECK: store <8 x i16> %{{[0-9]+}}, ptr %{{.+}}, align 1 + // CHECK-LE: store <8 x i16> %{{[0-9]+}}, ptr %{{.+}}, align 1 vec_xst(vus, param_sll, ¶m_us); - // CHECK: store <8 x i16> %{{[0-9]+}}, <8 x i16>* %{{[0-9]+}}, align 1 - // CHECK-LE: store <8 x i16> %{{[0-9]+}}, <8 x i16>* %{{[0-9]+}}, align 1 + // CHECK: store <8 x i16> %{{[0-9]+}}, ptr %{{.+}}, align 1 + // CHECK-LE: store <8 x i16> %{{[0-9]+}}, ptr %{{.+}}, align 1 vec_xst(vi, param_sll, ¶m_i); - // CHECK: store <4 x i32> %{{[0-9]+}}, <4 x i32>* %{{[0-9]+}}, align 1 - // CHECK-LE: store <4 x i32> %{{[0-9]+}}, <4 x i32>* %{{[0-9]+}}, align 1 + // CHECK: store <4 x i32> %{{[0-9]+}}, ptr %{{.+}}, align 1 + // CHECK-LE: store <4 x i32> %{{[0-9]+}}, ptr %{{.+}}, align 1 vec_xst(vui, param_sll, ¶m_ui); - // CHECK: store <4 x i32> %{{[0-9]+}}, <4 x i32>* %{{[0-9]+}}, align 1 - // CHECK-LE: store <4 x i32> %{{[0-9]+}}, <4 x i32>* %{{[0-9]+}}, align 1 + // CHECK: store <4 x i32> %{{[0-9]+}}, ptr %{{.+}}, align 1 + // CHECK-LE: store <4 x i32> %{{[0-9]+}}, ptr %{{.+}}, align 1 vec_xst(vf, param_sll, ¶m_f); - // CHECK: store <4 x float> %{{[0-9]+}}, <4 x float>* %{{[0-9]+}}, align 1 - // CHECK-LE: store <4 x float> %{{[0-9]+}}, <4 x float>* %{{[0-9]+}}, align 1 + // CHECK: store <4 x float> %{{[0-9]+}}, ptr %{{.+}}, align 1 + // CHECK-LE: store <4 x float> %{{[0-9]+}}, ptr %{{.+}}, align 1 } /* ----------------------------- vec_xl_be ---------------------------------- */ @@ -9533,36 +9531,36 @@ void test11() { // CHECK-LABEL: define{{.*}} void @test11 // CHECK-LE-LABEL: define{{.*}} void @test11 res_vsc = vec_xl_be(param_sll, param_sc_ld); - // CHECK: load <16 x i8>, <16 x i8>* %{{[0-9]+}}, align 1 - // CHECK-LE: call <2 x double> @llvm.ppc.vsx.lxvd2x.be(i8* %{{[0-9]+}}) + // CHECK: load <16 x i8>, ptr %{{.+}}, align 1 + // CHECK-LE: call <2 x double> @llvm.ppc.vsx.lxvd2x.be(ptr %{{[0-9]+}}) // CHECK-LE: shufflevector <16 x i8> %{{[0-9]+}}, <16 x i8> %{{[0-9]+}}, <16 x i32> res_vuc = vec_xl_be(param_sll, param_uc_ld); - // CHECK: load <16 x i8>, <16 x i8>* %{{[0-9]+}}, align 1 - // CHECK-LE: call <2 x double> @llvm.ppc.vsx.lxvd2x.be(i8* %{{[0-9]+}}) + // CHECK: load <16 x i8>, ptr %{{.+}}, align 1 + // CHECK-LE: call <2 x double> @llvm.ppc.vsx.lxvd2x.be(ptr %{{[0-9]+}}) // CHECK-LE: shufflevector <16 x i8> %{{[0-9]+}}, <16 x i8> %{{[0-9]+}}, <16 x i32> res_vs = vec_xl_be(param_sll, param_s_ld); - // CHECK: load <8 x i16>, <8 x i16>* %{{[0-9]+}}, align 1 - // CHECK-LE: call <2 x double> @llvm.ppc.vsx.lxvd2x.be(i8* %{{[0-9]+}}) + // CHECK: load <8 x i16>, ptr %{{.+}}, align 1 + // CHECK-LE: call <2 x double> @llvm.ppc.vsx.lxvd2x.be(ptr %{{[0-9]+}}) // CHECK-LE: shufflevector <8 x i16> %{{[0-9]+}}, <8 x i16> %{{[0-9]+}}, <8 x i32> res_vus = vec_xl_be(param_sll, param_us_ld); - // CHECK: load <8 x i16>, <8 x i16>* %{{[0-9]+}}, align 1 - // CHECK-LE: call <2 x double> @llvm.ppc.vsx.lxvd2x.be(i8* %{{[0-9]+}}) + // CHECK: load <8 x i16>, ptr %{{.+}}, align 1 + // CHECK-LE: call <2 x double> @llvm.ppc.vsx.lxvd2x.be(ptr %{{[0-9]+}}) // CHECK-LE: shufflevector <8 x i16> %{{[0-9]+}}, <8 x i16> %{{[0-9]+}}, <8 x i32> res_vi = vec_xl_be(param_sll, param_i_ld); - // CHECK: load <4 x i32>, <4 x i32>* %{{[0-9]+}}, align 1 - // CHECK-LE: call <4 x i32> @llvm.ppc.vsx.lxvw4x.be(i8* %{{[0-9]+}}) + // CHECK: load <4 x i32>, ptr %{{.+}}, align 1 + // CHECK-LE: call <4 x i32> @llvm.ppc.vsx.lxvw4x.be(ptr %{{[0-9]+}}) res_vui = vec_xl_be(param_sll, param_ui_ld); - // CHECK: load <4 x i32>, <4 x i32>* %{{[0-9]+}}, align 1 - // CHECK-LE: call <4 x i32> @llvm.ppc.vsx.lxvw4x.be(i8* %{{[0-9]+}}) + // CHECK: load <4 x i32>, ptr %{{.+}}, align 1 + // CHECK-LE: call <4 x i32> @llvm.ppc.vsx.lxvw4x.be(ptr %{{[0-9]+}}) res_vf = vec_xl_be(param_sll, param_f_ld); - // CHECK: load <4 x float>, <4 x float>* %{{[0-9]+}}, align 1 - // CHECK-LE: call <4 x i32> @llvm.ppc.vsx.lxvw4x.be(i8* %{{[0-9]+}}) + // CHECK: load <4 x float>, ptr %{{.+}}, align 1 + // CHECK-LE: call <4 x i32> @llvm.ppc.vsx.lxvw4x.be(ptr %{{[0-9]+}}) } /* ----------------------------- vec_xst_be --------------------------------- */ @@ -9570,36 +9568,36 @@ void test12() { // CHECK-LABEL: define{{.*}} void @test12 // CHECK-LE-LABEL: define{{.*}} void @test12 vec_xst_be(vsc, param_sll, ¶m_sc); - // CHECK: store <16 x i8> %{{[0-9]+}}, <16 x i8>* %{{[0-9]+}}, align 1 + // CHECK: store <16 x i8> %{{[0-9]+}}, ptr %{{.+}}, align 1 // CHECK-LE: shufflevector <16 x i8> %{{[0-9]+}}, <16 x i8> %{{[0-9]+}}, <16 x i32> - // CHECK-LE: call void @llvm.ppc.vsx.stxvd2x.be(<2 x double> %{{[0-9]+}}, i8* %{{[0-9]+}}) + // CHECK-LE: call void @llvm.ppc.vsx.stxvd2x.be(<2 x double> %{{[0-9]+}}, ptr %{{[0-9]+}}) vec_xst_be(vuc, param_sll, ¶m_uc); - // CHECK: store <16 x i8> %{{[0-9]+}}, <16 x i8>* %{{[0-9]+}}, align 1 + // CHECK: store <16 x i8> %{{[0-9]+}}, ptr %{{.+}}, align 1 // CHECK-LE: shufflevector <16 x i8> %{{[0-9]+}}, <16 x i8> %{{[0-9]+}}, <16 x i32> - // CHECK-LE: call void @llvm.ppc.vsx.stxvd2x.be(<2 x double> %{{[0-9]+}}, i8* %{{[0-9]+}}) + // CHECK-LE: call void @llvm.ppc.vsx.stxvd2x.be(<2 x double> %{{[0-9]+}}, ptr %{{[0-9]+}}) vec_xst_be(vs, param_sll, ¶m_s); - // CHECK: store <8 x i16> %{{[0-9]+}}, <8 x i16>* %{{[0-9]+}}, align 1 + // CHECK: store <8 x i16> %{{[0-9]+}}, ptr %{{.+}}, align 1 // CHECK-LE: shufflevector <8 x i16> %{{[0-9]+}}, <8 x i16> %{{[0-9]+}}, <8 x i32> - // CHECK-LE: call void @llvm.ppc.vsx.stxvd2x.be(<2 x double> %{{[0-9]+}}, i8* %{{[0-9]+}}) + // CHECK-LE: call void @llvm.ppc.vsx.stxvd2x.be(<2 x double> %{{[0-9]+}}, ptr %{{[0-9]+}}) vec_xst_be(vus, param_sll, ¶m_us); - // CHECK: store <8 x i16> %{{[0-9]+}}, <8 x i16>* %{{[0-9]+}}, align 1 + // CHECK: store <8 x i16> %{{[0-9]+}}, ptr %{{.+}}, align 1 // CHECK-LE: shufflevector <8 x i16> %{{[0-9]+}}, <8 x i16> %{{[0-9]+}}, <8 x i32> - // CHECK-LE: call void @llvm.ppc.vsx.stxvd2x.be(<2 x double> %{{[0-9]+}}, i8* %{{[0-9]+}}) + // CHECK-LE: call void @llvm.ppc.vsx.stxvd2x.be(<2 x double> %{{[0-9]+}}, ptr %{{[0-9]+}}) vec_xst_be(vi, param_sll, ¶m_i); - // CHECK: store <4 x i32> %{{[0-9]+}}, <4 x i32>* %{{[0-9]+}}, align 1 - // CHECK-LE: call void @llvm.ppc.vsx.stxvw4x.be(<4 x i32> %{{[0-9]+}}, i8* %{{[0-9]+}}) + // CHECK: store <4 x i32> %{{[0-9]+}}, ptr %{{.+}}, align 1 + // CHECK-LE: call void @llvm.ppc.vsx.stxvw4x.be(<4 x i32> %{{[0-9]+}}, ptr %{{[0-9]+}}) vec_xst_be(vui, param_sll, ¶m_ui); - // CHECK: store <4 x i32> %{{[0-9]+}}, <4 x i32>* %{{[0-9]+}}, align 1 - // CHECK-LE: call void @llvm.ppc.vsx.stxvw4x.be(<4 x i32> %{{[0-9]+}}, i8* %{{[0-9]+}}) + // CHECK: store <4 x i32> %{{[0-9]+}}, ptr %{{.+}}, align 1 + // CHECK-LE: call void @llvm.ppc.vsx.stxvw4x.be(<4 x i32> %{{[0-9]+}}, ptr %{{[0-9]+}}) vec_xst_be(vf, param_sll, ¶m_f); - // CHECK: store <4 x float> %{{[0-9]+}}, <4 x float>* %{{[0-9]+}}, align 1 - // CHECK-LE: call void @llvm.ppc.vsx.stxvw4x.be(<4 x i32> %{{[0-9]+}}, i8* %{{[0-9]+}}) + // CHECK: store <4 x float> %{{[0-9]+}}, ptr %{{.+}}, align 1 + // CHECK-LE: call void @llvm.ppc.vsx.stxvw4x.be(<4 x i32> %{{[0-9]+}}, ptr %{{[0-9]+}}) } vector float test_rsqrtf(vector float a, vector float b) { diff --git a/clang/test/CodeGen/PowerPC/builtins-ppc-p10vector.c b/clang/test/CodeGen/PowerPC/builtins-ppc-p10vector.c index 312b5fe1894ea0..8a2ad8fd8a6742 100644 --- a/clang/test/CodeGen/PowerPC/builtins-ppc-p10vector.c +++ b/clang/test/CodeGen/PowerPC/builtins-ppc-p10vector.c @@ -1,11 +1,11 @@ // REQUIRES: powerpc-registered-target -// RUN: %clang_cc1 -flax-vector-conversions=none -no-opaque-pointers -target-feature +vsx \ +// RUN: %clang_cc1 -flax-vector-conversions=none -target-feature +vsx \ // RUN: -target-cpu pwr10 -triple powerpc64-unknown-unknown -emit-llvm %s \ // RUN: -o - | FileCheck %s -check-prefixes=CHECK-BE,CHECK -// RUN: %clang_cc1 -flax-vector-conversions=none -no-opaque-pointers -target-feature +vsx \ +// RUN: %clang_cc1 -flax-vector-conversions=none -target-feature +vsx \ // RUN: -target-cpu pwr10 -triple powerpc64le-unknown-unknown -emit-llvm %s \ // RUN: -o - | FileCheck %s -check-prefixes=CHECK-LE,CHECK -// RUN: %clang_cc1 -flax-vector-conversions=none -no-opaque-pointers -target-feature +vsx \ +// RUN: %clang_cc1 -flax-vector-conversions=none -target-feature +vsx \ // RUN: -target-cpu pwr10 -triple powerpc64-ibm-aix-xcoff -emit-llvm %s \ // RUN: -o - | FileCheck %s -check-prefixes=CHECK-BE,CHECK @@ -1020,9 +1020,9 @@ vector double test_vec_blend_d(void) { // CHECK-BE-LABEL: @test_vec_replace_elt_si( // CHECK-BE-NEXT: entry: -// CHECK-BE-NEXT: [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* @vsia, align 16 +// CHECK-BE-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr @vsia, align 16 // CHECK-BE-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8> -// CHECK-BE-NEXT: [[TMP2:%.*]] = load i32, i32* @sia, align 4 +// CHECK-BE-NEXT: [[TMP2:%.*]] = load i32, ptr @sia, align 4 // CHECK-BE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> // CHECK-BE-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[TMP2]], i32 0) // CHECK-BE-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8> @@ -1031,9 +1031,9 @@ vector double test_vec_blend_d(void) { // // CHECK-LE-LABEL: @test_vec_replace_elt_si( // CHECK-LE-NEXT: entry: -// CHECK-LE-NEXT: [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* @vsia, align 16 +// CHECK-LE-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr @vsia, align 16 // CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8> -// CHECK-LE-NEXT: [[TMP2:%.*]] = load i32, i32* @sia, align 4 +// CHECK-LE-NEXT: [[TMP2:%.*]] = load i32, ptr @sia, align 4 // CHECK-LE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> // CHECK-LE-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[TMP2]], i32 12) // CHECK-LE-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8> @@ -1046,9 +1046,9 @@ vector signed int test_vec_replace_elt_si(void) { // CHECK-BE-LABEL: @test_vec_replace_elt_ui( // CHECK-BE-NEXT: entry: -// CHECK-BE-NEXT: [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* @vuia, align 16 +// CHECK-BE-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr @vuia, align 16 // CHECK-BE-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8> -// CHECK-BE-NEXT: [[TMP2:%.*]] = load i32, i32* @uia, align 4 +// CHECK-BE-NEXT: [[TMP2:%.*]] = load i32, ptr @uia, align 4 // CHECK-BE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> // CHECK-BE-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[TMP2]], i32 4) // CHECK-BE-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8> @@ -1057,9 +1057,9 @@ vector signed int test_vec_replace_elt_si(void) { // // CHECK-LE-LABEL: @test_vec_replace_elt_ui( // CHECK-LE-NEXT: entry: -// CHECK-LE-NEXT: [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* @vuia, align 16 +// CHECK-LE-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr @vuia, align 16 // CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8> -// CHECK-LE-NEXT: [[TMP2:%.*]] = load i32, i32* @uia, align 4 +// CHECK-LE-NEXT: [[TMP2:%.*]] = load i32, ptr @uia, align 4 // CHECK-LE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> // CHECK-LE-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[TMP2]], i32 8) // CHECK-LE-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8> @@ -1072,9 +1072,9 @@ vector unsigned int test_vec_replace_elt_ui(void) { // CHECK-BE-LABEL: @test_vec_replace_elt_f( // CHECK-BE-NEXT: entry: -// CHECK-BE-NEXT: [[TMP0:%.*]] = load <4 x float>, <4 x float>* @vfa, align 16 +// CHECK-BE-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr @vfa, align 16 // CHECK-BE-NEXT: [[TMP1:%.*]] = bitcast <4 x float> [[TMP0]] to <16 x i8> -// CHECK-BE-NEXT: [[TMP2:%.*]] = load float, float* @fa, align 4 +// CHECK-BE-NEXT: [[TMP2:%.*]] = load float, ptr @fa, align 4 // CHECK-BE-NEXT: [[CONV:%.*]] = fptoui float [[TMP2]] to i32 // CHECK-BE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> // CHECK-BE-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[CONV]], i32 8) @@ -1084,9 +1084,9 @@ vector unsigned int test_vec_replace_elt_ui(void) { // // CHECK-LE-LABEL: @test_vec_replace_elt_f( // CHECK-LE-NEXT: entry: -// CHECK-LE-NEXT: [[TMP0:%.*]] = load <4 x float>, <4 x float>* @vfa, align 16 +// CHECK-LE-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr @vfa, align 16 // CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <4 x float> [[TMP0]] to <16 x i8> -// CHECK-LE-NEXT: [[TMP2:%.*]] = load float, float* @fa, align 4 +// CHECK-LE-NEXT: [[TMP2:%.*]] = load float, ptr @fa, align 4 // CHECK-LE-NEXT: [[CONV:%.*]] = fptoui float [[TMP2]] to i32 // CHECK-LE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> // CHECK-LE-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[CONV]], i32 4) @@ -1100,9 +1100,9 @@ vector float test_vec_replace_elt_f(void) { // CHECK-BE-LABEL: @test_vec_replace_elt_sll( // CHECK-BE-NEXT: entry: -// CHECK-BE-NEXT: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vslla, align 16 +// CHECK-BE-NEXT: [[TMP0:%.*]] = load <2 x i64>, ptr @vslla, align 16 // CHECK-BE-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8> -// CHECK-BE-NEXT: [[TMP2:%.*]] = load i64, i64* @llb, align 8 +// CHECK-BE-NEXT: [[TMP2:%.*]] = load i64, ptr @llb, align 8 // CHECK-BE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> // CHECK-BE-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP3]], i64 [[TMP2]], i32 0) // CHECK-BE-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <16 x i8> @@ -1111,9 +1111,9 @@ vector float test_vec_replace_elt_f(void) { // // CHECK-LE-LABEL: @test_vec_replace_elt_sll( // CHECK-LE-NEXT: entry: -// CHECK-LE-NEXT: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vslla, align 16 +// CHECK-LE-NEXT: [[TMP0:%.*]] = load <2 x i64>, ptr @vslla, align 16 // CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8> -// CHECK-LE-NEXT: [[TMP2:%.*]] = load i64, i64* @llb, align 8 +// CHECK-LE-NEXT: [[TMP2:%.*]] = load i64, ptr @llb, align 8 // CHECK-LE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> // CHECK-LE-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP3]], i64 [[TMP2]], i32 8) // CHECK-LE-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <16 x i8> @@ -1126,9 +1126,9 @@ vector signed long long test_vec_replace_elt_sll(void) { // CHECK-BE-LABEL: @test_vec_replace_elt_ull( // CHECK-BE-NEXT: entry: -// CHECK-BE-NEXT: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vulla, align 16 +// CHECK-BE-NEXT: [[TMP0:%.*]] = load <2 x i64>, ptr @vulla, align 16 // CHECK-BE-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8> -// CHECK-BE-NEXT: [[TMP2:%.*]] = load i64, i64* @ulla, align 8 +// CHECK-BE-NEXT: [[TMP2:%.*]] = load i64, ptr @ulla, align 8 // CHECK-BE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> // CHECK-BE-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP3]], i64 [[TMP2]], i32 0) // CHECK-BE-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <16 x i8> @@ -1137,9 +1137,9 @@ vector signed long long test_vec_replace_elt_sll(void) { // // CHECK-LE-LABEL: @test_vec_replace_elt_ull( // CHECK-LE-NEXT: entry: -// CHECK-LE-NEXT: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vulla, align 16 +// CHECK-LE-NEXT: [[TMP0:%.*]] = load <2 x i64>, ptr @vulla, align 16 // CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8> -// CHECK-LE-NEXT: [[TMP2:%.*]] = load i64, i64* @ulla, align 8 +// CHECK-LE-NEXT: [[TMP2:%.*]] = load i64, ptr @ulla, align 8 // CHECK-LE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> // CHECK-LE-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP3]], i64 [[TMP2]], i32 8) // CHECK-LE-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <16 x i8> @@ -1152,9 +1152,9 @@ vector unsigned long long test_vec_replace_elt_ull(void) { // CHECK-BE-LABEL: @test_vec_replace_elt_d( // CHECK-BE-NEXT: entry: -// CHECK-BE-NEXT: [[TMP0:%.*]] = load <2 x double>, <2 x double>* @vda, align 16 +// CHECK-BE-NEXT: [[TMP0:%.*]] = load <2 x double>, ptr @vda, align 16 // CHECK-BE-NEXT: [[TMP1:%.*]] = bitcast <2 x double> [[TMP0]] to <16 x i8> -// CHECK-BE-NEXT: [[TMP2:%.*]] = load double, double* @da, align 8 +// CHECK-BE-NEXT: [[TMP2:%.*]] = load double, ptr @da, align 8 // CHECK-BE-NEXT: [[CONV:%.*]] = fptoui double [[TMP2]] to i64 // CHECK-BE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> // CHECK-BE-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP3]], i64 [[CONV]], i32 8) @@ -1164,9 +1164,9 @@ vector unsigned long long test_vec_replace_elt_ull(void) { // // CHECK-LE-LABEL: @test_vec_replace_elt_d( // CHECK-LE-NEXT: entry: -// CHECK-LE-NEXT: [[TMP0:%.*]] = load <2 x double>, <2 x double>* @vda, align 16 +// CHECK-LE-NEXT: [[TMP0:%.*]] = load <2 x double>, ptr @vda, align 16 // CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <2 x double> [[TMP0]] to <16 x i8> -// CHECK-LE-NEXT: [[TMP2:%.*]] = load double, double* @da, align 8 +// CHECK-LE-NEXT: [[TMP2:%.*]] = load double, ptr @da, align 8 // CHECK-LE-NEXT: [[CONV:%.*]] = fptoui double [[TMP2]] to i64 // CHECK-LE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> // CHECK-LE-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP3]], i64 [[CONV]], i32 0) @@ -1180,9 +1180,9 @@ vector double test_vec_replace_elt_d(void) { // CHECK-BE-LABEL: @test_vec_replace_unaligned_si( // CHECK-BE-NEXT: entry: -// CHECK-BE-NEXT: [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* @vsia, align 16 +// CHECK-BE-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr @vsia, align 16 // CHECK-BE-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8> -// CHECK-BE-NEXT: [[TMP2:%.*]] = load i32, i32* @sia, align 4 +// CHECK-BE-NEXT: [[TMP2:%.*]] = load i32, ptr @sia, align 4 // CHECK-BE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> // CHECK-BE-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[TMP2]], i32 6) // CHECK-BE-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8> @@ -1190,9 +1190,9 @@ vector double test_vec_replace_elt_d(void) { // // CHECK-LE-LABEL: @test_vec_replace_unaligned_si( // CHECK-LE-NEXT: entry: -// CHECK-LE-NEXT: [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* @vsia, align 16 +// CHECK-LE-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr @vsia, align 16 // CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8> -// CHECK-LE-NEXT: [[TMP2:%.*]] = load i32, i32* @sia, align 4 +// CHECK-LE-NEXT: [[TMP2:%.*]] = load i32, ptr @sia, align 4 // CHECK-LE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> // CHECK-LE-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[TMP2]], i32 6) // CHECK-LE-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8> @@ -1204,9 +1204,9 @@ vector unsigned char test_vec_replace_unaligned_si(void) { // CHECK-BE-LABEL: @test_vec_replace_unaligned_ui( // CHECK-BE-NEXT: entry: -// CHECK-BE-NEXT: [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* @vuia, align 16 +// CHECK-BE-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr @vuia, align 16 // CHECK-BE-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8> -// CHECK-BE-NEXT: [[TMP2:%.*]] = load i32, i32* @uia, align 4 +// CHECK-BE-NEXT: [[TMP2:%.*]] = load i32, ptr @uia, align 4 // CHECK-BE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> // CHECK-BE-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[TMP2]], i32 8) // CHECK-BE-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8> @@ -1214,9 +1214,9 @@ vector unsigned char test_vec_replace_unaligned_si(void) { // // CHECK-LE-LABEL: @test_vec_replace_unaligned_ui( // CHECK-LE-NEXT: entry: -// CHECK-LE-NEXT: [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* @vuia, align 16 +// CHECK-LE-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr @vuia, align 16 // CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8> -// CHECK-LE-NEXT: [[TMP2:%.*]] = load i32, i32* @uia, align 4 +// CHECK-LE-NEXT: [[TMP2:%.*]] = load i32, ptr @uia, align 4 // CHECK-LE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> // CHECK-LE-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[TMP2]], i32 8) // CHECK-LE-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8> @@ -1228,9 +1228,9 @@ vector unsigned char test_vec_replace_unaligned_ui(void) { // CHECK-BE-LABEL: @test_vec_replace_unaligned_f( // CHECK-BE-NEXT: entry: -// CHECK-BE-NEXT: [[TMP0:%.*]] = load <4 x float>, <4 x float>* @vfa, align 16 +// CHECK-BE-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr @vfa, align 16 // CHECK-BE-NEXT: [[TMP1:%.*]] = bitcast <4 x float> [[TMP0]] to <16 x i8> -// CHECK-BE-NEXT: [[TMP2:%.*]] = load float, float* @fa, align 4 +// CHECK-BE-NEXT: [[TMP2:%.*]] = load float, ptr @fa, align 4 // CHECK-BE-NEXT: [[CONV:%.*]] = fptoui float [[TMP2]] to i32 // CHECK-BE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> // CHECK-BE-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[CONV]], i32 12) @@ -1239,9 +1239,9 @@ vector unsigned char test_vec_replace_unaligned_ui(void) { // // CHECK-LE-LABEL: @test_vec_replace_unaligned_f( // CHECK-LE-NEXT: entry: -// CHECK-LE-NEXT: [[TMP0:%.*]] = load <4 x float>, <4 x float>* @vfa, align 16 +// CHECK-LE-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr @vfa, align 16 // CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <4 x float> [[TMP0]] to <16 x i8> -// CHECK-LE-NEXT: [[TMP2:%.*]] = load float, float* @fa, align 4 +// CHECK-LE-NEXT: [[TMP2:%.*]] = load float, ptr @fa, align 4 // CHECK-LE-NEXT: [[CONV:%.*]] = fptoui float [[TMP2]] to i32 // CHECK-LE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> // CHECK-LE-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[CONV]], i32 12) @@ -1254,9 +1254,9 @@ vector unsigned char test_vec_replace_unaligned_f(void) { // CHECK-BE-LABEL: @test_vec_replace_unaligned_sll( // CHECK-BE-NEXT: entry: -// CHECK-BE-NEXT: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vslla, align 16 +// CHECK-BE-NEXT: [[TMP0:%.*]] = load <2 x i64>, ptr @vslla, align 16 // CHECK-BE-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8> -// CHECK-BE-NEXT: [[TMP2:%.*]] = load i64, i64* @llb, align 8 +// CHECK-BE-NEXT: [[TMP2:%.*]] = load i64, ptr @llb, align 8 // CHECK-BE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> // CHECK-BE-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP3]], i64 [[TMP2]], i32 6) // CHECK-BE-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <16 x i8> @@ -1264,9 +1264,9 @@ vector unsigned char test_vec_replace_unaligned_f(void) { // // CHECK-LE-LABEL: @test_vec_replace_unaligned_sll( // CHECK-LE-NEXT: entry: -// CHECK-LE-NEXT: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vslla, align 16 +// CHECK-LE-NEXT: [[TMP0:%.*]] = load <2 x i64>, ptr @vslla, align 16 // CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8> -// CHECK-LE-NEXT: [[TMP2:%.*]] = load i64, i64* @llb, align 8 +// CHECK-LE-NEXT: [[TMP2:%.*]] = load i64, ptr @llb, align 8 // CHECK-LE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> // CHECK-LE-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP3]], i64 [[TMP2]], i32 6) // CHECK-LE-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <16 x i8> @@ -1278,9 +1278,9 @@ vector unsigned char test_vec_replace_unaligned_sll(void) { // CHECK-BE-LABEL: @test_vec_replace_unaligned_ull( // CHECK-BE-NEXT: entry: -// CHECK-BE-NEXT: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vulla, align 16 +// CHECK-BE-NEXT: [[TMP0:%.*]] = load <2 x i64>, ptr @vulla, align 16 // CHECK-BE-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8> -// CHECK-BE-NEXT: [[TMP2:%.*]] = load i64, i64* @ulla, align 8 +// CHECK-BE-NEXT: [[TMP2:%.*]] = load i64, ptr @ulla, align 8 // CHECK-BE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> // CHECK-BE-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP3]], i64 [[TMP2]], i32 7) // CHECK-BE-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <16 x i8> @@ -1288,9 +1288,9 @@ vector unsigned char test_vec_replace_unaligned_sll(void) { // // CHECK-LE-LABEL: @test_vec_replace_unaligned_ull( // CHECK-LE-NEXT: entry: -// CHECK-LE-NEXT: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vulla, align 16 +// CHECK-LE-NEXT: [[TMP0:%.*]] = load <2 x i64>, ptr @vulla, align 16 // CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8> -// CHECK-LE-NEXT: [[TMP2:%.*]] = load i64, i64* @ulla, align 8 +// CHECK-LE-NEXT: [[TMP2:%.*]] = load i64, ptr @ulla, align 8 // CHECK-LE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> // CHECK-LE-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP3]], i64 [[TMP2]], i32 7) // CHECK-LE-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <16 x i8> @@ -1302,9 +1302,9 @@ vector unsigned char test_vec_replace_unaligned_ull(void) { // CHECK-BE-LABEL: @test_vec_replace_unaligned_d( // CHECK-BE-NEXT: entry: -// CHECK-BE-NEXT: [[TMP0:%.*]] = load <2 x double>, <2 x double>* @vda, align 16 +// CHECK-BE-NEXT: [[TMP0:%.*]] = load <2 x double>, ptr @vda, align 16 // CHECK-BE-NEXT: [[TMP1:%.*]] = bitcast <2 x double> [[TMP0]] to <16 x i8> -// CHECK-BE-NEXT: [[TMP2:%.*]] = load double, double* @da, align 8 +// CHECK-BE-NEXT: [[TMP2:%.*]] = load double, ptr @da, align 8 // CHECK-BE-NEXT: [[CONV:%.*]] = fptoui double [[TMP2]] to i64 // CHECK-BE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> // CHECK-BE-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP3]], i64 [[CONV]], i32 8) @@ -1313,9 +1313,9 @@ vector unsigned char test_vec_replace_unaligned_ull(void) { // // CHECK-LE-LABEL: @test_vec_replace_unaligned_d( // CHECK-LE-NEXT: entry: -// CHECK-LE-NEXT: [[TMP0:%.*]] = load <2 x double>, <2 x double>* @vda, align 16 +// CHECK-LE-NEXT: [[TMP0:%.*]] = load <2 x double>, ptr @vda, align 16 // CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <2 x double> [[TMP0]] to <16 x i8> -// CHECK-LE-NEXT: [[TMP2:%.*]] = load double, double* @da, align 8 +// CHECK-LE-NEXT: [[TMP2:%.*]] = load double, ptr @da, align 8 // CHECK-LE-NEXT: [[CONV:%.*]] = fptoui double [[TMP2]] to i64 // CHECK-LE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> // CHECK-LE-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP3]], i64 [[CONV]], i32 8) @@ -1626,49 +1626,49 @@ vector signed int test_vec_vec_splati_ins_range(void) { void test_vec_xst_trunc_sc(vector signed __int128 __a, signed long long __b, signed char *__c) { - // CHECK: store i8 %{{.+}}, i8* %{{.+}}, align 1 + // CHECK: store i8 %{{.+}}, ptr %{{.+}}, align 1 vec_xst_trunc(__a, __b, __c); } void test_vec_xst_trunc_uc(vector unsigned __int128 __a, signed long long __b, unsigned char *__c) { - // CHECK: store i8 %{{.+}}, i8* %{{.+}}, align 1 + // CHECK: store i8 %{{.+}}, ptr %{{.+}}, align 1 vec_xst_trunc(__a, __b, __c); } void test_vec_xst_trunc_ss(vector signed __int128 __a, signed long long __b, signed short *__c) { - // CHECK: store i16 %{{.+}}, i16* %{{.+}}, align 2 + // CHECK: store i16 %{{.+}}, ptr %{{.+}}, align 2 vec_xst_trunc(__a, __b, __c); } void test_vec_xst_trunc_us(vector unsigned __int128 __a, signed long long __b, unsigned short *__c) { - // CHECK: store i16 %{{.+}}, i16* %{{.+}}, align 2 + // CHECK: store i16 %{{.+}}, ptr %{{.+}}, align 2 vec_xst_trunc(__a, __b, __c); } void test_vec_xst_trunc_si(vector signed __int128 __a, signed long long __b, signed int *__c) { - // CHECK: store i32 %{{.+}}, i32* %{{.+}}, align 4 + // CHECK: store i32 %{{.+}}, ptr %{{.+}}, align 4 vec_xst_trunc(__a, __b, __c); } void test_vec_xst_trunc_ui(vector unsigned __int128 __a, signed long long __b, unsigned int *__c) { - // CHECK: store i32 %{{.+}}, i32* %{{.+}}, align 4 + // CHECK: store i32 %{{.+}}, ptr %{{.+}}, align 4 vec_xst_trunc(__a, __b, __c); } void test_vec_xst_trunc_sll(vector signed __int128 __a, signed long long __b, signed long long *__c) { - // CHECK: store i64 %{{.+}}, i64* %{{.+}}, align 8 + // CHECK: store i64 %{{.+}}, ptr %{{.+}}, align 8 vec_xst_trunc(__a, __b, __c); } void test_vec_xst_trunc_ull(vector unsigned __int128 __a, signed long long __b, unsigned long long *__c) { - // CHECK: store i64 %{{.+}}, i64* %{{.+}}, align 8 + // CHECK: store i64 %{{.+}}, ptr %{{.+}}, align 8 vec_xst_trunc(__a, __b, __c); } diff --git a/clang/test/CodeGen/PowerPC/builtins-ppc-pair-mma.c b/clang/test/CodeGen/PowerPC/builtins-ppc-pair-mma.c index f7811a4d1129c1..95e28da9b0bf0e 100644 --- a/clang/test/CodeGen/PowerPC/builtins-ppc-pair-mma.c +++ b/clang/test/CodeGen/PowerPC/builtins-ppc-pair-mma.c @@ -1,14 +1,13 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -no-opaque-pointers -O3 -triple powerpc64le-unknown-unknown -target-cpu pwr10 \ +// RUN: %clang_cc1 -O3 -triple powerpc64le-unknown-unknown -target-cpu pwr10 \ // RUN: -emit-llvm %s -o - | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -O3 -triple powerpc64-unknown-unknown -target-cpu pwr10 \ +// RUN: %clang_cc1 -O3 -triple powerpc64-unknown-unknown -target-cpu pwr10 \ // RUN: -emit-llvm %s -o - | FileCheck %s -// CHECK-LABEL: @test1( +// CHECK-LABEL: define {{[^@]+}}@test1( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> [[VC:%.*]], <16 x i8> [[VC]], <16 x i8> [[VC]], <16 x i8> [[VC]]) -// CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>* -// CHECK-NEXT: store <512 x i1> [[TMP0]], <512 x i1>* [[TMP1]], align 64, !tbaa [[TBAA2:![0-9]+]] +// CHECK-NEXT: store <512 x i1> [[TMP0]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2:![0-9]+]] // CHECK-NEXT: ret void // void test1(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { @@ -19,37 +18,31 @@ void test1(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsi *((__vector_quad *)resp) = res; } -// CHECK-LABEL: @test2( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>* -// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64 -// CHECK-NEXT: [[TMP2:%.*]] = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1> [[TMP1]]) -// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <16 x i8>* -// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[TMP2]], 0 -// CHECK-NEXT: store <16 x i8> [[TMP4]], <16 x i8>* [[TMP3]], align 16 -// CHECK-NEXT: [[TMP5:%.*]] = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[TMP2]], 1 -// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i8, i8* [[RESP]], i64 16 -// CHECK-NEXT: [[TMP7:%.*]] = bitcast i8* [[TMP6]] to <16 x i8>* -// CHECK-NEXT: store <16 x i8> [[TMP5]], <16 x i8>* [[TMP7]], align 16 -// CHECK-NEXT: [[TMP8:%.*]] = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[TMP2]], 2 -// CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i8, i8* [[RESP]], i64 32 -// CHECK-NEXT: [[TMP10:%.*]] = bitcast i8* [[TMP9]] to <16 x i8>* -// CHECK-NEXT: store <16 x i8> [[TMP8]], <16 x i8>* [[TMP10]], align 16 -// CHECK-NEXT: [[TMP11:%.*]] = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[TMP2]], 3 -// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds i8, i8* [[RESP]], i64 48 -// CHECK-NEXT: [[TMP13:%.*]] = bitcast i8* [[TMP12]] to <16 x i8>* -// CHECK-NEXT: store <16 x i8> [[TMP11]], <16 x i8>* [[TMP13]], align 16 +// CHECK-LABEL: define {{[^@]+}}@test2( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = load <512 x i1>, ptr [[VQP:%.*]], align 64 +// CHECK-NEXT: [[TMP1:%.*]] = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1> [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[TMP1]], 0 +// CHECK-NEXT: store <16 x i8> [[TMP2]], ptr [[RESP:%.*]], align 16 +// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[TMP1]], 1 +// CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds <16 x i8>, ptr [[RESP]], i64 1 +// CHECK-NEXT: store <16 x i8> [[TMP3]], ptr [[TMP4]], align 16 +// CHECK-NEXT: [[TMP5:%.*]] = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[TMP1]], 2 +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds <16 x i8>, ptr [[RESP]], i64 2 +// CHECK-NEXT: store <16 x i8> [[TMP5]], ptr [[TMP6]], align 16 +// CHECK-NEXT: [[TMP7:%.*]] = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[TMP1]], 3 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds <16 x i8>, ptr [[RESP]], i64 3 +// CHECK-NEXT: store <16 x i8> [[TMP7]], ptr [[TMP8]], align 16 // CHECK-NEXT: ret void // void test2(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { __builtin_mma_disassemble_acc(resp, (__vector_quad*)vqp); } -// CHECK-LABEL: @test3( +// CHECK-LABEL: define {{[^@]+}}@test3( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8> [[VC:%.*]], <16 x i8> [[VC]]) -// CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <256 x i1>* -// CHECK-NEXT: store <256 x i1> [[TMP0]], <256 x i1>* [[TMP1]], align 32, !tbaa [[TBAA6:![0-9]+]] +// CHECK-NEXT: store <256 x i1> [[TMP0]], ptr [[RESP:%.*]], align 32, !tbaa [[TBAA6:![0-9]+]] // CHECK-NEXT: ret void // void test3(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { @@ -60,31 +53,26 @@ void test3(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsi *((__vector_pair *)resp) = res; } -// CHECK-LABEL: @test4( +// CHECK-LABEL: define {{[^@]+}}@test4( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VPP:%.*]] to <256 x i1>* -// CHECK-NEXT: [[TMP1:%.*]] = load <256 x i1>, <256 x i1>* [[TMP0]], align 32 -// CHECK-NEXT: [[TMP2:%.*]] = tail call { <16 x i8>, <16 x i8> } @llvm.ppc.vsx.disassemble.pair(<256 x i1> [[TMP1]]) -// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <16 x i8>* -// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[TMP2]], 0 -// CHECK-NEXT: store <16 x i8> [[TMP4]], <16 x i8>* [[TMP3]], align 16 -// CHECK-NEXT: [[TMP5:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[TMP2]], 1 -// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i8, i8* [[RESP]], i64 16 -// CHECK-NEXT: [[TMP7:%.*]] = bitcast i8* [[TMP6]] to <16 x i8>* -// CHECK-NEXT: store <16 x i8> [[TMP5]], <16 x i8>* [[TMP7]], align 16 +// CHECK-NEXT: [[TMP0:%.*]] = load <256 x i1>, ptr [[VPP:%.*]], align 32 +// CHECK-NEXT: [[TMP1:%.*]] = tail call { <16 x i8>, <16 x i8> } @llvm.ppc.vsx.disassemble.pair(<256 x i1> [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[TMP1]], 0 +// CHECK-NEXT: store <16 x i8> [[TMP2]], ptr [[RESP:%.*]], align 16 +// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[TMP1]], 1 +// CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds <16 x i8>, ptr [[RESP]], i64 1 +// CHECK-NEXT: store <16 x i8> [[TMP3]], ptr [[TMP4]], align 16 // CHECK-NEXT: ret void // void test4(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { __builtin_vsx_disassemble_pair(resp, (__vector_pair*)vpp); } -// CHECK-LABEL: @test5( +// CHECK-LABEL: define {{[^@]+}}@test5( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>* -// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa [[TBAA2]] -// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xxmtacc(<512 x i1> [[TMP1]]) -// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>* -// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP0:%.*]] = load <512 x i1>, ptr [[VQP:%.*]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP1:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xxmtacc(<512 x i1> [[TMP0]]) +// CHECK-NEXT: store <512 x i1> [[TMP1]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2]] // CHECK-NEXT: ret void // void test5(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { @@ -94,13 +82,11 @@ void test5(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsi *((__vector_quad *)resp) = vq; } -// CHECK-LABEL: @test6( +// CHECK-LABEL: define {{[^@]+}}@test6( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>* -// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa [[TBAA2]] -// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xxmfacc(<512 x i1> [[TMP1]]) -// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>* -// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP0:%.*]] = load <512 x i1>, ptr [[VQP:%.*]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP1:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xxmfacc(<512 x i1> [[TMP0]]) +// CHECK-NEXT: store <512 x i1> [[TMP1]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2]] // CHECK-NEXT: ret void // void test6(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { @@ -110,11 +96,10 @@ void test6(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsi *((__vector_quad *)resp) = vq; } -// CHECK-LABEL: @test7( +// CHECK-LABEL: define {{[^@]+}}@test7( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xxsetaccz() -// CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>* -// CHECK-NEXT: store <512 x i1> [[TMP0]], <512 x i1>* [[TMP1]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: store <512 x i1> [[TMP0]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2]] // CHECK-NEXT: ret void // void test7(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { @@ -124,11 +109,10 @@ void test7(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsi *((__vector_quad *)resp) = vq; } -// CHECK-LABEL: @test8( +// CHECK-LABEL: define {{[^@]+}}@test8( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvi4ger8(<16 x i8> [[VC:%.*]], <16 x i8> [[VC]]) -// CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>* -// CHECK-NEXT: store <512 x i1> [[TMP0]], <512 x i1>* [[TMP1]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: store <512 x i1> [[TMP0]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2]] // CHECK-NEXT: ret void // void test8(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { @@ -138,11 +122,10 @@ void test8(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsi *((__vector_quad *)resp) = vq; } -// CHECK-LABEL: @test9( +// CHECK-LABEL: define {{[^@]+}}@test9( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvi8ger4(<16 x i8> [[VC:%.*]], <16 x i8> [[VC]]) -// CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>* -// CHECK-NEXT: store <512 x i1> [[TMP0]], <512 x i1>* [[TMP1]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: store <512 x i1> [[TMP0]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2]] // CHECK-NEXT: ret void // void test9(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { @@ -152,11 +135,10 @@ void test9(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsi *((__vector_quad *)resp) = vq; } -// CHECK-LABEL: @test10( +// CHECK-LABEL: define {{[^@]+}}@test10( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvi16ger2(<16 x i8> [[VC:%.*]], <16 x i8> [[VC]]) -// CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>* -// CHECK-NEXT: store <512 x i1> [[TMP0]], <512 x i1>* [[TMP1]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: store <512 x i1> [[TMP0]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2]] // CHECK-NEXT: ret void // void test10(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { @@ -166,11 +148,10 @@ void test10(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, uns *((__vector_quad *)resp) = vq; } -// CHECK-LABEL: @test11( +// CHECK-LABEL: define {{[^@]+}}@test11( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvi16ger2s(<16 x i8> [[VC:%.*]], <16 x i8> [[VC]]) -// CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>* -// CHECK-NEXT: store <512 x i1> [[TMP0]], <512 x i1>* [[TMP1]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: store <512 x i1> [[TMP0]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2]] // CHECK-NEXT: ret void // void test11(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { @@ -180,11 +161,10 @@ void test11(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, uns *((__vector_quad *)resp) = vq; } -// CHECK-LABEL: @test12( +// CHECK-LABEL: define {{[^@]+}}@test12( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2(<16 x i8> [[VC:%.*]], <16 x i8> [[VC]]) -// CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>* -// CHECK-NEXT: store <512 x i1> [[TMP0]], <512 x i1>* [[TMP1]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: store <512 x i1> [[TMP0]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2]] // CHECK-NEXT: ret void // void test12(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { @@ -194,11 +174,10 @@ void test12(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, uns *((__vector_quad *)resp) = vq; } -// CHECK-LABEL: @test13( +// CHECK-LABEL: define {{[^@]+}}@test13( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvf32ger(<16 x i8> [[VC:%.*]], <16 x i8> [[VC]]) -// CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>* -// CHECK-NEXT: store <512 x i1> [[TMP0]], <512 x i1>* [[TMP1]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: store <512 x i1> [[TMP0]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2]] // CHECK-NEXT: ret void // void test13(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { @@ -208,13 +187,11 @@ void test13(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, uns *((__vector_quad *)resp) = vq; } -// CHECK-LABEL: @test14( +// CHECK-LABEL: define {{[^@]+}}@test14( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VPP:%.*]] to <256 x i1>* -// CHECK-NEXT: [[TMP1:%.*]] = load <256 x i1>, <256 x i1>* [[TMP0]], align 32, !tbaa [[TBAA6]] -// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvf64ger(<256 x i1> [[TMP1]], <16 x i8> [[VC:%.*]]) -// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>* -// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP0:%.*]] = load <256 x i1>, ptr [[VPP:%.*]], align 32, !tbaa [[TBAA6]] +// CHECK-NEXT: [[TMP1:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvf64ger(<256 x i1> [[TMP0]], <16 x i8> [[VC:%.*]]) +// CHECK-NEXT: store <512 x i1> [[TMP1]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2]] // CHECK-NEXT: ret void // void test14(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { @@ -224,11 +201,10 @@ void test14(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, uns *((__vector_quad *)resp) = vq; } -// CHECK-LABEL: @test15( +// CHECK-LABEL: define {{[^@]+}}@test15( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvi4ger8(<16 x i8> [[VC:%.*]], <16 x i8> [[VC]], i32 0, i32 0, i32 0) -// CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>* -// CHECK-NEXT: store <512 x i1> [[TMP0]], <512 x i1>* [[TMP1]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: store <512 x i1> [[TMP0]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2]] // CHECK-NEXT: ret void // void test15(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { @@ -238,11 +214,10 @@ void test15(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, uns *((__vector_quad *)resp) = vq; } -// CHECK-LABEL: @test16( +// CHECK-LABEL: define {{[^@]+}}@test16( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvi8ger4(<16 x i8> [[VC:%.*]], <16 x i8> [[VC]], i32 0, i32 0, i32 0) -// CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>* -// CHECK-NEXT: store <512 x i1> [[TMP0]], <512 x i1>* [[TMP1]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: store <512 x i1> [[TMP0]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2]] // CHECK-NEXT: ret void // void test16(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { @@ -252,11 +227,10 @@ void test16(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, uns *((__vector_quad *)resp) = vq; } -// CHECK-LABEL: @test17( +// CHECK-LABEL: define {{[^@]+}}@test17( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvi16ger2(<16 x i8> [[VC:%.*]], <16 x i8> [[VC]], i32 0, i32 0, i32 0) -// CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>* -// CHECK-NEXT: store <512 x i1> [[TMP0]], <512 x i1>* [[TMP1]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: store <512 x i1> [[TMP0]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2]] // CHECK-NEXT: ret void // void test17(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { @@ -266,11 +240,10 @@ void test17(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, uns *((__vector_quad *)resp) = vq; } -// CHECK-LABEL: @test18( +// CHECK-LABEL: define {{[^@]+}}@test18( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvi16ger2s(<16 x i8> [[VC:%.*]], <16 x i8> [[VC]], i32 0, i32 0, i32 0) -// CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>* -// CHECK-NEXT: store <512 x i1> [[TMP0]], <512 x i1>* [[TMP1]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: store <512 x i1> [[TMP0]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2]] // CHECK-NEXT: ret void // void test18(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { @@ -280,11 +253,10 @@ void test18(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, uns *((__vector_quad *)resp) = vq; } -// CHECK-LABEL: @test19( +// CHECK-LABEL: define {{[^@]+}}@test19( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvf16ger2(<16 x i8> [[VC:%.*]], <16 x i8> [[VC]], i32 0, i32 0, i32 0) -// CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>* -// CHECK-NEXT: store <512 x i1> [[TMP0]], <512 x i1>* [[TMP1]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: store <512 x i1> [[TMP0]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2]] // CHECK-NEXT: ret void // void test19(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { @@ -294,11 +266,10 @@ void test19(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, uns *((__vector_quad *)resp) = vq; } -// CHECK-LABEL: @test20( +// CHECK-LABEL: define {{[^@]+}}@test20( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvf32ger(<16 x i8> [[VC:%.*]], <16 x i8> [[VC]], i32 0, i32 0) -// CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>* -// CHECK-NEXT: store <512 x i1> [[TMP0]], <512 x i1>* [[TMP1]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: store <512 x i1> [[TMP0]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2]] // CHECK-NEXT: ret void // void test20(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { @@ -308,13 +279,11 @@ void test20(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, uns *((__vector_quad *)resp) = vq; } -// CHECK-LABEL: @test21( +// CHECK-LABEL: define {{[^@]+}}@test21( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VPP:%.*]] to <256 x i1>* -// CHECK-NEXT: [[TMP1:%.*]] = load <256 x i1>, <256 x i1>* [[TMP0]], align 32, !tbaa [[TBAA6]] -// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvf64ger(<256 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], i32 0, i32 0) -// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>* -// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP0:%.*]] = load <256 x i1>, ptr [[VPP:%.*]], align 32, !tbaa [[TBAA6]] +// CHECK-NEXT: [[TMP1:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvf64ger(<256 x i1> [[TMP0]], <16 x i8> [[VC:%.*]], i32 0, i32 0) +// CHECK-NEXT: store <512 x i1> [[TMP1]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2]] // CHECK-NEXT: ret void // void test21(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { @@ -324,13 +293,11 @@ void test21(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, uns *((__vector_quad *)resp) = vq; } -// CHECK-LABEL: @test22( +// CHECK-LABEL: define {{[^@]+}}@test22( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>* -// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa [[TBAA2]] -// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvi4ger8pp(<512 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]]) -// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>* -// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP0:%.*]] = load <512 x i1>, ptr [[VQP:%.*]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP1:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvi4ger8pp(<512 x i1> [[TMP0]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]]) +// CHECK-NEXT: store <512 x i1> [[TMP1]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2]] // CHECK-NEXT: ret void // void test22(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { @@ -340,13 +307,11 @@ void test22(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, uns *((__vector_quad *)resp) = vq; } -// CHECK-LABEL: @test23( +// CHECK-LABEL: define {{[^@]+}}@test23( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>* -// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa [[TBAA2]] -// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvi8ger4pp(<512 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]]) -// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>* -// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP0:%.*]] = load <512 x i1>, ptr [[VQP:%.*]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP1:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvi8ger4pp(<512 x i1> [[TMP0]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]]) +// CHECK-NEXT: store <512 x i1> [[TMP1]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2]] // CHECK-NEXT: ret void // void test23(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { @@ -356,13 +321,11 @@ void test23(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, uns *((__vector_quad *)resp) = vq; } -// CHECK-LABEL: @test24( +// CHECK-LABEL: define {{[^@]+}}@test24( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>* -// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa [[TBAA2]] -// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvi8ger4spp(<512 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]]) -// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>* -// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP0:%.*]] = load <512 x i1>, ptr [[VQP:%.*]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP1:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvi8ger4spp(<512 x i1> [[TMP0]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]]) +// CHECK-NEXT: store <512 x i1> [[TMP1]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2]] // CHECK-NEXT: ret void // void test24(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { @@ -372,13 +335,11 @@ void test24(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, uns *((__vector_quad *)resp) = vq; } -// CHECK-LABEL: @test25( +// CHECK-LABEL: define {{[^@]+}}@test25( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>* -// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa [[TBAA2]] -// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvi16ger2pp(<512 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]]) -// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>* -// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP0:%.*]] = load <512 x i1>, ptr [[VQP:%.*]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP1:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvi16ger2pp(<512 x i1> [[TMP0]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]]) +// CHECK-NEXT: store <512 x i1> [[TMP1]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2]] // CHECK-NEXT: ret void // void test25(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { @@ -388,13 +349,11 @@ void test25(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, uns *((__vector_quad *)resp) = vq; } -// CHECK-LABEL: @test26( +// CHECK-LABEL: define {{[^@]+}}@test26( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>* -// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa [[TBAA2]] -// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvi16ger2spp(<512 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]]) -// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>* -// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP0:%.*]] = load <512 x i1>, ptr [[VQP:%.*]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP1:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvi16ger2spp(<512 x i1> [[TMP0]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]]) +// CHECK-NEXT: store <512 x i1> [[TMP1]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2]] // CHECK-NEXT: ret void // void test26(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { @@ -404,13 +363,11 @@ void test26(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, uns *((__vector_quad *)resp) = vq; } -// CHECK-LABEL: @test27( +// CHECK-LABEL: define {{[^@]+}}@test27( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>* -// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa [[TBAA2]] -// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvi4ger8pp(<512 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]], i32 0, i32 0, i32 0) -// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>* -// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP0:%.*]] = load <512 x i1>, ptr [[VQP:%.*]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP1:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvi4ger8pp(<512 x i1> [[TMP0]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]], i32 0, i32 0, i32 0) +// CHECK-NEXT: store <512 x i1> [[TMP1]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2]] // CHECK-NEXT: ret void // void test27(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { @@ -420,13 +377,11 @@ void test27(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, uns *((__vector_quad *)resp) = vq; } -// CHECK-LABEL: @test28( +// CHECK-LABEL: define {{[^@]+}}@test28( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>* -// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa [[TBAA2]] -// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvi8ger4pp(<512 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]], i32 0, i32 0, i32 0) -// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>* -// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP0:%.*]] = load <512 x i1>, ptr [[VQP:%.*]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP1:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvi8ger4pp(<512 x i1> [[TMP0]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]], i32 0, i32 0, i32 0) +// CHECK-NEXT: store <512 x i1> [[TMP1]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2]] // CHECK-NEXT: ret void // void test28(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { @@ -436,13 +391,11 @@ void test28(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, uns *((__vector_quad *)resp) = vq; } -// CHECK-LABEL: @test29( +// CHECK-LABEL: define {{[^@]+}}@test29( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>* -// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa [[TBAA2]] -// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvi8ger4spp(<512 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]], i32 0, i32 0, i32 0) -// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>* -// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP0:%.*]] = load <512 x i1>, ptr [[VQP:%.*]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP1:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvi8ger4spp(<512 x i1> [[TMP0]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]], i32 0, i32 0, i32 0) +// CHECK-NEXT: store <512 x i1> [[TMP1]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2]] // CHECK-NEXT: ret void // void test29(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { @@ -452,13 +405,11 @@ void test29(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, uns *((__vector_quad *)resp) = vq; } -// CHECK-LABEL: @test30( +// CHECK-LABEL: define {{[^@]+}}@test30( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>* -// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa [[TBAA2]] -// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvi16ger2pp(<512 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]], i32 0, i32 0, i32 0) -// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>* -// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP0:%.*]] = load <512 x i1>, ptr [[VQP:%.*]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP1:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvi16ger2pp(<512 x i1> [[TMP0]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]], i32 0, i32 0, i32 0) +// CHECK-NEXT: store <512 x i1> [[TMP1]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2]] // CHECK-NEXT: ret void // void test30(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { @@ -468,13 +419,11 @@ void test30(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, uns *((__vector_quad *)resp) = vq; } -// CHECK-LABEL: @test31( +// CHECK-LABEL: define {{[^@]+}}@test31( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>* -// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa [[TBAA2]] -// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvi16ger2spp(<512 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]], i32 0, i32 0, i32 0) -// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>* -// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP0:%.*]] = load <512 x i1>, ptr [[VQP:%.*]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP1:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvi16ger2spp(<512 x i1> [[TMP0]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]], i32 0, i32 0, i32 0) +// CHECK-NEXT: store <512 x i1> [[TMP1]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2]] // CHECK-NEXT: ret void // void test31(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { @@ -484,13 +433,11 @@ void test31(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, uns *((__vector_quad *)resp) = vq; } -// CHECK-LABEL: @test32( +// CHECK-LABEL: define {{[^@]+}}@test32( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>* -// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa [[TBAA2]] -// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2pp(<512 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]]) -// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>* -// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP0:%.*]] = load <512 x i1>, ptr [[VQP:%.*]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP1:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2pp(<512 x i1> [[TMP0]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]]) +// CHECK-NEXT: store <512 x i1> [[TMP1]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2]] // CHECK-NEXT: ret void // void test32(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { @@ -500,13 +447,11 @@ void test32(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, uns *((__vector_quad *)resp) = vq; } -// CHECK-LABEL: @test33( +// CHECK-LABEL: define {{[^@]+}}@test33( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>* -// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa [[TBAA2]] -// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2pn(<512 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]]) -// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>* -// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP0:%.*]] = load <512 x i1>, ptr [[VQP:%.*]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP1:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2pn(<512 x i1> [[TMP0]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]]) +// CHECK-NEXT: store <512 x i1> [[TMP1]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2]] // CHECK-NEXT: ret void // void test33(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { @@ -516,13 +461,11 @@ void test33(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, uns *((__vector_quad *)resp) = vq; } -// CHECK-LABEL: @test34( +// CHECK-LABEL: define {{[^@]+}}@test34( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>* -// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa [[TBAA2]] -// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2np(<512 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]]) -// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>* -// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP0:%.*]] = load <512 x i1>, ptr [[VQP:%.*]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP1:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2np(<512 x i1> [[TMP0]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]]) +// CHECK-NEXT: store <512 x i1> [[TMP1]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2]] // CHECK-NEXT: ret void // void test34(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { @@ -532,13 +475,11 @@ void test34(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, uns *((__vector_quad *)resp) = vq; } -// CHECK-LABEL: @test35( +// CHECK-LABEL: define {{[^@]+}}@test35( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>* -// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa [[TBAA2]] -// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2nn(<512 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]]) -// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>* -// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP0:%.*]] = load <512 x i1>, ptr [[VQP:%.*]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP1:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2nn(<512 x i1> [[TMP0]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]]) +// CHECK-NEXT: store <512 x i1> [[TMP1]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2]] // CHECK-NEXT: ret void // void test35(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { @@ -548,13 +489,11 @@ void test35(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, uns *((__vector_quad *)resp) = vq; } -// CHECK-LABEL: @test36( +// CHECK-LABEL: define {{[^@]+}}@test36( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>* -// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa [[TBAA2]] -// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvf16ger2pp(<512 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]], i32 0, i32 0, i32 0) -// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>* -// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP0:%.*]] = load <512 x i1>, ptr [[VQP:%.*]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP1:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvf16ger2pp(<512 x i1> [[TMP0]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]], i32 0, i32 0, i32 0) +// CHECK-NEXT: store <512 x i1> [[TMP1]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2]] // CHECK-NEXT: ret void // void test36(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { @@ -564,13 +503,11 @@ void test36(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, uns *((__vector_quad *)resp) = vq; } -// CHECK-LABEL: @test37( +// CHECK-LABEL: define {{[^@]+}}@test37( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>* -// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa [[TBAA2]] -// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvf16ger2pn(<512 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]], i32 0, i32 0, i32 0) -// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>* -// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP0:%.*]] = load <512 x i1>, ptr [[VQP:%.*]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP1:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvf16ger2pn(<512 x i1> [[TMP0]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]], i32 0, i32 0, i32 0) +// CHECK-NEXT: store <512 x i1> [[TMP1]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2]] // CHECK-NEXT: ret void // void test37(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { @@ -580,13 +517,11 @@ void test37(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, uns *((__vector_quad *)resp) = vq; } -// CHECK-LABEL: @test38( +// CHECK-LABEL: define {{[^@]+}}@test38( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>* -// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa [[TBAA2]] -// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvf16ger2np(<512 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]], i32 0, i32 0, i32 0) -// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>* -// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP0:%.*]] = load <512 x i1>, ptr [[VQP:%.*]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP1:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvf16ger2np(<512 x i1> [[TMP0]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]], i32 0, i32 0, i32 0) +// CHECK-NEXT: store <512 x i1> [[TMP1]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2]] // CHECK-NEXT: ret void // void test38(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { @@ -596,13 +531,11 @@ void test38(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, uns *((__vector_quad *)resp) = vq; } -// CHECK-LABEL: @test39( +// CHECK-LABEL: define {{[^@]+}}@test39( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>* -// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa [[TBAA2]] -// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvf16ger2nn(<512 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]], i32 0, i32 0, i32 0) -// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>* -// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP0:%.*]] = load <512 x i1>, ptr [[VQP:%.*]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP1:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvf16ger2nn(<512 x i1> [[TMP0]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]], i32 0, i32 0, i32 0) +// CHECK-NEXT: store <512 x i1> [[TMP1]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2]] // CHECK-NEXT: ret void // void test39(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { @@ -612,13 +545,11 @@ void test39(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, uns *((__vector_quad *)resp) = vq; } -// CHECK-LABEL: @test40( +// CHECK-LABEL: define {{[^@]+}}@test40( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>* -// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa [[TBAA2]] -// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvf32gerpp(<512 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]]) -// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>* -// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP0:%.*]] = load <512 x i1>, ptr [[VQP:%.*]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP1:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvf32gerpp(<512 x i1> [[TMP0]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]]) +// CHECK-NEXT: store <512 x i1> [[TMP1]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2]] // CHECK-NEXT: ret void // void test40(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { @@ -628,13 +559,11 @@ void test40(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, uns *((__vector_quad *)resp) = vq; } -// CHECK-LABEL: @test41( +// CHECK-LABEL: define {{[^@]+}}@test41( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>* -// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa [[TBAA2]] -// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvf32gerpn(<512 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]]) -// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>* -// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP0:%.*]] = load <512 x i1>, ptr [[VQP:%.*]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP1:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvf32gerpn(<512 x i1> [[TMP0]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]]) +// CHECK-NEXT: store <512 x i1> [[TMP1]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2]] // CHECK-NEXT: ret void // void test41(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { @@ -644,13 +573,11 @@ void test41(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, uns *((__vector_quad *)resp) = vq; } -// CHECK-LABEL: @test42( +// CHECK-LABEL: define {{[^@]+}}@test42( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>* -// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa [[TBAA2]] -// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvf32gernp(<512 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]]) -// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>* -// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP0:%.*]] = load <512 x i1>, ptr [[VQP:%.*]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP1:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvf32gernp(<512 x i1> [[TMP0]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]]) +// CHECK-NEXT: store <512 x i1> [[TMP1]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2]] // CHECK-NEXT: ret void // void test42(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { @@ -660,13 +587,11 @@ void test42(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, uns *((__vector_quad *)resp) = vq; } -// CHECK-LABEL: @test43( +// CHECK-LABEL: define {{[^@]+}}@test43( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>* -// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa [[TBAA2]] -// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvf32gernn(<512 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]]) -// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>* -// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP0:%.*]] = load <512 x i1>, ptr [[VQP:%.*]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP1:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvf32gernn(<512 x i1> [[TMP0]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]]) +// CHECK-NEXT: store <512 x i1> [[TMP1]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2]] // CHECK-NEXT: ret void // void test43(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { @@ -676,13 +601,11 @@ void test43(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, uns *((__vector_quad *)resp) = vq; } -// CHECK-LABEL: @test44( +// CHECK-LABEL: define {{[^@]+}}@test44( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>* -// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa [[TBAA2]] -// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvf32gerpp(<512 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]], i32 0, i32 0) -// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>* -// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP0:%.*]] = load <512 x i1>, ptr [[VQP:%.*]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP1:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvf32gerpp(<512 x i1> [[TMP0]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]], i32 0, i32 0) +// CHECK-NEXT: store <512 x i1> [[TMP1]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2]] // CHECK-NEXT: ret void // void test44(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { @@ -692,13 +615,11 @@ void test44(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, uns *((__vector_quad *)resp) = vq; } -// CHECK-LABEL: @test45( +// CHECK-LABEL: define {{[^@]+}}@test45( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>* -// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa [[TBAA2]] -// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvf32gerpn(<512 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]], i32 0, i32 0) -// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>* -// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP0:%.*]] = load <512 x i1>, ptr [[VQP:%.*]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP1:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvf32gerpn(<512 x i1> [[TMP0]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]], i32 0, i32 0) +// CHECK-NEXT: store <512 x i1> [[TMP1]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2]] // CHECK-NEXT: ret void // void test45(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { @@ -708,13 +629,11 @@ void test45(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, uns *((__vector_quad *)resp) = vq; } -// CHECK-LABEL: @test46( +// CHECK-LABEL: define {{[^@]+}}@test46( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>* -// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa [[TBAA2]] -// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvf32gernp(<512 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]], i32 0, i32 0) -// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>* -// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP0:%.*]] = load <512 x i1>, ptr [[VQP:%.*]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP1:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvf32gernp(<512 x i1> [[TMP0]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]], i32 0, i32 0) +// CHECK-NEXT: store <512 x i1> [[TMP1]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2]] // CHECK-NEXT: ret void // void test46(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { @@ -724,13 +643,11 @@ void test46(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, uns *((__vector_quad *)resp) = vq; } -// CHECK-LABEL: @test47( +// CHECK-LABEL: define {{[^@]+}}@test47( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>* -// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa [[TBAA2]] -// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvf32gernn(<512 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]], i32 0, i32 0) -// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>* -// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP0:%.*]] = load <512 x i1>, ptr [[VQP:%.*]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP1:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvf32gernn(<512 x i1> [[TMP0]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]], i32 0, i32 0) +// CHECK-NEXT: store <512 x i1> [[TMP1]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2]] // CHECK-NEXT: ret void // void test47(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { @@ -740,15 +657,12 @@ void test47(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, uns *((__vector_quad *)resp) = vq; } -// CHECK-LABEL: @test48( +// CHECK-LABEL: define {{[^@]+}}@test48( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>* -// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa [[TBAA2]] -// CHECK-NEXT: [[TMP2:%.*]] = bitcast i8* [[VPP:%.*]] to <256 x i1>* -// CHECK-NEXT: [[TMP3:%.*]] = load <256 x i1>, <256 x i1>* [[TMP2]], align 32, !tbaa [[TBAA6]] -// CHECK-NEXT: [[TMP4:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> [[TMP1]], <256 x i1> [[TMP3]], <16 x i8> [[VC:%.*]]) -// CHECK-NEXT: [[TMP5:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>* -// CHECK-NEXT: store <512 x i1> [[TMP4]], <512 x i1>* [[TMP5]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP0:%.*]] = load <512 x i1>, ptr [[VQP:%.*]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP1:%.*]] = load <256 x i1>, ptr [[VPP:%.*]], align 32, !tbaa [[TBAA6]] +// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> [[TMP0]], <256 x i1> [[TMP1]], <16 x i8> [[VC:%.*]]) +// CHECK-NEXT: store <512 x i1> [[TMP2]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2]] // CHECK-NEXT: ret void // void test48(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { @@ -758,15 +672,12 @@ void test48(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, uns *((__vector_quad *)resp) = vq; } -// CHECK-LABEL: @test49( +// CHECK-LABEL: define {{[^@]+}}@test49( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>* -// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa [[TBAA2]] -// CHECK-NEXT: [[TMP2:%.*]] = bitcast i8* [[VPP:%.*]] to <256 x i1>* -// CHECK-NEXT: [[TMP3:%.*]] = load <256 x i1>, <256 x i1>* [[TMP2]], align 32, !tbaa [[TBAA6]] -// CHECK-NEXT: [[TMP4:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpn(<512 x i1> [[TMP1]], <256 x i1> [[TMP3]], <16 x i8> [[VC:%.*]]) -// CHECK-NEXT: [[TMP5:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>* -// CHECK-NEXT: store <512 x i1> [[TMP4]], <512 x i1>* [[TMP5]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP0:%.*]] = load <512 x i1>, ptr [[VQP:%.*]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP1:%.*]] = load <256 x i1>, ptr [[VPP:%.*]], align 32, !tbaa [[TBAA6]] +// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpn(<512 x i1> [[TMP0]], <256 x i1> [[TMP1]], <16 x i8> [[VC:%.*]]) +// CHECK-NEXT: store <512 x i1> [[TMP2]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2]] // CHECK-NEXT: ret void // void test49(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { @@ -776,15 +687,12 @@ void test49(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, uns *((__vector_quad *)resp) = vq; } -// CHECK-LABEL: @test50( +// CHECK-LABEL: define {{[^@]+}}@test50( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>* -// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa [[TBAA2]] -// CHECK-NEXT: [[TMP2:%.*]] = bitcast i8* [[VPP:%.*]] to <256 x i1>* -// CHECK-NEXT: [[TMP3:%.*]] = load <256 x i1>, <256 x i1>* [[TMP2]], align 32, !tbaa [[TBAA6]] -// CHECK-NEXT: [[TMP4:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvf64gernp(<512 x i1> [[TMP1]], <256 x i1> [[TMP3]], <16 x i8> [[VC:%.*]]) -// CHECK-NEXT: [[TMP5:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>* -// CHECK-NEXT: store <512 x i1> [[TMP4]], <512 x i1>* [[TMP5]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP0:%.*]] = load <512 x i1>, ptr [[VQP:%.*]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP1:%.*]] = load <256 x i1>, ptr [[VPP:%.*]], align 32, !tbaa [[TBAA6]] +// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvf64gernp(<512 x i1> [[TMP0]], <256 x i1> [[TMP1]], <16 x i8> [[VC:%.*]]) +// CHECK-NEXT: store <512 x i1> [[TMP2]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2]] // CHECK-NEXT: ret void // void test50(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { @@ -794,15 +702,12 @@ void test50(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, uns *((__vector_quad *)resp) = vq; } -// CHECK-LABEL: @test51( +// CHECK-LABEL: define {{[^@]+}}@test51( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>* -// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa [[TBAA2]] -// CHECK-NEXT: [[TMP2:%.*]] = bitcast i8* [[VPP:%.*]] to <256 x i1>* -// CHECK-NEXT: [[TMP3:%.*]] = load <256 x i1>, <256 x i1>* [[TMP2]], align 32, !tbaa [[TBAA6]] -// CHECK-NEXT: [[TMP4:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvf64gernn(<512 x i1> [[TMP1]], <256 x i1> [[TMP3]], <16 x i8> [[VC:%.*]]) -// CHECK-NEXT: [[TMP5:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>* -// CHECK-NEXT: store <512 x i1> [[TMP4]], <512 x i1>* [[TMP5]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP0:%.*]] = load <512 x i1>, ptr [[VQP:%.*]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP1:%.*]] = load <256 x i1>, ptr [[VPP:%.*]], align 32, !tbaa [[TBAA6]] +// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvf64gernn(<512 x i1> [[TMP0]], <256 x i1> [[TMP1]], <16 x i8> [[VC:%.*]]) +// CHECK-NEXT: store <512 x i1> [[TMP2]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2]] // CHECK-NEXT: ret void // void test51(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { @@ -812,15 +717,12 @@ void test51(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, uns *((__vector_quad *)resp) = vq; } -// CHECK-LABEL: @test52( +// CHECK-LABEL: define {{[^@]+}}@test52( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>* -// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa [[TBAA2]] -// CHECK-NEXT: [[TMP2:%.*]] = bitcast i8* [[VPP:%.*]] to <256 x i1>* -// CHECK-NEXT: [[TMP3:%.*]] = load <256 x i1>, <256 x i1>* [[TMP2]], align 32, !tbaa [[TBAA6]] -// CHECK-NEXT: [[TMP4:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvf64gerpp(<512 x i1> [[TMP1]], <256 x i1> [[TMP3]], <16 x i8> [[VC:%.*]], i32 0, i32 0) -// CHECK-NEXT: [[TMP5:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>* -// CHECK-NEXT: store <512 x i1> [[TMP4]], <512 x i1>* [[TMP5]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP0:%.*]] = load <512 x i1>, ptr [[VQP:%.*]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP1:%.*]] = load <256 x i1>, ptr [[VPP:%.*]], align 32, !tbaa [[TBAA6]] +// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvf64gerpp(<512 x i1> [[TMP0]], <256 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], i32 0, i32 0) +// CHECK-NEXT: store <512 x i1> [[TMP2]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2]] // CHECK-NEXT: ret void // void test52(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { @@ -830,15 +732,12 @@ void test52(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, uns *((__vector_quad *)resp) = vq; } -// CHECK-LABEL: @test53( +// CHECK-LABEL: define {{[^@]+}}@test53( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>* -// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa [[TBAA2]] -// CHECK-NEXT: [[TMP2:%.*]] = bitcast i8* [[VPP:%.*]] to <256 x i1>* -// CHECK-NEXT: [[TMP3:%.*]] = load <256 x i1>, <256 x i1>* [[TMP2]], align 32, !tbaa [[TBAA6]] -// CHECK-NEXT: [[TMP4:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvf64gerpn(<512 x i1> [[TMP1]], <256 x i1> [[TMP3]], <16 x i8> [[VC:%.*]], i32 0, i32 0) -// CHECK-NEXT: [[TMP5:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>* -// CHECK-NEXT: store <512 x i1> [[TMP4]], <512 x i1>* [[TMP5]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP0:%.*]] = load <512 x i1>, ptr [[VQP:%.*]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP1:%.*]] = load <256 x i1>, ptr [[VPP:%.*]], align 32, !tbaa [[TBAA6]] +// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvf64gerpn(<512 x i1> [[TMP0]], <256 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], i32 0, i32 0) +// CHECK-NEXT: store <512 x i1> [[TMP2]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2]] // CHECK-NEXT: ret void // void test53(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { @@ -848,15 +747,12 @@ void test53(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, uns *((__vector_quad *)resp) = vq; } -// CHECK-LABEL: @test54( +// CHECK-LABEL: define {{[^@]+}}@test54( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>* -// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa [[TBAA2]] -// CHECK-NEXT: [[TMP2:%.*]] = bitcast i8* [[VPP:%.*]] to <256 x i1>* -// CHECK-NEXT: [[TMP3:%.*]] = load <256 x i1>, <256 x i1>* [[TMP2]], align 32, !tbaa [[TBAA6]] -// CHECK-NEXT: [[TMP4:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvf64gernp(<512 x i1> [[TMP1]], <256 x i1> [[TMP3]], <16 x i8> [[VC:%.*]], i32 0, i32 0) -// CHECK-NEXT: [[TMP5:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>* -// CHECK-NEXT: store <512 x i1> [[TMP4]], <512 x i1>* [[TMP5]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP0:%.*]] = load <512 x i1>, ptr [[VQP:%.*]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP1:%.*]] = load <256 x i1>, ptr [[VPP:%.*]], align 32, !tbaa [[TBAA6]] +// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvf64gernp(<512 x i1> [[TMP0]], <256 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], i32 0, i32 0) +// CHECK-NEXT: store <512 x i1> [[TMP2]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2]] // CHECK-NEXT: ret void // void test54(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { @@ -866,15 +762,12 @@ void test54(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, uns *((__vector_quad *)resp) = vq; } -// CHECK-LABEL: @test55( +// CHECK-LABEL: define {{[^@]+}}@test55( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>* -// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa [[TBAA2]] -// CHECK-NEXT: [[TMP2:%.*]] = bitcast i8* [[VPP:%.*]] to <256 x i1>* -// CHECK-NEXT: [[TMP3:%.*]] = load <256 x i1>, <256 x i1>* [[TMP2]], align 32, !tbaa [[TBAA6]] -// CHECK-NEXT: [[TMP4:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvf64gernn(<512 x i1> [[TMP1]], <256 x i1> [[TMP3]], <16 x i8> [[VC:%.*]], i32 0, i32 0) -// CHECK-NEXT: [[TMP5:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>* -// CHECK-NEXT: store <512 x i1> [[TMP4]], <512 x i1>* [[TMP5]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP0:%.*]] = load <512 x i1>, ptr [[VQP:%.*]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP1:%.*]] = load <256 x i1>, ptr [[VPP:%.*]], align 32, !tbaa [[TBAA6]] +// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvf64gernn(<512 x i1> [[TMP0]], <256 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], i32 0, i32 0) +// CHECK-NEXT: store <512 x i1> [[TMP2]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2]] // CHECK-NEXT: ret void // void test55(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { @@ -884,11 +777,10 @@ void test55(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, uns *((__vector_quad *)resp) = vq; } -// CHECK-LABEL: @test56( +// CHECK-LABEL: define {{[^@]+}}@test56( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvbf16ger2(<16 x i8> [[VC:%.*]], <16 x i8> [[VC]]) -// CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>* -// CHECK-NEXT: store <512 x i1> [[TMP0]], <512 x i1>* [[TMP1]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: store <512 x i1> [[TMP0]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2]] // CHECK-NEXT: ret void // void test56(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { @@ -898,11 +790,10 @@ void test56(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, uns *((__vector_quad *)resp) = vq; } -// CHECK-LABEL: @test57( +// CHECK-LABEL: define {{[^@]+}}@test57( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvbf16ger2(<16 x i8> [[VC:%.*]], <16 x i8> [[VC]], i32 0, i32 0, i32 0) -// CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>* -// CHECK-NEXT: store <512 x i1> [[TMP0]], <512 x i1>* [[TMP1]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: store <512 x i1> [[TMP0]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2]] // CHECK-NEXT: ret void // void test57(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { @@ -912,13 +803,11 @@ void test57(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, uns *((__vector_quad *)resp) = vq; } -// CHECK-LABEL: @test58( +// CHECK-LABEL: define {{[^@]+}}@test58( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>* -// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa [[TBAA2]] -// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvbf16ger2pp(<512 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]]) -// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>* -// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP0:%.*]] = load <512 x i1>, ptr [[VQP:%.*]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP1:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvbf16ger2pp(<512 x i1> [[TMP0]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]]) +// CHECK-NEXT: store <512 x i1> [[TMP1]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2]] // CHECK-NEXT: ret void // void test58(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { @@ -928,13 +817,11 @@ void test58(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, uns *((__vector_quad *)resp) = vq; } -// CHECK-LABEL: @test59( +// CHECK-LABEL: define {{[^@]+}}@test59( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>* -// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa [[TBAA2]] -// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvbf16ger2pn(<512 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]]) -// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>* -// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP0:%.*]] = load <512 x i1>, ptr [[VQP:%.*]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP1:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvbf16ger2pn(<512 x i1> [[TMP0]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]]) +// CHECK-NEXT: store <512 x i1> [[TMP1]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2]] // CHECK-NEXT: ret void // void test59(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { @@ -944,13 +831,11 @@ void test59(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, uns *((__vector_quad *)resp) = vq; } -// CHECK-LABEL: @test60( +// CHECK-LABEL: define {{[^@]+}}@test60( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>* -// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa [[TBAA2]] -// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvbf16ger2np(<512 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]]) -// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>* -// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP0:%.*]] = load <512 x i1>, ptr [[VQP:%.*]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP1:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvbf16ger2np(<512 x i1> [[TMP0]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]]) +// CHECK-NEXT: store <512 x i1> [[TMP1]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2]] // CHECK-NEXT: ret void // void test60(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { @@ -960,13 +845,11 @@ void test60(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, uns *((__vector_quad *)resp) = vq; } -// CHECK-LABEL: @test61( +// CHECK-LABEL: define {{[^@]+}}@test61( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>* -// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa [[TBAA2]] -// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvbf16ger2nn(<512 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]]) -// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>* -// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP0:%.*]] = load <512 x i1>, ptr [[VQP:%.*]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP1:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvbf16ger2nn(<512 x i1> [[TMP0]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]]) +// CHECK-NEXT: store <512 x i1> [[TMP1]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2]] // CHECK-NEXT: ret void // void test61(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { @@ -976,13 +859,11 @@ void test61(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, uns *((__vector_quad *)resp) = vq; } -// CHECK-LABEL: @test62( +// CHECK-LABEL: define {{[^@]+}}@test62( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>* -// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa [[TBAA2]] -// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvbf16ger2pp(<512 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]], i32 0, i32 0, i32 0) -// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>* -// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP0:%.*]] = load <512 x i1>, ptr [[VQP:%.*]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP1:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvbf16ger2pp(<512 x i1> [[TMP0]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]], i32 0, i32 0, i32 0) +// CHECK-NEXT: store <512 x i1> [[TMP1]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2]] // CHECK-NEXT: ret void // void test62(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { @@ -992,13 +873,11 @@ void test62(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, uns *((__vector_quad *)resp) = vq; } -// CHECK-LABEL: @test63( +// CHECK-LABEL: define {{[^@]+}}@test63( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>* -// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa [[TBAA2]] -// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvbf16ger2pn(<512 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]], i32 0, i32 0, i32 0) -// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>* -// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP0:%.*]] = load <512 x i1>, ptr [[VQP:%.*]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP1:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvbf16ger2pn(<512 x i1> [[TMP0]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]], i32 0, i32 0, i32 0) +// CHECK-NEXT: store <512 x i1> [[TMP1]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2]] // CHECK-NEXT: ret void // void test63(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { @@ -1008,13 +887,11 @@ void test63(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, uns *((__vector_quad *)resp) = vq; } -// CHECK-LABEL: @test64( +// CHECK-LABEL: define {{[^@]+}}@test64( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>* -// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa [[TBAA2]] -// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvbf16ger2np(<512 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]], i32 0, i32 0, i32 0) -// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>* -// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP0:%.*]] = load <512 x i1>, ptr [[VQP:%.*]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP1:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvbf16ger2np(<512 x i1> [[TMP0]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]], i32 0, i32 0, i32 0) +// CHECK-NEXT: store <512 x i1> [[TMP1]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2]] // CHECK-NEXT: ret void // void test64(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { @@ -1024,13 +901,11 @@ void test64(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, uns *((__vector_quad *)resp) = vq; } -// CHECK-LABEL: @test65( +// CHECK-LABEL: define {{[^@]+}}@test65( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>* -// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa [[TBAA2]] -// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvbf16ger2nn(<512 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]], i32 0, i32 0, i32 0) -// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>* -// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP0:%.*]] = load <512 x i1>, ptr [[VQP:%.*]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP1:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvbf16ger2nn(<512 x i1> [[TMP0]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]], i32 0, i32 0, i32 0) +// CHECK-NEXT: store <512 x i1> [[TMP1]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2]] // CHECK-NEXT: ret void // void test65(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { @@ -1040,12 +915,10 @@ void test65(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, uns *((__vector_quad *)resp) = vq; } -// CHECK-LABEL: @test66( +// CHECK-LABEL: define {{[^@]+}}@test66( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <256 x i1>* [[VPP:%.*]] to i8* -// CHECK-NEXT: [[TMP1:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* [[TMP0]]) -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <256 x i1>* [[VP2:%.*]] to i8* -// CHECK-NEXT: tail call void @llvm.ppc.vsx.stxvp(<256 x i1> [[TMP1]], i8* [[TMP2]]) +// CHECK-NEXT: [[TMP0:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(ptr [[VPP:%.*]]) +// CHECK-NEXT: tail call void @llvm.ppc.vsx.stxvp(<256 x i1> [[TMP0]], ptr [[VP2:%.*]]) // CHECK-NEXT: ret void // void test66(const __vector_pair *vpp, __vector_pair *vp2) { @@ -1053,14 +926,12 @@ void test66(const __vector_pair *vpp, __vector_pair *vp2) { __builtin_vsx_stxvp(vp, 0L, vp2); } -// CHECK-LABEL: @test67( +// CHECK-LABEL: define {{[^@]+}}@test67( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <256 x i1>* [[VPP:%.*]] to i8* -// CHECK-NEXT: [[TMP1:%.*]] = getelementptr i8, i8* [[TMP0]], i64 [[OFFSET:%.*]] -// CHECK-NEXT: [[TMP2:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* [[TMP1]]) -// CHECK-NEXT: [[TMP3:%.*]] = bitcast <256 x i1>* [[VP2:%.*]] to i8* -// CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, i8* [[TMP3]], i64 [[OFFSET]] -// CHECK-NEXT: tail call void @llvm.ppc.vsx.stxvp(<256 x i1> [[TMP2]], i8* [[TMP4]]) +// CHECK-NEXT: [[TMP0:%.*]] = getelementptr i8, ptr [[VPP:%.*]], i64 [[OFFSET:%.*]] +// CHECK-NEXT: [[TMP1:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(ptr [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[VP2:%.*]], i64 [[OFFSET]] +// CHECK-NEXT: tail call void @llvm.ppc.vsx.stxvp(<256 x i1> [[TMP1]], ptr [[TMP2]]) // CHECK-NEXT: ret void // void test67(const __vector_pair *vpp, signed long offset, __vector_pair *vp2) { @@ -1068,14 +939,12 @@ void test67(const __vector_pair *vpp, signed long offset, __vector_pair *vp2) { __builtin_vsx_stxvp(vp, offset, vp2); } -// CHECK-LABEL: @test68( +// CHECK-LABEL: define {{[^@]+}}@test68( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <256 x i1>* [[VPP:%.*]] to i8* -// CHECK-NEXT: [[TMP1:%.*]] = getelementptr i8, i8* [[TMP0]], i64 18 -// CHECK-NEXT: [[TMP2:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* [[TMP1]]) -// CHECK-NEXT: [[TMP3:%.*]] = bitcast <256 x i1>* [[VP2:%.*]] to i8* -// CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, i8* [[TMP3]], i64 18 -// CHECK-NEXT: tail call void @llvm.ppc.vsx.stxvp(<256 x i1> [[TMP2]], i8* [[TMP4]]) +// CHECK-NEXT: [[TMP0:%.*]] = getelementptr i8, ptr [[VPP:%.*]], i64 18 +// CHECK-NEXT: [[TMP1:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(ptr [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[VP2:%.*]], i64 18 +// CHECK-NEXT: tail call void @llvm.ppc.vsx.stxvp(<256 x i1> [[TMP1]], ptr [[TMP2]]) // CHECK-NEXT: ret void // void test68(const __vector_pair *vpp, __vector_pair *vp2) { @@ -1083,14 +952,12 @@ void test68(const __vector_pair *vpp, __vector_pair *vp2) { __builtin_vsx_stxvp(vp, 18L, vp2); } -// CHECK-LABEL: @test69( +// CHECK-LABEL: define {{[^@]+}}@test69( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <256 x i1>* [[VPP:%.*]] to i8* -// CHECK-NEXT: [[TMP1:%.*]] = getelementptr i8, i8* [[TMP0]], i64 1 -// CHECK-NEXT: [[TMP2:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* [[TMP1]]) -// CHECK-NEXT: [[TMP3:%.*]] = bitcast <256 x i1>* [[VP2:%.*]] to i8* -// CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, i8* [[TMP3]], i64 1 -// CHECK-NEXT: tail call void @llvm.ppc.vsx.stxvp(<256 x i1> [[TMP2]], i8* [[TMP4]]) +// CHECK-NEXT: [[TMP0:%.*]] = getelementptr i8, ptr [[VPP:%.*]], i64 1 +// CHECK-NEXT: [[TMP1:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(ptr [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[VP2:%.*]], i64 1 +// CHECK-NEXT: tail call void @llvm.ppc.vsx.stxvp(<256 x i1> [[TMP1]], ptr [[TMP2]]) // CHECK-NEXT: ret void // void test69(const __vector_pair *vpp, __vector_pair *vp2) { @@ -1098,14 +965,12 @@ void test69(const __vector_pair *vpp, __vector_pair *vp2) { __builtin_vsx_stxvp(vp, 1L, vp2); } -// CHECK-LABEL: @test70( +// CHECK-LABEL: define {{[^@]+}}@test70( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <256 x i1>* [[VPP:%.*]] to i8* -// CHECK-NEXT: [[TMP1:%.*]] = getelementptr i8, i8* [[TMP0]], i64 42 -// CHECK-NEXT: [[TMP2:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* [[TMP1]]) -// CHECK-NEXT: [[TMP3:%.*]] = bitcast <256 x i1>* [[VP2:%.*]] to i8* -// CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, i8* [[TMP3]], i64 42 -// CHECK-NEXT: tail call void @llvm.ppc.vsx.stxvp(<256 x i1> [[TMP2]], i8* [[TMP4]]) +// CHECK-NEXT: [[TMP0:%.*]] = getelementptr i8, ptr [[VPP:%.*]], i64 42 +// CHECK-NEXT: [[TMP1:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(ptr [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[VP2:%.*]], i64 42 +// CHECK-NEXT: tail call void @llvm.ppc.vsx.stxvp(<256 x i1> [[TMP1]], ptr [[TMP2]]) // CHECK-NEXT: ret void // void test70(const __vector_pair *vpp, __vector_pair *vp2) { @@ -1113,14 +978,12 @@ void test70(const __vector_pair *vpp, __vector_pair *vp2) { __builtin_vsx_stxvp(vp, 42L, vp2); } -// CHECK-LABEL: @test71( +// CHECK-LABEL: define {{[^@]+}}@test71( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = getelementptr <256 x i1>, <256 x i1>* [[VPP:%.*]], i64 1024 -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <256 x i1>* [[TMP0]] to i8* -// CHECK-NEXT: [[TMP2:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* [[TMP1]]) -// CHECK-NEXT: [[TMP3:%.*]] = getelementptr <256 x i1>, <256 x i1>* [[VP2:%.*]], i64 1024 -// CHECK-NEXT: [[TMP4:%.*]] = bitcast <256 x i1>* [[TMP3]] to i8* -// CHECK-NEXT: tail call void @llvm.ppc.vsx.stxvp(<256 x i1> [[TMP2]], i8* [[TMP4]]) +// CHECK-NEXT: [[TMP0:%.*]] = getelementptr i8, ptr [[VPP:%.*]], i64 32768 +// CHECK-NEXT: [[TMP1:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(ptr [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[VP2:%.*]], i64 32768 +// CHECK-NEXT: tail call void @llvm.ppc.vsx.stxvp(<256 x i1> [[TMP1]], ptr [[TMP2]]) // CHECK-NEXT: ret void // void test71(const __vector_pair *vpp, __vector_pair *vp2) { @@ -1128,14 +991,12 @@ void test71(const __vector_pair *vpp, __vector_pair *vp2) { __builtin_vsx_stxvp(vp, 32768L, vp2); } -// CHECK-LABEL: @test72( +// CHECK-LABEL: define {{[^@]+}}@test72( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <256 x i1>* [[VPP:%.*]] to i8* -// CHECK-NEXT: [[TMP1:%.*]] = getelementptr i8, i8* [[TMP0]], i64 32799 -// CHECK-NEXT: [[TMP2:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* [[TMP1]]) -// CHECK-NEXT: [[TMP3:%.*]] = bitcast <256 x i1>* [[VP2:%.*]] to i8* -// CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, i8* [[TMP3]], i64 32799 -// CHECK-NEXT: tail call void @llvm.ppc.vsx.stxvp(<256 x i1> [[TMP2]], i8* [[TMP4]]) +// CHECK-NEXT: [[TMP0:%.*]] = getelementptr i8, ptr [[VPP:%.*]], i64 32799 +// CHECK-NEXT: [[TMP1:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(ptr [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[VP2:%.*]], i64 32799 +// CHECK-NEXT: tail call void @llvm.ppc.vsx.stxvp(<256 x i1> [[TMP1]], ptr [[TMP2]]) // CHECK-NEXT: ret void // void test72(const __vector_pair *vpp, __vector_pair *vp2) { @@ -1143,16 +1004,13 @@ void test72(const __vector_pair *vpp, __vector_pair *vp2) { __builtin_vsx_stxvp(vp, 32799L, vp2); } -// CHECK-LABEL: @test73( +// CHECK-LABEL: define {{[^@]+}}@test73( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>* -// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa [[TBAA2]] -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <256 x i1>* [[VPP:%.*]] to i8* -// CHECK-NEXT: [[TMP3:%.*]] = getelementptr i8, i8* [[TMP2]], i64 8 -// CHECK-NEXT: [[TMP4:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* [[TMP3]]) -// CHECK-NEXT: [[TMP5:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvf64gernn(<512 x i1> [[TMP1]], <256 x i1> [[TMP4]], <16 x i8> [[VC:%.*]], i32 0, i32 0) -// CHECK-NEXT: [[TMP6:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>* -// CHECK-NEXT: store <512 x i1> [[TMP5]], <512 x i1>* [[TMP6]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP0:%.*]] = load <512 x i1>, ptr [[VQP:%.*]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr [[VPP:%.*]], i64 8 +// CHECK-NEXT: [[TMP2:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(ptr [[TMP1]]) +// CHECK-NEXT: [[TMP3:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvf64gernn(<512 x i1> [[TMP0]], <256 x i1> [[TMP2]], <16 x i8> [[VC:%.*]], i32 0, i32 0) +// CHECK-NEXT: store <512 x i1> [[TMP3]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2]] // CHECK-NEXT: ret void // void test73(unsigned char *vqp, const __vector_pair *vpp, vector unsigned char vc, unsigned char *resp) { @@ -1162,15 +1020,12 @@ void test73(unsigned char *vqp, const __vector_pair *vpp, vector unsigned char v *((__vector_quad *)resp) = vq; } -// CHECK-LABEL: @test74( +// CHECK-LABEL: define {{[^@]+}}@test74( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>* -// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa [[TBAA2]] -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <256 x i1>* [[VPP:%.*]] to i8* -// CHECK-NEXT: [[TMP3:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* [[TMP2]]) -// CHECK-NEXT: [[TMP4:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvf64gernp(<512 x i1> [[TMP1]], <256 x i1> [[TMP3]], <16 x i8> [[VC:%.*]]) -// CHECK-NEXT: [[TMP5:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>* -// CHECK-NEXT: store <512 x i1> [[TMP4]], <512 x i1>* [[TMP5]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP0:%.*]] = load <512 x i1>, ptr [[VQP:%.*]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP1:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(ptr [[VPP:%.*]]) +// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvf64gernp(<512 x i1> [[TMP0]], <256 x i1> [[TMP1]], <16 x i8> [[VC:%.*]]) +// CHECK-NEXT: store <512 x i1> [[TMP2]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2]] // CHECK-NEXT: ret void // void test74(unsigned char *vqp, const __vector_pair *vpp, vector unsigned char vc, unsigned char *resp) { @@ -1180,16 +1035,13 @@ void test74(unsigned char *vqp, const __vector_pair *vpp, vector unsigned char v *((__vector_quad *)resp) = vq; } -// CHECK-LABEL: @test75( +// CHECK-LABEL: define {{[^@]+}}@test75( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>* -// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa [[TBAA2]] -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <256 x i1>* [[VPP:%.*]] to i8* -// CHECK-NEXT: [[TMP3:%.*]] = getelementptr i8, i8* [[TMP2]], i64 [[OFFS:%.*]] -// CHECK-NEXT: [[TMP4:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* [[TMP3]]) -// CHECK-NEXT: [[TMP5:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvf64gernp(<512 x i1> [[TMP1]], <256 x i1> [[TMP4]], <16 x i8> [[VC:%.*]]) -// CHECK-NEXT: [[TMP6:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>* -// CHECK-NEXT: store <512 x i1> [[TMP5]], <512 x i1>* [[TMP6]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP0:%.*]] = load <512 x i1>, ptr [[VQP:%.*]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr [[VPP:%.*]], i64 [[OFFS:%.*]] +// CHECK-NEXT: [[TMP2:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(ptr [[TMP1]]) +// CHECK-NEXT: [[TMP3:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvf64gernp(<512 x i1> [[TMP0]], <256 x i1> [[TMP2]], <16 x i8> [[VC:%.*]]) +// CHECK-NEXT: store <512 x i1> [[TMP3]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2]] // CHECK-NEXT: ret void // void test75(unsigned char *vqp, signed long offs, const __vector_pair *vpp, vector unsigned char vc, unsigned char *resp) { @@ -1199,11 +1051,10 @@ void test75(unsigned char *vqp, signed long offs, const __vector_pair *vpp, vect *((__vector_quad *)resp) = vq; } -// CHECK-LABEL: @test76( +// CHECK-LABEL: define {{[^@]+}}@test76( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8> [[VC:%.*]], <16 x i8> [[VC]]) -// CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <256 x i1>* -// CHECK-NEXT: store <256 x i1> [[TMP0]], <256 x i1>* [[TMP1]], align 32, !tbaa [[TBAA6]] +// CHECK-NEXT: store <256 x i1> [[TMP0]], ptr [[RESP:%.*]], align 32, !tbaa [[TBAA6]] // CHECK-NEXT: ret void // void test76(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { @@ -1214,30 +1065,25 @@ void test76(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, uns *((__vector_pair *)resp) = res; } -// CHECK-LABEL: @test77( +// CHECK-LABEL: define {{[^@]+}}@test77( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VPP:%.*]] to <256 x i1>* -// CHECK-NEXT: [[TMP1:%.*]] = load <256 x i1>, <256 x i1>* [[TMP0]], align 32 -// CHECK-NEXT: [[TMP2:%.*]] = tail call { <16 x i8>, <16 x i8> } @llvm.ppc.vsx.disassemble.pair(<256 x i1> [[TMP1]]) -// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <16 x i8>* -// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[TMP2]], 0 -// CHECK-NEXT: store <16 x i8> [[TMP4]], <16 x i8>* [[TMP3]], align 16 -// CHECK-NEXT: [[TMP5:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[TMP2]], 1 -// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i8, i8* [[RESP]], i64 16 -// CHECK-NEXT: [[TMP7:%.*]] = bitcast i8* [[TMP6]] to <16 x i8>* -// CHECK-NEXT: store <16 x i8> [[TMP5]], <16 x i8>* [[TMP7]], align 16 +// CHECK-NEXT: [[TMP0:%.*]] = load <256 x i1>, ptr [[VPP:%.*]], align 32 +// CHECK-NEXT: [[TMP1:%.*]] = tail call { <16 x i8>, <16 x i8> } @llvm.ppc.vsx.disassemble.pair(<256 x i1> [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[TMP1]], 0 +// CHECK-NEXT: store <16 x i8> [[TMP2]], ptr [[RESP:%.*]], align 16 +// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[TMP1]], 1 +// CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds <16 x i8>, ptr [[RESP]], i64 1 +// CHECK-NEXT: store <16 x i8> [[TMP3]], ptr [[TMP4]], align 16 // CHECK-NEXT: ret void // void test77(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) { __builtin_mma_disassemble_pair(resp, (__vector_pair*)vpp); } -// CHECK-LABEL: @test78( +// CHECK-LABEL: define {{[^@]+}}@test78( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <256 x i1>* [[VPP:%.*]] to i8* -// CHECK-NEXT: [[TMP1:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* [[TMP0]]) -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <256 x i1>* [[VP2:%.*]] to i8* -// CHECK-NEXT: tail call void @llvm.ppc.vsx.stxvp(<256 x i1> [[TMP1]], i8* [[TMP2]]) +// CHECK-NEXT: [[TMP0:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(ptr [[VPP:%.*]]) +// CHECK-NEXT: tail call void @llvm.ppc.vsx.stxvp(<256 x i1> [[TMP0]], ptr [[VP2:%.*]]) // CHECK-NEXT: ret void // void test78(const __vector_pair *vpp, __vector_pair *vp2) { @@ -1245,14 +1091,12 @@ void test78(const __vector_pair *vpp, __vector_pair *vp2) { __builtin_mma_stxvp(vp, 0L, vp2); } -// CHECK-LABEL: @test79( +// CHECK-LABEL: define {{[^@]+}}@test79( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <256 x i1>* [[VPP:%.*]] to i8* -// CHECK-NEXT: [[TMP1:%.*]] = getelementptr i8, i8* [[TMP0]], i64 [[OFFSET:%.*]] -// CHECK-NEXT: [[TMP2:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* [[TMP1]]) -// CHECK-NEXT: [[TMP3:%.*]] = bitcast <256 x i1>* [[VP2:%.*]] to i8* -// CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, i8* [[TMP3]], i64 [[OFFSET]] -// CHECK-NEXT: tail call void @llvm.ppc.vsx.stxvp(<256 x i1> [[TMP2]], i8* [[TMP4]]) +// CHECK-NEXT: [[TMP0:%.*]] = getelementptr i8, ptr [[VPP:%.*]], i64 [[OFFSET:%.*]] +// CHECK-NEXT: [[TMP1:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(ptr [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[VP2:%.*]], i64 [[OFFSET]] +// CHECK-NEXT: tail call void @llvm.ppc.vsx.stxvp(<256 x i1> [[TMP1]], ptr [[TMP2]]) // CHECK-NEXT: ret void // void test79(const __vector_pair *vpp, signed long offset, __vector_pair *vp2) { @@ -1260,14 +1104,12 @@ void test79(const __vector_pair *vpp, signed long offset, __vector_pair *vp2) { __builtin_mma_stxvp(vp, offset, vp2); } -// CHECK-LABEL: @test80( +// CHECK-LABEL: define {{[^@]+}}@test80( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <256 x i1>* [[VPP:%.*]] to i8* -// CHECK-NEXT: [[TMP1:%.*]] = getelementptr i8, i8* [[TMP0]], i64 18 -// CHECK-NEXT: [[TMP2:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* [[TMP1]]) -// CHECK-NEXT: [[TMP3:%.*]] = bitcast <256 x i1>* [[VP2:%.*]] to i8* -// CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, i8* [[TMP3]], i64 18 -// CHECK-NEXT: tail call void @llvm.ppc.vsx.stxvp(<256 x i1> [[TMP2]], i8* [[TMP4]]) +// CHECK-NEXT: [[TMP0:%.*]] = getelementptr i8, ptr [[VPP:%.*]], i64 18 +// CHECK-NEXT: [[TMP1:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(ptr [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[VP2:%.*]], i64 18 +// CHECK-NEXT: tail call void @llvm.ppc.vsx.stxvp(<256 x i1> [[TMP1]], ptr [[TMP2]]) // CHECK-NEXT: ret void // void test80(const __vector_pair *vpp, __vector_pair *vp2) { @@ -1275,14 +1117,12 @@ void test80(const __vector_pair *vpp, __vector_pair *vp2) { __builtin_mma_stxvp(vp, 18L, vp2); } -// CHECK-LABEL: @test81( +// CHECK-LABEL: define {{[^@]+}}@test81( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <256 x i1>* [[VPP:%.*]] to i8* -// CHECK-NEXT: [[TMP1:%.*]] = getelementptr i8, i8* [[TMP0]], i64 1 -// CHECK-NEXT: [[TMP2:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* [[TMP1]]) -// CHECK-NEXT: [[TMP3:%.*]] = bitcast <256 x i1>* [[VP2:%.*]] to i8* -// CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, i8* [[TMP3]], i64 1 -// CHECK-NEXT: tail call void @llvm.ppc.vsx.stxvp(<256 x i1> [[TMP2]], i8* [[TMP4]]) +// CHECK-NEXT: [[TMP0:%.*]] = getelementptr i8, ptr [[VPP:%.*]], i64 1 +// CHECK-NEXT: [[TMP1:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(ptr [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[VP2:%.*]], i64 1 +// CHECK-NEXT: tail call void @llvm.ppc.vsx.stxvp(<256 x i1> [[TMP1]], ptr [[TMP2]]) // CHECK-NEXT: ret void // void test81(const __vector_pair *vpp, __vector_pair *vp2) { @@ -1290,14 +1130,12 @@ void test81(const __vector_pair *vpp, __vector_pair *vp2) { __builtin_mma_stxvp(vp, 1L, vp2); } -// CHECK-LABEL: @test82( +// CHECK-LABEL: define {{[^@]+}}@test82( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <256 x i1>* [[VPP:%.*]] to i8* -// CHECK-NEXT: [[TMP1:%.*]] = getelementptr i8, i8* [[TMP0]], i64 42 -// CHECK-NEXT: [[TMP2:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* [[TMP1]]) -// CHECK-NEXT: [[TMP3:%.*]] = bitcast <256 x i1>* [[VP2:%.*]] to i8* -// CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, i8* [[TMP3]], i64 42 -// CHECK-NEXT: tail call void @llvm.ppc.vsx.stxvp(<256 x i1> [[TMP2]], i8* [[TMP4]]) +// CHECK-NEXT: [[TMP0:%.*]] = getelementptr i8, ptr [[VPP:%.*]], i64 42 +// CHECK-NEXT: [[TMP1:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(ptr [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[VP2:%.*]], i64 42 +// CHECK-NEXT: tail call void @llvm.ppc.vsx.stxvp(<256 x i1> [[TMP1]], ptr [[TMP2]]) // CHECK-NEXT: ret void // void test82(const __vector_pair *vpp, __vector_pair *vp2) { @@ -1305,14 +1143,12 @@ void test82(const __vector_pair *vpp, __vector_pair *vp2) { __builtin_mma_stxvp(vp, 42L, vp2); } -// CHECK-LABEL: @test83( +// CHECK-LABEL: define {{[^@]+}}@test83( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = getelementptr <256 x i1>, <256 x i1>* [[VPP:%.*]], i64 1024 -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <256 x i1>* [[TMP0]] to i8* -// CHECK-NEXT: [[TMP2:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* [[TMP1]]) -// CHECK-NEXT: [[TMP3:%.*]] = getelementptr <256 x i1>, <256 x i1>* [[VP2:%.*]], i64 1024 -// CHECK-NEXT: [[TMP4:%.*]] = bitcast <256 x i1>* [[TMP3]] to i8* -// CHECK-NEXT: tail call void @llvm.ppc.vsx.stxvp(<256 x i1> [[TMP2]], i8* [[TMP4]]) +// CHECK-NEXT: [[TMP0:%.*]] = getelementptr i8, ptr [[VPP:%.*]], i64 32768 +// CHECK-NEXT: [[TMP1:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(ptr [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[VP2:%.*]], i64 32768 +// CHECK-NEXT: tail call void @llvm.ppc.vsx.stxvp(<256 x i1> [[TMP1]], ptr [[TMP2]]) // CHECK-NEXT: ret void // void test83(const __vector_pair *vpp, __vector_pair *vp2) { @@ -1320,14 +1156,12 @@ void test83(const __vector_pair *vpp, __vector_pair *vp2) { __builtin_mma_stxvp(vp, 32768L, vp2); } -// CHECK-LABEL: @test84( +// CHECK-LABEL: define {{[^@]+}}@test84( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <256 x i1>* [[VPP:%.*]] to i8* -// CHECK-NEXT: [[TMP1:%.*]] = getelementptr i8, i8* [[TMP0]], i64 32799 -// CHECK-NEXT: [[TMP2:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* [[TMP1]]) -// CHECK-NEXT: [[TMP3:%.*]] = bitcast <256 x i1>* [[VP2:%.*]] to i8* -// CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, i8* [[TMP3]], i64 32799 -// CHECK-NEXT: tail call void @llvm.ppc.vsx.stxvp(<256 x i1> [[TMP2]], i8* [[TMP4]]) +// CHECK-NEXT: [[TMP0:%.*]] = getelementptr i8, ptr [[VPP:%.*]], i64 32799 +// CHECK-NEXT: [[TMP1:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(ptr [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[VP2:%.*]], i64 32799 +// CHECK-NEXT: tail call void @llvm.ppc.vsx.stxvp(<256 x i1> [[TMP1]], ptr [[TMP2]]) // CHECK-NEXT: ret void // void test84(const __vector_pair *vpp, __vector_pair *vp2) { @@ -1335,16 +1169,13 @@ void test84(const __vector_pair *vpp, __vector_pair *vp2) { __builtin_mma_stxvp(vp, 32799L, vp2); } -// CHECK-LABEL: @test85( +// CHECK-LABEL: define {{[^@]+}}@test85( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>* -// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa [[TBAA2]] -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <256 x i1>* [[VPP:%.*]] to i8* -// CHECK-NEXT: [[TMP3:%.*]] = getelementptr i8, i8* [[TMP2]], i64 8 -// CHECK-NEXT: [[TMP4:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* [[TMP3]]) -// CHECK-NEXT: [[TMP5:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvf64gernn(<512 x i1> [[TMP1]], <256 x i1> [[TMP4]], <16 x i8> [[VC:%.*]], i32 0, i32 0) -// CHECK-NEXT: [[TMP6:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>* -// CHECK-NEXT: store <512 x i1> [[TMP5]], <512 x i1>* [[TMP6]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP0:%.*]] = load <512 x i1>, ptr [[VQP:%.*]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr [[VPP:%.*]], i64 8 +// CHECK-NEXT: [[TMP2:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(ptr [[TMP1]]) +// CHECK-NEXT: [[TMP3:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvf64gernn(<512 x i1> [[TMP0]], <256 x i1> [[TMP2]], <16 x i8> [[VC:%.*]], i32 0, i32 0) +// CHECK-NEXT: store <512 x i1> [[TMP3]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2]] // CHECK-NEXT: ret void // void test85(unsigned char *vqp, const __vector_pair *vpp, vector unsigned char vc, unsigned char *resp) { @@ -1354,15 +1185,12 @@ void test85(unsigned char *vqp, const __vector_pair *vpp, vector unsigned char v *((__vector_quad *)resp) = vq; } -// CHECK-LABEL: @test86( +// CHECK-LABEL: define {{[^@]+}}@test86( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>* -// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa [[TBAA2]] -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <256 x i1>* [[VPP:%.*]] to i8* -// CHECK-NEXT: [[TMP3:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* [[TMP2]]) -// CHECK-NEXT: [[TMP4:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvf64gernp(<512 x i1> [[TMP1]], <256 x i1> [[TMP3]], <16 x i8> [[VC:%.*]]) -// CHECK-NEXT: [[TMP5:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>* -// CHECK-NEXT: store <512 x i1> [[TMP4]], <512 x i1>* [[TMP5]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP0:%.*]] = load <512 x i1>, ptr [[VQP:%.*]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP1:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(ptr [[VPP:%.*]]) +// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvf64gernp(<512 x i1> [[TMP0]], <256 x i1> [[TMP1]], <16 x i8> [[VC:%.*]]) +// CHECK-NEXT: store <512 x i1> [[TMP2]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2]] // CHECK-NEXT: ret void // void test86(unsigned char *vqp, const __vector_pair *vpp, vector unsigned char vc, unsigned char *resp) { @@ -1372,16 +1200,13 @@ void test86(unsigned char *vqp, const __vector_pair *vpp, vector unsigned char v *((__vector_quad *)resp) = vq; } -// CHECK-LABEL: @test87( +// CHECK-LABEL: define {{[^@]+}}@test87( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>* -// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa [[TBAA2]] -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <256 x i1>* [[VPP:%.*]] to i8* -// CHECK-NEXT: [[TMP3:%.*]] = getelementptr i8, i8* [[TMP2]], i64 [[OFFS:%.*]] -// CHECK-NEXT: [[TMP4:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* [[TMP3]]) -// CHECK-NEXT: [[TMP5:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvf64gernp(<512 x i1> [[TMP1]], <256 x i1> [[TMP4]], <16 x i8> [[VC:%.*]]) -// CHECK-NEXT: [[TMP6:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>* -// CHECK-NEXT: store <512 x i1> [[TMP5]], <512 x i1>* [[TMP6]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP0:%.*]] = load <512 x i1>, ptr [[VQP:%.*]], align 64, !tbaa [[TBAA2]] +// CHECK-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr [[VPP:%.*]], i64 [[OFFS:%.*]] +// CHECK-NEXT: [[TMP2:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(ptr [[TMP1]]) +// CHECK-NEXT: [[TMP3:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvf64gernp(<512 x i1> [[TMP0]], <256 x i1> [[TMP2]], <16 x i8> [[VC:%.*]]) +// CHECK-NEXT: store <512 x i1> [[TMP3]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2]] // CHECK-NEXT: ret void // void test87(unsigned char *vqp, signed long offs, const __vector_pair *vpp, vector unsigned char vc, unsigned char *resp) { diff --git a/clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c b/clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c index 780131c8a82c7b..e85a09be64230a 100644 --- a/clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c +++ b/clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c @@ -1,8 +1,8 @@ // REQUIRES: powerpc-registered-target -// RUN: %clang_cc1 -flax-vector-conversions=none -no-opaque-pointers -target-feature \ +// RUN: %clang_cc1 -flax-vector-conversions=none -target-feature \ // RUN: +altivec -target-feature +vsx -triple powerpc64-unknown-unknown -emit-llvm \ // RUN: -U__XL_COMPAT_ALTIVEC__ %s -o - | FileCheck %s -// RUN: %clang_cc1 -flax-vector-conversions=none -no-opaque-pointers -target-feature \ +// RUN: %clang_cc1 -flax-vector-conversions=none -target-feature \ // RUN: +altivec -target-feature +vsx -triple powerpc64le-unknown-unknown \ // RUN: -emit-llvm -U__XL_COMPAT_ALTIVEC__ %s -o - | FileCheck %s -check-prefix=CHECK-LE #include @@ -1778,34 +1778,34 @@ void test1() { // CHECK-LE: shufflevector <2 x double> %{{[0-9]+}}, <2 x double> %{{[0-9]+}}, <2 x i32> res_vbll = vec_revb(vbll); -// CHECK: store <16 x i8> , <16 x i8>* {{%.+}}, align 16 +// CHECK: store <16 x i8> , ptr {{%.+}}, align 16 // CHECK: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}}) -// CHECK-LE: store <16 x i8> , <16 x i8>* {{%.+}}, align 16 -// CHECK-LE: store <16 x i8> , <16 x i8>* {{%.+}}, align 16 +// CHECK-LE: store <16 x i8> , ptr {{%.+}}, align 16 +// CHECK-LE: store <16 x i8> , ptr {{%.+}}, align 16 // CHECK-LE: xor <16 x i8> // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}}) res_vsll = vec_revb(vsll); -// CHECK: store <16 x i8> , <16 x i8>* {{%.+}}, align 16 +// CHECK: store <16 x i8> , ptr {{%.+}}, align 16 // CHECK: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}}) -// CHECK-LE: store <16 x i8> , <16 x i8>* {{%.+}}, align 16 -// CHECK-LE: store <16 x i8> , <16 x i8>* {{%.+}}, align 16 +// CHECK-LE: store <16 x i8> , ptr {{%.+}}, align 16 +// CHECK-LE: store <16 x i8> , ptr {{%.+}}, align 16 // CHECK-LE: xor <16 x i8> // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}}) res_vull = vec_revb(vull); -// CHECK: store <16 x i8> , <16 x i8>* {{%.+}}, align 16 +// CHECK: store <16 x i8> , ptr {{%.+}}, align 16 // CHECK: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}}) -// CHECK-LE: store <16 x i8> , <16 x i8>* {{%.+}}, align 16 -// CHECK-LE: store <16 x i8> , <16 x i8>* {{%.+}}, align 16 +// CHECK-LE: store <16 x i8> , ptr {{%.+}}, align 16 +// CHECK-LE: store <16 x i8> , ptr {{%.+}}, align 16 // CHECK-LE: xor <16 x i8> // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}}) res_vd = vec_revb(vd); -// CHECK: store <16 x i8> , <16 x i8>* {{%.+}}, align 16 +// CHECK: store <16 x i8> , ptr {{%.+}}, align 16 // CHECK: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}}) -// CHECK-LE: store <16 x i8> , <16 x i8>* {{%.+}}, align 16 -// CHECK-LE: store <16 x i8> , <16 x i8>* {{%.+}}, align 16 +// CHECK-LE: store <16 x i8> , ptr {{%.+}}, align 16 +// CHECK-LE: store <16 x i8> , ptr {{%.+}}, align 16 // CHECK-LE: xor <16 x i8> // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}}) @@ -1942,40 +1942,40 @@ res_vsll = vec_slo(vsll, vsc); // CHECK-LE: @llvm.ppc.altivec.vsro res_vsll = vec_xl(sll, asll); -// CHECK: load <2 x i64>, <2 x i64>* %{{[0-9]+}}, align 1 -// CHECK-LE: load <2 x i64>, <2 x i64>* %{{[0-9]+}}, align 1 +// CHECK: load <2 x i64>, ptr %{{[0-9]+}}, align 1 +// CHECK-LE: load <2 x i64>, ptr %{{[0-9]+}}, align 1 res_vull = vec_xl(sll, aull); -// CHECK: load <2 x i64>, <2 x i64>* %{{[0-9]+}}, align 1 -// CHECK-LE: load <2 x i64>, <2 x i64>* %{{[0-9]+}}, align 1 +// CHECK: load <2 x i64>, ptr %{{[0-9]+}}, align 1 +// CHECK-LE: load <2 x i64>, ptr %{{[0-9]+}}, align 1 res_vd = vec_xl(sll, ad); -// CHECK: load <2 x double>, <2 x double>* %{{[0-9]+}}, align 1 -// CHECK-LE: load <2 x double>, <2 x double>* %{{[0-9]+}}, align 1 +// CHECK: load <2 x double>, ptr %{{[0-9]+}}, align 1 +// CHECK-LE: load <2 x double>, ptr %{{[0-9]+}}, align 1 vec_xst(vsll, sll, asll); -// CHECK: store <2 x i64> %{{[0-9]+}}, <2 x i64>* %{{[0-9]+}}, align 1 -// CHECK-LE: store <2 x i64> %{{[0-9]+}}, <2 x i64>* %{{[0-9]+}}, align 1 +// CHECK: store <2 x i64> %{{[0-9]+}}, ptr %{{[0-9]+}}, align 1 +// CHECK-LE: store <2 x i64> %{{[0-9]+}}, ptr %{{[0-9]+}}, align 1 vec_xst(vull, sll, aull); -// CHECK: store <2 x i64> %{{[0-9]+}}, <2 x i64>* %{{[0-9]+}}, align 1 -// CHECK-LE: store <2 x i64> %{{[0-9]+}}, <2 x i64>* %{{[0-9]+}}, align 1 +// CHECK: store <2 x i64> %{{[0-9]+}}, ptr %{{[0-9]+}}, align 1 +// CHECK-LE: store <2 x i64> %{{[0-9]+}}, ptr %{{[0-9]+}}, align 1 vec_xst(vd, sll, ad); -// CHECK: store <2 x double> %{{[0-9]+}}, <2 x double>* %{{[0-9]+}}, align 1 -// CHECK-LE: store <2 x double> %{{[0-9]+}}, <2 x double>* %{{[0-9]+}}, align 1 +// CHECK: store <2 x double> %{{[0-9]+}}, ptr %{{[0-9]+}}, align 1 +// CHECK-LE: store <2 x double> %{{[0-9]+}}, ptr %{{[0-9]+}}, align 1 res_vsll = vec_xl_be(sll, asll); -// CHECK: load <2 x i64>, <2 x i64>* %{{[0-9]+}}, align 1 -// CHECK-LE: call <2 x double> @llvm.ppc.vsx.lxvd2x.be(i8* %{{[0-9]+}}) +// CHECK: load <2 x i64>, ptr %{{[0-9]+}}, align 1 +// CHECK-LE: call <2 x double> @llvm.ppc.vsx.lxvd2x.be(ptr %{{[0-9]+}}) res_vull = vec_xl_be(sll, aull); -// CHECK: load <2 x i64>, <2 x i64>* %{{[0-9]+}}, align 1 -// CHECK-LE: call <2 x double> @llvm.ppc.vsx.lxvd2x.be(i8* %{{[0-9]+}}) +// CHECK: load <2 x i64>, ptr %{{[0-9]+}}, align 1 +// CHECK-LE: call <2 x double> @llvm.ppc.vsx.lxvd2x.be(ptr %{{[0-9]+}}) res_vd = vec_xl_be(sll, ad); -// CHECK: load <2 x double>, <2 x double>* %{{[0-9]+}}, align 1 -// CHECK-LE: call <2 x double> @llvm.ppc.vsx.lxvd2x.be(i8* %{{[0-9]+}}) +// CHECK: load <2 x double>, ptr %{{[0-9]+}}, align 1 +// CHECK-LE: call <2 x double> @llvm.ppc.vsx.lxvd2x.be(ptr %{{[0-9]+}}) res_vsll = vec_xlds(sll, asll); // CHECK: load i64 @@ -2050,16 +2050,16 @@ res_vf = vec_load_splats(ull, af); // CHECK-LE: shufflevector <4 x float> vec_xst_be(vsll, sll, asll); -// CHECK: store <2 x i64> %{{[0-9]+}}, <2 x i64>* %{{[0-9]+}}, align 1 -// CHECK-LE: call void @llvm.ppc.vsx.stxvd2x.be(<2 x double> %{{[0-9]+}}, i8* %{{[0-9]+}}) +// CHECK: store <2 x i64> %{{[0-9]+}}, ptr %{{[0-9]+}}, align 1 +// CHECK-LE: call void @llvm.ppc.vsx.stxvd2x.be(<2 x double> %{{[0-9]+}}, ptr %{{[0-9]+}}) vec_xst_be(vull, sll, aull); -// CHECK: store <2 x i64> %{{[0-9]+}}, <2 x i64>* %{{[0-9]+}}, align 1 -// CHECK-LE: call void @llvm.ppc.vsx.stxvd2x.be(<2 x double> %{{[0-9]+}}, i8* %{{[0-9]+}}) +// CHECK: store <2 x i64> %{{[0-9]+}}, ptr %{{[0-9]+}}, align 1 +// CHECK-LE: call void @llvm.ppc.vsx.stxvd2x.be(<2 x double> %{{[0-9]+}}, ptr %{{[0-9]+}}) vec_xst_be(vd, sll, ad); -// CHECK: store <2 x double> %{{[0-9]+}}, <2 x double>* %{{[0-9]+}}, align 1 -// CHECK-LE: call void @llvm.ppc.vsx.stxvd2x.be(<2 x double> %{{[0-9]+}}, i8* %{{[0-9]+}}) +// CHECK: store <2 x double> %{{[0-9]+}}, ptr %{{[0-9]+}}, align 1 +// CHECK-LE: call void @llvm.ppc.vsx.stxvd2x.be(<2 x double> %{{[0-9]+}}, ptr %{{[0-9]+}}) res_vf = vec_neg(vf); // CHECK: fneg <4 x float> {{%[0-9]+}} @@ -2218,8 +2218,8 @@ vector double xxsldwi_should_not_assert(vector double a, vector double b) { void test_vector_cpsgn_float(vector float a, vector float b) { // CHECK-LABEL: test_vector_cpsgn_float // CHECK-NOT: SEPARATOR -// CHECK-DAG: [[RA:%[0-9]+]] = load <4 x float>, <4 x float>* %__a.addr -// CHECK-DAG: [[RB:%[0-9]+]] = load <4 x float>, <4 x float>* %__b.addr +// CHECK-DAG: [[RA:%[0-9]+]] = load <4 x float>, ptr %__a.addr +// CHECK-DAG: [[RB:%[0-9]+]] = load <4 x float>, ptr %__b.addr // CHECK-NEXT: call <4 x float> @llvm.copysign.v4f32(<4 x float> [[RB]], <4 x float> [[RA]]) vec_cpsgn(a, b); } @@ -2227,8 +2227,8 @@ void test_vector_cpsgn_float(vector float a, vector float b) { void test_vector_cpsgn_double(vector double a, vector double b) { // CHECK-LABEL: test_vector_cpsgn_double // CHECK-NOT: SEPARATOR -// CHECK-DAG: [[RA:%[0-9]+]] = load <2 x double>, <2 x double>* %__a.addr -// CHECK-DAG: [[RB:%[0-9]+]] = load <2 x double>, <2 x double>* %__b.addr +// CHECK-DAG: [[RA:%[0-9]+]] = load <2 x double>, ptr %__a.addr +// CHECK-DAG: [[RB:%[0-9]+]] = load <2 x double>, ptr %__b.addr // CHECK-NEXT: call <2 x double> @llvm.copysign.v2f64(<2 x double> [[RB]], <2 x double> [[RA]]) vec_cpsgn(a, b); } @@ -2236,8 +2236,8 @@ void test_vector_cpsgn_double(vector double a, vector double b) { void test_builtin_xvcpsgnsp(vector float a, vector float b) { // CHECK-LABEL: test_builtin_xvcpsgnsp // CHECK-NOT: SEPARATOR -// CHECK-DAG: [[RA:%[0-9]+]] = load <4 x float>, <4 x float>* %a.addr -// CHECK-DAG: [[RB:%[0-9]+]] = load <4 x float>, <4 x float>* %b.addr +// CHECK-DAG: [[RA:%[0-9]+]] = load <4 x float>, ptr %a.addr +// CHECK-DAG: [[RB:%[0-9]+]] = load <4 x float>, ptr %b.addr // CHECK-NEXT: call <4 x float> @llvm.copysign.v4f32(<4 x float> [[RA]], <4 x float> [[RB]]) __builtin_vsx_xvcpsgnsp(a, b); } @@ -2245,8 +2245,8 @@ void test_builtin_xvcpsgnsp(vector float a, vector float b) { void test_builtin_xvcpsgndp(vector double a, vector double b) { // CHECK-LABEL: test_builtin_xvcpsgndp // CHECK-NOT: SEPARATOR -// CHECK-DAG: [[RA:%[0-9]+]] = load <2 x double>, <2 x double>* %a.addr -// CHECK-DAG: [[RB:%[0-9]+]] = load <2 x double>, <2 x double>* %b.addr +// CHECK-DAG: [[RA:%[0-9]+]] = load <2 x double>, ptr %a.addr +// CHECK-DAG: [[RB:%[0-9]+]] = load <2 x double>, ptr %b.addr // CHECK-NEXT: call <2 x double> @llvm.copysign.v2f64(<2 x double> [[RA]], <2 x double> [[RB]]) __builtin_vsx_xvcpsgndp(a, b); } diff --git a/clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReseve-StoreCond.c b/clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReseve-StoreCond.c index afdd5ba4ad906e..e05e35fa98b744 100644 --- a/clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReseve-StoreCond.c +++ b/clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReseve-StoreCond.c @@ -1,48 +1,46 @@ // REQUIRES: powerpc-registered-target -// RUN: %clang_cc1 -no-opaque-pointers -O2 -target-cpu pwr8 -triple=powerpc-unknown-aix \ +// RUN: %clang_cc1 -O2 -target-cpu pwr8 -triple=powerpc-unknown-aix \ // RUN: -emit-llvm %s -o - | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -O2 -target-cpu pwr8 -triple=powerpc64-unknown-aix \ +// RUN: %clang_cc1 -O2 -target-cpu pwr8 -triple=powerpc64-unknown-aix \ // RUN: -emit-llvm %s -o - | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -O2 -target-cpu pwr8 -triple=powerpc64le-unknown-linux-gnu \ +// RUN: %clang_cc1 -O2 -target-cpu pwr8 -triple=powerpc64le-unknown-linux-gnu \ // RUN: -emit-llvm %s -o - | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -O2 -target-cpu pwr8 -triple=powerpc64-unknown-linux-gnu \ +// RUN: %clang_cc1 -O2 -target-cpu pwr8 -triple=powerpc64-unknown-linux-gnu \ // RUN: -emit-llvm %s -o - | FileCheck %s -// RAUN: not %clang_cc1 -no-opaque-pointers -O2 -target-cpu pwr7 -triple=powerpc-unknown-aix \ +// RAUN: not %clang_cc1 -O2 -target-cpu pwr7 -triple=powerpc-unknown-aix \ // RAUN: -emit-llvm %s -o - 2>&1 | FileCheck %s \ // RAUN: --check-prefix=CHECK-NON-PWR8-ERR int test_lwarx(volatile int* a) { // CHECK-LABEL: @test_lwarx - // CHECK: %0 = tail call i32 asm sideeffect "lwarx $0, ${1:y}", "=r,*Z,~{memory}"(i32* elementtype(i32) %a) + // CHECK: %0 = tail call i32 asm sideeffect "lwarx $0, ${1:y}", "=r,*Z,~{memory}"(ptr elementtype(i32) %a) return __lwarx(a); } short test_lharx(volatile short *a) { // CHECK-LABEL: @test_lharx - // CHECK: %0 = tail call i16 asm sideeffect "lharx $0, ${1:y}", "=r,*Z,~{memory}"(i16* elementtype(i16) %a) + // CHECK: %0 = tail call i16 asm sideeffect "lharx $0, ${1:y}", "=r,*Z,~{memory}"(ptr elementtype(i16) %a) // CHECK-NON-PWR8-ERR: error: this builtin is only valid on POWER8 or later CPUs return __lharx(a); } char test_lbarx(volatile char *a) { // CHECK-LABEL: @test_lbarx - // CHECK: %0 = tail call i8 asm sideeffect "lbarx $0, ${1:y}", "=r,*Z,~{memory}"(i8* elementtype(i8) %a) + // CHECK: %0 = tail call i8 asm sideeffect "lbarx $0, ${1:y}", "=r,*Z,~{memory}"(ptr elementtype(i8) %a) // CHECK-NON-PWR8-ERR: error: this builtin is only valid on POWER8 or later CPUs return __lbarx(a); } int test_stwcx(volatile int* a, int val) { // CHECK-LABEL: @test_stwcx - // CHECK: %0 = bitcast i32* %a to i8* - // CHECK: %1 = tail call i32 @llvm.ppc.stwcx(i8* %0, i32 %val) + // CHECK: %0 = tail call i32 @llvm.ppc.stwcx(ptr %a, i32 %val) return __stwcx(a, val); } int test_sthcx(volatile short *a, short val) { // CHECK-LABEL: @test_sthcx - // CHECK: %0 = bitcast i16* %a to i8* - // CHECK: %1 = sext i16 %val to i32 - // CHECK: %2 = tail call i32 @llvm.ppc.sthcx(i8* %0, i32 %1) + // CHECK: %0 = sext i16 %val to i32 + // CHECK: %1 = tail call i32 @llvm.ppc.sthcx(ptr %a, i32 %0) // CHECK-NON-PWR8-ERR: error: this builtin is only valid on POWER8 or later CPUs return __sthcx(a, val); } @@ -50,14 +48,14 @@ int test_sthcx(volatile short *a, short val) { // Extra test cases that previously caused error during usage. int test_lharx_intret(volatile short *a) { // CHECK-LABEL: @test_lharx_intret - // CHECK: %0 = tail call i16 asm sideeffect "lharx $0, ${1:y}", "=r,*Z,~{memory}"(i16* elementtype(i16) %a) + // CHECK: %0 = tail call i16 asm sideeffect "lharx $0, ${1:y}", "=r,*Z,~{memory}"(ptr elementtype(i16) %a) // CHECK-NON-PWR8-ERR: error: this builtin is only valid on POWER8 or later CPUs return __lharx(a); } int test_lbarx_intret(volatile char *a) { // CHECK-LABEL: @test_lbarx_intret - // CHECK: %0 = tail call i8 asm sideeffect "lbarx $0, ${1:y}", "=r,*Z,~{memory}"(i8* elementtype(i8) %a) + // CHECK: %0 = tail call i8 asm sideeffect "lbarx $0, ${1:y}", "=r,*Z,~{memory}"(ptr elementtype(i8) %a) // CHECK-NON-PWR8-ERR: error: this builtin is only valid on POWER8 or later CPUs return __lbarx(a); } diff --git a/clang/test/CodeGen/PowerPC/ppc-emmintrin.c b/clang/test/CodeGen/PowerPC/ppc-emmintrin.c index fa47304267b71f..e2d26e611ac81c 100644 --- a/clang/test/CodeGen/PowerPC/ppc-emmintrin.c +++ b/clang/test/CodeGen/PowerPC/ppc-emmintrin.c @@ -1,16 +1,16 @@ // REQUIRES: powerpc-registered-target -// RUN: %clang -Xclang -no-opaque-pointers -S -emit-llvm -target powerpc64-unknown-linux-gnu -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \ +// RUN: %clang -S -emit-llvm -target powerpc64-unknown-linux-gnu -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \ // RUN: -ffp-contract=off -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-BE -// RUN: %clang -Xclang -no-opaque-pointers -S -emit-llvm -target powerpc64le-unknown-linux-gnu -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \ +// RUN: %clang -S -emit-llvm -target powerpc64le-unknown-linux-gnu -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \ // RUN: -ffp-contract=off -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-LE -// RUN: %clang -Xclang -no-opaque-pointers -S -emit-llvm -target powerpc64le-unknown-linux-gnu -mcpu=pwr10 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \ +// RUN: %clang -S -emit-llvm -target powerpc64le-unknown-linux-gnu -mcpu=pwr10 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \ // RUN: -ffp-contract=off -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK-P10 -// RUN: %clang -Xclang -no-opaque-pointers -S -emit-llvm -target powerpc64-ibm-aix -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \ +// RUN: %clang -S -emit-llvm -target powerpc64-ibm-aix -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \ // RUN: -ffp-contract=off -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-BE -// RUN: %clang -Xclang -no-opaque-pointers -S -emit-llvm -target powerpc64-ibm-aix -mcpu=pwr10 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \ +// RUN: %clang -S -emit-llvm -target powerpc64-ibm-aix -mcpu=pwr10 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \ // RUN: -ffp-contract=off -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK-P10 // CHECK-BE-DAG: @_mm_movemask_pd.__perm_mask = internal constant <4 x i32> , align 16 @@ -113,7 +113,7 @@ test_bs() { // CHECK: %[[CMP:[0-9a-zA-Z_.]+]] = icmp slt i32 %{{[0-9a-zA-Z_.]+}}, 16 // CHECK: br i1 %[[CMP]] // CHECK: call <16 x i8> @vec_sld(unsigned char vector[16], unsigned char vector[16], unsigned int)(<16 x i8> noundef %{{[0-9a-zA-Z_.]+}}, <16 x i8> noundef zeroinitializer, i32 noundef zeroext %{{[0-9a-zA-Z_.]+}}) -// CHECK: store <16 x i8> zeroinitializer, <16 x i8>* %{{[0-9a-zA-Z_.]+}}, align 16 +// CHECK: store <16 x i8> zeroinitializer, ptr %{{[0-9a-zA-Z_.]+}}, align 16 // CHECK-LABEL: define available_externally <2 x i64> @_mm_bsrli_si128 // CHECK: %[[CMP:[0-9a-zA-Z_.]+]] = icmp slt i32 %{{[0-9a-zA-Z_.]+}}, 16 @@ -125,12 +125,12 @@ test_bs() { // CHECK-LE: %[[TRUNC:[0-9a-zA-Z_.]+]] = trunc i32 %[[MUL]] to i8 // CHECK-LE: call <16 x i8> @vec_splats(unsigned char)(i8 noundef zeroext %[[TRUNC]]) // CHECK-LE: call <16 x i8> @vec_sro(unsigned char vector[16], unsigned char vector[16]) -// CHECK-LE: store <16 x i8> zeroinitializer, <16 x i8>* %{{[0-9a-zA-Z_.]+}}, align 16 +// CHECK-LE: store <16 x i8> zeroinitializer, ptr %{{[0-9a-zA-Z_.]+}}, align 16 // CHECK-BE: %[[MUL:[0-9a-zA-Z_.]+]] = mul nsw i32 %{{[0-9a-zA-Z_.]+}}, 8 // CHECK-BE: %[[TRUNC:[0-9a-zA-Z_.]+]] = trunc i32 %[[MUL]] to i8 // CHECK-BE: call <16 x i8> @vec_splats(unsigned char)(i8 noundef zeroext %[[TRUNC]]) // CHECK-BE: call <16 x i8> @vec_slo(unsigned char vector[16], unsigned char vector[16]) -// CHECK-BE: store <16 x i8> zeroinitializer, <16 x i8>* %{{[0-9a-zA-Z_.]+}}, align 16 +// CHECK-BE: store <16 x i8> zeroinitializer, ptr %{{[0-9a-zA-Z_.]+}}, align 16 void __attribute__((noinline)) test_cast() { @@ -145,22 +145,16 @@ test_cast() { // CHECK-LABEL: @test_cast // CHECK-LABEL: define available_externally <4 x float> @_mm_castpd_ps -// CHECK: bitcast <2 x double> %{{[0-9a-zA-Z_.]+}} to <4 x float> // CHECK-LABEL: define available_externally <2 x i64> @_mm_castpd_si128 -// CHECK: bitcast <2 x double> %{{[0-9a-zA-Z_.]+}} to <2 x i64> // CHECK-LABEL: define available_externally <2 x double> @_mm_castps_pd -// CHECK: bitcast <4 x float> %{{[0-9a-zA-Z_.]+}} to <2 x double> // CHECK-LABEL: define available_externally <2 x i64> @_mm_castps_si128 -// CHECK: bitcast <4 x float> %{{[0-9a-zA-Z_.]+}} to <2 x i64> // CHECK-LABEL: define available_externally <2 x double> @_mm_castsi128_pd -// CHECK: bitcast <2 x i64> %{{[0-9a-zA-Z_.]+}} to <2 x double> // CHECK-LABEL: define available_externally <4 x float> @_mm_castsi128_ps -// CHECK: bitcast <2 x i64> %{{[0-9a-zA-Z_.]+}} to <4 x float> void __attribute__((noinline)) test_cmp() { @@ -390,7 +384,7 @@ test_control() { // CHECK-LABEL: @test_control // CHECK-LABEL: define available_externally void @_mm_clflush -// CHECK: call void asm sideeffect "dcbf 0,$0", "b,~{memory}"(i8* %{{[0-9a-zA-Z_.]+}}) +// CHECK: call void asm sideeffect "dcbf 0,$0", "b,~{memory}"(ptr %{{[0-9a-zA-Z_.]+}}) // CHECK-LABEL: define available_externally void @_mm_lfence() // CHECK: fence release @@ -446,7 +440,7 @@ test_converts() { // CHECK-LABEL: define available_externally <2 x i64> @_mm_cvtpd_epi32 // CHECK: call <2 x double> @vec_rint(double vector[2]) -// CHECK: store <4 x i32> zeroinitializer, <4 x i32>* %{{[0-9a-zA-Z_.]+}}, align 16 +// CHECK: store <4 x i32> zeroinitializer, ptr %{{[0-9a-zA-Z_.]+}}, align 16 // CHECK: call <4 x i32> asm "xvcvdpsxws ${0:x},${1:x}", "=^wa,^wa"(<2 x double> %{{[0-9a-zA-Z_.]+}}) // CHECK-LE: call <4 x i32> @vec_mergeo(int vector[4], int vector[4]) // CHECK-BE: call <4 x i32> @vec_mergee(int vector[4], int vector[4]) @@ -457,7 +451,7 @@ test_converts() { // CHECK: extractelement <2 x i64> %{{[0-9a-zA-Z_.]+}}, i32 0 // CHECK-LABEL: define available_externally <4 x float> @_mm_cvtpd_ps -// CHECK: store <4 x i32> zeroinitializer, <4 x i32>* %{{[0-9a-zA-Z_.]+}}, align 16 +// CHECK: store <4 x i32> zeroinitializer, ptr %{{[0-9a-zA-Z_.]+}}, align 16 // CHECK: call <4 x i32> asm "xvcvdpsp ${0:x},${1:x}", "=^wa,^wa"(<2 x double> %{{[0-9a-zA-Z_.]+}}) // CHECK-LE: call <4 x i32> @vec_mergeo(int vector[4], int vector[4]) // CHECK-BE: call <4 x i32> @vec_mergee(int vector[4], int vector[4]) @@ -614,50 +608,50 @@ test_load() { // CHECK-LABEL: @test_load // CHECK-LABEL: define available_externally <2 x double> @_mm_load_pd -// CHECK: call <16 x i8> @vec_ld(long, unsigned char vector[16] const*)(i64 noundef 0, <16 x i8>* noundef %{{[0-9a-zA-Z_.]+}}) +// CHECK: call <16 x i8> @vec_ld(long, unsigned char vector[16] const*)(i64 noundef 0, ptr noundef %{{[0-9a-zA-Z_.]+}}) // CHECK-LABEL: define available_externally <2 x double> @_mm_load_pd1 -// CHECK: call <2 x double> @_mm_load1_pd(double* noundef %{{[0-9a-zA-Z_.]+}}) +// CHECK: call <2 x double> @_mm_load1_pd(ptr noundef %{{[0-9a-zA-Z_.]+}}) // CHECK-LABEL: define available_externally <2 x double> @_mm_load_sd // CHECK: call <2 x double> @_mm_set_sd(double noundef %{{[0-9a-zA-Z_.]+}}) // CHECK-LABEL: define available_externally <2 x i64> @_mm_load_si128 -// CHECK: %[[ADDR:[0-9a-zA-Z_.]+]] = load <2 x i64>*, <2 x i64>** %{{[0-9a-zA-Z_.]+}}, align 8 -// CHECK: load <2 x i64>, <2 x i64>* %[[ADDR]], align 16 +// CHECK: %[[ADDR:[0-9a-zA-Z_.]+]] = load ptr, ptr %{{[0-9a-zA-Z_.]+}}, align 8 +// CHECK: load <2 x i64>, ptr %[[ADDR]], align 16 // CHECK-LABEL: define available_externally <2 x double> @_mm_load1_pd -// CHECK: %[[ADDR:[0-9a-zA-Z_.]+]] = load double*, double** %{{[0-9a-zA-Z_.]+}}, align 8 -// CHECK: %[[VAL:[0-9a-zA-Z_.]+]] = load double, double* %[[ADDR]] +// CHECK: %[[ADDR:[0-9a-zA-Z_.]+]] = load ptr, ptr %{{[0-9a-zA-Z_.]+}}, align 8 +// CHECK: %[[VAL:[0-9a-zA-Z_.]+]] = load double, ptr %[[ADDR]] // CHECK: call <2 x double> @vec_splats(double)(double noundef %[[VAL]]) // CHECK-LABEL: define available_externally <2 x double> @_mm_loadh_pd -// CHECK: %[[ADDR:[0-9a-zA-Z_.]+]] = load double*, double** %{{[0-9a-zA-Z_.]+}}, align 8 -// CHECK: %[[VAL:[0-9a-zA-Z_.]+]] = load double, double* %{{[0-9a-zA-Z_.]+}} -// CHECK: %[[VEC:[0-9a-zA-Z_.]+]] = load <2 x double>, <2 x double>* %{{[0-9a-zA-Z_.]+}}, align 16 +// CHECK: %[[ADDR:[0-9a-zA-Z_.]+]] = load ptr, ptr %{{[0-9a-zA-Z_.]+}}, align 8 +// CHECK: %[[VAL:[0-9a-zA-Z_.]+]] = load double, ptr %{{[0-9a-zA-Z_.]+}} +// CHECK: %[[VEC:[0-9a-zA-Z_.]+]] = load <2 x double>, ptr %{{[0-9a-zA-Z_.]+}}, align 16 // CHECK: insertelement <2 x double> %[[VEC]], double %[[VAL]], i32 1 // CHECK-LABEL: define available_externally <2 x i64> @_mm_loadl_epi64 // CHECK: call <2 x i64> @_mm_set_epi64(i64 noundef 0, i64 noundef %{{[0-9a-zA-Z_.]+}}) // CHECK-LABEL: define available_externally <2 x double> @_mm_loadl_pd -// CHECK: %[[ADDR:[0-9a-zA-Z_.]+]] = load double*, double** %{{[0-9a-zA-Z_.]+}}, align 8 -// CHECK: %[[ADDR2:[0-9a-zA-Z_.]+]] = load double, double* %[[ADDR]] -// CHECK: %[[VEC:[0-9a-zA-Z_.]+]] = load <2 x double>, <2 x double>* %{{[0-9a-zA-Z_.]+}}, align 16 +// CHECK: %[[ADDR:[0-9a-zA-Z_.]+]] = load ptr, ptr %{{[0-9a-zA-Z_.]+}}, align 8 +// CHECK: %[[ADDR2:[0-9a-zA-Z_.]+]] = load double, ptr %[[ADDR]] +// CHECK: %[[VEC:[0-9a-zA-Z_.]+]] = load <2 x double>, ptr %{{[0-9a-zA-Z_.]+}}, align 16 // CHECK: insertelement <2 x double> %[[VEC]], double %[[ADDR2]], i32 0 // CHECK-LABEL: define available_externally <2 x double> @_mm_loadr_pd -// CHECK: %[[ADDR:[0-9a-zA-Z_.]+]] = load double*, double** %{{[0-9a-zA-Z_.]+}}, align 8 -// CHECK: call <2 x double> @_mm_load_pd(double* noundef %[[ADDR]]) +// CHECK: %[[ADDR:[0-9a-zA-Z_.]+]] = load ptr, ptr %{{[0-9a-zA-Z_.]+}}, align 8 +// CHECK: call <2 x double> @_mm_load_pd(ptr noundef %[[ADDR]]) // CHECK: shufflevector <2 x i64> %{{[0-9a-zA-Z_.]+}}, <2 x i64> %{{[0-9a-zA-Z_.]+}}, <2 x i32> // CHECK-LABEL: define available_externally <2 x double> @_mm_loadu_pd -// CHECK: %[[ADDR:[0-9a-zA-Z_.]+]] = load double*, double** %{{[0-9a-zA-Z_.]+}}, align 8 -// CHECK: call <2 x double> @vec_vsx_ld(int, double const*)(i32 noundef signext 0, double* noundef %[[ADDR]]) +// CHECK: %[[ADDR:[0-9a-zA-Z_.]+]] = load ptr, ptr %{{[0-9a-zA-Z_.]+}}, align 8 +// CHECK: call <2 x double> @vec_vsx_ld(int, double const*)(i32 noundef signext 0, ptr noundef %[[ADDR]]) // CHECK-LABEL: define available_externally <2 x i64> @_mm_loadu_si128 -// CHECK: load <2 x i64>*, <2 x i64>** %{{[0-9a-zA-Z_.]+}}, align 8 -// CHECK: call <4 x i32> @vec_vsx_ld(int, int const*)(i32 noundef signext 0, i32* noundef %{{[0-9a-zA-Z_.]+}}) +// CHECK: load ptr, ptr %{{[0-9a-zA-Z_.]+}}, align 8 +// CHECK: call <4 x i32> @vec_vsx_ld(int, int const*)(i32 noundef signext 0, ptr noundef %{{[0-9a-zA-Z_.]+}}) void __attribute__((noinline)) test_logical() { @@ -792,10 +786,10 @@ test_move() { // CHECK: call <2 x i64> @_mm_set_epi64(i64 noundef 0, i64 noundef %{{[0-9a-zA-Z_.]+}}) // CHECK-LABEL: define available_externally void @_mm_maskmoveu_si128 -// CHECK: call <2 x i64> @_mm_loadu_si128(<2 x i64>* noundef %{{[0-9a-zA-Z_.]+}}) +// CHECK: call <2 x i64> @_mm_loadu_si128(ptr noundef %{{[0-9a-zA-Z_.]+}}) // CHECK: call <16 x i8> @vec_cmpgt(unsigned char vector[16], unsigned char vector[16]) // CHECK: call <16 x i8> @vec_sel(unsigned char vector[16], unsigned char vector[16], unsigned char vector[16]) -// CHECK: call void @_mm_storeu_si128(<2 x i64>* noundef %{{[0-9a-zA-Z_.]+}}, <2 x i64> noundef %{{[0-9a-zA-Z_.]+}}) +// CHECK: call void @_mm_storeu_si128(ptr noundef %{{[0-9a-zA-Z_.]+}}, <2 x i64> noundef %{{[0-9a-zA-Z_.]+}}) void __attribute__((noinline)) test_mul() { @@ -828,15 +822,15 @@ test_mul() { // CHECK: mul i64 %[[EXT1]], %[[EXT2]] // CHECK-LABEL: define available_externally <2 x i64> @_mm_mulhi_epi16 -// CHECK-LE: store <16 x i8> , <16 x i8>* %{{[0-9a-zA-Z_.]+}}, align 16 -// CHECK-BE: store <16 x i8> , <16 x i8>* %{{[0-9a-zA-Z_.]+}}, align 16 +// CHECK-LE: store <16 x i8> , ptr %{{[0-9a-zA-Z_.]+}}, align 16 +// CHECK-BE: store <16 x i8> , ptr %{{[0-9a-zA-Z_.]+}}, align 16 // CHECK: call <4 x i32> @vec_vmulesh(<8 x i16> noundef %{{[0-9a-zA-Z_.]+}}, <8 x i16> noundef %{{[0-9a-zA-Z_.]+}}) // CHECK: call <4 x i32> @vec_vmulosh(<8 x i16> noundef %{{[0-9a-zA-Z_.]+}}, <8 x i16> noundef %{{[0-9a-zA-Z_.]+}}) // CHECK: call <4 x i32> @vec_perm(int vector[4], int vector[4], unsigned char vector[16]) // CHECK-LABEL: define available_externally <2 x i64> @_mm_mulhi_epu16 -// CHECK-LE: store <16 x i8> , <16 x i8>* %{{[0-9a-zA-Z_.]+}}, align 16 -// CHECK-BE: store <16 x i8> , <16 x i8>* %{{[0-9a-zA-Z_.]+}}, align 16 +// CHECK-LE: store <16 x i8> , ptr %{{[0-9a-zA-Z_.]+}}, align 16 +// CHECK-BE: store <16 x i8> , ptr %{{[0-9a-zA-Z_.]+}}, align 16 // CHECK: call <4 x i32> @vec_vmuleuh(<8 x i16> noundef %{{[0-9a-zA-Z_.]+}}, <8 x i16> noundef %{{[0-9a-zA-Z_.]+}}) // CHECK: call <4 x i32> @vec_vmulouh(<8 x i16> noundef %{{[0-9a-zA-Z_.]+}}, <8 x i16> noundef %{{[0-9a-zA-Z_.]+}}) // CHECK: call <4 x i32> @vec_perm(unsigned int vector[4], unsigned int vector[4], unsigned char vector[16]) @@ -906,12 +900,12 @@ test_set() { // CHECK-LABEL: @test_set // CHECK-LABEL: define available_externally <2 x i64> @_mm_set_epi16 -// CHECK-COUNT-8: store i16 {{[0-9a-zA-Z_%.]+}}, i16* {{[0-9a-zA-Z_%.]+}}, align 2 +// CHECK-COUNT-8: store i16 {{[0-9a-zA-Z_%.]+}}, ptr {{[0-9a-zA-Z_%.]+}}, align 2 // CHECK: insertelement <8 x i16> undef, i16 {{[0-9a-zA-Z_%.]+}}, i32 0 // CHECK-COUNT-7: insertelement <8 x i16> {{[0-9a-zA-Z_%.]+}}, i16 {{[0-9a-zA-Z_%.]+}}, i32 {{[1-7]}} // CHECK-LABEL: define available_externally <2 x i64> @_mm_set_epi32 -// CHECK-COUNT-4: store i32 {{[0-9a-zA-Z_%.]+}}, i32* {{[0-9a-zA-Z_%.]+}}, align 4 +// CHECK-COUNT-4: store i32 {{[0-9a-zA-Z_%.]+}}, ptr {{[0-9a-zA-Z_%.]+}}, align 4 // CHECK: insertelement <4 x i32> undef, i32 {{[0-9a-zA-Z_%.]+}}, i32 0 // CHECK-COUNT-3: insertelement <4 x i32> {{[0-9a-zA-Z_%.]+}}, i32 {{[0-9a-zA-Z_%.]+}}, i32 {{[1-3]}} @@ -923,7 +917,7 @@ test_set() { // CHECK: insertelement <2 x i64> %[[VEC]], i64 %{{[0-9a-zA-Z_.]+}}, i32 1 // CHECK-LABEL: define available_externally <2 x i64> @_mm_set_epi8 -// CHECK-COUNT-16: store i8 {{[0-9a-zA-Z_%.]+}}, i8* {{[0-9a-zA-Z_%.]+}}, align 1 +// CHECK-COUNT-16: store i8 {{[0-9a-zA-Z_%.]+}}, ptr {{[0-9a-zA-Z_%.]+}}, align 1 // CHECK: insertelement <16 x i8> undef, i8 {{[0-9a-zA-Z_%.]+}}, i32 {{[0-9]+}} // CHECK-COUNT-15: {{[0-9a-zA-Z_%.]+}} = insertelement <16 x i8> {{[0-9a-zA-Z_%.]+}}, i8 {{[0-9a-zA-Z_%.]+}}, i32 {{[0-9]+}} @@ -939,25 +933,25 @@ test_set() { // CHECK: insertelement <2 x double> %[[VEC]], double 0.000000e+00, i32 1 // CHECK-LABEL: define available_externally <2 x i64> @_mm_set1_epi16 -// CHECK-COUNT-8: load i16, i16* %{{[0-9a-zA-Z_.]+}}, align 2 +// CHECK-COUNT-8: load i16, ptr %{{[0-9a-zA-Z_.]+}}, align 2 // CHECK: call <2 x i64> @_mm_set_epi16 // CHECK-LABEL: define available_externally <2 x i64> @_mm_set1_epi32 -// CHECK-COUNT-4: load i32, i32* %{{[0-9a-zA-Z_.]+}}, align 4 +// CHECK-COUNT-4: load i32, ptr %{{[0-9a-zA-Z_.]+}}, align 4 // CHECK: call <2 x i64> @_mm_set_epi32 // CHECK-LABEL: define available_externally <2 x i64> @_mm_set1_epi64 -// CHECK: %[[VAL1:[0-9a-zA-Z_.]+]] = load i64, i64* %{{[0-9a-zA-Z_.]+}}, align 8 -// CHECK: %[[VAL2:[0-9a-zA-Z_.]+]] = load i64, i64* %{{[0-9a-zA-Z_.]+}}, align 8 +// CHECK: %[[VAL1:[0-9a-zA-Z_.]+]] = load i64, ptr %{{[0-9a-zA-Z_.]+}}, align 8 +// CHECK: %[[VAL2:[0-9a-zA-Z_.]+]] = load i64, ptr %{{[0-9a-zA-Z_.]+}}, align 8 // CHECK: call <2 x i64> @_mm_set_epi64(i64 noundef %[[VAL1]], i64 noundef %[[VAL2]]) // CHECK-LABEL: define available_externally <2 x i64> @_mm_set1_epi64x -// CHECK: %[[VAL1:[0-9a-zA-Z_.]+]] = load i64, i64* %{{[0-9a-zA-Z_.]+}}, align 8 -// CHECK: %[[VAL2:[0-9a-zA-Z_.]+]] = load i64, i64* %{{[0-9a-zA-Z_.]+}}, align 8 +// CHECK: %[[VAL1:[0-9a-zA-Z_.]+]] = load i64, ptr %{{[0-9a-zA-Z_.]+}}, align 8 +// CHECK: %[[VAL2:[0-9a-zA-Z_.]+]] = load i64, ptr %{{[0-9a-zA-Z_.]+}}, align 8 // CHECK: call <2 x i64> @_mm_set_epi64x(i64 noundef %[[VAL1]], i64 noundef %[[VAL2]]) // CHECK-LABEL: define available_externally <2 x i64> @_mm_set1_epi8 -// CHECK-COUNT-16: load i8, i8* %{{[0-9a-zA-Z_.]+}}, align 1 +// CHECK-COUNT-16: load i8, ptr %{{[0-9a-zA-Z_.]+}}, align 1 // CHECK: call <2 x i64> @_mm_set_epi8 // CHECK-LABEL: define available_externally <2 x double> @_mm_set1_pd @@ -965,20 +959,20 @@ test_set() { // CHECK: insertelement <2 x double> %[[VEC]], double %{{[0-9a-zA-Z_.]+}}, i32 1 // CHECK-LABEL: define available_externally <2 x i64> @_mm_setr_epi16 -// CHECK-COUNT-8: load i16, i16* {{[0-9a-zA-Z_%.]+}}, align 2 +// CHECK-COUNT-8: load i16, ptr {{[0-9a-zA-Z_%.]+}}, align 2 // CHECK: call <2 x i64> @_mm_set_epi16 // CHECK-LABEL: define available_externally <2 x i64> @_mm_setr_epi32 -// CHECK-COUNT-4: load i32, i32* {{[0-9a-zA-Z_%.]+}}, align 4 +// CHECK-COUNT-4: load i32, ptr {{[0-9a-zA-Z_%.]+}}, align 4 // CHECK: call <2 x i64> @_mm_set_epi32 // CHECK-LABEL: define available_externally <2 x i64> @_mm_setr_epi64 -// CHECK: %[[VAL1:[0-9a-zA-Z_.]+]] = load i64, i64* %{{[0-9a-zA-Z_.]+}}, align 8 -// CHECK: %[[VAL2:[0-9a-zA-Z_.]+]] = load i64, i64* %{{[0-9a-zA-Z_.]+}}, align 8 +// CHECK: %[[VAL1:[0-9a-zA-Z_.]+]] = load i64, ptr %{{[0-9a-zA-Z_.]+}}, align 8 +// CHECK: %[[VAL2:[0-9a-zA-Z_.]+]] = load i64, ptr %{{[0-9a-zA-Z_.]+}}, align 8 // CHECK: call <2 x i64> @_mm_set_epi64(i64 noundef %[[VAL1]], i64 noundef %[[VAL2]]) // CHECK-LABEL: define available_externally <2 x i64> @_mm_setr_epi8 -// CHECK-COUNT-16: load i8, i8* {{[0-9a-zA-Z_%.]+}}, align 1 +// CHECK-COUNT-16: load i8, ptr {{[0-9a-zA-Z_%.]+}}, align 1 // CHECK: call <2 x i64> @_mm_set_epi8 // CHECK-LABEL: define available_externally <2 x double> @_mm_setr_pd @@ -989,7 +983,7 @@ test_set() { // CHECK: call <4 x i32> @vec_splats(int)(i32 noundef signext 0) // CHECK-LABEL: define available_externally <2 x i64> @_mm_setzero_si128() -// CHECK: store <4 x i32> zeroinitializer, <4 x i32>* %{{[0-9a-zA-Z_.]+}}, align 16 +// CHECK: store <4 x i32> zeroinitializer, ptr %{{[0-9a-zA-Z_.]+}}, align 16 void __attribute__((noinline)) test_shuffle() { @@ -1013,14 +1007,14 @@ test_shuffle() { // CHECK: %[[SHR:[0-9a-zA-Z_.]+]] = ashr i32 %{{[0-9a-zA-Z_.]+}}, 6 // CHECK: %[[AND4:[0-9a-zA-Z_.]+]] = and i32 %[[SHR]], 3 // CHECK: sext i32 %[[AND4]] to i64 -// CHECK: getelementptr inbounds [4 x i32], [4 x i32]* @_mm_shuffle_epi32.__permute_selectors, i64 0, i64 %{{[0-9a-zA-Z_.]+}} +// CHECK: getelementptr inbounds [4 x i32], ptr @_mm_shuffle_epi32.__permute_selectors, i64 0, i64 %{{[0-9a-zA-Z_.]+}} // CHECK: insertelement <4 x i32> %{{[0-9a-zA-Z_.]+}}, i32 %{{[0-9a-zA-Z_.]+}}, i32 0 -// CHECK: getelementptr inbounds [4 x i32], [4 x i32]* @_mm_shuffle_epi32.__permute_selectors, i64 0, i64 %{{[0-9a-zA-Z_.]+}} +// CHECK: getelementptr inbounds [4 x i32], ptr @_mm_shuffle_epi32.__permute_selectors, i64 0, i64 %{{[0-9a-zA-Z_.]+}} // CHECK: insertelement <4 x i32> %{{[0-9a-zA-Z_.]+}}, i32 %{{[0-9a-zA-Z_.]+}}, i32 1 -// CHECK: getelementptr inbounds [4 x i32], [4 x i32]* @_mm_shuffle_epi32.__permute_selectors, i64 0, i64 %{{[0-9a-zA-Z_.]+}} +// CHECK: getelementptr inbounds [4 x i32], ptr @_mm_shuffle_epi32.__permute_selectors, i64 0, i64 %{{[0-9a-zA-Z_.]+}} // CHECK: %[[ADD:[0-9a-zA-Z_.]+]] = add i32 %{{[0-9a-zA-Z_.]+}}, 269488144 // CHECK: insertelement <4 x i32> %{{[0-9a-zA-Z_.]+}}, i32 %[[ADD]], i32 2 -// CHECK: getelementptr inbounds [4 x i32], [4 x i32]* @_mm_shuffle_epi32.__permute_selectors, i64 0, i64 %{{[0-9a-zA-Z_.]+}} +// CHECK: getelementptr inbounds [4 x i32], ptr @_mm_shuffle_epi32.__permute_selectors, i64 0, i64 %{{[0-9a-zA-Z_.]+}} // CHECK: add i32 %{{[0-9a-zA-Z_.]+}}, 269488144 // CHECK: call <4 x i32> @vec_perm(int vector[4], int vector[4], unsigned char vector[16]) @@ -1049,9 +1043,9 @@ test_shuffle() { // CHECK: %[[SHR3:[0-9a-zA-Z_.]+]] = ashr i32 %{{[0-9a-zA-Z_.]+}}, 6 // CHECK: %[[AND4:[0-9a-zA-Z_.]+]] = and i32 %[[SHR3]], 3 // CHECK: sext i32 %[[AND4]] to i64 -// CHECK-LE: store <2 x i64> , <2 x i64>* %{{[0-9a-zA-Z_.]+}}, align 16 -// CHECK-BE: store <2 x i64> , <2 x i64>* %{{[0-9a-zA-Z_.]+}}, align 16 -// CHECK-COUNT-4: getelementptr inbounds [4 x i16], [4 x i16]* @_mm_shufflehi_epi16.__permute_selectors, i64 0, i64 {{[0-9a-zA-Z_%.]+}} +// CHECK-LE: store <2 x i64> , ptr %{{[0-9a-zA-Z_.]+}}, align 16 +// CHECK-BE: store <2 x i64> , ptr %{{[0-9a-zA-Z_.]+}}, align 16 +// CHECK-COUNT-4: getelementptr inbounds [4 x i16], ptr @_mm_shufflehi_epi16.__permute_selectors, i64 0, i64 {{[0-9a-zA-Z_%.]+}} // CHECK: call <2 x i64> @vec_perm(unsigned long long vector[2], unsigned long long vector[2], unsigned char vector[16]) // CHECK-LABEL: define available_externally <2 x i64> @_mm_shufflelo_epi16 @@ -1066,9 +1060,9 @@ test_shuffle() { // CHECK: %[[SHR3:[0-9a-zA-Z_.]+]] = ashr i32 {{[0-9a-zA-Z_%.]+}}, 6 // CHECK: %[[AND4:[0-9a-zA-Z_.]+]] = and i32 %[[SHR3]], 3 // CHECK: sext i32 %[[AND4]] to i64 -// CHECK-LE: store <2 x i64> , <2 x i64>* %{{[0-9a-zA-Z_.]+}}, align 16 -// CHECK-BE: store <2 x i64> , <2 x i64>* %{{[0-9a-zA-Z_.]+}}, align 16 -// CHECK-COUNT-4: getelementptr inbounds [4 x i16], [4 x i16]* @_mm_shufflelo_epi16.__permute_selectors, i64 0, i64 {{[0-9a-zA-Z_%.]+}} +// CHECK-LE: store <2 x i64> , ptr %{{[0-9a-zA-Z_.]+}}, align 16 +// CHECK-BE: store <2 x i64> , ptr %{{[0-9a-zA-Z_.]+}}, align 16 +// CHECK-COUNT-4: getelementptr inbounds [4 x i16], ptr @_mm_shufflelo_epi16.__permute_selectors, i64 0, i64 {{[0-9a-zA-Z_%.]+}} // CHECK: call <2 x i64> @vec_perm(unsigned long long vector[2], unsigned long long vector[2], unsigned char vector[16]) void __attribute__((noinline)) @@ -1085,7 +1079,7 @@ test_sll() { // CHECK-LABEL: @test_sll // CHECK-LABEL: define available_externally <2 x i64> @_mm_sll_epi16 -// CHECK: store <8 x i16> , <8 x i16>* %{{[0-9a-zA-Z_.]+}}, align 16 +// CHECK: store <8 x i16> , ptr %{{[0-9a-zA-Z_.]+}}, align 16 // CHECK-LE: call <8 x i16> @vec_splat(unsigned short vector[8], unsigned int) // CHECK-BE: call <8 x i16> @vec_splat(unsigned short vector[8], unsigned int) // CHECK: call <8 x i16> @vec_cmple(unsigned short vector[8], unsigned short vector[8])(<8 x i16> noundef %{{[0-9a-zA-Z_.]+}}, <8 x i16> noundef ) @@ -1106,7 +1100,7 @@ test_sll() { // CHECK: call <2 x i64> @vec_sel(unsigned long long vector[2], unsigned long long vector[2], bool vector[2]) // CHECK-LABEL: define available_externally <2 x i64> @_mm_slli_epi16 -// CHECK: store <8 x i16> zeroinitializer, <8 x i16>* %{{[0-9a-zA-Z_.]+}}, align 16 +// CHECK: store <8 x i16> zeroinitializer, ptr %{{[0-9a-zA-Z_.]+}}, align 16 // CHECK: %[[CMP:[0-9a-zA-Z_.]+]] = icmp sge i32 %{{[0-9a-zA-Z_.]+}}, 0 // CHECK: br i1 %[[CMP]] // CHECK: %[[CMP2:[0-9a-zA-Z_.]+]] = icmp slt i32 %{{[0-9a-zA-Z_.]+}}, 16 @@ -1119,7 +1113,7 @@ test_sll() { // CHECK: call <8 x i16> @vec_sl(short vector[8], unsigned short vector[8]) // CHECK-LABEL: define available_externally <2 x i64> @_mm_slli_epi32 -// CHECK: store <4 x i32> zeroinitializer, <4 x i32>* %{{[0-9a-zA-Z_.]+}}, align 16 +// CHECK: store <4 x i32> zeroinitializer, ptr %{{[0-9a-zA-Z_.]+}}, align 16 // CHECK: %[[CMP:[0-9a-zA-Z_.]+]] = icmp sge i32 %{{[0-9a-zA-Z_.]+}}, 0 // CHECK: br i1 %[[CMP]] // CHECK: %[[CMP2:[0-9a-zA-Z_.]+]] = icmp slt i32 %{{[0-9a-zA-Z_.]+}}, 32 @@ -1133,7 +1127,7 @@ test_sll() { // CHECK: call <4 x i32> @vec_sl(int vector[4], unsigned int vector[4]) // CHECK-LABEL: define available_externally <2 x i64> @_mm_slli_epi64 -// CHECK: store <2 x i64> zeroinitializer, <2 x i64>* %{{[0-9a-zA-Z_.]+}}, align 16 +// CHECK: store <2 x i64> zeroinitializer, ptr %{{[0-9a-zA-Z_.]+}}, align 16 // CHECK: %[[CMP:[0-9a-zA-Z_.]+]] = icmp sge i32 %{{[0-9a-zA-Z_.]+}}, 0 // CHECK: br i1 %[[CMP]] // CHECK: %[[CMP2:[0-9a-zA-Z_.]+]] = icmp slt i32 %{{[0-9a-zA-Z_.]+}}, 64 @@ -1147,11 +1141,11 @@ test_sll() { // CHECK: call <2 x i64> @vec_sl(long long vector[2], unsigned long long vector[2]) // CHECK-LABEL: define available_externally <2 x i64> @_mm_slli_si128 -// CHECK: store <16 x i8> zeroinitializer, <16 x i8>* %{{[0-9a-zA-Z_.]+}}, align 16 +// CHECK: store <16 x i8> zeroinitializer, ptr %{{[0-9a-zA-Z_.]+}}, align 16 // CHECK-BE: %[[SUB:[0-9a-zA-Z_.]+]] = sub nsw i32 16, %{{[0-9a-zA-Z_.]+}} // CHECK-BE: call <16 x i8> @vec_sld(unsigned char vector[16], unsigned char vector[16], unsigned int)(<16 x i8> noundef zeroinitializer, <16 x i8> noundef %{{[0-9a-zA-Z_.]+}}, i32 noundef zeroext %[[SUB]]) // CHECK-LE: call <16 x i8> @vec_sld(unsigned char vector[16], unsigned char vector[16], unsigned int)(<16 x i8> noundef %{{[0-9a-zA-Z_.]+}}, <16 x i8> noundef zeroinitializer, i32 noundef zeroext %{{[0-9a-zA-Z_.]+}}) -// CHECK: store <16 x i8> zeroinitializer, <16 x i8>* %{{[0-9a-zA-Z_.]+}}, align 16 +// CHECK: store <16 x i8> zeroinitializer, ptr %{{[0-9a-zA-Z_.]+}}, align 16 void __attribute__((noinline)) test_sqrt() { @@ -1180,21 +1174,21 @@ test_sra() { // CHECK-LABEL: @test_sra // CHECK-LABEL: define available_externally <2 x i64> @_mm_sra_epi16 -// CHECK: store <8 x i16> , <8 x i16>* %{{[0-9a-zA-Z_.]+}}, align 16 +// CHECK: store <8 x i16> , ptr %{{[0-9a-zA-Z_.]+}}, align 16 // CHECK-LE: call <8 x i16> @vec_splat(unsigned short vector[8], unsigned int)(<8 x i16> noundef %{{[0-9a-zA-Z_.]+}}, i32 noundef zeroext 0) // CHECK-BE: call <8 x i16> @vec_splat(unsigned short vector[8], unsigned int)(<8 x i16> noundef %{{[0-9a-zA-Z_.]+}}, i32 noundef zeroext 3) // CHECK: call <8 x i16> @vec_min(unsigned short vector[8], unsigned short vector[8])(<8 x i16> noundef %{{[0-9a-zA-Z_.]+}}, <8 x i16> noundef ) // CHECK: call <8 x i16> @vec_sra(short vector[8], unsigned short vector[8]) // CHECK-LABEL: define available_externally <2 x i64> @_mm_sra_epi32 -// CHECK: store <4 x i32> , <4 x i32>* %{{[0-9a-zA-Z_.]+}}, align 16 +// CHECK: store <4 x i32> , ptr %{{[0-9a-zA-Z_.]+}}, align 16 // CHECK-LE: call <4 x i32> @vec_splat(unsigned int vector[4], unsigned int)(<4 x i32> noundef %{{[0-9a-zA-Z_.]+}}, i32 noundef zeroext 0) // CHECK-BE: call <4 x i32> @vec_splat(unsigned int vector[4], unsigned int)(<4 x i32> noundef %{{[0-9a-zA-Z_.]+}}, i32 noundef zeroext 1) // CHECK: call <4 x i32> @vec_min(unsigned int vector[4], unsigned int vector[4])(<4 x i32> noundef %{{[0-9a-zA-Z_.]+}}, <4 x i32> noundef ) // CHECK: call <4 x i32> @vec_sra(int vector[4], unsigned int vector[4]) // CHECK-LABEL: define available_externally <2 x i64> @_mm_srai_epi16 -// CHECK: store <8 x i16> , <8 x i16>* %{{[0-9a-zA-Z_.]+}}, align 16 +// CHECK: store <8 x i16> , ptr %{{[0-9a-zA-Z_.]+}}, align 16 // CHECK: %[[CMP:[0-9a-zA-Z_.]+]] = icmp slt i32 %{{[0-9a-zA-Z_.]+}}, 16 // CHECK: br i1 %[[CMP]] // CHECK: call i1 @llvm.is.constant @@ -1205,7 +1199,7 @@ test_sra() { // CHECK: call <8 x i16> @vec_sra(short vector[8], unsigned short vector[8]) // CHECK-LABEL: define available_externally <2 x i64> @_mm_srai_epi32 -// CHECK: store <4 x i32> , <4 x i32>* %{{[0-9a-zA-Z_.]+}}, align 16 +// CHECK: store <4 x i32> , ptr %{{[0-9a-zA-Z_.]+}}, align 16 // CHECK: %[[CMP:[0-9a-zA-Z_.]+]] = icmp slt i32 %{{[0-9a-zA-Z_.]+}}, 32 // CHECK: br i1 %[[CMP]] // CHECK: call i1 @llvm.is.constant @@ -1231,7 +1225,7 @@ test_srl() { // CHECK-LABEL: @test_srl // CHECK-LABEL: define available_externally <2 x i64> @_mm_srl_epi16 -// CHECK: store <8 x i16> , <8 x i16>* %{{[0-9a-zA-Z_.]+}}, align 16 +// CHECK: store <8 x i16> , ptr %{{[0-9a-zA-Z_.]+}}, align 16 // CHECK-LE: call <8 x i16> @vec_splat(unsigned short vector[8], unsigned int)(<8 x i16> noundef %{{[0-9a-zA-Z_.]+}}, i32 noundef zeroext 0) // CHECK-BE: call <8 x i16> @vec_splat(unsigned short vector[8], unsigned int)(<8 x i16> noundef %{{[0-9a-zA-Z_.]+}}, i32 noundef zeroext 3) // CHECK: call <8 x i16> @vec_cmple(unsigned short vector[8], unsigned short vector[8])(<8 x i16> noundef %{{[0-9a-zA-Z_.]+}}, <8 x i16> noundef ) @@ -1252,7 +1246,7 @@ test_srl() { // CHECK: call <2 x i64> @vec_sel(unsigned long long vector[2], unsigned long long vector[2], bool vector[2]) // CHECK-LABEL: define available_externally <2 x i64> @_mm_srli_epi16 -// CHECK: store <8 x i16> zeroinitializer, <8 x i16>* %{{[0-9a-zA-Z_.]+}}, align 16 +// CHECK: store <8 x i16> zeroinitializer, ptr %{{[0-9a-zA-Z_.]+}}, align 16 // CHECK: %[[CMP:[0-9a-zA-Z_.]+]] = icmp slt i32 %{{[0-9a-zA-Z_.]+}}, 16 // CHECK: br i1 %[[CMP]] // CHECK: call i1 @llvm.is.constant @@ -1263,7 +1257,7 @@ test_srl() { // CHECK: call <8 x i16> @vec_sr(short vector[8], unsigned short vector[8]) // CHECK-LABEL: define available_externally <2 x i64> @_mm_srli_epi32 -// CHECK: store <4 x i32> zeroinitializer, <4 x i32>* %{{[0-9a-zA-Z_.]+}}, align 16 +// CHECK: store <4 x i32> zeroinitializer, ptr %{{[0-9a-zA-Z_.]+}}, align 16 // CHECK: %[[CMP:[0-9a-zA-Z_.]+]] = icmp slt i32 %{{[0-9a-zA-Z_.]+}}, 32 // CHECK: br i1 %[[CMP]] // CHECK: call i1 @llvm.is.constant @@ -1276,7 +1270,7 @@ test_srl() { // CHECK: call <4 x i32> @vec_sr(int vector[4], unsigned int vector[4]) // CHECK-LABEL: define available_externally <2 x i64> @_mm_srli_epi64 -// CHECK: store <2 x i64> zeroinitializer, <2 x i64>* %{{[0-9a-zA-Z_.]+}}, align 16 +// CHECK: store <2 x i64> zeroinitializer, ptr %{{[0-9a-zA-Z_.]+}}, align 16 // CHECK: %[[CMP:[0-9a-zA-Z_.]+]] = icmp slt i32 %{{[0-9a-zA-Z_.]+}}, 64 // CHECK: br i1 %[[CMP]] // CHECK: call i1 @llvm.is.constant @@ -1310,56 +1304,52 @@ test_store() { // CHECK-LABEL: @test_store // CHECK-LABEL: define available_externally void @_mm_store_pd -// CHECK: %[[ADDR:[0-9a-zA-Z_.]+]] = load double*, double** %{{[0-9a-zA-Z_.]+}}, align 8 -// CHECK: %[[CAST:[0-9a-zA-Z_.]+]] = bitcast double* %[[ADDR]] to <16 x i8>* -// CHECK: call void @vec_st(unsigned char vector[16], long, unsigned char vector[16]*)(<16 x i8> noundef %{{[0-9a-zA-Z_.]+}}, i64 noundef 0, <16 x i8>* noundef %[[CAST]]) +// CHECK: %[[ADDR:[0-9a-zA-Z_.]+]] = load ptr, ptr %{{[0-9a-zA-Z_.]+}}, align 8 +// CHECK: call void @vec_st(unsigned char vector[16], long, unsigned char vector[16]*)(<16 x i8> noundef %{{[0-9a-zA-Z_.]+}}, i64 noundef 0, ptr noundef %[[ADDR]]) // CHECK-LABEL: define available_externally void @_mm_store_pd1 -// CHECK: %[[ADDR:[0-9a-zA-Z_.]+]] = load double*, double** %{{[0-9a-zA-Z_.]+}}, align 8 -// CHECK: %[[ADDR2:[0-9a-zA-Z_.]+]] = load <2 x double>, <2 x double>* %{{[0-9a-zA-Z_.]+}}, align 16 -// CHECK: call void @_mm_store1_pd(double* noundef %[[ADDR]], <2 x double> noundef %[[ADDR2]]) +// CHECK: %[[ADDR:[0-9a-zA-Z_.]+]] = load ptr, ptr %{{[0-9a-zA-Z_.]+}}, align 8 +// CHECK: %[[ADDR2:[0-9a-zA-Z_.]+]] = load <2 x double>, ptr %{{[0-9a-zA-Z_.]+}}, align 16 +// CHECK: call void @_mm_store1_pd(ptr noundef %[[ADDR]], <2 x double> noundef %[[ADDR2]]) // CHECK-LABEL: define available_externally void @_mm_store_sd -// CHECK: %[[ADDR:[0-9a-zA-Z_.]+]] = load double*, double** %{{[0-9a-zA-Z_.]+}}, align 8 -// CHECK: store double %{{[0-9a-zA-Z_.]+}}, double* %[[ADDR]] +// CHECK: %[[ADDR:[0-9a-zA-Z_.]+]] = load ptr, ptr %{{[0-9a-zA-Z_.]+}}, align 8 +// CHECK: store double %{{[0-9a-zA-Z_.]+}}, ptr %[[ADDR]] // CHECK-LABEL: define available_externally void @_mm_store_si128 -// CHECK: %[[LOAD:[0-9a-zA-Z_.]+]] = load <2 x i64>*, <2 x i64>** %{{[0-9a-zA-Z_.]+}}, align 8 -// CHECK: %[[CAST:[0-9a-zA-Z_.]+]] = bitcast <2 x i64>* %[[LOAD]] to <16 x i8>* -// CHECK: call void @vec_st(unsigned char vector[16], long, unsigned char vector[16]*)(<16 x i8> noundef %{{[0-9a-zA-Z_.]+}}, i64 noundef 0, <16 x i8>* noundef %[[CAST]]) +// CHECK: %[[LOAD:[0-9a-zA-Z_.]+]] = load ptr, ptr %{{[0-9a-zA-Z_.]+}}, align 8 +// CHECK: call void @vec_st(unsigned char vector[16], long, unsigned char vector[16]*)(<16 x i8> noundef %{{[0-9a-zA-Z_.]+}}, i64 noundef 0, ptr noundef %[[LOAD]]) // CHECK-LABEL: define available_externally void @_mm_store1_pd -// CHECK: %[[ADDR:[0-9a-zA-Z_.]+]] = load double*, double** %{{[0-9a-zA-Z_.]+}}, align 8 -// CHECK: %[[VAL:[0-9a-zA-Z_.]+]] = load <2 x double>, <2 x double>* %{{[0-9a-zA-Z_.]+}}, align 16 +// CHECK: %[[ADDR:[0-9a-zA-Z_.]+]] = load ptr, ptr %{{[0-9a-zA-Z_.]+}}, align 8 +// CHECK: %[[VAL:[0-9a-zA-Z_.]+]] = load <2 x double>, ptr %{{[0-9a-zA-Z_.]+}}, align 16 // CHECK: %[[CALL:[0-9a-zA-Z_.]+]] = call <2 x double> @vec_splat(double vector[2], unsigned int)(<2 x double> noundef %[[VAL]], i32 noundef zeroext 0) -// CHECK: call void @_mm_store_pd(double* noundef %[[ADDR]], <2 x double> noundef %[[CALL]]) +// CHECK: call void @_mm_store_pd(ptr noundef %[[ADDR]], <2 x double> noundef %[[CALL]]) // CHECK-LABEL: define available_externally void @_mm_storeh_pd -// CHECK: %[[ADDR:[0-9a-zA-Z_.]+]] = load double*, double** %{{[0-9a-zA-Z_.]+}}, align 8 -// CHECK: store double %{{[0-9a-zA-Z_.]+}}, double* %[[ADDR]] +// CHECK: %[[ADDR:[0-9a-zA-Z_.]+]] = load ptr, ptr %{{[0-9a-zA-Z_.]+}}, align 8 +// CHECK: store double %{{[0-9a-zA-Z_.]+}}, ptr %[[ADDR]] // CHECK-LABEL: define available_externally void @_mm_storel_epi64 -// CHECK: %[[ADDR:[0-9a-zA-Z_.]+]] = load <2 x i64>*, <2 x i64>** %{{[0-9a-zA-Z_.]+}}, align 8 -// CHECK: %[[CAST:[0-9a-zA-Z_.]+]] = bitcast <2 x i64>* %[[ADDR]] to i64* -// CHECK: store i64 %{{[0-9a-zA-Z_.]+}}, i64* %[[CAST]], align 8 +// CHECK: %[[ADDR:[0-9a-zA-Z_.]+]] = load ptr, ptr %{{[0-9a-zA-Z_.]+}}, align 8 +// CHECK: store i64 %{{[0-9a-zA-Z_.]+}}, ptr %[[ADDR]], align 8 // CHECK-LABEL: define available_externally void @_mm_storel_pd -// CHECK: %[[ADDR:[0-9a-zA-Z_.]+]] = load double*, double** %{{[0-9a-zA-Z_.]+}}, align 8 -// CHECK: %[[VAL:[0-9a-zA-Z_.]+]] = load <2 x double>, <2 x double>* %{{[0-9a-zA-Z_.]+}}, align 16 -// CHECK: call void @_mm_store_sd(double* noundef %[[ADDR]], <2 x double> noundef %[[VAL]]) +// CHECK: %[[ADDR:[0-9a-zA-Z_.]+]] = load ptr, ptr %{{[0-9a-zA-Z_.]+}}, align 8 +// CHECK: %[[VAL:[0-9a-zA-Z_.]+]] = load <2 x double>, ptr %{{[0-9a-zA-Z_.]+}}, align 16 +// CHECK: call void @_mm_store_sd(ptr noundef %[[ADDR]], <2 x double> noundef %[[VAL]]) // CHECK-LABEL: define available_externally void @_mm_storer_pd // CHECK: shufflevector <2 x i64> %{{[0-9a-zA-Z_.]+}}, <2 x i64> %{{[0-9a-zA-Z_.]+}}, <2 x i32> -// CHECK: call void @_mm_store_pd(double* noundef %{{[0-9a-zA-Z_.]+}}, <2 x double> noundef %{{[0-9a-zA-Z_.]+}}) +// CHECK: call void @_mm_store_pd(ptr noundef %{{[0-9a-zA-Z_.]+}}, <2 x double> noundef %{{[0-9a-zA-Z_.]+}}) // CHECK-LABEL: define available_externally void @_mm_storeu_pd -// CHECK: %[[ADDR:[0-9a-zA-Z_.]+]] = load double*, double** %{{[0-9a-zA-Z_.]+}}, align 8 -// CHECK: %[[CAST:[0-9a-zA-Z_.]+]] = bitcast double* %[[ADDR]] to <2 x double>* -// CHECK: store <2 x double> %{{[0-9a-zA-Z_.]+}}, <2 x double>* %[[CAST]], align 1 +// CHECK: %[[ADDR:[0-9a-zA-Z_.]+]] = load ptr, ptr %{{[0-9a-zA-Z_.]+}}, align 8 +// CHECK: store <2 x double> %{{[0-9a-zA-Z_.]+}}, ptr %[[ADDR]], align 1 // CHECK-LABEL: define available_externally void @_mm_storeu_si128 -// CHECK: %[[ADDR:[0-9a-zA-Z_.]+]] = load <2 x i64>*, <2 x i64>** %{{[0-9a-zA-Z_.]+}}, align 8 -// CHECK: store <2 x i64> %{{[0-9a-zA-Z_.]+}}, <2 x i64>* %[[ADDR]], align 1 +// CHECK: %[[ADDR:[0-9a-zA-Z_.]+]] = load ptr, ptr %{{[0-9a-zA-Z_.]+}}, align 8 +// CHECK: store <2 x i64> %{{[0-9a-zA-Z_.]+}}, ptr %[[ADDR]], align 1 void __attribute__((noinline)) test_stream() { @@ -1372,16 +1362,16 @@ test_stream() { // CHECK-LABEL: @test_stream // CHECK-LABEL: define available_externally void @_mm_stream_pd -// CHECK: call void asm sideeffect "dcbtstt 0,$0", "b,~{memory}"(double* %{{[0-9a-zA-Z_.]+}}) +// CHECK: call void asm sideeffect "dcbtstt 0,$0", "b,~{memory}"(ptr %{{[0-9a-zA-Z_.]+}}) // CHECK-LABEL: define available_externally void @_mm_stream_si128 -// CHECK: call void asm sideeffect "dcbtstt 0,$0", "b,~{memory}"(<2 x i64>* %{{[0-9a-zA-Z_.]+}}) +// CHECK: call void asm sideeffect "dcbtstt 0,$0", "b,~{memory}"(ptr %{{[0-9a-zA-Z_.]+}}) // CHECK-LABEL: define available_externally void @_mm_stream_si32 -// CHECK: call void asm sideeffect "dcbtstt 0,$0", "b,~{memory}"(i32* %{{[0-9a-zA-Z_.]+}}) +// CHECK: call void asm sideeffect "dcbtstt 0,$0", "b,~{memory}"(ptr %{{[0-9a-zA-Z_.]+}}) // CHECK-LABEL: define available_externally void @_mm_stream_si64 -// CHECK: call void asm sideeffect "\09dcbtstt\090,$0", "b,~{memory}"(i64* %{{[0-9a-zA-Z_.]+}}) +// CHECK: call void asm sideeffect "\09dcbtstt\090,$0", "b,~{memory}"(ptr %{{[0-9a-zA-Z_.]+}}) void __attribute__((noinline)) test_sub() { @@ -1472,14 +1462,14 @@ test_undefined() { // CHECK-LABEL: @test_undefined // CHECK-LABEL: define available_externally <2 x double> @_mm_undefined_pd() -// CHECK: %[[VAL:[0-9a-zA-Z_.]+]] = load <2 x double>, <2 x double>* %[[ADDR:[0-9a-zA-Z_.]+]], align 16 -// CHECK: store <2 x double> %[[VAL]], <2 x double>* %[[ADDR]], align 16 -// CHECK: load <2 x double>, <2 x double>* %[[ADDR]], align 16 +// CHECK: %[[VAL:[0-9a-zA-Z_.]+]] = load <2 x double>, ptr %[[ADDR:[0-9a-zA-Z_.]+]], align 16 +// CHECK: store <2 x double> %[[VAL]], ptr %[[ADDR]], align 16 +// CHECK: load <2 x double>, ptr %[[ADDR]], align 16 // CHECK-LABEL: define available_externally <2 x i64> @_mm_undefined_si128() -// CHECK: %[[VAL:[0-9a-zA-Z_.]+]] = load <2 x i64>, <2 x i64>* %[[ADDR:[0-9a-zA-Z_.]+]], align 16 -// CHECK: store <2 x i64> %[[VAL]], <2 x i64>* %[[ADDR]], align 16 -// CHECK: load <2 x i64>, <2 x i64>* %[[ADDR]], align 16 +// CHECK: %[[VAL:[0-9a-zA-Z_.]+]] = load <2 x i64>, ptr %[[ADDR:[0-9a-zA-Z_.]+]], align 16 +// CHECK: store <2 x i64> %[[VAL]], ptr %[[ADDR]], align 16 +// CHECK: load <2 x i64>, ptr %[[ADDR]], align 16 void __attribute__((noinline)) test_unpack() { diff --git a/clang/test/CodeGen/PowerPC/ppc-varargs-struct.c b/clang/test/CodeGen/PowerPC/ppc-varargs-struct.c index 17d6e1cb74cc4c..6b699758708352 100644 --- a/clang/test/CodeGen/PowerPC/ppc-varargs-struct.c +++ b/clang/test/CodeGen/PowerPC/ppc-varargs-struct.c @@ -1,8 +1,8 @@ // REQUIRES: powerpc-registered-target // REQUIRES: asserts -// RUN: %clang_cc1 -no-opaque-pointers -triple powerpc64-unknown-linux-gnu -emit-llvm -o - %s | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -triple powerpc-unknown-linux-gnu -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-PPC -// RUN: %clang_cc1 -no-opaque-pointers -triple powerpc64-ibm-aix-xcoff -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -triple powerpc64-unknown-linux-gnu -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -triple powerpc-unknown-linux-gnu -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-PPC +// RUN: %clang_cc1 -triple powerpc64-ibm-aix-xcoff -emit-llvm -o - %s | FileCheck %s #include @@ -16,84 +16,73 @@ void testva (int n, ...) va_list ap; struct x t = va_arg (ap, struct x); -// CHECK: bitcast i8* %{{[a-z.0-9]*}} to %struct.x* -// CHECK: bitcast %struct.x* %t to i8* -// CHECK: bitcast %struct.x* %{{[0-9]+}} to i8* // CHECK: call void @llvm.memcpy -// CHECK-PPC: [[ARRAYDECAY:%.+]] = getelementptr inbounds [1 x %struct.__va_list_tag], [1 x %struct.__va_list_tag]* %ap, i32 0, i32 0 -// CHECK-PPC-NEXT: [[GPRPTR:%.+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* [[ARRAYDECAY]], i32 0, i32 0 -// CHECK-PPC-NEXT: [[GPR:%.+]] = load i8, i8* [[GPRPTR]], align 4 +// CHECK-PPC: [[ARRAYDECAY:%.+]] = getelementptr inbounds [1 x %struct.__va_list_tag], ptr %ap, i32 0, i32 0 +// CHECK-PPC-NEXT: [[GPRPTR:%.+]] = getelementptr inbounds %struct.__va_list_tag, ptr [[ARRAYDECAY]], i32 0, i32 0 +// CHECK-PPC-NEXT: [[GPR:%.+]] = load i8, ptr [[GPRPTR]], align 4 // CHECK-PPC-NEXT: [[COND:%.+]] = icmp ult i8 [[GPR]], 8 // CHECK-PPC-NEXT: br i1 [[COND]], label %[[USING_REGS:[a-z_0-9]+]], label %[[USING_OVERFLOW:[a-z_0-9]+]] // // CHECK-PPC:[[USING_REGS]] -// CHECK-PPC-NEXT: [[REGSAVE_AREA_P:%.+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* [[ARRAYDECAY]], i32 0, i32 4 -// CHECK-PPC-NEXT: [[REGSAVE_AREA:%.+]] = load i8*, i8** [[REGSAVE_AREA_P]], align 4 +// CHECK-PPC-NEXT: [[REGSAVE_AREA_P:%.+]] = getelementptr inbounds %struct.__va_list_tag, ptr [[ARRAYDECAY]], i32 0, i32 4 +// CHECK-PPC-NEXT: [[REGSAVE_AREA:%.+]] = load ptr, ptr [[REGSAVE_AREA_P]], align 4 // CHECK-PPC-NEXT: [[OFFSET:%.+]] = mul i8 [[GPR]], 4 -// CHECK-PPC-NEXT: [[RAW_REGADDR:%.+]] = getelementptr inbounds i8, i8* [[REGSAVE_AREA]], i8 [[OFFSET]] -// CHECK-PPC-NEXT: [[REGADDR:%.+]] = bitcast i8* [[RAW_REGADDR]] to %struct.x** +// CHECK-PPC-NEXT: [[RAW_REGADDR:%.+]] = getelementptr inbounds i8, ptr [[REGSAVE_AREA]], i8 [[OFFSET]] // CHECK-PPC-NEXT: [[USED_GPR:%[0-9]+]] = add i8 [[GPR]], 1 -// CHECK-PPC-NEXT: store i8 [[USED_GPR]], i8* [[GPRPTR]], align 4 +// CHECK-PPC-NEXT: store i8 [[USED_GPR]], ptr [[GPRPTR]], align 4 // CHECK-PPC-NEXT: br label %[[CONT:[a-z0-9]+]] // // CHECK-PPC:[[USING_OVERFLOW]] -// CHECK-PPC-NEXT: store i8 8, i8* [[GPRPTR]], align 4 -// CHECK-PPC-NEXT: [[OVERFLOW_AREA_P:%[0-9]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* [[ARRAYDECAY]], i32 0, i32 3 -// CHECK-PPC-NEXT: [[OVERFLOW_AREA:%.+]] = load i8*, i8** [[OVERFLOW_AREA_P]], align 4 -// CHECK-PPC-NEXT: %{{[0-9]+}} = ptrtoint i8* %argp.cur to i32 +// CHECK-PPC-NEXT: store i8 8, ptr [[GPRPTR]], align 4 +// CHECK-PPC-NEXT: [[OVERFLOW_AREA_P:%[0-9]+]] = getelementptr inbounds %struct.__va_list_tag, ptr [[ARRAYDECAY]], i32 0, i32 3 +// CHECK-PPC-NEXT: [[OVERFLOW_AREA:%.+]] = load ptr, ptr [[OVERFLOW_AREA_P]], align 4 +// CHECK-PPC-NEXT: %{{[0-9]+}} = ptrtoint ptr %argp.cur to i32 // CHECK-PPC-NEXT: %{{[0-9]+}} = add i32 %{{[0-9]+}}, 7 // CHECK-PPC-NEXT: %{{[0-9]+}} = and i32 %{{[0-9]+}}, -8 -// CHECK-PPC-NEXT: %argp.cur.aligned = inttoptr i32 %{{[0-9]+}} to i8* -// CHECK-PPC-NEXT: [[MEMADDR:%.+]] = bitcast i8* %argp.cur.aligned to %struct.x** -// CHECK-PPC-NEXT: [[NEW_OVERFLOW_AREA:%[0-9]+]] = getelementptr inbounds i8, i8* %argp.cur.aligned, i32 4 -// CHECK-PPC-NEXT: store i8* [[NEW_OVERFLOW_AREA:%[0-9]+]], i8** [[OVERFLOW_AREA_P]], align 4 +// CHECK-PPC-NEXT: %argp.cur.aligned = inttoptr i32 %{{[0-9]+}} to ptr +// CHECK-PPC-NEXT: [[NEW_OVERFLOW_AREA:%[0-9]+]] = getelementptr inbounds i8, ptr %argp.cur.aligned, i32 4 +// CHECK-PPC-NEXT: store ptr [[NEW_OVERFLOW_AREA:%[0-9]+]], ptr [[OVERFLOW_AREA_P]], align 4 // CHECK-PPC-NEXT: br label %[[CONT]] // // CHECK-PPC:[[CONT]] -// CHECK-PPC-NEXT: [[VAARG_ADDR:%[a-z.0-9]+]] = phi %struct.x** [ [[REGADDR]], %[[USING_REGS]] ], [ [[MEMADDR]], %[[USING_OVERFLOW]] ] -// CHECK-PPC-NEXT: [[AGGR:%[a-z0-9]+]] = load %struct.x*, %struct.x** [[VAARG_ADDR]] -// CHECK-PPC-NEXT: [[DEST:%[0-9]+]] = bitcast %struct.x* %t to i8* -// CHECK-PPC-NEXT: [[SRC:%.+]] = bitcast %struct.x* [[AGGR]] to i8* -// CHECK-PPC-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 [[DEST]], i8* align 8 [[SRC]], i32 16, i1 false) +// CHECK-PPC-NEXT: [[VAARG_ADDR:%[a-z.0-9]+]] = phi ptr [ [[RAW_REGADDR]], %[[USING_REGS]] ], [ %argp.cur.aligned, %[[USING_OVERFLOW]] ] +// CHECK-PPC-NEXT: [[AGGR:%[a-z0-9]+]] = load ptr, ptr [[VAARG_ADDR]] +// CHECK-PPC-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 8 %t, ptr align 8 [[AGGR]], i32 16, i1 false) int v = va_arg (ap, int); -// CHECK: getelementptr inbounds i8, i8* %{{[a-z.0-9]*}}, i64 4 -// CHECK: bitcast i8* %{{[0-9]+}} to i32* -// CHECK-PPC: [[ARRAYDECAY:%[a-z0-9]+]] = getelementptr inbounds [1 x %struct.__va_list_tag], [1 x %struct.__va_list_tag]* %ap, i32 0, i32 0 -// CHECK-PPC-NEXT: [[GPRPTR:%.+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* [[ARRAYDECAY]], i32 0, i32 0 -// CHECK-PPC-NEXT: [[GPR:%.+]] = load i8, i8* [[GPRPTR]], align 4 +// CHECK: getelementptr inbounds i8, ptr %{{[a-z.0-9]*}}, i64 4 +// CHECK-PPC: [[ARRAYDECAY:%[a-z0-9]+]] = getelementptr inbounds [1 x %struct.__va_list_tag], ptr %ap, i32 0, i32 0 +// CHECK-PPC-NEXT: [[GPRPTR:%.+]] = getelementptr inbounds %struct.__va_list_tag, ptr [[ARRAYDECAY]], i32 0, i32 0 +// CHECK-PPC-NEXT: [[GPR:%.+]] = load i8, ptr [[GPRPTR]], align 4 // CHECK-PPC-NEXT: [[COND:%.+]] = icmp ult i8 [[GPR]], 8 // CHECK-PPC-NEXT: br i1 [[COND]], label %[[USING_REGS:.+]], label %[[USING_OVERFLOW:.+]]{{$}} // // CHECK-PPC:[[USING_REGS]] -// CHECK-PPC-NEXT: [[REGSAVE_AREA_P:%.+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* [[ARRAYDECAY]], i32 0, i32 4 -// CHECK-PPC-NEXT: [[REGSAVE_AREA:%.+]] = load i8*, i8** [[REGSAVE_AREA_P]], align 4 +// CHECK-PPC-NEXT: [[REGSAVE_AREA_P:%.+]] = getelementptr inbounds %struct.__va_list_tag, ptr [[ARRAYDECAY]], i32 0, i32 4 +// CHECK-PPC-NEXT: [[REGSAVE_AREA:%.+]] = load ptr, ptr [[REGSAVE_AREA_P]], align 4 // CHECK-PPC-NEXT: [[OFFSET:%.+]] = mul i8 [[GPR]], 4 -// CHECK-PPC-NEXT: [[RAW_REGADDR:%.+]] = getelementptr inbounds i8, i8* [[REGSAVE_AREA]], i8 [[OFFSET]] -// CHECK-PPC-NEXT: [[REGADDR:%.+]] = bitcast i8* [[RAW_REGADDR]] to i32* +// CHECK-PPC-NEXT: [[RAW_REGADDR:%.+]] = getelementptr inbounds i8, ptr [[REGSAVE_AREA]], i8 [[OFFSET]] // CHECK-PPC-NEXT: [[USED_GPR:%[0-9]+]] = add i8 [[GPR]], 1 -// CHECK-PPC-NEXT: store i8 [[USED_GPR]], i8* [[GPRPTR]], align 4 +// CHECK-PPC-NEXT: store i8 [[USED_GPR]], ptr [[GPRPTR]], align 4 // CHECK-PPC-NEXT: br label %[[CONT:[a-z0-9]+]] // // CHECK-PPC:[[USING_OVERFLOW]] -// CHECK-PPC-NEXT: store i8 8, i8* [[GPRPTR]], align 4 -// CHECK-PPC-NEXT: [[OVERFLOW_AREA_P:%[0-9]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* [[ARRAYDECAY]], i32 0, i32 3 -// CHECK-PPC-NEXT: [[OVERFLOW_AREA:%.+]] = load i8*, i8** [[OVERFLOW_AREA_P]], align 4 -// CHECK-PPC-NEXT: [[MEMADDR:%.+]] = bitcast i8* [[OVERFLOW_AREA]] to i32* -// CHECK-PPC-NEXT: [[NEW_OVERFLOW_AREA:%[0-9]+]] = getelementptr inbounds i8, i8* [[OVERFLOW_AREA]], i32 4 -// CHECK-PPC-NEXT: store i8* [[NEW_OVERFLOW_AREA]], i8** [[OVERFLOW_AREA_P]] +// CHECK-PPC-NEXT: store i8 8, ptr [[GPRPTR]], align 4 +// CHECK-PPC-NEXT: [[OVERFLOW_AREA_P:%[0-9]+]] = getelementptr inbounds %struct.__va_list_tag, ptr [[ARRAYDECAY]], i32 0, i32 3 +// CHECK-PPC-NEXT: [[OVERFLOW_AREA:%.+]] = load ptr, ptr [[OVERFLOW_AREA_P]], align 4 +// CHECK-PPC-NEXT: [[NEW_OVERFLOW_AREA:%[0-9]+]] = getelementptr inbounds i8, ptr [[OVERFLOW_AREA]], i32 4 +// CHECK-PPC-NEXT: store ptr [[NEW_OVERFLOW_AREA]], ptr [[OVERFLOW_AREA_P]] // CHECK-PPC-NEXT: br label %[[CONT]] // // CHECK-PPC:[[CONT]] -// CHECK-PPC-NEXT: [[VAARG_ADDR:%[a-z.0-9]+]] = phi i32* [ [[REGADDR]], %[[USING_REGS]] ], [ [[MEMADDR]], %[[USING_OVERFLOW]] ] -// CHECK-PPC-NEXT: [[THIRTYFIVE:%[0-9]+]] = load i32, i32* [[VAARG_ADDR]] -// CHECK-PPC-NEXT: store i32 [[THIRTYFIVE]], i32* %v, align 4 +// CHECK-PPC-NEXT: [[VAARG_ADDR:%[a-z.0-9]+]] = phi ptr [ [[RAW_REGADDR]], %[[USING_REGS]] ], [ [[OVERFLOW_AREA]], %[[USING_OVERFLOW]] ] +// CHECK-PPC-NEXT: [[THIRTYFIVE:%[0-9]+]] = load i32, ptr [[VAARG_ADDR]] +// CHECK-PPC-NEXT: store i32 [[THIRTYFIVE]], ptr %v, align 4 #ifdef __powerpc64__ __int128_t u = va_arg (ap, __int128_t); #endif -// CHECK: bitcast i8* %{{[a-z.0-9]+}} to i128* -// CHECK-NEXT: load i128, i128* %{{[0-9]+}} +// CHECK: load i128, ptr %argp.cur3 } diff --git a/clang/test/CodeGen/PowerPC/ppc-xmmintrin.c b/clang/test/CodeGen/PowerPC/ppc-xmmintrin.c index ac49dbbd06c955..ce002f001e1823 100644 --- a/clang/test/CodeGen/PowerPC/ppc-xmmintrin.c +++ b/clang/test/CodeGen/PowerPC/ppc-xmmintrin.c @@ -1,31 +1,31 @@ // REQUIRES: powerpc-registered-target -// RUN: %clang -Xclang -no-opaque-pointers -S -emit-llvm -target powerpc64-unknown-linux-gnu -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \ +// RUN: %clang -S -emit-llvm -target powerpc64-unknown-linux-gnu -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \ // RUN: -ffp-contract=off -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-BE -// RUN: %clang -Xclang -no-opaque-pointers -x c++ -fsyntax-only -target powerpc64-unknown-linux-gnu -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \ +// RUN: %clang -x c++ -fsyntax-only -target powerpc64-unknown-linux-gnu -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \ // RUN: -fno-discard-value-names -mllvm -disable-llvm-optzns -// RUN: %clang -Xclang -no-opaque-pointers -S -emit-llvm -target powerpc64le-unknown-linux-gnu -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \ +// RUN: %clang -S -emit-llvm -target powerpc64le-unknown-linux-gnu -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \ // RUN: -ffp-contract=off -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-LE -// RUN: %clang -Xclang -no-opaque-pointers -x c++ -fsyntax-only -target powerpc64le-unknown-linux-gnu -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \ +// RUN: %clang -x c++ -fsyntax-only -target powerpc64le-unknown-linux-gnu -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \ // RUN: -fno-discard-value-names -mllvm -disable-llvm-optzns -// RUN: %clang -Xclang -no-opaque-pointers -S -emit-llvm -target powerpc64le-unknown-linux-gnu -mcpu=pwr10 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \ +// RUN: %clang -S -emit-llvm -target powerpc64le-unknown-linux-gnu -mcpu=pwr10 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \ // RUN: -ffp-contract=off -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-P10-LE -// RUN: %clang -Xclang -no-opaque-pointers -S -emit-llvm -target powerpc64-unknown-freebsd13.0 -mcpu=pwr8 -ffreestanding -nostdlibinc -DNO_WARN_X86_INTRINSICS %s \ +// RUN: %clang -S -emit-llvm -target powerpc64-unknown-freebsd13.0 -mcpu=pwr8 -ffreestanding -nostdlibinc -DNO_WARN_X86_INTRINSICS %s \ // RUN: -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-BE -// RUN: %clang -Xclang -no-opaque-pointers -x c++ -fsyntax-only -target powerpc64-unknown-freebsd13.0 -mcpu=pwr8 -ffreestanding -nostdlibinc -DNO_WARN_X86_INTRINSICS %s \ +// RUN: %clang -x c++ -fsyntax-only -target powerpc64-unknown-freebsd13.0 -mcpu=pwr8 -ffreestanding -nostdlibinc -DNO_WARN_X86_INTRINSICS %s \ // RUN: -fno-discard-value-names -mllvm -disable-llvm-optzns -// RUN: %clang -Xclang -no-opaque-pointers -S -emit-llvm -target powerpc64le-unknown-freebsd13.0 -mcpu=pwr8 -ffreestanding -nostdlibinc -DNO_WARN_X86_INTRINSICS %s \ +// RUN: %clang -S -emit-llvm -target powerpc64le-unknown-freebsd13.0 -mcpu=pwr8 -ffreestanding -nostdlibinc -DNO_WARN_X86_INTRINSICS %s \ // RUN: -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-LE -// RUN: %clang -Xclang -no-opaque-pointers -x c++ -fsyntax-only -target powerpc64le-unknown-freebsd13.0 -mcpu=pwr8 -ffreestanding -nostdlibinc -DNO_WARN_X86_INTRINSICS %s \ +// RUN: %clang -x c++ -fsyntax-only -target powerpc64le-unknown-freebsd13.0 -mcpu=pwr8 -ffreestanding -nostdlibinc -DNO_WARN_X86_INTRINSICS %s \ // RUN: -fno-discard-value-names -mllvm -disable-llvm-optzns -// RUN: %clang -Xclang -no-opaque-pointers -S -emit-llvm -target powerpc64-ibm-aix -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \ +// RUN: %clang -S -emit-llvm -target powerpc64-ibm-aix -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \ // RUN: -ffp-contract=off -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-BE -// RUN: %clang -Xclang -no-opaque-pointers -x c++ -fsyntax-only -target powerpc64-ibm-aix -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \ +// RUN: %clang -x c++ -fsyntax-only -target powerpc64-ibm-aix -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \ // RUN: -fno-discard-value-names -mllvm -disable-llvm-optzns -// RUN: %clang -Xclang -no-opaque-pointers -S -emit-llvm -target powerpc64-ibm-aix -mcpu=pwr10 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \ +// RUN: %clang -S -emit-llvm -target powerpc64-ibm-aix -mcpu=pwr10 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \ // RUN: -ffp-contract=off -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-P10-BE #include @@ -71,7 +71,6 @@ test_avg() { // CHECK: call <2 x i64> @vec_splats(unsigned long long) // CHECK: call <2 x i64> @vec_splats(unsigned long long) // CHECK: call <8 x i16> @vec_avg(unsigned short vector[8], unsigned short vector[8]) -// CHECK: bitcast <8 x i16> %{{[0-9a-zA-Z_.]+}} to <2 x i64> // CHECK: extractelement <2 x i64> %{{[0-9a-zA-Z_.]+}}, i32 0 // CHECK-LABEL: define available_externally i64 @_mm_avg_pu8 @@ -666,7 +665,7 @@ test_move() { // CHECK-LABEL: @test_move // CHECK-LABEL: define available_externally void @_mm_maskmove_si64 -// CHECK: store i64 -9187201950435737472, i64* %{{[0-9a-zA-Z_.]+}}, align 8 +// CHECK: store i64 -9187201950435737472, ptr %{{[0-9a-zA-Z_.]+}}, align 8 // CHECK: %[[AND:[0-9a-zA-Z_.]+]] = and i64 // CHECK: call i64 @_mm_cmpeq_pi8(i64 noundef %[[AND]], i64 noundef %{{[0-9a-zA-Z_.]+}}) // CHECK: %[[XOR:[0-9a-zA-Z_.]+]] = xor i64 %{{[0-9a-zA-Z_.]+}}, -1 @@ -684,8 +683,8 @@ test_move() { // CHECK: call <2 x i64> @vec_mergeh(unsigned long long vector[2], unsigned long long vector[2]) // CHECK-LABEL: define available_externally signext i32 @_mm_movemask_pi8 -// CHECK-LE: store i64 2269495618449464, i64* %{{[0-9a-zA-Z_.]+}}, align 8 -// CHECK-BE: store i64 4048780183313844224, i64* %{{[0-9a-zA-Z_.]+}}, align 8 +// CHECK-LE: store i64 2269495618449464, ptr %{{[0-9a-zA-Z_.]+}}, align 8 +// CHECK-BE: store i64 4048780183313844224, ptr %{{[0-9a-zA-Z_.]+}}, align 8 // CHECK: %[[CALL:[0-9a-zA-Z_.]+]] = call i64 @llvm.ppc.bpermd // CHECK: trunc i64 %[[CALL]] to i32 @@ -733,8 +732,8 @@ test_mul() { // CHECK: call <4 x float> @vec_sel(float vector[4], float vector[4], unsigned int vector[4])(<4 x float> noundef %{{[0-9a-zA-Z_.]+}}, <4 x float> noundef %{{[0-9a-zA-Z_.]+}}, <4 x i32> noundef ) // CHECK-LABEL: define available_externally i64 @_mm_mulhi_pu16 -// CHECK-LE: store <16 x i8> , <16 x i8>* %{{[0-9a-zA-Z_.]+}}, align 16 -// CHECK-BE: store <16 x i8> , <16 x i8>* %{{[0-9a-zA-Z_.]+}}, align 16 +// CHECK-LE: store <16 x i8> , ptr %{{[0-9a-zA-Z_.]+}}, align 16 +// CHECK-BE: store <16 x i8> , ptr %{{[0-9a-zA-Z_.]+}}, align 16 // CHECK: call <2 x i64> @vec_splats(unsigned long long) // CHECK: call <2 x i64> @vec_splats(unsigned long long) // CHECK: call <4 x i32> @vec_vmuleuh(<8 x i16> noundef %{{[0-9a-zA-Z_.]+}}, <8 x i16> noundef %{{[0-9a-zA-Z_.]+}}) @@ -753,7 +752,7 @@ test_prefetch() { // CHECK-LABEL: @test_prefetch // CHECK-LABEL: define available_externally void @_mm_prefetch -// CHECK: call void @llvm.prefetch.p0i8(i8* %{{[0-9a-zA-Z_.]+}}, i32 0, i32 3, i32 1) +// CHECK: call void @llvm.prefetch.p0(ptr %{{[0-9a-zA-Z_.]+}}, i32 0, i32 3, i32 1) void __attribute__((noinline)) test_rcp() { @@ -796,7 +795,7 @@ test_sad() { // CHECK-LABEL: @test_sad // CHECK-LABEL: define available_externally i64 @_mm_sad_pu8 -// CHECK: call void @llvm.memset.p0i8.i64(i8* align 8 %{{[0-9a-zA-Z_.]+}}, i8 0, i64 8, i1 false) +// CHECK: call void @llvm.memset.p0.i64(ptr align 8 %{{[0-9a-zA-Z_.]+}}, i8 0, i64 8, i1 false) // CHECK: insertelement <2 x i64> , i64 %{{[0-9a-zA-Z_.]+}}, i32 1 // CHECK: insertelement <2 x i64> , i64 %{{[0-9a-zA-Z_.]+}}, i32 1 // CHECK: call <16 x i8> @vec_min(unsigned char vector[16], unsigned char vector[16]) @@ -806,9 +805,8 @@ test_sad() { // CHECK: call <4 x i32> @vec_sums(<4 x i32> noundef %{{[0-9a-zA-Z_.]+}}, <4 x i32> noundef zeroinitializer) // CHECK: %[[EXT:[0-9a-zA-Z_.]+]] = extractelement <4 x i32> %{{[0-9a-zA-Z_.]+}}, i32 3 // CHECK: %[[TRUNC:[0-9a-zA-Z_.]+]] = trunc i32 %[[EXT]] to i16 -// CHECK: %[[CAST:[0-9a-zA-Z_.]+]] = bitcast %{{[0-9a-zA-Z_.]+}}* %{{[0-9a-zA-Z_.]+}} to [4 x i16]* -// CHECK: %[[GEP:[0-9a-zA-Z_.]+]] = getelementptr inbounds [4 x i16], [4 x i16]* %[[CAST]], i64 0, i64 0 -// CHECK: store i16 %[[TRUNC]], i16* %[[GEP]], align 8 +// CHECK: %[[GEP:[0-9a-zA-Z_.]+]] = getelementptr inbounds [4 x i16], ptr %{{[0-9a-zA-Z_.]+}}, i64 0, i64 0 +// CHECK: store i16 %[[TRUNC]], ptr %[[GEP]], align 8 // CHECK-LABEL: define available_externally i64 @_m_psadbw // CHECK: call i64 @_mm_sad_pu8 @@ -829,7 +827,7 @@ test_set() { // CHECK: %[[VEC2:[0-9a-zA-Z_.]+]] = insertelement <4 x float> %[[VEC]], float %{{[0-9a-zA-Z_.]+}}, i32 1 // CHECK: %[[VEC3:[0-9a-zA-Z_.]+]] = insertelement <4 x float> %[[VEC2]], float %{{[0-9a-zA-Z_.]+}}, i32 2 // CHECK: %[[VEC4:[0-9a-zA-Z_.]+]] = insertelement <4 x float> %[[VEC3]], float %{{[0-9a-zA-Z_.]+}}, i32 3 -// CHECK: store <4 x float> %[[VEC4]], <4 x float>* %{{[0-9a-zA-Z_.]+}}, align 16 +// CHECK: store <4 x float> %[[VEC4]], ptr %{{[0-9a-zA-Z_.]+}}, align 16 // CHECK-LABEL: define available_externally <4 x float> @_mm_set_ps1 // CHECK: call <4 x float> @_mm_set1_ps @@ -839,21 +837,21 @@ test_set() { // CHECK: %[[VEC2:[0-9a-zA-Z_.]+]] = insertelement <4 x float> %[[VEC]], float 0.000000e+00, i32 1 // CHECK: %[[VEC3:[0-9a-zA-Z_.]+]] = insertelement <4 x float> %[[VEC2]], float 0.000000e+00, i32 2 // CHECK: %[[VEC4:[0-9a-zA-Z_.]+]] = insertelement <4 x float> %[[VEC3]], float 0.000000e+00, i32 3 -// CHECK: store <4 x float> %[[VEC4]], <4 x float>* %{{[0-9a-zA-Z_.]+}}, align 16 +// CHECK: store <4 x float> %[[VEC4]], ptr %{{[0-9a-zA-Z_.]+}}, align 16 // CHECK-LABEL: define available_externally <4 x float> @_mm_set1_ps // CHECK: %[[VEC:[0-9a-zA-Z_.]+]] = insertelement <4 x float> undef, float %{{[0-9a-zA-Z_.]+}}, i32 0 // CHECK: %[[VEC2:[0-9a-zA-Z_.]+]] = insertelement <4 x float> %[[VEC]], float %{{[0-9a-zA-Z_.]+}}, i32 1 // CHECK: %[[VEC3:[0-9a-zA-Z_.]+]] = insertelement <4 x float> %[[VEC2]], float %{{[0-9a-zA-Z_.]+}}, i32 2 // CHECK: %[[VEC4:[0-9a-zA-Z_.]+]] = insertelement <4 x float> %[[VEC3]], float %{{[0-9a-zA-Z_.]+}}, i32 3 -// CHECK: store <4 x float> %[[VEC4]], <4 x float>* %{{[0-9a-zA-Z_.]+}}, align 16 +// CHECK: store <4 x float> %[[VEC4]], ptr %{{[0-9a-zA-Z_.]+}}, align 16 // CHECK-LABEL: define available_externally <4 x float> @_mm_setr_ps // CHECK: %[[VEC:[0-9a-zA-Z_.]+]] = insertelement <4 x float> undef, float %{{[0-9a-zA-Z_.]+}}, i32 0 // CHECK: %[[VEC2:[0-9a-zA-Z_.]+]] = insertelement <4 x float> %[[VEC]], float %{{[0-9a-zA-Z_.]+}}, i32 1 // CHECK: %[[VEC3:[0-9a-zA-Z_.]+]] = insertelement <4 x float> %[[VEC2]], float %{{[0-9a-zA-Z_.]+}}, i32 2 // CHECK: %[[VEC4:[0-9a-zA-Z_.]+]] = insertelement <4 x float> %[[VEC3]], float %{{[0-9a-zA-Z_.]+}}, i32 3 -// CHECK: store <4 x float> %[[VEC4]], <4 x float>* %{{[0-9a-zA-Z_.]+}}, align 16 +// CHECK: store <4 x float> %[[VEC4]], ptr %{{[0-9a-zA-Z_.]+}}, align 16 void __attribute__((noinline)) test_setzero() { @@ -863,7 +861,7 @@ test_setzero() { // CHECK-LABEL: @test_setzero // CHECK-LABEL: define available_externally <4 x float> @_mm_setzero_ps -// CHECK: store <4 x float> zeroinitializer, <4 x float>* %{{[0-9a-zA-Z_.]+}}, align 16 +// CHECK: store <4 x float> zeroinitializer, ptr %{{[0-9a-zA-Z_.]+}}, align 16 void __attribute__((noinline)) test_sfence() { @@ -896,18 +894,18 @@ test_shuffle() { // CHECK: %[[SHR3:[0-9a-zA-Z_.]+]] = ashr i32 %{{[0-9a-zA-Z_.]+}}, 6 // CHECK: %[[AND4:[0-9a-zA-Z_.]+]] = and i32 %[[SHR3]], 3 // CHECK: sext i32 %[[AND4]] to i64 -// CHECK: getelementptr inbounds [4 x i16], [4 x i16]* @_mm_shuffle_pi16.__permute_selectors, i64 0, i64 %{{[0-9a-zA-Z_.]+}} -// CHECK-LE: getelementptr inbounds [4 x i16], [4 x i16]* %{{[0-9a-zA-Z_.]+}}, i64 0, i64 0 -// CHECK-BE: getelementptr inbounds [4 x i16], [4 x i16]* %{{[0-9a-zA-Z_.]+}}, i64 0, i64 3 -// CHECK: getelementptr inbounds [4 x i16], [4 x i16]* @_mm_shuffle_pi16.__permute_selectors, i64 0, i64 %{{[0-9a-zA-Z_.]+}} -// CHECK-LE: getelementptr inbounds [4 x i16], [4 x i16]* %{{[0-9a-zA-Z_.]+}}, i64 0, i64 1 -// CHECK-BE: getelementptr inbounds [4 x i16], [4 x i16]* %{{[0-9a-zA-Z_.]+}}, i64 0, i64 2 -// CHECK: getelementptr inbounds [4 x i16], [4 x i16]* @_mm_shuffle_pi16.__permute_selectors, i64 0, i64 %{{[0-9a-zA-Z_.]+}} -// CHECK-LE: getelementptr inbounds [4 x i16], [4 x i16]* %{{[0-9a-zA-Z_.]+}}, i64 0, i64 2 -// CHECK-BE: getelementptr inbounds [4 x i16], [4 x i16]* %{{[0-9a-zA-Z_.]+}}, i64 0, i64 1 -// CHECK: getelementptr inbounds [4 x i16], [4 x i16]* @_mm_shuffle_pi16.__permute_selectors, i64 0, i64 %{{[0-9a-zA-Z_.]+}} -// CHECK-LE: getelementptr inbounds [4 x i16], [4 x i16]* %{{[0-9a-zA-Z_.]+}}, i64 0, i64 3 -// CHECK-BE: getelementptr inbounds [4 x i16], [4 x i16]* %{{[0-9a-zA-Z_.]+}}, i64 0, i64 0 +// CHECK: getelementptr inbounds [4 x i16], ptr @_mm_shuffle_pi16.__permute_selectors, i64 0, i64 %{{[0-9a-zA-Z_.]+}} +// CHECK-LE: getelementptr inbounds [4 x i16], ptr %{{[0-9a-zA-Z_.]+}}, i64 0, i64 0 +// CHECK-BE: getelementptr inbounds [4 x i16], ptr %{{[0-9a-zA-Z_.]+}}, i64 0, i64 3 +// CHECK: getelementptr inbounds [4 x i16], ptr @_mm_shuffle_pi16.__permute_selectors, i64 0, i64 %{{[0-9a-zA-Z_.]+}} +// CHECK-LE: getelementptr inbounds [4 x i16], ptr %{{[0-9a-zA-Z_.]+}}, i64 0, i64 1 +// CHECK-BE: getelementptr inbounds [4 x i16], ptr %{{[0-9a-zA-Z_.]+}}, i64 0, i64 2 +// CHECK: getelementptr inbounds [4 x i16], ptr @_mm_shuffle_pi16.__permute_selectors, i64 0, i64 %{{[0-9a-zA-Z_.]+}} +// CHECK-LE: getelementptr inbounds [4 x i16], ptr %{{[0-9a-zA-Z_.]+}}, i64 0, i64 2 +// CHECK-BE: getelementptr inbounds [4 x i16], ptr %{{[0-9a-zA-Z_.]+}}, i64 0, i64 1 +// CHECK: getelementptr inbounds [4 x i16], ptr @_mm_shuffle_pi16.__permute_selectors, i64 0, i64 %{{[0-9a-zA-Z_.]+}} +// CHECK-LE: getelementptr inbounds [4 x i16], ptr %{{[0-9a-zA-Z_.]+}}, i64 0, i64 3 +// CHECK-BE: getelementptr inbounds [4 x i16], ptr %{{[0-9a-zA-Z_.]+}}, i64 0, i64 0 // CHECK: call <2 x i64> @vec_splats(unsigned long long) // CHECK: call <2 x i64> @vec_splats(unsigned long long) // CHECK: call <2 x i64> @vec_perm(unsigned long long vector[2], unsigned long long vector[2], unsigned char vector[16]) @@ -925,14 +923,14 @@ test_shuffle() { // CHECK: %[[SHR3:[0-9a-zA-Z_.]+]] = ashr i32 %{{[0-9a-zA-Z_.]+}}, 6 // CHECK: %[[AND4:[0-9a-zA-Z_.]+]] = and i32 %[[SHR3]], 3 // CHECK: sext i32 %[[AND4]] to i64 -// CHECK: getelementptr inbounds [4 x i32], [4 x i32]* @_mm_shuffle_ps.__permute_selectors, i64 0, i64 +// CHECK: getelementptr inbounds [4 x i32], ptr @_mm_shuffle_ps.__permute_selectors, i64 0, i64 // CHECK: insertelement <4 x i32> %{{[0-9a-zA-Z_.]+}}, i32 %{{[0-9a-zA-Z_.]+}}, i32 0 -// CHECK: getelementptr inbounds [4 x i32], [4 x i32]* @_mm_shuffle_ps.__permute_selectors, i64 0, i64 +// CHECK: getelementptr inbounds [4 x i32], ptr @_mm_shuffle_ps.__permute_selectors, i64 0, i64 // CHECK: insertelement <4 x i32> %{{[0-9a-zA-Z_.]+}}, i32 %{{[0-9a-zA-Z_.]+}}, i32 1 -// CHECK: getelementptr inbounds [4 x i32], [4 x i32]* @_mm_shuffle_ps.__permute_selectors, i64 0, i64 +// CHECK: getelementptr inbounds [4 x i32], ptr @_mm_shuffle_ps.__permute_selectors, i64 0, i64 // CHECK: %[[ADD:[0-9a-zA-Z_.]+]] = add i32 %{{[0-9a-zA-Z_.]+}}, 269488144 // CHECK: insertelement <4 x i32> %{{[0-9a-zA-Z_.]+}}, i32 %[[ADD]], i32 2 -// CHECK: getelementptr inbounds [4 x i32], [4 x i32]* @_mm_shuffle_ps.__permute_selectors, i64 0, i64 +// CHECK: getelementptr inbounds [4 x i32], ptr @_mm_shuffle_ps.__permute_selectors, i64 0, i64 // CHECK: %[[ADD2:[0-9a-zA-Z_.]+]] = add i32 %{{[0-9a-zA-Z_.]+}}, 269488144 // CHECK: insertelement <4 x i32> %{{[0-9a-zA-Z_.]+}}, i32 %[[ADD2]], i32 3 // CHECK: call <4 x float> @vec_perm(float vector[4], float vector[4], unsigned char vector[16]) @@ -970,14 +968,14 @@ test_store() { // CHECK-LABEL: @test_store // CHECK-LABEL: define available_externally void @_mm_store_ps -// CHECK: call void @vec_st(float vector[4], long, float vector[4]*)(<4 x float> noundef %{{[0-9a-zA-Z_.]+}}, i64 noundef 0, <4 x float>* noundef %{{[0-9a-zA-Z_.]+}}) +// CHECK: call void @vec_st(float vector[4], long, float vector[4]*)(<4 x float> noundef %{{[0-9a-zA-Z_.]+}}, i64 noundef 0, ptr noundef %{{[0-9a-zA-Z_.]+}}) // CHECK-LABEL: define available_externally void @_mm_store_ps1 // CHECK: call void @_mm_store1_ps // CHECK-LABEL: define available_externally void @_mm_store_ss // CHECK: %[[VAL:[0-9a-zA-Z_.]+]] = extractelement <4 x float> %{{[0-9a-zA-Z_.]+}}, i32 0 -// CHECK: store float %[[VAL]], float* %{{[0-9a-zA-Z_.]+}}, align 4 +// CHECK: store float %[[VAL]], ptr %{{[0-9a-zA-Z_.]+}}, align 4 // CHECK-LABEL: define available_externally void @_mm_store1_ps // CHECK: call <4 x float> @vec_splat(float vector[4], unsigned int)(<4 x float> noundef %{{[0-9a-zA-Z_.]+}}, i32 noundef zeroext 0) @@ -985,11 +983,11 @@ test_store() { // CHECK-LABEL: define available_externally void @_mm_storeh_pi // CHECK: %[[VAL:[0-9a-zA-Z_.]+]] = extractelement <2 x i64> %{{[0-9a-zA-Z_.]+}}, i32 1 -// CHECK: store i64 %[[VAL]], i64* %{{[0-9a-zA-Z_.]+}}, align 8 +// CHECK: store i64 %[[VAL]], ptr %{{[0-9a-zA-Z_.]+}}, align 8 // CHECK-LABEL: define available_externally void @_mm_storel_pi // CHECK: %[[VAL:[0-9a-zA-Z_.]+]] = extractelement <2 x i64> %{{[0-9a-zA-Z_.]+}}, i32 0 -// CHECK: store i64 %[[VAL]], i64* %{{[0-9a-zA-Z_.]+}}, align 8 +// CHECK: store i64 %[[VAL]], ptr %{{[0-9a-zA-Z_.]+}}, align 8 // CHECK-LABEL: define available_externally void @_mm_storer_ps // CHECK: call <4 x float> @vec_perm(float vector[4], float vector[4], unsigned char vector[16])(<4 x float> noundef %{{[0-9a-zA-Z_.]+}}, <4 x float> noundef %{{[0-9a-zA-Z_.]+}}, <16 x i8> noundef ) @@ -1004,10 +1002,10 @@ test_stream() { // CHECK-LABEL: @test_stream // CHECK-LABEL: define available_externally void @_mm_stream_pi -// CHECK: call void asm sideeffect "\09dcbtstt\090,$0", "b,~{memory}"(i64* %{{[0-9a-zA-Z_.]+}}) +// CHECK: call void asm sideeffect "\09dcbtstt\090,$0", "b,~{memory}"(ptr %{{[0-9a-zA-Z_.]+}}) // CHECK-LABEL: define available_externally void @_mm_stream_ps -// CHECK: call void asm sideeffect "\09dcbtstt\090,$0", "b,~{memory}"(float* %{{[0-9a-zA-Z_.]+}}) +// CHECK: call void asm sideeffect "\09dcbtstt\090,$0", "b,~{memory}"(ptr %{{[0-9a-zA-Z_.]+}}) // CHECK: call void @_mm_store_ps void __attribute__((noinline)) @@ -1095,8 +1093,8 @@ test_undefined() { // CHECK-LABEL: define available_externally <4 x float> @_mm_undefined_ps // CHECK: alloca <4 x float>, align 16 -// CHECK: load <4 x float>, <4 x float>* %[[ADDR:[0-9a-zA-Z_.]+]], align 16 -// CHECK: load <4 x float>, <4 x float>* %[[ADDR]], align 16 +// CHECK: load <4 x float>, ptr %[[ADDR:[0-9a-zA-Z_.]+]], align 16 +// CHECK: load <4 x float>, ptr %[[ADDR]], align 16 void __attribute__((noinline)) test_unpack() { diff --git a/clang/test/CodeGen/PowerPC/ppc32-dwarf.c b/clang/test/CodeGen/PowerPC/ppc32-dwarf.c index 80875ac0969bc4..8ef5f33b3199c3 100644 --- a/clang/test/CodeGen/PowerPC/ppc32-dwarf.c +++ b/clang/test/CodeGen/PowerPC/ppc32-dwarf.c @@ -1,5 +1,5 @@ -// RUN: %clang_cc1 -no-opaque-pointers -triple powerpc-unknown-aix -emit-llvm %s -o - | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -triple powerpc-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,PPC32 +// RUN: %clang_cc1 -triple powerpc-unknown-aix -emit-llvm %s -o - | FileCheck %s +// RUN: %clang_cc1 -triple powerpc-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,PPC32 static unsigned char dwarf_reg_size_table[1024]; int test(void) { @@ -9,118 +9,118 @@ int test(void) { } // CHECK-LABEL: define{{.*}} i32 @test() -// CHECK: store i8 4, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 0), align 1 -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 1), align 1 -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 2), align 1 -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 3), align 1 -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 4), align 1 -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 5), align 1 -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 6), align 1 -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 7), align 1 -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 8), align 1 -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 9), align 1 -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 10), align 1 -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 11), align 1 -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 12), align 1 -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 13), align 1 -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 14), align 1 -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 15), align 1 -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 16), align 1 -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 17), align 1 -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 18), align 1 -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 19), align 1 -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 20), align 1 -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 21), align 1 -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 22), align 1 -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 23), align 1 -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 24), align 1 -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 25), align 1 -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 26), align 1 -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 27), align 1 -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 28), align 1 -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 29), align 1 -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 30), align 1 -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 31), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 32), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 33), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 34), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 35), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 36), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 37), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 38), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 39), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 40), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 41), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 42), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 43), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 44), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 45), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 46), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 47), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 48), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 49), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 50), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 51), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 52), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 53), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 54), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 55), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 56), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 57), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 58), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 59), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 60), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 61), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 62), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 63), align 1 -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 64), align 1 -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 65), align 1 -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 66), align 1 -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 67), align 1 -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 68), align 1 -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 69), align 1 -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 70), align 1 -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 71), align 1 -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 72), align 1 -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 73), align 1 -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 74), align 1 -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 75), align 1 -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 76), align 1 -// CHECK-NEXT: store i8 16, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 77), align 1 -// CHECK-NEXT: store i8 16, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 78), align 1 -// CHECK-NEXT: store i8 16, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 79), align 1 -// CHECK-NEXT: store i8 16, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 80), align 1 -// CHECK-NEXT: store i8 16, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 81), align 1 -// CHECK-NEXT: store i8 16, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 82), align 1 -// CHECK-NEXT: store i8 16, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 83), align 1 -// CHECK-NEXT: store i8 16, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 84), align 1 -// CHECK-NEXT: store i8 16, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 85), align 1 -// CHECK-NEXT: store i8 16, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 86), align 1 -// CHECK-NEXT: store i8 16, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 87), align 1 -// CHECK-NEXT: store i8 16, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 88), align 1 -// CHECK-NEXT: store i8 16, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 89), align 1 -// CHECK-NEXT: store i8 16, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 90), align 1 -// CHECK-NEXT: store i8 16, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 91), align 1 -// CHECK-NEXT: store i8 16, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 92), align 1 -// CHECK-NEXT: store i8 16, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 93), align 1 -// CHECK-NEXT: store i8 16, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 94), align 1 -// CHECK-NEXT: store i8 16, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 95), align 1 -// CHECK-NEXT: store i8 16, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 96), align 1 -// CHECK-NEXT: store i8 16, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 97), align 1 -// CHECK-NEXT: store i8 16, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 98), align 1 -// CHECK-NEXT: store i8 16, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 99), align 1 -// CHECK-NEXT: store i8 16, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 100), align 1 -// CHECK-NEXT: store i8 16, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 101), align 1 -// CHECK-NEXT: store i8 16, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 102), align 1 -// CHECK-NEXT: store i8 16, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 103), align 1 -// CHECK-NEXT: store i8 16, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 104), align 1 -// CHECK-NEXT: store i8 16, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 105), align 1 -// CHECK-NEXT: store i8 16, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 106), align 1 -// CHECK-NEXT: store i8 16, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 107), align 1 -// CHECK-NEXT: store i8 16, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 108), align 1 -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 109), align 1 -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 110), align 1 -// PPC32-NEXT: store i8 4, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 111), align 1 -// PPC32-NEXT: store i8 4, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 112), align 1 -// PPC32-NEXT: store i8 4, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i32 0, i32 113), align 1 +// CHECK: store i8 4, ptr @dwarf_reg_size_table, align 1 +// CHECK-NEXT: store i8 4, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 1), align 1 +// CHECK-NEXT: store i8 4, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 2), align 1 +// CHECK-NEXT: store i8 4, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 3), align 1 +// CHECK-NEXT: store i8 4, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 4), align 1 +// CHECK-NEXT: store i8 4, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 5), align 1 +// CHECK-NEXT: store i8 4, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 6), align 1 +// CHECK-NEXT: store i8 4, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 7), align 1 +// CHECK-NEXT: store i8 4, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 8), align 1 +// CHECK-NEXT: store i8 4, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 9), align 1 +// CHECK-NEXT: store i8 4, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 10), align 1 +// CHECK-NEXT: store i8 4, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 11), align 1 +// CHECK-NEXT: store i8 4, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 12), align 1 +// CHECK-NEXT: store i8 4, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 13), align 1 +// CHECK-NEXT: store i8 4, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 14), align 1 +// CHECK-NEXT: store i8 4, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 15), align 1 +// CHECK-NEXT: store i8 4, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 16), align 1 +// CHECK-NEXT: store i8 4, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 17), align 1 +// CHECK-NEXT: store i8 4, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 18), align 1 +// CHECK-NEXT: store i8 4, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 19), align 1 +// CHECK-NEXT: store i8 4, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 20), align 1 +// CHECK-NEXT: store i8 4, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 21), align 1 +// CHECK-NEXT: store i8 4, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 22), align 1 +// CHECK-NEXT: store i8 4, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 23), align 1 +// CHECK-NEXT: store i8 4, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 24), align 1 +// CHECK-NEXT: store i8 4, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 25), align 1 +// CHECK-NEXT: store i8 4, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 26), align 1 +// CHECK-NEXT: store i8 4, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 27), align 1 +// CHECK-NEXT: store i8 4, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 28), align 1 +// CHECK-NEXT: store i8 4, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 29), align 1 +// CHECK-NEXT: store i8 4, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 30), align 1 +// CHECK-NEXT: store i8 4, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 31), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 32), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 33), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 34), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 35), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 36), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 37), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 38), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 39), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 40), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 41), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 42), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 43), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 44), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 45), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 46), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 47), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 48), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 49), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 50), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 51), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 52), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 53), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 54), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 55), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 56), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 57), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 58), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 59), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 60), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 61), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 62), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 63), align 1 +// CHECK-NEXT: store i8 4, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 64), align 1 +// CHECK-NEXT: store i8 4, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 65), align 1 +// CHECK-NEXT: store i8 4, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 66), align 1 +// CHECK-NEXT: store i8 4, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 67), align 1 +// CHECK-NEXT: store i8 4, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 68), align 1 +// CHECK-NEXT: store i8 4, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 69), align 1 +// CHECK-NEXT: store i8 4, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 70), align 1 +// CHECK-NEXT: store i8 4, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 71), align 1 +// CHECK-NEXT: store i8 4, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 72), align 1 +// CHECK-NEXT: store i8 4, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 73), align 1 +// CHECK-NEXT: store i8 4, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 74), align 1 +// CHECK-NEXT: store i8 4, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 75), align 1 +// CHECK-NEXT: store i8 4, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 76), align 1 +// CHECK-NEXT: store i8 16, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 77), align 1 +// CHECK-NEXT: store i8 16, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 78), align 1 +// CHECK-NEXT: store i8 16, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 79), align 1 +// CHECK-NEXT: store i8 16, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 80), align 1 +// CHECK-NEXT: store i8 16, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 81), align 1 +// CHECK-NEXT: store i8 16, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 82), align 1 +// CHECK-NEXT: store i8 16, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 83), align 1 +// CHECK-NEXT: store i8 16, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 84), align 1 +// CHECK-NEXT: store i8 16, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 85), align 1 +// CHECK-NEXT: store i8 16, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 86), align 1 +// CHECK-NEXT: store i8 16, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 87), align 1 +// CHECK-NEXT: store i8 16, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 88), align 1 +// CHECK-NEXT: store i8 16, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 89), align 1 +// CHECK-NEXT: store i8 16, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 90), align 1 +// CHECK-NEXT: store i8 16, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 91), align 1 +// CHECK-NEXT: store i8 16, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 92), align 1 +// CHECK-NEXT: store i8 16, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 93), align 1 +// CHECK-NEXT: store i8 16, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 94), align 1 +// CHECK-NEXT: store i8 16, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 95), align 1 +// CHECK-NEXT: store i8 16, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 96), align 1 +// CHECK-NEXT: store i8 16, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 97), align 1 +// CHECK-NEXT: store i8 16, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 98), align 1 +// CHECK-NEXT: store i8 16, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 99), align 1 +// CHECK-NEXT: store i8 16, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 100), align 1 +// CHECK-NEXT: store i8 16, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 101), align 1 +// CHECK-NEXT: store i8 16, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 102), align 1 +// CHECK-NEXT: store i8 16, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 103), align 1 +// CHECK-NEXT: store i8 16, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 104), align 1 +// CHECK-NEXT: store i8 16, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 105), align 1 +// CHECK-NEXT: store i8 16, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 106), align 1 +// CHECK-NEXT: store i8 16, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 107), align 1 +// CHECK-NEXT: store i8 16, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 108), align 1 +// CHECK-NEXT: store i8 4, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 109), align 1 +// CHECK-NEXT: store i8 4, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 110), align 1 +// PPC32-NEXT: store i8 4, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 111), align 1 +// PPC32-NEXT: store i8 4, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 112), align 1 +// PPC32-NEXT: store i8 4, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 113), align 1 // PPC32-NEXT: ret i32 1 diff --git a/clang/test/CodeGen/PowerPC/ppc64-dwarf.c b/clang/test/CodeGen/PowerPC/ppc64-dwarf.c index cdb0c2cc85345a..30db8b18c9c92f 100644 --- a/clang/test/CodeGen/PowerPC/ppc64-dwarf.c +++ b/clang/test/CodeGen/PowerPC/ppc64-dwarf.c @@ -1,5 +1,5 @@ -// RUN: %clang_cc1 -no-opaque-pointers -triple powerpc64-unknown-aix -emit-llvm %s -o - | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -triple powerpc64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,PPC64 +// RUN: %clang_cc1 -triple powerpc64-unknown-aix -emit-llvm %s -o - | FileCheck %s +// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,PPC64 static unsigned char dwarf_reg_size_table[1024]; int test(void) { @@ -9,121 +9,121 @@ int test(void) { } // CHECK-LABEL: define{{.*}} signext i32 @test() -// CHECK: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 0), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 1), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 2), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 3), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 4), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 5), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 6), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 7), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 8), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 9), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 10), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 11), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 12), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 13), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 14), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 15), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 16), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 17), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 18), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 19), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 20), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 21), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 22), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 23), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 24), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 25), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 26), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 27), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 28), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 29), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 30), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 31), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 32), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 33), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 34), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 35), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 36), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 37), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 38), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 39), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 40), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 41), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 42), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 43), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 44), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 45), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 46), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 47), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 48), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 49), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 50), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 51), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 52), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 53), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 54), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 55), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 56), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 57), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 58), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 59), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 60), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 61), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 62), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 63), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 64), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 65), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 66), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 67), align 1 -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 68), align 1 -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 69), align 1 -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 70), align 1 -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 71), align 1 -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 72), align 1 -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 73), align 1 -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 74), align 1 -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 75), align 1 -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 76), align 1 -// CHECK-NEXT: store i8 16, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 77), align 1 -// CHECK-NEXT: store i8 16, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 78), align 1 -// CHECK-NEXT: store i8 16, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 79), align 1 -// CHECK-NEXT: store i8 16, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 80), align 1 -// CHECK-NEXT: store i8 16, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 81), align 1 -// CHECK-NEXT: store i8 16, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 82), align 1 -// CHECK-NEXT: store i8 16, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 83), align 1 -// CHECK-NEXT: store i8 16, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 84), align 1 -// CHECK-NEXT: store i8 16, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 85), align 1 -// CHECK-NEXT: store i8 16, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 86), align 1 -// CHECK-NEXT: store i8 16, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 87), align 1 -// CHECK-NEXT: store i8 16, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 88), align 1 -// CHECK-NEXT: store i8 16, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 89), align 1 -// CHECK-NEXT: store i8 16, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 90), align 1 -// CHECK-NEXT: store i8 16, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 91), align 1 -// CHECK-NEXT: store i8 16, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 92), align 1 -// CHECK-NEXT: store i8 16, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 93), align 1 -// CHECK-NEXT: store i8 16, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 94), align 1 -// CHECK-NEXT: store i8 16, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 95), align 1 -// CHECK-NEXT: store i8 16, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 96), align 1 -// CHECK-NEXT: store i8 16, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 97), align 1 -// CHECK-NEXT: store i8 16, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 98), align 1 -// CHECK-NEXT: store i8 16, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 99), align 1 -// CHECK-NEXT: store i8 16, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 100), align 1 -// CHECK-NEXT: store i8 16, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 101), align 1 -// CHECK-NEXT: store i8 16, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 102), align 1 -// CHECK-NEXT: store i8 16, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 103), align 1 -// CHECK-NEXT: store i8 16, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 104), align 1 -// CHECK-NEXT: store i8 16, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 105), align 1 -// CHECK-NEXT: store i8 16, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 106), align 1 -// CHECK-NEXT: store i8 16, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 107), align 1 -// CHECK-NEXT: store i8 16, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 108), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 109), align 1 -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 110), align 1 -// PPC64-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 111), align 1 -// PPC64-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 112), align 1 -// PPC64-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 113), align 1 -// PPC64-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 114), align 1 -// PPC64-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 115), align 1 -// PPC64-NEXT: store i8 8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @dwarf_reg_size_table, i64 0, i64 116), align 1 +// CHECK: store i8 8, ptr @dwarf_reg_size_table, align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 1), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 2), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 3), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 4), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 5), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 6), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 7), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 8), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 9), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 10), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 11), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 12), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 13), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 14), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 15), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 16), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 17), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 18), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 19), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 20), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 21), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 22), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 23), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 24), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 25), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 26), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 27), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 28), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 29), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 30), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 31), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 32), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 33), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 34), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 35), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 36), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 37), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 38), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 39), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 40), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 41), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 42), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 43), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 44), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 45), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 46), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 47), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 48), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 49), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 50), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 51), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 52), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 53), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 54), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 55), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 56), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 57), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 58), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 59), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 60), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 61), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 62), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 63), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 64), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 65), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 66), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 67), align 1 +// CHECK-NEXT: store i8 4, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 68), align 1 +// CHECK-NEXT: store i8 4, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 69), align 1 +// CHECK-NEXT: store i8 4, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 70), align 1 +// CHECK-NEXT: store i8 4, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 71), align 1 +// CHECK-NEXT: store i8 4, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 72), align 1 +// CHECK-NEXT: store i8 4, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 73), align 1 +// CHECK-NEXT: store i8 4, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 74), align 1 +// CHECK-NEXT: store i8 4, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 75), align 1 +// CHECK-NEXT: store i8 4, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 76), align 1 +// CHECK-NEXT: store i8 16, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 77), align 1 +// CHECK-NEXT: store i8 16, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 78), align 1 +// CHECK-NEXT: store i8 16, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 79), align 1 +// CHECK-NEXT: store i8 16, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 80), align 1 +// CHECK-NEXT: store i8 16, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 81), align 1 +// CHECK-NEXT: store i8 16, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 82), align 1 +// CHECK-NEXT: store i8 16, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 83), align 1 +// CHECK-NEXT: store i8 16, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 84), align 1 +// CHECK-NEXT: store i8 16, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 85), align 1 +// CHECK-NEXT: store i8 16, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 86), align 1 +// CHECK-NEXT: store i8 16, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 87), align 1 +// CHECK-NEXT: store i8 16, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 88), align 1 +// CHECK-NEXT: store i8 16, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 89), align 1 +// CHECK-NEXT: store i8 16, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 90), align 1 +// CHECK-NEXT: store i8 16, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 91), align 1 +// CHECK-NEXT: store i8 16, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 92), align 1 +// CHECK-NEXT: store i8 16, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 93), align 1 +// CHECK-NEXT: store i8 16, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 94), align 1 +// CHECK-NEXT: store i8 16, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 95), align 1 +// CHECK-NEXT: store i8 16, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 96), align 1 +// CHECK-NEXT: store i8 16, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 97), align 1 +// CHECK-NEXT: store i8 16, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 98), align 1 +// CHECK-NEXT: store i8 16, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 99), align 1 +// CHECK-NEXT: store i8 16, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 100), align 1 +// CHECK-NEXT: store i8 16, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 101), align 1 +// CHECK-NEXT: store i8 16, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 102), align 1 +// CHECK-NEXT: store i8 16, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 103), align 1 +// CHECK-NEXT: store i8 16, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 104), align 1 +// CHECK-NEXT: store i8 16, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 105), align 1 +// CHECK-NEXT: store i8 16, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 106), align 1 +// CHECK-NEXT: store i8 16, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 107), align 1 +// CHECK-NEXT: store i8 16, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 108), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 109), align 1 +// CHECK-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 110), align 1 +// PPC64-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 111), align 1 +// PPC64-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 112), align 1 +// PPC64-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 113), align 1 +// PPC64-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 114), align 1 +// PPC64-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 115), align 1 +// PPC64-NEXT: store i8 8, ptr getelementptr inbounds (i8, ptr @dwarf_reg_size_table, i32 116), align 1 // CHECK-NEXT: ret i32 1 diff --git a/clang/test/CodeGen/PowerPC/ppc64-soft-float.c b/clang/test/CodeGen/PowerPC/ppc64-soft-float.c index a6450098eaa931..c2e887ef7ab6e2 100644 --- a/clang/test/CodeGen/PowerPC/ppc64-soft-float.c +++ b/clang/test/CodeGen/PowerPC/ppc64-soft-float.c @@ -1,5 +1,5 @@ -// RUN: %clang_cc1 -no-opaque-pointers -msoft-float -mfloat-abi soft -triple powerpc64le-unknown-linux-gnu -emit-llvm -o - %s | FileCheck -check-prefix=CHECK -check-prefix=CHECK-LE %s -// RUN: %clang_cc1 -no-opaque-pointers -msoft-float -mfloat-abi soft -triple powerpc64-unknown-linux-gnu -emit-llvm -o - %s | FileCheck -check-prefix=CHECK -check-prefix=CHECK-BE %s +// RUN: %clang_cc1 -msoft-float -mfloat-abi soft -triple powerpc64le-unknown-linux-gnu -emit-llvm -o - %s | FileCheck -check-prefix=CHECK -check-prefix=CHECK-LE %s +// RUN: %clang_cc1 -msoft-float -mfloat-abi soft -triple powerpc64-unknown-linux-gnu -emit-llvm -o - %s | FileCheck -check-prefix=CHECK -check-prefix=CHECK-BE %s // Test float returns and params. @@ -30,142 +30,137 @@ struct fabc { float a; float b; float c; }; struct f2a2b { float a[2]; float b[2]; }; // CHECK-LE: define{{.*}} i32 @func_f1(float inreg %x.coerce) -// CHECK-BE: define{{.*}} void @func_f1(%struct.f1* noalias sret(%struct.f1) align 4 %agg.result, float inreg %x.coerce) +// CHECK-BE: define{{.*}} void @func_f1(ptr noalias sret(%struct.f1) align 4 %agg.result, float inreg %x.coerce) struct f1 func_f1(struct f1 x) { return x; } // CHECK-LE: define{{.*}} i64 @func_f2(i64 %x.coerce) -// CHECK-BE: define{{.*}} void @func_f2(%struct.f2* noalias sret(%struct.f2) align 4 %agg.result, i64 %x.coerce) +// CHECK-BE: define{{.*}} void @func_f2(ptr noalias sret(%struct.f2) align 4 %agg.result, i64 %x.coerce) struct f2 func_f2(struct f2 x) { return x; } // CHECK-LE: define{{.*}} { i64, i64 } @func_f3([2 x i64] %x.coerce) -// CHECK-BE: define{{.*}} void @func_f3(%struct.f3* noalias sret(%struct.f3) align 4 %agg.result, [2 x i64] %x.coerce) +// CHECK-BE: define{{.*}} void @func_f3(ptr noalias sret(%struct.f3) align 4 %agg.result, [2 x i64] %x.coerce) struct f3 func_f3(struct f3 x) { return x; } // CHECK-LE: define{{.*}} { i64, i64 } @func_f4([2 x i64] %x.coerce) -// CHECK-BE: define{{.*}} void @func_f4(%struct.f4* noalias sret(%struct.f4) align 4 %agg.result, [2 x i64] %x.coerce) +// CHECK-BE: define{{.*}} void @func_f4(ptr noalias sret(%struct.f4) align 4 %agg.result, [2 x i64] %x.coerce) struct f4 func_f4(struct f4 x) { return x; } -// CHECK: define{{.*}} void @func_f5(%struct.f5* noalias sret(%struct.f5) align 4 %agg.result, [3 x i64] %x.coerce) +// CHECK: define{{.*}} void @func_f5(ptr noalias sret(%struct.f5) align 4 %agg.result, [3 x i64] %x.coerce) struct f5 func_f5(struct f5 x) { return x; } -// CHECK: define{{.*}} void @func_f6(%struct.f6* noalias sret(%struct.f6) align 4 %agg.result, [3 x i64] %x.coerce) +// CHECK: define{{.*}} void @func_f6(ptr noalias sret(%struct.f6) align 4 %agg.result, [3 x i64] %x.coerce) struct f6 func_f6(struct f6 x) { return x; } -// CHECK: define{{.*}} void @func_f7(%struct.f7* noalias sret(%struct.f7) align 4 %agg.result, [4 x i64] %x.coerce) +// CHECK: define{{.*}} void @func_f7(ptr noalias sret(%struct.f7) align 4 %agg.result, [4 x i64] %x.coerce) struct f7 func_f7(struct f7 x) { return x; } -// CHECK: define{{.*}} void @func_f8(%struct.f8* noalias sret(%struct.f8) align 4 %agg.result, [4 x i64] %x.coerce) +// CHECK: define{{.*}} void @func_f8(ptr noalias sret(%struct.f8) align 4 %agg.result, [4 x i64] %x.coerce) struct f8 func_f8(struct f8 x) { return x; } -// CHECK: define{{.*}} void @func_f9(%struct.f9* noalias sret(%struct.f9) align 4 %agg.result, [5 x i64] %x.coerce) +// CHECK: define{{.*}} void @func_f9(ptr noalias sret(%struct.f9) align 4 %agg.result, [5 x i64] %x.coerce) struct f9 func_f9(struct f9 x) { return x; } // CHECK-LE: define{{.*}} i64 @func_fab(i64 %x.coerce) -// CHECK-BE: define{{.*}} void @func_fab(%struct.fab* noalias sret(%struct.fab) align 4 %agg.result, i64 %x.coerce) +// CHECK-BE: define{{.*}} void @func_fab(ptr noalias sret(%struct.fab) align 4 %agg.result, i64 %x.coerce) struct fab func_fab(struct fab x) { return x; } // CHECK-LE: define{{.*}} { i64, i64 } @func_fabc([2 x i64] %x.coerce) -// CHECK-BE: define{{.*}} void @func_fabc(%struct.fabc* noalias sret(%struct.fabc) align 4 %agg.result, [2 x i64] %x.coerce) +// CHECK-BE: define{{.*}} void @func_fabc(ptr noalias sret(%struct.fabc) align 4 %agg.result, [2 x i64] %x.coerce) struct fabc func_fabc(struct fabc x) { return x; } // CHECK-LE: define{{.*}} { i64, i64 } @func_f2a2b([2 x i64] %x.coerce) -// CHECK-BE: define{{.*}} void @func_f2a2b(%struct.f2a2b* noalias sret(%struct.f2a2b) align 4 %agg.result, [2 x i64] %x.coerce) +// CHECK-BE: define{{.*}} void @func_f2a2b(ptr noalias sret(%struct.f2a2b) align 4 %agg.result, [2 x i64] %x.coerce) struct f2a2b func_f2a2b(struct f2a2b x) { return x; } // CHECK-LABEL: @call_f1 // CHECK-BE: %[[TMP0:[^ ]+]] = alloca %struct.f1, align 4 -// CHECK: %[[TMP:[^ ]+]] = load float, float* getelementptr inbounds (%struct.f1, %struct.f1* @global_f1, i32 0, i32 0, i32 0), align 4 +// CHECK: %[[TMP:[^ ]+]] = load float, ptr @global_f1, align 4 // CHECK-LE: call i32 @func_f1(float inreg %[[TMP]]) -// CHECK-BE: call void @func_f1(%struct.f1* sret(%struct.f1) align 4 %[[TMP0]], float inreg %[[TMP]]) +// CHECK-BE: call void @func_f1(ptr sret(%struct.f1) align 4 %[[TMP0]], float inreg %[[TMP]]) struct f1 global_f1; void call_f1(void) { global_f1 = func_f1(global_f1); } // CHECK-LABEL: @call_f2 // CHECK-BE: %[[TMP0:[^ ]+]] = alloca %struct.f2, align 4 -// CHECK: %[[TMP:[^ ]+]] = load i64, i64* bitcast (%struct.f2* @global_f2 to i64*), align 4 +// CHECK: %[[TMP:[^ ]+]] = load i64, ptr @global_f2, align 4 // CHECK-LE: call i64 @func_f2(i64 %[[TMP]]) -// CHECK-BE: call void @func_f2(%struct.f2* sret(%struct.f2) align 4 %[[TMP0]], i64 %[[TMP]]) +// CHECK-BE: call void @func_f2(ptr sret(%struct.f2) align 4 %[[TMP0]], i64 %[[TMP]]) struct f2 global_f2; void call_f2(void) { global_f2 = func_f2(global_f2); } // CHECK-LABEL: @call_f3 // CHECK-BE: %[[TMP0:[^ ]+]] = alloca %struct.f3, align 4 // CHECK: %[[TMP1:[^ ]+]] = alloca [2 x i64] -// CHECK: %[[TMP2:[^ ]+]] = bitcast [2 x i64]* %[[TMP1]] to i8* -// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 %[[TMP2]], i8* align 4 bitcast (%struct.f3* @global_f3 to i8*), i64 12, i1 false) -// CHECK: %[[TMP3:[^ ]+]] = load [2 x i64], [2 x i64]* %[[TMP1]] +// CHECK: call void @llvm.memcpy.p0.p0.i64(ptr align 8 %[[TMP1]], ptr align 4 @global_f3, i64 12, i1 false) +// CHECK: %[[TMP3:[^ ]+]] = load [2 x i64], ptr %[[TMP1]] // CHECK-LE: call { i64, i64 } @func_f3([2 x i64] %[[TMP3]]) -// CHECK-BE: call void @func_f3(%struct.f3* sret(%struct.f3) align 4 %[[TMP0]], [2 x i64] %[[TMP3]]) +// CHECK-BE: call void @func_f3(ptr sret(%struct.f3) align 4 %[[TMP0]], [2 x i64] %[[TMP3]]) struct f3 global_f3; void call_f3(void) { global_f3 = func_f3(global_f3); } // CHECK-LABEL: @call_f4 // CHECK-BE: %[[TMP0:[^ ]+]] = alloca %struct.f4, align 4 -// CHECK: %[[TMP:[^ ]+]] = load [2 x i64], [2 x i64]* bitcast (%struct.f4* @global_f4 to [2 x i64]*), align 4 +// CHECK: %[[TMP:[^ ]+]] = load [2 x i64], ptr @global_f4, align 4 // CHECK-LE: call { i64, i64 } @func_f4([2 x i64] %[[TMP]]) -// CHECK-BE: call void @func_f4(%struct.f4* sret(%struct.f4) align 4 %[[TMP0]], [2 x i64] %[[TMP]]) +// CHECK-BE: call void @func_f4(ptr sret(%struct.f4) align 4 %[[TMP0]], [2 x i64] %[[TMP]]) struct f4 global_f4; void call_f4(void) { global_f4 = func_f4(global_f4); } // CHECK-LABEL: @call_f5 // CHECK: %[[TMP0:[^ ]+]] = alloca %struct.f5, align 4 // CHECK: %[[TMP1:[^ ]+]] = alloca [3 x i64] -// CHECK: %[[TMP2:[^ ]+]] = bitcast [3 x i64]* %[[TMP1]] to i8* -// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 %[[TMP2]], i8* align 4 bitcast (%struct.f5* @global_f5 to i8*), i64 20, i1 false) -// CHECK: %[[TMP3:[^ ]+]] = load [3 x i64], [3 x i64]* %[[TMP1]] -// CHECK: call void @func_f5(%struct.f5* sret(%struct.f5) align 4 %[[TMP0]], [3 x i64] %[[TMP3]]) +// CHECK: call void @llvm.memcpy.p0.p0.i64(ptr align 8 %[[TMP1]], ptr align 4 @global_f5, i64 20, i1 false) +// CHECK: %[[TMP3:[^ ]+]] = load [3 x i64], ptr %[[TMP1]] +// CHECK: call void @func_f5(ptr sret(%struct.f5) align 4 %[[TMP0]], [3 x i64] %[[TMP3]]) struct f5 global_f5; void call_f5(void) { global_f5 = func_f5(global_f5); } // CHECK-LABEL: @call_f6 // CHECK: %[[TMP0:[^ ]+]] = alloca %struct.f6, align 4 -// CHECK: %[[TMP:[^ ]+]] = load [3 x i64], [3 x i64]* bitcast (%struct.f6* @global_f6 to [3 x i64]*), align 4 -// CHECK: call void @func_f6(%struct.f6* sret(%struct.f6) align 4 %[[TMP0]], [3 x i64] %[[TMP]]) +// CHECK: %[[TMP:[^ ]+]] = load [3 x i64], ptr @global_f6, align 4 +// CHECK: call void @func_f6(ptr sret(%struct.f6) align 4 %[[TMP0]], [3 x i64] %[[TMP]]) struct f6 global_f6; void call_f6(void) { global_f6 = func_f6(global_f6); } // CHECK-LABEL: @call_f7 // CHECK: %[[TMP0:[^ ]+]] = alloca %struct.f7, align 4 // CHECK: %[[TMP1:[^ ]+]] = alloca [4 x i64], align 8 -// CHECK: %[[TMP2:[^ ]+]] = bitcast [4 x i64]* %[[TMP1]] to i8* -// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 %[[TMP2]], i8* align 4 bitcast (%struct.f7* @global_f7 to i8*), i64 28, i1 false) -// CHECK: %[[TMP3:[^ ]+]] = load [4 x i64], [4 x i64]* %[[TMP1]], align 8 -// CHECK: call void @func_f7(%struct.f7* sret(%struct.f7) align 4 %[[TMP0]], [4 x i64] %[[TMP3]]) +// CHECK: call void @llvm.memcpy.p0.p0.i64(ptr align 8 %[[TMP1]], ptr align 4 @global_f7, i64 28, i1 false) +// CHECK: %[[TMP3:[^ ]+]] = load [4 x i64], ptr %[[TMP1]], align 8 +// CHECK: call void @func_f7(ptr sret(%struct.f7) align 4 %[[TMP0]], [4 x i64] %[[TMP3]]) struct f7 global_f7; void call_f7(void) { global_f7 = func_f7(global_f7); } // CHECK-LABEL: @call_f8 // CHECK: %[[TMP0:[^ ]+]] = alloca %struct.f8, align 4 -// CHECK: %[[TMP:[^ ]+]] = load [4 x i64], [4 x i64]* bitcast (%struct.f8* @global_f8 to [4 x i64]*), align 4 -// CHECK: call void @func_f8(%struct.f8* sret(%struct.f8) align 4 %[[TMP0]], [4 x i64] %[[TMP]]) +// CHECK: %[[TMP:[^ ]+]] = load [4 x i64], ptr @global_f8, align 4 +// CHECK: call void @func_f8(ptr sret(%struct.f8) align 4 %[[TMP0]], [4 x i64] %[[TMP]]) struct f8 global_f8; void call_f8(void) { global_f8 = func_f8(global_f8); } // CHECK-LABEL: @call_f9 // CHECK: %[[TMP1:[^ ]+]] = alloca [5 x i64] -// CHECK: %[[TMP2:[^ ]+]] = bitcast [5 x i64]* %[[TMP1]] to i8* -// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 %[[TMP2]], i8* align 4 bitcast (%struct.f9* @global_f9 to i8*), i64 36, i1 false) -// CHECK: %[[TMP3:[^ ]+]] = load [5 x i64], [5 x i64]* %[[TMP1]] -// CHECK: call void @func_f9(%struct.f9* sret(%struct.f9) align 4 %{{[^ ]+}}, [5 x i64] %[[TMP3]]) +// CHECK: call void @llvm.memcpy.p0.p0.i64(ptr align 8 %[[TMP1]], ptr align 4 @global_f9, i64 36, i1 false) +// CHECK: %[[TMP3:[^ ]+]] = load [5 x i64], ptr %[[TMP1]] +// CHECK: call void @func_f9(ptr sret(%struct.f9) align 4 %{{[^ ]+}}, [5 x i64] %[[TMP3]]) struct f9 global_f9; void call_f9(void) { global_f9 = func_f9(global_f9); } // CHECK-LABEL: @call_fab // CHECK: %[[TMP0:[^ ]+]] = alloca %struct.fab, align 4 -// CHECK: %[[TMP:[^ ]+]] = load i64, i64* bitcast (%struct.fab* @global_fab to i64*), align 4 +// CHECK: %[[TMP:[^ ]+]] = load i64, ptr @global_fab, align 4 // CHECK-LE: %call = call i64 @func_fab(i64 %[[TMP]]) -// CHECK-BE: call void @func_fab(%struct.fab* sret(%struct.fab) align 4 %[[TMP0]], i64 %[[TMP]]) +// CHECK-BE: call void @func_fab(ptr sret(%struct.fab) align 4 %[[TMP0]], i64 %[[TMP]]) struct fab global_fab; void call_fab(void) { global_fab = func_fab(global_fab); } // CHECK-LABEL: @call_fabc // CHECK-BE: %[[TMPX:[^ ]+]] = alloca %struct.fabc, align 4 // CHECK: %[[TMP0:[^ ]+]] = alloca [2 x i64], align 8 -// CHECK: %[[TMP2:[^ ]+]] = bitcast [2 x i64]* %[[TMP0]] to i8* -// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 %[[TMP2]], i8* align 4 bitcast (%struct.fabc* @global_fabc to i8*), i64 12, i1 false) -// CHECK: %[[TMP3:[^ ]+]] = load [2 x i64], [2 x i64]* %[[TMP0]], align 8 +// CHECK: call void @llvm.memcpy.p0.p0.i64(ptr align 8 %[[TMP0]], ptr align 4 @global_fabc, i64 12, i1 false) +// CHECK: %[[TMP3:[^ ]+]] = load [2 x i64], ptr %[[TMP0]], align 8 // CHECK-LE: %call = call { i64, i64 } @func_fabc([2 x i64] %[[TMP3]]) -// CHECK-BE: call void @func_fabc(%struct.fabc* sret(%struct.fabc) align 4 %[[TMPX]], [2 x i64] %[[TMP3]]) +// CHECK-BE: call void @func_fabc(ptr sret(%struct.fabc) align 4 %[[TMPX]], [2 x i64] %[[TMP3]]) struct fabc global_fabc; void call_fabc(void) { global_fabc = func_fabc(global_fabc); } diff --git a/clang/test/CodeGen/PowerPC/ppc64le-aggregates.c b/clang/test/CodeGen/PowerPC/ppc64le-aggregates.c index d3fcf938ffa53f..42b179217dd2ec 100644 --- a/clang/test/CodeGen/PowerPC/ppc64le-aggregates.c +++ b/clang/test/CodeGen/PowerPC/ppc64le-aggregates.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -no-opaque-pointers -target-feature +altivec -triple powerpc64le-unknown-linux-gnu -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -target-feature +altivec -triple powerpc64le-unknown-linux-gnu -emit-llvm -o - %s | FileCheck %s // Test homogeneous float aggregate passing and returning. @@ -41,7 +41,7 @@ struct f7 func_f7(struct f7 x) { return x; } // CHECK: define{{.*}} [8 x float] @func_f8([8 x float] %x.coerce) struct f8 func_f8(struct f8 x) { return x; } -// CHECK: define{{.*}} void @func_f9(%struct.f9* noalias sret(%struct.f9) align 4 %agg.result, [5 x i64] %x.coerce) +// CHECK: define{{.*}} void @func_f9(ptr noalias sret(%struct.f9) align 4 %agg.result, [5 x i64] %x.coerce) struct f9 func_f9(struct f9 x) { return x; } // CHECK: define{{.*}} [2 x float] @func_fab([2 x float] %x.coerce) @@ -54,70 +54,69 @@ struct fabc func_fabc(struct fabc x) { return x; } struct f2a2b func_f2a2b(struct f2a2b x) { return x; } // CHECK-LABEL: @call_f1 -// CHECK: %[[TMP:[^ ]+]] = load float, float* getelementptr inbounds (%struct.f1, %struct.f1* @global_f1, i32 0, i32 0, i32 0), align 4 +// CHECK: %[[TMP:[^ ]+]] = load float, ptr @global_f1, align 4 // CHECK: call [1 x float] @func_f1(float inreg %[[TMP]]) struct f1 global_f1; void call_f1(void) { global_f1 = func_f1(global_f1); } // CHECK-LABEL: @call_f2 -// CHECK: %[[TMP:[^ ]+]] = load [2 x float], [2 x float]* getelementptr inbounds (%struct.f2, %struct.f2* @global_f2, i32 0, i32 0), align 4 +// CHECK: %[[TMP:[^ ]+]] = load [2 x float], ptr @global_f2, align 4 // CHECK: call [2 x float] @func_f2([2 x float] %[[TMP]]) struct f2 global_f2; void call_f2(void) { global_f2 = func_f2(global_f2); } // CHECK-LABEL: @call_f3 -// CHECK: %[[TMP:[^ ]+]] = load [3 x float], [3 x float]* getelementptr inbounds (%struct.f3, %struct.f3* @global_f3, i32 0, i32 0), align 4 +// CHECK: %[[TMP:[^ ]+]] = load [3 x float], ptr @global_f3, align 4 // CHECK: call [3 x float] @func_f3([3 x float] %[[TMP]]) struct f3 global_f3; void call_f3(void) { global_f3 = func_f3(global_f3); } // CHECK-LABEL: @call_f4 -// CHECK: %[[TMP:[^ ]+]] = load [4 x float], [4 x float]* getelementptr inbounds (%struct.f4, %struct.f4* @global_f4, i32 0, i32 0), align 4 +// CHECK: %[[TMP:[^ ]+]] = load [4 x float], ptr @global_f4, align 4 // CHECK: call [4 x float] @func_f4([4 x float] %[[TMP]]) struct f4 global_f4; void call_f4(void) { global_f4 = func_f4(global_f4); } // CHECK-LABEL: @call_f5 -// CHECK: %[[TMP:[^ ]+]] = load [5 x float], [5 x float]* getelementptr inbounds (%struct.f5, %struct.f5* @global_f5, i32 0, i32 0), align 4 +// CHECK: %[[TMP:[^ ]+]] = load [5 x float], ptr @global_f5, align 4 // CHECK: call [5 x float] @func_f5([5 x float] %[[TMP]]) struct f5 global_f5; void call_f5(void) { global_f5 = func_f5(global_f5); } // CHECK-LABEL: @call_f6 -// CHECK: %[[TMP:[^ ]+]] = load [6 x float], [6 x float]* getelementptr inbounds (%struct.f6, %struct.f6* @global_f6, i32 0, i32 0), align 4 +// CHECK: %[[TMP:[^ ]+]] = load [6 x float], ptr @global_f6, align 4 // CHECK: call [6 x float] @func_f6([6 x float] %[[TMP]]) struct f6 global_f6; void call_f6(void) { global_f6 = func_f6(global_f6); } // CHECK-LABEL: @call_f7 -// CHECK: %[[TMP:[^ ]+]] = load [7 x float], [7 x float]* getelementptr inbounds (%struct.f7, %struct.f7* @global_f7, i32 0, i32 0), align 4 +// CHECK: %[[TMP:[^ ]+]] = load [7 x float], ptr @global_f7, align 4 // CHECK: call [7 x float] @func_f7([7 x float] %[[TMP]]) struct f7 global_f7; void call_f7(void) { global_f7 = func_f7(global_f7); } // CHECK-LABEL: @call_f8 -// CHECK: %[[TMP:[^ ]+]] = load [8 x float], [8 x float]* getelementptr inbounds (%struct.f8, %struct.f8* @global_f8, i32 0, i32 0), align 4 +// CHECK: %[[TMP:[^ ]+]] = load [8 x float], ptr @global_f8, align 4 // CHECK: call [8 x float] @func_f8([8 x float] %[[TMP]]) struct f8 global_f8; void call_f8(void) { global_f8 = func_f8(global_f8); } // CHECK-LABEL: @call_f9 // CHECK: %[[TMP1:[^ ]+]] = alloca [5 x i64] -// CHECK: %[[TMP2:[^ ]+]] = bitcast [5 x i64]* %[[TMP1]] to i8* -// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 %[[TMP2]], i8* align 4 bitcast (%struct.f9* @global_f9 to i8*), i64 36, i1 false) -// CHECK: %[[TMP3:[^ ]+]] = load [5 x i64], [5 x i64]* %[[TMP1]] -// CHECK: call void @func_f9(%struct.f9* sret(%struct.f9) align 4 %{{[^ ]+}}, [5 x i64] %[[TMP3]]) +// CHECK: call void @llvm.memcpy.p0.p0.i64(ptr align 8 %[[TMP1]], ptr align 4 @global_f9, i64 36, i1 false) +// CHECK: %[[TMP3:[^ ]+]] = load [5 x i64], ptr %[[TMP1]] +// CHECK: call void @func_f9(ptr sret(%struct.f9) align 4 %{{[^ ]+}}, [5 x i64] %[[TMP3]]) struct f9 global_f9; void call_f9(void) { global_f9 = func_f9(global_f9); } // CHECK-LABEL: @call_fab -// CHECK: %[[TMP:[^ ]+]] = load [2 x float], [2 x float]* bitcast (%struct.fab* @global_fab to [2 x float]*) +// CHECK: %[[TMP:[^ ]+]] = load [2 x float], ptr @global_fab // CHECK: call [2 x float] @func_fab([2 x float] %[[TMP]]) struct fab global_fab; void call_fab(void) { global_fab = func_fab(global_fab); } // CHECK-LABEL: @call_fabc -// CHECK: %[[TMP:[^ ]+]] = load [3 x float], [3 x float]* bitcast (%struct.fabc* @global_fabc to [3 x float]*) +// CHECK: %[[TMP:[^ ]+]] = load [3 x float], ptr @global_fabc // CHECK: call [3 x float] @func_fabc([3 x float] %[[TMP]]) struct fabc global_fabc; void call_fabc(void) { global_fabc = func_fabc(global_fabc); } @@ -162,7 +161,7 @@ struct v7 func_v7(struct v7 x) { return x; } // CHECK: define{{.*}} [8 x <4 x i32>] @func_v8([8 x <4 x i32>] %x.coerce) struct v8 func_v8(struct v8 x) { return x; } -// CHECK: define{{.*}} void @func_v9(%struct.v9* noalias sret(%struct.v9) align 16 %agg.result, %struct.v9* noundef byval(%struct.v9) align 16 %x) +// CHECK: define{{.*}} void @func_v9(ptr noalias sret(%struct.v9) align 16 %agg.result, ptr noundef byval(%struct.v9) align 16 %x) struct v9 func_v9(struct v9 x) { return x; } // CHECK: define{{.*}} [2 x <4 x i32>] @func_vab([2 x <4 x i32>] %x.coerce) @@ -172,66 +171,66 @@ struct vab func_vab(struct vab x) { return x; } struct vabc func_vabc(struct vabc x) { return x; } // CHECK-LABEL: @call_v1 -// CHECK: %[[TMP:[^ ]+]] = load <4 x i32>, <4 x i32>* getelementptr inbounds (%struct.v1, %struct.v1* @global_v1, i32 0, i32 0, i32 0), align 1 +// CHECK: %[[TMP:[^ ]+]] = load <4 x i32>, ptr @global_v1, align 1 // CHECK: call [1 x <4 x i32>] @func_v1(<4 x i32> inreg %[[TMP]]) struct v1 global_v1; void call_v1(void) { global_v1 = func_v1(global_v1); } // CHECK-LABEL: @call_v2 -// CHECK: %[[TMP:[^ ]+]] = load [2 x <4 x i32>], [2 x <4 x i32>]* getelementptr inbounds (%struct.v2, %struct.v2* @global_v2, i32 0, i32 0), align 1 +// CHECK: %[[TMP:[^ ]+]] = load [2 x <4 x i32>], ptr @global_v2, align 1 // CHECK: call [2 x <4 x i32>] @func_v2([2 x <4 x i32>] %[[TMP]]) struct v2 global_v2; void call_v2(void) { global_v2 = func_v2(global_v2); } // CHECK-LABEL: @call_v3 -// CHECK: %[[TMP:[^ ]+]] = load [3 x <4 x i32>], [3 x <4 x i32>]* getelementptr inbounds (%struct.v3, %struct.v3* @global_v3, i32 0, i32 0), align 1 +// CHECK: %[[TMP:[^ ]+]] = load [3 x <4 x i32>], ptr @global_v3, align 1 // CHECK: call [3 x <4 x i32>] @func_v3([3 x <4 x i32>] %[[TMP]]) struct v3 global_v3; void call_v3(void) { global_v3 = func_v3(global_v3); } // CHECK-LABEL: @call_v4 -// CHECK: %[[TMP:[^ ]+]] = load [4 x <4 x i32>], [4 x <4 x i32>]* getelementptr inbounds (%struct.v4, %struct.v4* @global_v4, i32 0, i32 0), align 1 +// CHECK: %[[TMP:[^ ]+]] = load [4 x <4 x i32>], ptr @global_v4, align 1 // CHECK: call [4 x <4 x i32>] @func_v4([4 x <4 x i32>] %[[TMP]]) struct v4 global_v4; void call_v4(void) { global_v4 = func_v4(global_v4); } // CHECK-LABEL: @call_v5 -// CHECK: %[[TMP:[^ ]+]] = load [5 x <4 x i32>], [5 x <4 x i32>]* getelementptr inbounds (%struct.v5, %struct.v5* @global_v5, i32 0, i32 0), align 1 +// CHECK: %[[TMP:[^ ]+]] = load [5 x <4 x i32>], ptr @global_v5, align 1 // CHECK: call [5 x <4 x i32>] @func_v5([5 x <4 x i32>] %[[TMP]]) struct v5 global_v5; void call_v5(void) { global_v5 = func_v5(global_v5); } // CHECK-LABEL: @call_v6 -// CHECK: %[[TMP:[^ ]+]] = load [6 x <4 x i32>], [6 x <4 x i32>]* getelementptr inbounds (%struct.v6, %struct.v6* @global_v6, i32 0, i32 0), align 1 +// CHECK: %[[TMP:[^ ]+]] = load [6 x <4 x i32>], ptr @global_v6, align 1 // CHECK: call [6 x <4 x i32>] @func_v6([6 x <4 x i32>] %[[TMP]]) struct v6 global_v6; void call_v6(void) { global_v6 = func_v6(global_v6); } // CHECK-LABEL: @call_v7 -// CHECK: %[[TMP:[^ ]+]] = load [7 x <4 x i32>], [7 x <4 x i32>]* getelementptr inbounds (%struct.v7, %struct.v7* @global_v7, i32 0, i32 0), align 1 +// CHECK: %[[TMP:[^ ]+]] = load [7 x <4 x i32>], ptr @global_v7, align 1 // CHECK: call [7 x <4 x i32>] @func_v7([7 x <4 x i32>] %[[TMP]]) struct v7 global_v7; void call_v7(void) { global_v7 = func_v7(global_v7); } // CHECK-LABEL: @call_v8 -// CHECK: %[[TMP:[^ ]+]] = load [8 x <4 x i32>], [8 x <4 x i32>]* getelementptr inbounds (%struct.v8, %struct.v8* @global_v8, i32 0, i32 0), align 1 +// CHECK: %[[TMP:[^ ]+]] = load [8 x <4 x i32>], ptr @global_v8, align 1 // CHECK: call [8 x <4 x i32>] @func_v8([8 x <4 x i32>] %[[TMP]]) struct v8 global_v8; void call_v8(void) { global_v8 = func_v8(global_v8); } // CHECK-LABEL: @call_v9 -// CHECK: call void @func_v9(%struct.v9* sret(%struct.v9) align 16 %{{[^ ]+}}, %struct.v9* noundef byval(%struct.v9) align 16 @global_v9) +// CHECK: call void @func_v9(ptr sret(%struct.v9) align 16 %{{[^ ]+}}, ptr noundef byval(%struct.v9) align 16 @global_v9) struct v9 global_v9; void call_v9(void) { global_v9 = func_v9(global_v9); } // CHECK-LABEL: @call_vab -// CHECK: %[[TMP:[^ ]+]] = load [2 x <4 x i32>], [2 x <4 x i32>]* bitcast (%struct.vab* @global_vab to [2 x <4 x i32>]*) +// CHECK: %[[TMP:[^ ]+]] = load [2 x <4 x i32>], ptr @global_vab // CHECK: call [2 x <4 x i32>] @func_vab([2 x <4 x i32>] %[[TMP]]) struct vab global_vab; void call_vab(void) { global_vab = func_vab(global_vab); } // CHECK-LABEL: @call_vabc -// CHECK: %[[TMP:[^ ]+]] = load [3 x <4 x i32>], [3 x <4 x i32>]* bitcast (%struct.vabc* @global_vabc to [3 x <4 x i32>]*) +// CHECK: %[[TMP:[^ ]+]] = load [3 x <4 x i32>], ptr @global_vabc // CHECK: call [3 x <4 x i32>] @func_vabc([3 x <4 x i32>] %[[TMP]]) struct vabc global_vabc; void call_vabc(void) { global_vabc = func_vabc(global_vabc); } @@ -279,7 +278,7 @@ struct v3f7 func_v3f7(struct v3f7 x) { return x; } // CHECK: define{{.*}} [8 x <4 x float>] @func_v3f8([8 x <4 x float>] %x.coerce) struct v3f8 func_v3f8(struct v3f8 x) { return x; } -// CHECK: define{{.*}} void @func_v3f9(%struct.v3f9* noalias sret(%struct.v3f9) align 16 %agg.result, %struct.v3f9* noundef byval(%struct.v3f9) align 16 %x) +// CHECK: define{{.*}} void @func_v3f9(ptr noalias sret(%struct.v3f9) align 16 %agg.result, ptr noundef byval(%struct.v3f9) align 16 %x) struct v3f9 func_v3f9(struct v3f9 x) { return x; } // CHECK: define{{.*}} [2 x <4 x float>] @func_v3fab([2 x <4 x float>] %x.coerce) @@ -289,66 +288,66 @@ struct v3fab func_v3fab(struct v3fab x) { return x; } struct v3fabc func_v3fabc(struct v3fabc x) { return x; } // CHECK-LABEL: @call_v3f1 -// CHECK: %[[TMP:[^ ]+]] = load <3 x float>, <3 x float>* getelementptr inbounds (%struct.v3f1, %struct.v3f1* @global_v3f1, i32 0, i32 0, i32 0), align 1 +// CHECK: %[[TMP:[^ ]+]] = load <3 x float>, ptr @global_v3f1, align 1 // CHECK: call [1 x <4 x float>] @func_v3f1(<3 x float> inreg %[[TMP]]) struct v3f1 global_v3f1; void call_v3f1(void) { global_v3f1 = func_v3f1(global_v3f1); } // CHECK-LABEL: @call_v3f2 -// CHECK: %[[TMP:[^ ]+]] = load [2 x <4 x float>], [2 x <4 x float>]* bitcast (%struct.v3f2* @global_v3f2 to [2 x <4 x float>]*), align 16 +// CHECK: %[[TMP:[^ ]+]] = load [2 x <4 x float>], ptr @global_v3f2, align 16 // CHECK: call [2 x <4 x float>] @func_v3f2([2 x <4 x float>] %[[TMP]]) struct v3f2 global_v3f2; void call_v3f2(void) { global_v3f2 = func_v3f2(global_v3f2); } // CHECK-LABEL: @call_v3f3 -// CHECK: %[[TMP:[^ ]+]] = load [3 x <4 x float>], [3 x <4 x float>]* bitcast (%struct.v3f3* @global_v3f3 to [3 x <4 x float>]*), align 16 +// CHECK: %[[TMP:[^ ]+]] = load [3 x <4 x float>], ptr @global_v3f3, align 16 // CHECK: call [3 x <4 x float>] @func_v3f3([3 x <4 x float>] %[[TMP]]) struct v3f3 global_v3f3; void call_v3f3(void) { global_v3f3 = func_v3f3(global_v3f3); } // CHECK-LABEL: @call_v3f4 -// CHECK: %[[TMP:[^ ]+]] = load [4 x <4 x float>], [4 x <4 x float>]* bitcast (%struct.v3f4* @global_v3f4 to [4 x <4 x float>]*), align 16 +// CHECK: %[[TMP:[^ ]+]] = load [4 x <4 x float>], ptr @global_v3f4, align 16 // CHECK: call [4 x <4 x float>] @func_v3f4([4 x <4 x float>] %[[TMP]]) struct v3f4 global_v3f4; void call_v3f4(void) { global_v3f4 = func_v3f4(global_v3f4); } // CHECK-LABEL: @call_v3f5 -// CHECK: %[[TMP:[^ ]+]] = load [5 x <4 x float>], [5 x <4 x float>]* bitcast (%struct.v3f5* @global_v3f5 to [5 x <4 x float>]*), align 16 +// CHECK: %[[TMP:[^ ]+]] = load [5 x <4 x float>], ptr @global_v3f5, align 16 // CHECK: call [5 x <4 x float>] @func_v3f5([5 x <4 x float>] %[[TMP]]) struct v3f5 global_v3f5; void call_v3f5(void) { global_v3f5 = func_v3f5(global_v3f5); } // CHECK-LABEL: @call_v3f6 -// CHECK: %[[TMP:[^ ]+]] = load [6 x <4 x float>], [6 x <4 x float>]* bitcast (%struct.v3f6* @global_v3f6 to [6 x <4 x float>]*), align 16 +// CHECK: %[[TMP:[^ ]+]] = load [6 x <4 x float>], ptr @global_v3f6, align 16 // CHECK: call [6 x <4 x float>] @func_v3f6([6 x <4 x float>] %[[TMP]]) struct v3f6 global_v3f6; void call_v3f6(void) { global_v3f6 = func_v3f6(global_v3f6); } // CHECK-LABEL: @call_v3f7 -// CHECK: %[[TMP:[^ ]+]] = load [7 x <4 x float>], [7 x <4 x float>]* bitcast (%struct.v3f7* @global_v3f7 to [7 x <4 x float>]*), align 16 +// CHECK: %[[TMP:[^ ]+]] = load [7 x <4 x float>], ptr @global_v3f7, align 16 // CHECK: call [7 x <4 x float>] @func_v3f7([7 x <4 x float>] %[[TMP]]) struct v3f7 global_v3f7; void call_v3f7(void) { global_v3f7 = func_v3f7(global_v3f7); } // CHECK-LABEL: @call_v3f8 -// CHECK: %[[TMP:[^ ]+]] = load [8 x <4 x float>], [8 x <4 x float>]* bitcast (%struct.v3f8* @global_v3f8 to [8 x <4 x float>]*), align 16 +// CHECK: %[[TMP:[^ ]+]] = load [8 x <4 x float>], ptr @global_v3f8, align 16 // CHECK: call [8 x <4 x float>] @func_v3f8([8 x <4 x float>] %[[TMP]]) struct v3f8 global_v3f8; void call_v3f8(void) { global_v3f8 = func_v3f8(global_v3f8); } // CHECK-LABEL: @call_v3f9 -// CHECK: call void @func_v3f9(%struct.v3f9* sret(%struct.v3f9) align 16 %{{[^ ]+}}, %struct.v3f9* noundef byval(%struct.v3f9) align 16 @global_v3f9) +// CHECK: call void @func_v3f9(ptr sret(%struct.v3f9) align 16 %{{[^ ]+}}, ptr noundef byval(%struct.v3f9) align 16 @global_v3f9) struct v3f9 global_v3f9; void call_v3f9(void) { global_v3f9 = func_v3f9(global_v3f9); } // CHECK-LABEL: @call_v3fab -// CHECK: %[[TMP:[^ ]+]] = load [2 x <4 x float>], [2 x <4 x float>]* bitcast (%struct.v3fab* @global_v3fab to [2 x <4 x float>]*), align 16 +// CHECK: %[[TMP:[^ ]+]] = load [2 x <4 x float>], ptr @global_v3fab, align 16 // CHECK: call [2 x <4 x float>] @func_v3fab([2 x <4 x float>] %[[TMP]]) struct v3fab global_v3fab; void call_v3fab(void) { global_v3fab = func_v3fab(global_v3fab); } // CHECK-LABEL: @call_v3fabc -// CHECK: %[[TMP:[^ ]+]] = load [3 x <4 x float>], [3 x <4 x float>]* bitcast (%struct.v3fabc* @global_v3fabc to [3 x <4 x float>]*), align 16 +// CHECK: %[[TMP:[^ ]+]] = load [3 x <4 x float>], ptr @global_v3fabc, align 16 // CHECK: call [3 x <4 x float>] @func_v3fabc([3 x <4 x float>] %[[TMP]]) struct v3fabc global_v3fabc; void call_v3fabc(void) { global_v3fabc = func_v3fabc(global_v3fabc); } @@ -419,7 +418,7 @@ struct s16 ret_s16(void) { 25, 26, 27, 28, 29, 30, 31, 32 }; } -// CHECK: define{{.*}} void @ret_s17(%struct.s17* +// CHECK: define{{.*}} void @ret_s17(ptr struct s17 ret_s17(void) { return (struct s17) { 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33 }; diff --git a/clang/test/CodeGen/PowerPC/ppc64le-f128Aggregates.c b/clang/test/CodeGen/PowerPC/ppc64le-f128Aggregates.c index 5b3098a8cf2142..27c3b14f0a04b6 100644 --- a/clang/test/CodeGen/PowerPC/ppc64le-f128Aggregates.c +++ b/clang/test/CodeGen/PowerPC/ppc64le-f128Aggregates.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -no-opaque-pointers -triple powerpc64le-unknown-linux-gnu -emit-llvm \ +// RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu -emit-llvm \ // RUN: -target-cpu pwr9 -target-feature +float128 -o - %s | FileCheck %s // Test homogeneous fp128 aggregate passing and returning. @@ -42,7 +42,7 @@ struct fp7 func_f7(struct fp7 x) { return x; } // CHECK: define{{.*}} [8 x fp128] @func_f8([8 x fp128] %x.coerce) struct fp8 func_f8(struct fp8 x) { return x; } -// CHECK: define{{.*}} void @func_f9(%struct.fp9* noalias sret(%struct.fp9) align 16 %agg.result, %struct.fp9* noundef byval(%struct.fp9) align 16 %x) +// CHECK: define{{.*}} void @func_f9(ptr noalias sret(%struct.fp9) align 16 %agg.result, ptr noundef byval(%struct.fp9) align 16 %x) struct fp9 func_f9(struct fp9 x) { return x; } // CHECK: define{{.*}} [2 x fp128] @func_fab([2 x fp128] %x.coerce) @@ -55,70 +55,69 @@ struct fpabc func_fabc(struct fpabc x) { return x; } struct fp2a2b func_f2a2b(struct fp2a2b x) { return x; } // CHECK-LABEL: @call_fp1 -// CHECK: %[[TMP:[^ ]+]] = load fp128, fp128* getelementptr inbounds (%struct.fp1, %struct.fp1* @global_f1, i32 0, i32 0, i32 0), align 16 +// CHECK: %[[TMP:[^ ]+]] = load fp128, ptr @global_f1, align 16 // CHECK: call [1 x fp128] @func_f1(fp128 inreg %[[TMP]]) struct fp1 global_f1; void call_fp1(void) { global_f1 = func_f1(global_f1); } // CHECK-LABEL: @call_fp2 -// CHECK: %[[TMP:[^ ]+]] = load [2 x fp128], [2 x fp128]* getelementptr inbounds (%struct.fp2, %struct.fp2* @global_f2, i32 0, i32 0), align 16 +// CHECK: %[[TMP:[^ ]+]] = load [2 x fp128], ptr @global_f2, align 16 // CHECK: call [2 x fp128] @func_f2([2 x fp128] %[[TMP]]) struct fp2 global_f2; void call_fp2(void) { global_f2 = func_f2(global_f2); } // CHECK-LABEL: @call_fp3 -// CHECK: %[[TMP:[^ ]+]] = load [3 x fp128], [3 x fp128]* getelementptr inbounds (%struct.fp3, %struct.fp3* @global_f3, i32 0, i32 0), align 16 +// CHECK: %[[TMP:[^ ]+]] = load [3 x fp128], ptr @global_f3, align 16 // CHECK: call [3 x fp128] @func_f3([3 x fp128] %[[TMP]]) struct fp3 global_f3; void call_fp3(void) { global_f3 = func_f3(global_f3); } // CHECK-LABEL: @call_fp4 -// CHECK: %[[TMP:[^ ]+]] = load [4 x fp128], [4 x fp128]* getelementptr inbounds (%struct.fp4, %struct.fp4* @global_f4, i32 0, i32 0), align 16 +// CHECK: %[[TMP:[^ ]+]] = load [4 x fp128], ptr @global_f4, align 16 // CHECK: call [4 x fp128] @func_f4([4 x fp128] %[[TMP]]) struct fp4 global_f4; void call_fp4(void) { global_f4 = func_f4(global_f4); } // CHECK-LABEL: @call_fp5 -// CHECK: %[[TMP:[^ ]+]] = load [5 x fp128], [5 x fp128]* getelementptr inbounds (%struct.fp5, %struct.fp5* @global_f5, i32 0, i32 0), align 16 +// CHECK: %[[TMP:[^ ]+]] = load [5 x fp128], ptr @global_f5, align 16 // CHECK: call [5 x fp128] @func_f5([5 x fp128] %[[TMP]]) struct fp5 global_f5; void call_fp5(void) { global_f5 = func_f5(global_f5); } // CHECK-LABEL: @call_fp6 -// CHECK: %[[TMP:[^ ]+]] = load [6 x fp128], [6 x fp128]* getelementptr inbounds (%struct.fp6, %struct.fp6* @global_f6, i32 0, i32 0), align 16 +// CHECK: %[[TMP:[^ ]+]] = load [6 x fp128], ptr @global_f6, align 16 // CHECK: call [6 x fp128] @func_f6([6 x fp128] %[[TMP]]) struct fp6 global_f6; void call_fp6(void) { global_f6 = func_f6(global_f6); } // CHECK-LABEL: @call_fp7 -// CHECK: %[[TMP:[^ ]+]] = load [7 x fp128], [7 x fp128]* getelementptr inbounds (%struct.fp7, %struct.fp7* @global_f7, i32 0, i32 0), align 16 +// CHECK: %[[TMP:[^ ]+]] = load [7 x fp128], ptr @global_f7, align 16 // CHECK: call [7 x fp128] @func_f7([7 x fp128] %[[TMP]]) struct fp7 global_f7; void call_fp7(void) { global_f7 = func_f7(global_f7); } // CHECK-LABEL: @call_fp8 -// CHECK: %[[TMP:[^ ]+]] = load [8 x fp128], [8 x fp128]* getelementptr inbounds (%struct.fp8, %struct.fp8* @global_f8, i32 0, i32 0), align 16 +// CHECK: %[[TMP:[^ ]+]] = load [8 x fp128], ptr @global_f8, align 16 // CHECK: call [8 x fp128] @func_f8([8 x fp128] %[[TMP]]) struct fp8 global_f8; void call_fp8(void) { global_f8 = func_f8(global_f8); } // CHECK-LABEL: @call_fp9 // CHECK: %[[TMP1:[^ ]+]] = alloca %struct.fp9, align 16 -// CHECK: call void @func_f9(%struct.fp9* sret(%struct.fp9) align 16 %[[TMP2:[^ ]+]], %struct.fp9* noundef byval(%struct.fp9) align 16 @global_f9 -// CHECK: %[[TMP3:[^ ]+]] = bitcast %struct.fp9* %[[TMP2]] to i8* -// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 bitcast (%struct.fp9* @global_f9 to i8*), i8* align 16 %[[TMP3]], i64 144, i1 false +// CHECK: call void @func_f9(ptr sret(%struct.fp9) align 16 %[[TMP2:[^ ]+]], ptr noundef byval(%struct.fp9) align 16 @global_f9 +// CHECK: call void @llvm.memcpy.p0.p0.i64(ptr align 16 @global_f9, ptr align 16 %[[TMP2]], i64 144, i1 false // CHECK: ret void struct fp9 global_f9; void call_fp9(void) { global_f9 = func_f9(global_f9); } // CHECK-LABEL: @call_fpab -// CHECK: %[[TMP:[^ ]+]] = load [2 x fp128], [2 x fp128]* bitcast (%struct.fpab* @global_fab to [2 x fp128]*) +// CHECK: %[[TMP:[^ ]+]] = load [2 x fp128], ptr @global_fab // CHECK: call [2 x fp128] @func_fab([2 x fp128] %[[TMP]]) struct fpab global_fab; void call_fpab(void) { global_fab = func_fab(global_fab); } // CHECK-LABEL: @call_fpabc -// CHECK: %[[TMP:[^ ]+]] = load [3 x fp128], [3 x fp128]* bitcast (%struct.fpabc* @global_fabc to [3 x fp128]*) +// CHECK: %[[TMP:[^ ]+]] = load [3 x fp128], ptr @global_fabc // CHECK: call [3 x fp128] @func_fabc([3 x fp128] %[[TMP]]) struct fpabc global_fabc; void call_fpabc(void) { global_fabc = func_fabc(global_fabc); }