From 2ca194ff55632a98cf1f821564ed998ffe19945f Mon Sep 17 00:00:00 2001 From: Vang Thao Date: Wed, 2 Feb 2022 15:33:40 -0800 Subject: [PATCH] [AMDGPU] Fix scheduler live-ins with debug inst at start of block GCNDownwardRPTracker RPTracker.reset() skips debug instructions for NextMI so RPTracker.getNext() will never give the beginning of a sched region if it is a debug value. In this case we will never set the live-ins for that block. Add check to see if getNext also equals the MI after skipping debug instructions. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D118853 --- llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp | 6 +- .../AMDGPU/debug-value-scheduler-liveins.mir | 67 +++++++++++++++++++ 2 files changed, 70 insertions(+), 3 deletions(-) create mode 100644 llvm/test/CodeGen/AMDGPU/debug-value-scheduler-liveins.mir diff --git a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp index 75855a7a4f9c4..8bb53916fe6f6 100644 --- a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp +++ b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp @@ -493,14 +493,14 @@ void GCNScheduleDAGMILive::computeBlockPressure(const MachineBasicBlock *MBB) { auto I = MBB->begin(); auto LiveInIt = MBBLiveIns.find(MBB); + auto &Rgn = Regions[CurRegion]; + auto *NonDbgMI = &*skipDebugInstructionsForward(Rgn.first, Rgn.second); if (LiveInIt != MBBLiveIns.end()) { auto LiveIn = std::move(LiveInIt->second); RPTracker.reset(*MBB->begin(), &LiveIn); MBBLiveIns.erase(LiveInIt); } else { - auto &Rgn = Regions[CurRegion]; I = Rgn.first; - auto *NonDbgMI = &*skipDebugInstructionsForward(Rgn.first, Rgn.second); auto LRS = BBLiveInMap.lookup(NonDbgMI); #ifdef EXPENSIVE_CHECKS assert(isEqual(getLiveRegsBefore(*NonDbgMI, *LIS), LRS)); @@ -511,7 +511,7 @@ void GCNScheduleDAGMILive::computeBlockPressure(const MachineBasicBlock *MBB) { for ( ; ; ) { I = RPTracker.getNext(); - if (Regions[CurRegion].first == I) { + if (Regions[CurRegion].first == I || NonDbgMI == I) { LiveIns[CurRegion] = RPTracker.getLiveRegs(); RPTracker.clearMaxPressure(); } diff --git a/llvm/test/CodeGen/AMDGPU/debug-value-scheduler-liveins.mir b/llvm/test/CodeGen/AMDGPU/debug-value-scheduler-liveins.mir new file mode 100644 index 0000000000000..692a069bdef2f --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/debug-value-scheduler-liveins.mir @@ -0,0 +1,67 @@ +# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=machine-scheduler %s -o - -debug-only=machine-scheduler 2>&1 | FileCheck %s +# REQUIRES: asserts + +# CHECK: ********** MI Scheduling ********** +# CHECK-NEXT: test_get_liveins:%bb.1 +# CHECK: Region live-in pressure: VGPRs: 1 AGPRs: 0, SGPRs: 0, LVGPR WT: 0, LSGPR WT: 0 +# CHECK: ScheduleDAGMILive::schedule starting + +--- +name: test_get_liveins +tracksRegLiveness: true +frameInfo: + hasCalls: true +body: | + bb.0: + successors: %bb.1 + + %0:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 0, implicit $exec, implicit $mode, implicit-def $m0 + + bb.1: + successors: %bb.2 + + DBG_VALUE %0:vgpr_32, 0, 0 + %1:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 1, implicit $exec, implicit $mode, implicit-def $m0 + %2:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 2, implicit $exec, implicit $mode, implicit-def $m0 + %3:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 3, implicit $exec, implicit $mode, implicit-def $m0 + %4:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 4, implicit $exec, implicit $mode, implicit-def $m0 + %5:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 5, implicit $exec, implicit $mode, implicit-def $m0 + %6:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 6, implicit $exec, implicit $mode, implicit-def $m0 + %7:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 7, implicit $exec, implicit $mode, implicit-def $m0 + %8:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 8, implicit $exec, implicit $mode, implicit-def $m0 + %9:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 9, implicit $exec, implicit $mode, implicit-def $m0 + %10:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 10, implicit $exec, implicit $mode, implicit-def $m0 + %11:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 11, implicit $exec, implicit $mode, implicit-def $m0 + %12:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 12, implicit $exec, implicit $mode, implicit-def $m0 + %13:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 13, implicit $exec, implicit $mode, implicit-def $m0 + %14:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 14, implicit $exec, implicit $mode, implicit-def $m0 + %15:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 15, implicit $exec, implicit $mode, implicit-def $m0 + %16:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 16, implicit $exec, implicit $mode, implicit-def $m0 + %17:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 17, implicit $exec, implicit $mode, implicit-def $m0 + %18:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 18, implicit $exec, implicit $mode, implicit-def $m0 + %19:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 19, implicit $exec, implicit $mode, implicit-def $m0 + %20:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 20, implicit $exec, implicit $mode, implicit-def $m0 + %21:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 21, implicit $exec, implicit $mode, implicit-def $m0 + %22:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 22, implicit $exec, implicit $mode, implicit-def $m0 + %23:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 23, implicit $exec, implicit $mode, implicit-def $m0 + %24:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 24, implicit $exec, implicit $mode, implicit-def $m0 + + bb.2: + DBG_VALUE %24:vgpr_32, 0, 0 + S_NOP 0, implicit %0 + S_NOP 0, implicit %1, implicit %2 + S_NOP 0, implicit %3, implicit %4 + S_NOP 0, implicit %5, implicit %6 + S_NOP 0, implicit %7, implicit %8 + S_NOP 0, implicit %9, implicit %10 + S_NOP 0, implicit %11, implicit %12 + S_NOP 0, implicit %13, implicit %14 + S_NOP 0, implicit %15, implicit %16 + S_NOP 0, implicit %17, implicit %18 + S_NOP 0, implicit %19, implicit %20 + S_NOP 0, implicit %21, implicit %22 + S_NOP 0, implicit %23, implicit %23 + S_NOP 0, implicit %24 + S_ENDPGM 0 +... +