From 2e7d4b66197b40921b52af37705d4fdd7e3a6785 Mon Sep 17 00:00:00 2001 From: "chenglin.bi" Date: Mon, 6 Jun 2022 10:15:48 +0800 Subject: [PATCH] [InstCombine] Add more tests for shl+lshr transforms; NFC --- llvm/test/Transforms/InstCombine/and.ll | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/llvm/test/Transforms/InstCombine/and.ll b/llvm/test/Transforms/InstCombine/and.ll index 3fd81b82e3475..b2f43121b8059 100644 --- a/llvm/test/Transforms/InstCombine/and.ll +++ b/llvm/test/Transforms/InstCombine/and.ll @@ -1637,6 +1637,19 @@ define i16 @shl_lshr_pow2_const_case1(i16 %x) { define i16 @shl_lshr_pow2_const_case2(i16 %x) { ; CHECK-LABEL: @shl_lshr_pow2_const_case2( +; CHECK-NEXT: [[SHL:%.*]] = shl i16 4, [[X:%.*]] +; CHECK-NEXT: [[LSHR:%.*]] = lshr i16 [[SHL]], 6 +; CHECK-NEXT: [[R:%.*]] = or i16 [[LSHR]], -9 +; CHECK-NEXT: ret i16 [[R]] +; + %shl = shl i16 4, %x + %lshr = lshr i16 %shl, 6 + %r = or i16 %lshr, 65527 ; ~8 + ret i16 %r +} + +define i16 @shl_lshr_pow2_const_case3(i16 %x) { +; CHECK-LABEL: @shl_lshr_pow2_const_case3( ; CHECK-NEXT: [[SHL:%.*]] = shl i16 16, [[X:%.*]] ; CHECK-NEXT: [[LSHR:%.*]] = lshr exact i16 [[SHL]], 3 ; CHECK-NEXT: [[R:%.*]] = or i16 [[LSHR]], -9 @@ -1648,8 +1661,8 @@ define i16 @shl_lshr_pow2_const_case2(i16 %x) { ret i16 %r } -define i13 @shl_lshr_pow2_const_case3(i16 %x) { -; CHECK-LABEL: @shl_lshr_pow2_const_case3( +define i13 @shl_lshr_pow2_const_case4(i16 %x) { +; CHECK-LABEL: @shl_lshr_pow2_const_case4( ; CHECK-NEXT: [[SHL:%.*]] = shl i16 16, [[X:%.*]] ; CHECK-NEXT: [[LSHR:%.*]] = lshr exact i16 [[SHL]], 3 ; CHECK-NEXT: [[R:%.*]] = trunc i16 [[LSHR]] to i13