diff --git a/clang/lib/AST/ItaniumMangle.cpp b/clang/lib/AST/ItaniumMangle.cpp index 2a62ac0175afb..b1678479888eb 100644 --- a/clang/lib/AST/ItaniumMangle.cpp +++ b/clang/lib/AST/ItaniumMangle.cpp @@ -4029,7 +4029,7 @@ void CXXNameMangler::mangleRISCVFixedRVVVectorType(const VectorType *T) { case BuiltinType::ULong: TypeNameOS << "uint64"; break; - case BuiltinType::Half: + case BuiltinType::Float16: TypeNameOS << "float16"; break; case BuiltinType::Float: diff --git a/clang/test/CodeGenCXX/riscv-mangle-rvv-fixed-vectors.cpp b/clang/test/CodeGenCXX/riscv-mangle-rvv-fixed-vectors.cpp index 98fb27b704fd8..32bd49f4ff725 100644 --- a/clang/test/CodeGenCXX/riscv-mangle-rvv-fixed-vectors.cpp +++ b/clang/test/CodeGenCXX/riscv-mangle-rvv-fixed-vectors.cpp @@ -1,23 +1,23 @@ // RUN: %clang_cc1 -triple riscv64-none-linux-gnu %s -emit-llvm -o - \ -// RUN: -target-feature +f -target-feature +d \ -// RUN: -target-feature +zve64d -mvscale-min=1 -mvscale-max=1 \ -// RUN: | FileCheck %s --check-prefix=CHECK-64 +// RUN: -target-feature +f -target-feature +d -target-feature +zfh \ +// RUN: -target-feature +zve64d -target-feature +zvfh -mvscale-min=1 \ +// RUN: -mvscale-max=1 | FileCheck %s --check-prefix=CHECK-64 // RUN: %clang_cc1 -triple riscv64-none-linux-gnu %s -emit-llvm -o - \ -// RUN: -target-feature +f -target-feature +d \ -// RUN: -target-feature +zve64d -mvscale-min=2 -mvscale-max=2 \ -// RUN: | FileCheck %s --check-prefix=CHECK-128 +// RUN: -target-feature +f -target-feature +d -target-feature +zfh \ +// RUN: -target-feature +zve64d -target-feature +zvfh -mvscale-min=2 \ +// RUN: -mvscale-max=2 | FileCheck %s --check-prefix=CHECK-128 // RUN: %clang_cc1 -triple riscv64-none-linux-gnu %s -emit-llvm -o - \ -// RUN: -target-feature +f -target-feature +d \ -// RUN: -target-feature +zve64d -mvscale-min=4 -mvscale-max=4 \ -// RUN: | FileCheck %s --check-prefix=CHECK-256 +// RUN: -target-feature +f -target-feature +d -target-feature +zfh \ +// RUN: -target-feature +zve64d -target-feature +zvfh -mvscale-min=4 \ +// RUN: -mvscale-max=4 | FileCheck %s --check-prefix=CHECK-256 // RUN: %clang_cc1 -triple riscv64-none-linux-gnu %s -emit-llvm -o - \ -// RUN: -target-feature +f -target-feature +d \ -// RUN: -target-feature +zve64d -mvscale-min=8 -mvscale-max=8 \ -// RUN: | FileCheck %s --check-prefix=CHECK-512 +// RUN: -target-feature +f -target-feature +d -target-feature +zfh \ +// RUN: -target-feature +zve64d -target-feature +zvfh -mvscale-min=8 \ +// RUN: -mvscale-max=8 | FileCheck %s --check-prefix=CHECK-512 // RUN: %clang_cc1 -triple riscv64-none-linux-gnu %s -emit-llvm -o - \ -// RUN: -target-feature +f -target-feature +d \ -// RUN: -target-feature +zve64d -mvscale-min=16 -mvscale-max=16 \ -// RUN: | FileCheck %s --check-prefix=CHECK-1024 +// RUN: -target-feature +f -target-feature +d -target-feature +zfh \ +// RUN: -target-feature +zve64d -target-feature +zvfh -mvscale-min=16 \ +// RUN: -mvscale-max=16 | FileCheck %s --check-prefix=CHECK-1024 typedef __rvv_int8mf8_t vint8mf8_t; typedef __rvv_uint8mf8_t vuint8mf8_t; @@ -26,6 +26,7 @@ typedef __rvv_int8mf4_t vint8mf4_t; typedef __rvv_uint8mf4_t vuint8mf4_t; typedef __rvv_int16mf4_t vint16mf4_t; typedef __rvv_uint16mf4_t vuint16mf4_t; +typedef __rvv_float16mf4_t vfloat16mf4_t; typedef __rvv_int8mf2_t vint8mf2_t; typedef __rvv_uint8mf2_t vuint8mf2_t; @@ -33,6 +34,7 @@ typedef __rvv_int16mf2_t vint16mf2_t; typedef __rvv_uint16mf2_t vuint16mf2_t; typedef __rvv_int32mf2_t vint32mf2_t; typedef __rvv_uint32mf2_t vuint32mf2_t; +typedef __rvv_float16mf2_t vfloat16mf2_t; typedef __rvv_float32mf2_t vfloat32mf2_t; typedef __rvv_int8m1_t vint8m1_t; @@ -43,6 +45,7 @@ typedef __rvv_int32m1_t vint32m1_t; typedef __rvv_uint32m1_t vuint32m1_t; typedef __rvv_int64m1_t vint64m1_t; typedef __rvv_uint64m1_t vuint64m1_t; +typedef __rvv_float16m1_t vfloat16m1_t; typedef __rvv_float32m1_t vfloat32m1_t; typedef __rvv_float64m1_t vfloat64m1_t; @@ -54,6 +57,7 @@ typedef __rvv_int32m2_t vint32m2_t; typedef __rvv_uint32m2_t vuint32m2_t; typedef __rvv_int64m2_t vint64m2_t; typedef __rvv_uint64m2_t vuint64m2_t; +typedef __rvv_float16m2_t vfloat16m2_t; typedef __rvv_float32m2_t vfloat32m2_t; typedef __rvv_float64m2_t vfloat64m2_t; @@ -65,6 +69,7 @@ typedef __rvv_int32m4_t vint32m4_t; typedef __rvv_uint32m4_t vuint32m4_t; typedef __rvv_int64m4_t vint64m4_t; typedef __rvv_uint64m4_t vuint64m4_t; +typedef __rvv_float16m4_t vfloat16m4_t; typedef __rvv_float32m4_t vfloat32m4_t; typedef __rvv_float64m4_t vfloat64m4_t; @@ -76,6 +81,7 @@ typedef __rvv_int32m8_t vint32m8_t; typedef __rvv_uint32m8_t vuint32m8_t; typedef __rvv_int64m8_t vint64m8_t; typedef __rvv_uint64m8_t vuint64m8_t; +typedef __rvv_float16m8_t vfloat16m8_t; typedef __rvv_float32m8_t vfloat32m8_t; typedef __rvv_float64m8_t vfloat64m8_t; @@ -89,6 +95,8 @@ typedef vint16mf4_t fixed_int16mf4_t __attribute__((riscv_rvv_vector_bits(__risc typedef vuint8mf4_t fixed_uint8mf4_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen/4))); typedef vuint16mf4_t fixed_uint16mf4_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen/4))); +typedef vfloat16mf4_t fixed_float16mf4_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen/4))); + typedef vint8mf2_t fixed_int8mf2_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen/2))); typedef vint16mf2_t fixed_int16mf2_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen/2))); typedef vint32mf2_t fixed_int32mf2_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen/2))); @@ -97,6 +105,7 @@ typedef vuint8mf2_t fixed_uint8mf2_t __attribute__((riscv_rvv_vector_bits(__risc typedef vuint16mf2_t fixed_uint16mf2_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen/2))); typedef vuint32mf2_t fixed_uint32mf2_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen/2))); +typedef vfloat16mf2_t fixed_float16mf2_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen/2))); typedef vfloat32mf2_t fixed_float32mf2_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen/2))); typedef vint8m1_t fixed_int8m1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen))); @@ -109,6 +118,7 @@ typedef vuint16m1_t fixed_uint16m1_t __attribute__((riscv_rvv_vector_bits(__risc typedef vuint32m1_t fixed_uint32m1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen))); typedef vuint64m1_t fixed_uint64m1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen))); +typedef vfloat16m1_t fixed_float16m1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen))); typedef vfloat32m1_t fixed_float32m1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen))); typedef vfloat64m1_t fixed_float64m1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen))); @@ -122,6 +132,7 @@ typedef vuint16m2_t fixed_uint16m2_t __attribute__((riscv_rvv_vector_bits(__risc typedef vuint32m2_t fixed_uint32m2_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*2))); typedef vuint64m2_t fixed_uint64m2_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*2))); +typedef vfloat16m2_t fixed_float16m2_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*2))); typedef vfloat32m2_t fixed_float32m2_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*2))); typedef vfloat64m2_t fixed_float64m2_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*2))); @@ -135,6 +146,7 @@ typedef vuint16m4_t fixed_uint16m4_t __attribute__((riscv_rvv_vector_bits(__risc typedef vuint32m4_t fixed_uint32m4_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*4))); typedef vuint64m4_t fixed_uint64m4_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*4))); +typedef vfloat16m4_t fixed_float16m4_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*4))); typedef vfloat32m4_t fixed_float32m4_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*4))); typedef vfloat64m4_t fixed_float64m4_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*4))); @@ -148,6 +160,7 @@ typedef vuint16m8_t fixed_uint16m8_t __attribute__((riscv_rvv_vector_bits(__risc typedef vuint32m8_t fixed_uint32m8_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*8))); typedef vuint64m8_t fixed_uint64m8_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*8))); +typedef vfloat16m8_t fixed_float16m8_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*8))); typedef vfloat32m8_t fixed_float32m8_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*8))); typedef vfloat64m8_t fixed_float64m8_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*8))); @@ -223,6 +236,13 @@ void f9(S) {} // CHECK-1024: _Z3f101SI9__RVV_VLSIu17__rvv_float64m1_tLj1024EEE void f10(S) {} +// CHECK-64: _Z3f111SI9__RVV_VLSIu17__rvv_float16m1_tLj64EEE +// CHECK-128: _Z3f111SI9__RVV_VLSIu17__rvv_float16m1_tLj128EEE +// CHECK-256: _Z3f111SI9__RVV_VLSIu17__rvv_float16m1_tLj256EEE +// CHECK-512: _Z3f111SI9__RVV_VLSIu17__rvv_float16m1_tLj512EEE +// CHECK-1024: _Z3f111SI9__RVV_VLSIu17__rvv_float16m1_tLj1024EEE +void f11(S) {} + // CHECK-64: _Z4m2f11SI9__RVV_VLSIu14__rvv_int8m2_tLj128EEE // CHECK-128: _Z4m2f11SI9__RVV_VLSIu14__rvv_int8m2_tLj256EEE // CHECK-256: _Z4m2f11SI9__RVV_VLSIu14__rvv_int8m2_tLj512EEE @@ -293,6 +313,13 @@ void m2f9(S) {} // CHECK-1024: _Z5m2f101SI9__RVV_VLSIu17__rvv_float64m2_tLj2048EEE void m2f10(S) {} +// CHECK-64: _Z5m2f111SI9__RVV_VLSIu17__rvv_float16m2_tLj128EEE +// CHECK-128: _Z5m2f111SI9__RVV_VLSIu17__rvv_float16m2_tLj256EEE +// CHECK-256: _Z5m2f111SI9__RVV_VLSIu17__rvv_float16m2_tLj512EEE +// CHECK-512: _Z5m2f111SI9__RVV_VLSIu17__rvv_float16m2_tLj1024EEE +// CHECK-1024: _Z5m2f111SI9__RVV_VLSIu17__rvv_float16m2_tLj2048EEE +void m2f11(S) {} + // CHECK-64: _Z4m4f11SI9__RVV_VLSIu14__rvv_int8m4_tLj256EEE // CHECK-128: _Z4m4f11SI9__RVV_VLSIu14__rvv_int8m4_tLj512EEE // CHECK-256: _Z4m4f11SI9__RVV_VLSIu14__rvv_int8m4_tLj1024EEE @@ -363,6 +390,13 @@ void m4f9(S) {} // CHECK-1024: _Z5m4f101SI9__RVV_VLSIu17__rvv_float64m4_tLj4096EEE void m4f10(S) {} +// CHECK-64: _Z5m4f111SI9__RVV_VLSIu17__rvv_float16m4_tLj256EEE +// CHECK-128: _Z5m4f111SI9__RVV_VLSIu17__rvv_float16m4_tLj512EEE +// CHECK-256: _Z5m4f111SI9__RVV_VLSIu17__rvv_float16m4_tLj1024EEE +// CHECK-512: _Z5m4f111SI9__RVV_VLSIu17__rvv_float16m4_tLj2048EEE +// CHECK-1024: _Z5m4f111SI9__RVV_VLSIu17__rvv_float16m4_tLj4096EEE +void m4f11(S) {} + // CHECK-64: _Z4m8f11SI9__RVV_VLSIu14__rvv_int8m8_tLj512EEE // CHECK-128: _Z4m8f11SI9__RVV_VLSIu14__rvv_int8m8_tLj1024EEE // CHECK-256: _Z4m8f11SI9__RVV_VLSIu14__rvv_int8m8_tLj2048EEE @@ -433,6 +467,13 @@ void m8f9(S) {} // CHECK-1024: _Z5m8f101SI9__RVV_VLSIu17__rvv_float64m8_tLj8192EEE void m8f10(S) {} +// CHECK-64: _Z5m8f111SI9__RVV_VLSIu17__rvv_float16m8_tLj512EEE +// CHECK-128: _Z5m8f111SI9__RVV_VLSIu17__rvv_float16m8_tLj1024EEE +// CHECK-256: _Z5m8f111SI9__RVV_VLSIu17__rvv_float16m8_tLj2048EEE +// CHECK-512: _Z5m8f111SI9__RVV_VLSIu17__rvv_float16m8_tLj4096EEE +// CHECK-1024: _Z5m8f111SI9__RVV_VLSIu17__rvv_float16m8_tLj8192EEE +void m8f11(S) {} + // CHECK-64: _Z5mf2f11SI9__RVV_VLSIu15__rvv_int8mf2_tLj32EEE // CHECK-128: _Z5mf2f11SI9__RVV_VLSIu15__rvv_int8mf2_tLj64EEE // CHECK-256: _Z5mf2f11SI9__RVV_VLSIu15__rvv_int8mf2_tLj128EEE @@ -482,6 +523,13 @@ void mf2f7(S) {} // CHECK-1024: _Z5mf2f91SI9__RVV_VLSIu18__rvv_float32mf2_tLj512EEE void mf2f9(S) {} +// CHECK-64: _Z6mf2f101SI9__RVV_VLSIu18__rvv_float16mf2_tLj32EEE +// CHECK-128: _Z6mf2f101SI9__RVV_VLSIu18__rvv_float16mf2_tLj64EEE +// CHECK-256: _Z6mf2f101SI9__RVV_VLSIu18__rvv_float16mf2_tLj128EEE +// CHECK-512: _Z6mf2f101SI9__RVV_VLSIu18__rvv_float16mf2_tLj256EEE +// CHECK-1024: _Z6mf2f101SI9__RVV_VLSIu18__rvv_float16mf2_tLj512EEE +void mf2f10(S) {} + // CHECK-64: _Z5mf4f11SI9__RVV_VLSIu15__rvv_int8mf4_tLj16EEE // CHECK-128: _Z5mf4f11SI9__RVV_VLSIu15__rvv_int8mf4_tLj32EEE // CHECK-256: _Z5mf4f11SI9__RVV_VLSIu15__rvv_int8mf4_tLj64EEE @@ -510,6 +558,13 @@ void mf4f5(S) {} // CHECK-1024: _Z5mf4f61SI9__RVV_VLSIu17__rvv_uint16mf4_tLj256EEE void mf4f6(S) {} +// CHECK-64: _Z5mf4f71SI9__RVV_VLSIu18__rvv_float16mf4_tLj16EEE +// CHECK-128: _Z5mf4f71SI9__RVV_VLSIu18__rvv_float16mf4_tLj32EEE +// CHECK-256: _Z5mf4f71SI9__RVV_VLSIu18__rvv_float16mf4_tLj64EEE +// CHECK-512: _Z5mf4f71SI9__RVV_VLSIu18__rvv_float16mf4_tLj128EEE +// CHECK-1024: _Z5mf4f71SI9__RVV_VLSIu18__rvv_float16mf4_tLj256EEE +void mf4f7(S) {} + // CHECK-64: _Z5mf8f11SI9__RVV_VLSIu15__rvv_int8mf8_tLj8EEE // CHECK-128: _Z5mf8f11SI9__RVV_VLSIu15__rvv_int8mf8_tLj16EEE // CHECK-256: _Z5mf8f11SI9__RVV_VLSIu15__rvv_int8mf8_tLj32EEE