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[WebAssembly] Remove experimental SIMD instructions
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Removes the instruction definitions, intrinsics, and builtins for qfma/qfms,
signselect, and prefetch instructions, which were not included in the final
WebAssembly SIMD spec.

Depends on D98457.

Differential Revision: https://reviews.llvm.org/D98466
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tlively committed Mar 18, 2021
1 parent 0d8331c commit 2f2ae08
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16 changes: 0 additions & 16 deletions clang/include/clang/Basic/BuiltinsWebAssembly.def
Expand Up @@ -141,11 +141,6 @@ TARGET_BUILTIN(__builtin_wasm_extadd_pairwise_i16x8_u_i32x4, "V4UiV8Us", "nc", "

TARGET_BUILTIN(__builtin_wasm_bitselect, "V4iV4iV4iV4i", "nc", "simd128")

TARGET_BUILTIN(__builtin_wasm_signselect_i8x16, "V16ScV16ScV16ScV16Sc", "nc", "simd128")
TARGET_BUILTIN(__builtin_wasm_signselect_i16x8, "V8sV8sV8sV8s", "nc", "simd128")
TARGET_BUILTIN(__builtin_wasm_signselect_i32x4, "V4iV4iV4iV4i", "nc", "simd128")
TARGET_BUILTIN(__builtin_wasm_signselect_i64x2, "V2LLiV2LLiV2LLiV2LLi", "nc", "simd128")

TARGET_BUILTIN(__builtin_wasm_shuffle_v8x16, "V16ScV16ScV16ScIiIiIiIiIiIiIiIiIiIiIiIiIiIiIiIi", "nc", "simd128")

TARGET_BUILTIN(__builtin_wasm_any_true_i8x16, "iV16Sc", "nc", "simd128")
Expand Down Expand Up @@ -188,11 +183,6 @@ TARGET_BUILTIN(__builtin_wasm_dot_s_i32x4_i16x8, "V4iV8sV8s", "nc", "simd128")
TARGET_BUILTIN(__builtin_wasm_sqrt_f32x4, "V4fV4f", "nc", "simd128")
TARGET_BUILTIN(__builtin_wasm_sqrt_f64x2, "V2dV2d", "nc", "simd128")

TARGET_BUILTIN(__builtin_wasm_qfma_f32x4, "V4fV4fV4fV4f", "nc", "simd128")
TARGET_BUILTIN(__builtin_wasm_qfms_f32x4, "V4fV4fV4fV4f", "nc", "simd128")
TARGET_BUILTIN(__builtin_wasm_qfma_f64x2, "V2dV2dV2dV2d", "nc", "simd128")
TARGET_BUILTIN(__builtin_wasm_qfms_f64x2, "V2dV2dV2dV2d", "nc", "simd128")

TARGET_BUILTIN(__builtin_wasm_trunc_saturate_s_i32x4_f32x4, "V4iV4f", "nc", "simd128")
TARGET_BUILTIN(__builtin_wasm_trunc_saturate_u_i32x4_f32x4, "V4iV4f", "nc", "simd128")

Expand All @@ -206,9 +196,6 @@ TARGET_BUILTIN(__builtin_wasm_widen_high_s_i32x4_i64x2, "V2LLiV4i", "nc", "simd1
TARGET_BUILTIN(__builtin_wasm_widen_low_u_i32x4_i64x2, "V2LLUiV4Ui", "nc", "simd128")
TARGET_BUILTIN(__builtin_wasm_widen_high_u_i32x4_i64x2, "V2LLUiV4Ui", "nc", "simd128")

TARGET_BUILTIN(__builtin_wasm_widen_s_i8x16_i32x4, "V4iV16ScIi", "nc", "simd128")
TARGET_BUILTIN(__builtin_wasm_widen_u_i8x16_i32x4, "V4UiV16UcIi", "nc", "simd128")

TARGET_BUILTIN(__builtin_wasm_convert_low_s_i32x4_f64x2, "V2dV4i", "nc", "simd128")
TARGET_BUILTIN(__builtin_wasm_convert_low_u_i32x4_f64x2, "V2dV4Ui", "nc", "simd128")
TARGET_BUILTIN(__builtin_wasm_trunc_saturate_zero_s_f64x2_i32x4, "V4iV2d", "nc", "simd128")
Expand All @@ -230,8 +217,5 @@ TARGET_BUILTIN(__builtin_wasm_store64_lane, "vLLi*V2LLiIi", "n", "simd128")

TARGET_BUILTIN(__builtin_wasm_eq_i64x2, "V2LLiV2LLiV2LLi", "nc", "simd128")

TARGET_BUILTIN(__builtin_wasm_prefetch_t, "vv*", "n", "simd128")
TARGET_BUILTIN(__builtin_wasm_prefetch_nt, "vv*", "n", "simd128")

#undef BUILTIN
#undef TARGET_BUILTIN
64 changes: 0 additions & 64 deletions clang/lib/CodeGen/CGBuiltin.cpp
Expand Up @@ -17366,17 +17366,6 @@ Value *CodeGenFunction::EmitWebAssemblyBuiltinExpr(unsigned BuiltinID,
CGM.getIntrinsic(Intrinsic::wasm_bitselect, ConvertType(E->getType()));
return Builder.CreateCall(Callee, {V1, V2, C});
}
case WebAssembly::BI__builtin_wasm_signselect_i8x16:
case WebAssembly::BI__builtin_wasm_signselect_i16x8:
case WebAssembly::BI__builtin_wasm_signselect_i32x4:
case WebAssembly::BI__builtin_wasm_signselect_i64x2: {
Value *V1 = EmitScalarExpr(E->getArg(0));
Value *V2 = EmitScalarExpr(E->getArg(1));
Value *C = EmitScalarExpr(E->getArg(2));
Function *Callee =
CGM.getIntrinsic(Intrinsic::wasm_signselect, ConvertType(E->getType()));
return Builder.CreateCall(Callee, {V1, V2, C});
}
case WebAssembly::BI__builtin_wasm_dot_s_i32x4_i16x8: {
Value *LHS = EmitScalarExpr(E->getArg(0));
Value *RHS = EmitScalarExpr(E->getArg(1));
Expand Down Expand Up @@ -17444,29 +17433,6 @@ Value *CodeGenFunction::EmitWebAssemblyBuiltinExpr(unsigned BuiltinID,
Function *Callee = CGM.getIntrinsic(Intrinsic::sqrt, Vec->getType());
return Builder.CreateCall(Callee, {Vec});
}
case WebAssembly::BI__builtin_wasm_qfma_f32x4:
case WebAssembly::BI__builtin_wasm_qfms_f32x4:
case WebAssembly::BI__builtin_wasm_qfma_f64x2:
case WebAssembly::BI__builtin_wasm_qfms_f64x2: {
Value *A = EmitScalarExpr(E->getArg(0));
Value *B = EmitScalarExpr(E->getArg(1));
Value *C = EmitScalarExpr(E->getArg(2));
unsigned IntNo;
switch (BuiltinID) {
case WebAssembly::BI__builtin_wasm_qfma_f32x4:
case WebAssembly::BI__builtin_wasm_qfma_f64x2:
IntNo = Intrinsic::wasm_qfma;
break;
case WebAssembly::BI__builtin_wasm_qfms_f32x4:
case WebAssembly::BI__builtin_wasm_qfms_f64x2:
IntNo = Intrinsic::wasm_qfms;
break;
default:
llvm_unreachable("unexpected builtin ID");
}
Function *Callee = CGM.getIntrinsic(IntNo, A->getType());
return Builder.CreateCall(Callee, {A, B, C});
}
case WebAssembly::BI__builtin_wasm_narrow_s_i8x16_i16x8:
case WebAssembly::BI__builtin_wasm_narrow_u_i8x16_i16x8:
case WebAssembly::BI__builtin_wasm_narrow_s_i16x8_i32x4:
Expand Down Expand Up @@ -17515,26 +17481,6 @@ Value *CodeGenFunction::EmitWebAssemblyBuiltinExpr(unsigned BuiltinID,
Function *Callee = CGM.getIntrinsic(IntNo);
return Builder.CreateCall(Callee, Vec);
}
case WebAssembly::BI__builtin_wasm_widen_s_i8x16_i32x4:
case WebAssembly::BI__builtin_wasm_widen_u_i8x16_i32x4: {
Value *Vec = EmitScalarExpr(E->getArg(0));
llvm::APSInt SubVecConst =
*E->getArg(1)->getIntegerConstantExpr(getContext());
Value *SubVec = llvm::ConstantInt::get(getLLVMContext(), SubVecConst);
unsigned IntNo;
switch (BuiltinID) {
case WebAssembly::BI__builtin_wasm_widen_s_i8x16_i32x4:
IntNo = Intrinsic::wasm_widen_signed;
break;
case WebAssembly::BI__builtin_wasm_widen_u_i8x16_i32x4:
IntNo = Intrinsic::wasm_widen_unsigned;
break;
default:
llvm_unreachable("unexpected builtin ID");
}
Function *Callee = CGM.getIntrinsic(IntNo);
return Builder.CreateCall(Callee, {Vec, SubVec});
}
case WebAssembly::BI__builtin_wasm_convert_low_s_i32x4_f64x2:
case WebAssembly::BI__builtin_wasm_convert_low_u_i32x4_f64x2: {
Value *Vec = EmitScalarExpr(E->getArg(0));
Expand Down Expand Up @@ -17649,16 +17595,6 @@ Value *CodeGenFunction::EmitWebAssemblyBuiltinExpr(unsigned BuiltinID,
Function *Callee = CGM.getIntrinsic(Intrinsic::wasm_shuffle);
return Builder.CreateCall(Callee, Ops);
}
case WebAssembly::BI__builtin_wasm_prefetch_t: {
Value *Ptr = EmitScalarExpr(E->getArg(0));
Function *Callee = CGM.getIntrinsic(Intrinsic::wasm_prefetch_t);
return Builder.CreateCall(Callee, Ptr);
}
case WebAssembly::BI__builtin_wasm_prefetch_nt: {
Value *Ptr = EmitScalarExpr(E->getArg(0));
Function *Callee = CGM.getIntrinsic(Intrinsic::wasm_prefetch_nt);
return Builder.CreateCall(Callee, Ptr);
}
default:
return nullptr;
}
Expand Down
78 changes: 0 additions & 78 deletions clang/test/CodeGen/builtins-wasm.c
Expand Up @@ -644,34 +644,6 @@ i32x4 bitselect(i32x4 x, i32x4 y, i32x4 c) {
// WEBASSEMBLY-NEXT: ret
}

i8x16 signselect_i8x16(i8x16 x, i8x16 y, i8x16 c) {
return __builtin_wasm_signselect_i8x16(x, y, c);
// WEBASSEMBLY: call <16 x i8> @llvm.wasm.signselect.v16i8(
// WEBASSEMBLY-SAME: <16 x i8> %x, <16 x i8> %y, <16 x i8> %c)
// WEBASSEMBLY-NEXT: ret
}

i16x8 signselect_i16x8(i16x8 x, i16x8 y, i16x8 c) {
return __builtin_wasm_signselect_i16x8(x, y, c);
// WEBASSEMBLY: call <8 x i16> @llvm.wasm.signselect.v8i16(
// WEBASSEMBLY-SAME: <8 x i16> %x, <8 x i16> %y, <8 x i16> %c)
// WEBASSEMBLY-NEXT: ret
}

i32x4 signselect_i32x4(i32x4 x, i32x4 y, i32x4 c) {
return __builtin_wasm_signselect_i32x4(x, y, c);
// WEBASSEMBLY: call <4 x i32> @llvm.wasm.signselect.v4i32(
// WEBASSEMBLY-SAME: <4 x i32> %x, <4 x i32> %y, <4 x i32> %c)
// WEBASSEMBLY-NEXT: ret
}

i64x2 signselect_i64x2(i64x2 x, i64x2 y, i64x2 c) {
return __builtin_wasm_signselect_i64x2(x, y, c);
// WEBASSEMBLY: call <2 x i64> @llvm.wasm.signselect.v2i64(
// WEBASSEMBLY-SAME: <2 x i64> %x, <2 x i64> %y, <2 x i64> %c)
// WEBASSEMBLY-NEXT: ret
}

i8x16 popcnt(i8x16 x) {
return __builtin_wasm_popcnt_i8x16(x);
// WEBASSEMBLY: call <16 x i8> @llvm.wasm.popcnt(<16 x i8> %x)
Expand Down Expand Up @@ -884,34 +856,6 @@ f64x2 sqrt_f64x2(f64x2 x) {
// WEBASSEMBLY: ret
}

f32x4 qfma_f32x4(f32x4 a, f32x4 b, f32x4 c) {
return __builtin_wasm_qfma_f32x4(a, b, c);
// WEBASSEMBLY: call <4 x float> @llvm.wasm.qfma.v4f32(
// WEBASSEMBLY-SAME: <4 x float> %a, <4 x float> %b, <4 x float> %c)
// WEBASSEMBLY-NEXT: ret
}

f32x4 qfms_f32x4(f32x4 a, f32x4 b, f32x4 c) {
return __builtin_wasm_qfms_f32x4(a, b, c);
// WEBASSEMBLY: call <4 x float> @llvm.wasm.qfms.v4f32(
// WEBASSEMBLY-SAME: <4 x float> %a, <4 x float> %b, <4 x float> %c)
// WEBASSEMBLY-NEXT: ret
}

f64x2 qfma_f64x2(f64x2 a, f64x2 b, f64x2 c) {
return __builtin_wasm_qfma_f64x2(a, b, c);
// WEBASSEMBLY: call <2 x double> @llvm.wasm.qfma.v2f64(
// WEBASSEMBLY-SAME: <2 x double> %a, <2 x double> %b, <2 x double> %c)
// WEBASSEMBLY-NEXT: ret
}

f64x2 qfms_f64x2(f64x2 a, f64x2 b, f64x2 c) {
return __builtin_wasm_qfms_f64x2(a, b, c);
// WEBASSEMBLY: call <2 x double> @llvm.wasm.qfms.v2f64(
// WEBASSEMBLY-SAME: <2 x double> %a, <2 x double> %b, <2 x double> %c)
// WEBASSEMBLY-NEXT: ret
}

i32x4 trunc_saturate_s_i32x4_f32x4(f32x4 f) {
return __builtin_wasm_trunc_saturate_s_i32x4_f32x4(f);
// WEBASSEMBLY: call <4 x i32> @llvm.wasm.trunc.saturate.signed.v4i32.v4f32(<4 x float> %f)
Expand Down Expand Up @@ -976,18 +920,6 @@ u64x2 widen_high_u_i32x4_i64x2(u32x4 x) {
// WEBASSEMBLY: ret
}

i32x4 widen_s_i8x16_i32x4(i8x16 x) {
return __builtin_wasm_widen_s_i8x16_i32x4(x, 3);
// WEBASSEMBLY: call <4 x i32> @llvm.wasm.widen.signed(<16 x i8> %x, i32 3)
// WEBASSEMBLY: ret
}

u32x4 widen_u_i8x16_i32x4(u8x16 x) {
return __builtin_wasm_widen_u_i8x16_i32x4(x, 3);
// WEBASSEMBLY: call <4 x i32> @llvm.wasm.widen.unsigned(<16 x i8> %x, i32 3)
// WEBASSEMBLY: ret
}

f64x2 convert_low_s_i32x4_f64x2(i32x4 x) {
return __builtin_wasm_convert_low_s_i32x4_f64x2(x);
// WEBASSEMBLY: call <2 x double> @llvm.wasm.convert.low.signed(<4 x i32> %x)
Expand Down Expand Up @@ -1050,13 +982,3 @@ i8x16 shuffle(i8x16 x, i8x16 y) {
// WEBASSEMBLY-SAME: i32 15
// WEBASSEMBLY-NEXT: ret
}

void prefetch_t(void *p) {
return __builtin_wasm_prefetch_t(p);
// WEBASSEMBLY: call void @llvm.wasm.prefetch.t(i8* %p)
}

void prefetch_nt(void *p) {
return __builtin_wasm_prefetch_nt(p);
// WEBASSEMBLY: call void @llvm.wasm.prefetch.nt(i8* %p)
}
35 changes: 0 additions & 35 deletions llvm/include/llvm/IR/IntrinsicsWebAssembly.td
Expand Up @@ -143,14 +143,6 @@ def int_wasm_bitmask :
Intrinsic<[llvm_i32_ty],
[llvm_anyvector_ty],
[IntrNoMem, IntrSpeculatable]>;
def int_wasm_qfma :
Intrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
[IntrNoMem, IntrSpeculatable]>;
def int_wasm_qfms :
Intrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
[IntrNoMem, IntrSpeculatable]>;
def int_wasm_dot :
Intrinsic<[llvm_v4i32_ty],
[llvm_v8i16_ty, llvm_v8i16_ty],
Expand Down Expand Up @@ -302,32 +294,13 @@ def int_wasm_extadd_pairwise_unsigned :
[LLVMSubdivide2VectorType<0>],
[IntrNoMem, IntrSpeculatable]>;

def int_wasm_signselect :
Intrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
[IntrNoMem, IntrSpeculatable]>;

// TODO: Remove this intrinsic and the associated builtin if i64x2.eq gets
// merged to the proposal.
def int_wasm_eq :
Intrinsic<[llvm_v2i64_ty],
[llvm_v2i64_ty, llvm_v2i64_ty],
[IntrNoMem, IntrSpeculatable]>;

// TODO: Remove this after experiments have been run. Use the target-agnostic
// int_prefetch if this becomes specified at some point.
def int_wasm_prefetch_t :
Intrinsic<[], [llvm_ptr_ty],
[IntrInaccessibleMemOrArgMemOnly, IntrWillReturn,
ReadOnly<ArgIndex<0>>, NoCapture<ArgIndex<0>>],
"", [SDNPMemOperand]>;

def int_wasm_prefetch_nt :
Intrinsic<[], [llvm_ptr_ty],
[IntrInaccessibleMemOrArgMemOnly, IntrWillReturn,
ReadOnly<ArgIndex<0>>, NoCapture<ArgIndex<0>>],
"", [SDNPMemOperand]>;

// TODO: Remove these if possible if they are merged to the spec.
def int_wasm_convert_low_signed :
Intrinsic<[llvm_v2f64_ty], [llvm_v4i32_ty],
Expand All @@ -348,14 +321,6 @@ def int_wasm_promote_low :
Intrinsic<[llvm_v2f64_ty], [llvm_v4f32_ty],
[IntrNoMem, IntrSpeculatable]>;

// TODO: Remove these if possible if they are merged to the spec.
def int_wasm_widen_signed :
Intrinsic<[llvm_v4i32_ty], [llvm_v16i8_ty, llvm_i32_ty],
[IntrNoMem, IntrSpeculatable, ImmArg<ArgIndex<1>>]>;
def int_wasm_widen_unsigned :
Intrinsic<[llvm_v4i32_ty], [llvm_v16i8_ty, llvm_i32_ty],
[IntrNoMem, IntrSpeculatable, ImmArg<ArgIndex<1>>]>;

//===----------------------------------------------------------------------===//
// Thread-local storage intrinsics
//===----------------------------------------------------------------------===//
Expand Down
Expand Up @@ -196,8 +196,6 @@ inline unsigned GetDefaultP2AlignAny(unsigned Opc) {
WASM_LOAD_STORE(LOAD8_SPLAT)
WASM_LOAD_STORE(LOAD_LANE_I8x16)
WASM_LOAD_STORE(STORE_LANE_I8x16)
WASM_LOAD_STORE(PREFETCH_T)
WASM_LOAD_STORE(PREFETCH_NT)
return 0;
WASM_LOAD_STORE(LOAD16_S_I32)
WASM_LOAD_STORE(LOAD16_U_I32)
Expand Down
10 changes: 0 additions & 10 deletions llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
Expand Up @@ -761,16 +761,6 @@ bool WebAssemblyTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
Info.align = MemAlign;
return true;
}
case Intrinsic::wasm_prefetch_t:
case Intrinsic::wasm_prefetch_nt: {
Info.opc = ISD::INTRINSIC_VOID;
Info.memVT = MVT::i8;
Info.ptrVal = I.getArgOperand(0);
Info.offset = 0;
Info.align = Align(1);
Info.flags = MachineMemOperand::MOLoad;
return true;
}
default:
return false;
}
Expand Down

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