diff --git a/llvm/lib/Target/AArch64/AArch64InstrGISel.td b/llvm/lib/Target/AArch64/AArch64InstrGISel.td
index 0bd8a206705d3..6b7754d60ded7 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrGISel.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrGISel.td
@@ -30,6 +30,7 @@ def G_ADD_LOW : AArch64GenericInstruction {
 def G_REV16 : AArch64GenericInstruction {
   let OutOperandList = (outs type0:$dst);
   let InOperandList = (ins type0:$src);
+  let hasSideEffects = 0;
 }
 
 // Pseudo for a rev32 instruction. Produced post-legalization from
@@ -37,6 +38,7 @@ def G_REV16 : AArch64GenericInstruction {
 def G_REV32 : AArch64GenericInstruction {
   let OutOperandList = (outs type0:$dst);
   let InOperandList = (ins type0:$src);
+  let hasSideEffects = 0;
 }
 
 // Pseudo for a rev64 instruction. Produced post-legalization from
@@ -44,6 +46,7 @@ def G_REV32 : AArch64GenericInstruction {
 def G_REV64 : AArch64GenericInstruction {
   let OutOperandList = (outs type0:$dst);
   let InOperandList = (ins type0:$src);
+  let hasSideEffects = 0;
 }
 
 // Represents an uzp1 instruction. Produced post-legalization from
@@ -51,6 +54,7 @@ def G_REV64 : AArch64GenericInstruction {
 def G_UZP1 : AArch64GenericInstruction {
   let OutOperandList = (outs type0:$dst);
   let InOperandList = (ins type0:$v1, type0:$v2);
+  let hasSideEffects = 0;
 }
 
 // Represents an uzp2 instruction. Produced post-legalization from
@@ -58,6 +62,7 @@ def G_UZP1 : AArch64GenericInstruction {
 def G_UZP2 : AArch64GenericInstruction {
   let OutOperandList = (outs type0:$dst);
   let InOperandList = (ins type0:$v1, type0:$v2);
+  let hasSideEffects = 0;
 }
 
 // Represents a zip1 instruction. Produced post-legalization from
@@ -65,6 +70,7 @@ def G_UZP2 : AArch64GenericInstruction {
 def G_ZIP1 : AArch64GenericInstruction {
   let OutOperandList = (outs type0:$dst);
   let InOperandList = (ins type0:$v1, type0:$v2);
+  let hasSideEffects = 0;
 }
 
 // Represents a zip2 instruction. Produced post-legalization from
@@ -72,6 +78,7 @@ def G_ZIP1 : AArch64GenericInstruction {
 def G_ZIP2 : AArch64GenericInstruction {
   let OutOperandList = (outs type0:$dst);
   let InOperandList = (ins type0:$v1, type0:$v2);
+  let hasSideEffects = 0;
 }
 
 // Represents a dup instruction. Produced post-legalization from
@@ -79,12 +86,14 @@ def G_ZIP2 : AArch64GenericInstruction {
 def G_DUP: AArch64GenericInstruction {
   let OutOperandList = (outs type0:$dst);
   let InOperandList = (ins type1:$lane);
+  let hasSideEffects = 0;
 }
 // Represents a trn1 instruction. Produced post-legalization from
 // G_SHUFFLE_VECTORs with appropriate masks.
 def G_TRN1 : AArch64GenericInstruction {
   let OutOperandList = (outs type0:$dst);
   let InOperandList = (ins type0:$v1, type0:$v2);
+  let hasSideEffects = 0;
 }
 
 // Represents a trn2 instruction. Produced post-legalization from
@@ -92,6 +101,7 @@ def G_TRN1 : AArch64GenericInstruction {
 def G_TRN2 : AArch64GenericInstruction {
   let OutOperandList = (outs type0:$dst);
   let InOperandList = (ins type0:$v1, type0:$v2);
+  let hasSideEffects = 0;
 }
 
 def : GINodeEquiv<G_REV16, AArch64rev16>;
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-rev.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-rev.mir
index d3dd8a97e6f4e..e2779dfd84fda 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-rev.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-rev.mir
@@ -24,10 +24,12 @@ body:             |
     ; CHECK: liveins: $d0
     ; CHECK: %copy:fpr64 = COPY $d0
     ; CHECK: %rev:fpr64 = REV64v2i32 %copy
-    ; CHECK: RET_ReallyLR
+    ; CHECK: $d0 = COPY %rev
+    ; CHECK: RET_ReallyLR implicit $d0
     %copy:fpr(<2 x s32>) = COPY $d0
     %rev:fpr(<2 x s32>) = G_REV64 %copy
-    RET_ReallyLR
+    $d0 = COPY %rev(<2 x s32>)
+    RET_ReallyLR implicit $d0
 
 ...
 ---
@@ -43,10 +45,12 @@ body:             |
     ; CHECK: liveins: $d0
     ; CHECK: %copy:fpr64 = COPY $d0
     ; CHECK: %rev:fpr64 = REV64v4i16 %copy
-    ; CHECK: RET_ReallyLR
+    ; CHECK: $d0 = COPY %rev
+    ; CHECK: RET_ReallyLR implicit $d0
     %copy:fpr(<4 x s16>) = COPY $d0
     %rev:fpr(<4 x s16>) = G_REV64 %copy
-    RET_ReallyLR
+    $d0 = COPY %rev(<4 x s16>)
+    RET_ReallyLR implicit $d0
 
 ...
 ---
@@ -62,10 +66,12 @@ body:             |
     ; CHECK: liveins: $q0
     ; CHECK: %copy:fpr128 = COPY $q0
     ; CHECK: %rev:fpr128 = REV64v4i32 %copy
-    ; CHECK: RET_ReallyLR
+    ; CHECK: $q0 = COPY %rev
+    ; CHECK: RET_ReallyLR implicit $q0
     %copy:fpr(<4 x s32>) = COPY $q0
     %rev:fpr(<4 x s32>) = G_REV64 %copy
-    RET_ReallyLR
+    $q0 = COPY %rev(<4 x s32>)
+    RET_ReallyLR implicit $q0
 
 ...
 ---
@@ -81,10 +87,12 @@ body:             |
     ; CHECK: liveins: $q0
     ; CHECK: %copy:fpr64 = COPY $d0
     ; CHECK: %rev:fpr64 = REV64v8i8 %copy
-    ; CHECK: RET_ReallyLR
+    ; CHECK: $d0 = COPY %rev
+    ; CHECK: RET_ReallyLR implicit $d0
     %copy:fpr(<8 x s8>) = COPY $d0
     %rev:fpr(<8 x s8>) = G_REV64 %copy
-    RET_ReallyLR
+    $d0 = COPY %rev(<8 x s8>)
+    RET_ReallyLR implicit $d0
 
 ...
 ---
@@ -100,10 +108,12 @@ body:             |
     ; CHECK: liveins: $q0
     ; CHECK: %copy:fpr128 = COPY $q0
     ; CHECK: %rev:fpr128 = REV64v8i16 %copy
-    ; CHECK: RET_ReallyLR
+    ; CHECK: $q0 = COPY %rev
+    ; CHECK: RET_ReallyLR implicit $q0
     %copy:fpr(<8 x s16>) = COPY $q0
     %rev:fpr(<8 x s16>) = G_REV64 %copy
-    RET_ReallyLR
+    $q0 = COPY %rev(<8 x s16>)
+    RET_ReallyLR implicit $q0
 
 ...
 ---
@@ -119,10 +129,12 @@ body:             |
     ; CHECK: liveins: $q0
     ; CHECK: %copy:fpr128 = COPY $q0
     ; CHECK: %rev:fpr128 = REV64v16i8 %copy
-    ; CHECK: RET_ReallyLR
+    ; CHECK: $q0 = COPY %rev
+    ; CHECK: RET_ReallyLR implicit $q0
     %copy:fpr(<16 x s8>) = COPY $q0
     %rev:fpr(<16 x s8>) = G_REV64 %copy
-    RET_ReallyLR
+    $q0 = COPY %rev(<16 x s8>)
+    RET_ReallyLR implicit $q0
 
 ...
 ---
@@ -138,10 +150,12 @@ body:             |
     ; CHECK: liveins: $d0
     ; CHECK: %copy:fpr64 = COPY $d0
     ; CHECK: %rev:fpr64 = REV32v4i16 %copy
-    ; CHECK: RET_ReallyLR
+    ; CHECK: $d0 = COPY %rev
+    ; CHECK: RET_ReallyLR implicit $d0
     %copy:fpr(<4 x s16>) = COPY $d0
     %rev:fpr(<4 x s16>) = G_REV32 %copy
-    RET_ReallyLR
+    $d0 = COPY %rev(<4 x s16>)
+    RET_ReallyLR implicit $d0
 
 ...
 ---
@@ -157,10 +171,12 @@ body:             |
     ; CHECK: liveins: $d0
     ; CHECK: %copy:fpr64 = COPY $d0
     ; CHECK: %rev:fpr64 = REV32v8i8 %copy
-    ; CHECK: RET_ReallyLR
+    ; CHECK: $d0 = COPY %rev
+    ; CHECK: RET_ReallyLR implicit $d0
     %copy:fpr(<8 x s8>) = COPY $d0
     %rev:fpr(<8 x s8>) = G_REV32 %copy
-    RET_ReallyLR
+    $d0 = COPY %rev(<8 x s8>)
+    RET_ReallyLR implicit $d0
 
 ...
 ---
@@ -176,10 +192,12 @@ body:             |
     ; CHECK: liveins: $q0
     ; CHECK: %copy:fpr128 = COPY $q0
     ; CHECK: %rev:fpr128 = REV32v8i16 %copy
-    ; CHECK: RET_ReallyLR
+    ; CHECK: $q0 = COPY %rev
+    ; CHECK: RET_ReallyLR implicit $q0
     %copy:fpr(<8 x s16>) = COPY $q0
     %rev:fpr(<8 x s16>) = G_REV32 %copy
-    RET_ReallyLR
+    $q0 = COPY %rev(<8 x s16>)
+    RET_ReallyLR implicit $q0
 
 ...
 ---
@@ -195,10 +213,12 @@ body:             |
     ; CHECK: liveins: $q0
     ; CHECK: %copy:fpr128 = COPY $q0
     ; CHECK: %rev:fpr128 = REV32v16i8 %copy
-    ; CHECK: RET_ReallyLR
+    ; CHECK: $q0 = COPY %rev
+    ; CHECK: RET_ReallyLR implicit $q0
     %copy:fpr(<16 x s8>) = COPY $q0
     %rev:fpr(<16 x s8>) = G_REV32 %copy
-    RET_ReallyLR
+    $q0 = COPY %rev(<16 x s8>)
+    RET_ReallyLR implicit $q0
 
 ...
 ---
@@ -214,10 +234,12 @@ body:             |
     ; CHECK: liveins: $q0
     ; CHECK: %copy:fpr64 = COPY $d0
     ; CHECK: %rev:fpr64 = REV16v8i8 %copy
-    ; CHECK: RET_ReallyLR
+    ; CHECK: $d0 = COPY %rev
+    ; CHECK: RET_ReallyLR implicit $d0
     %copy:fpr(<8 x s8>) = COPY $d0
     %rev:fpr(<8 x s8>) = G_REV16 %copy
-    RET_ReallyLR
+    $d0 = COPY %rev(<8 x s8>)
+    RET_ReallyLR implicit $d0
 
 ...
 ---
@@ -233,7 +255,9 @@ body:             |
     ; CHECK: liveins: $q0
     ; CHECK: %copy:fpr128 = COPY $q0
     ; CHECK: %rev:fpr128 = REV16v16i8 %copy
-    ; CHECK: RET_ReallyLR
+    ; CHECK: $q0 = COPY %rev
+    ; CHECK: RET_ReallyLR implicit $q0
     %copy:fpr(<16 x s8>) = COPY $q0
     %rev:fpr(<16 x s8>) = G_REV16 %copy
-    RET_ReallyLR
+    $q0 = COPY %rev(<16 x s8>)
+    RET_ReallyLR implicit $q0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-trn.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-trn.mir
index 738aacf2c372c..be735c15fd916 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-trn.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-trn.mir
@@ -20,11 +20,13 @@ body:             |
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
     ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
     ; CHECK: [[TRN1v2i32_:%[0-9]+]]:fpr64 = TRN1v2i32 [[COPY]], [[COPY1]]
-    ; CHECK: RET_ReallyLR
+    ; CHECK: $d0 = COPY [[TRN1v2i32_]]
+    ; CHECK: RET_ReallyLR implicit $d0
     %0:fpr(<2 x s32>) = COPY $d0
     %1:fpr(<2 x s32>) = COPY $d1
     %2:fpr(<2 x s32>) = G_TRN1 %0, %1
-    RET_ReallyLR
+    $d0 = COPY %2(<2 x s32>)
+    RET_ReallyLR implicit $d0
 
 ...
 ---
@@ -41,11 +43,13 @@ body:             |
     ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
     ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
     ; CHECK: [[TRN1v2i64_:%[0-9]+]]:fpr128 = TRN1v2i64 [[COPY]], [[COPY1]]
-    ; CHECK: RET_ReallyLR
+    ; CHECK: $q0 = COPY [[TRN1v2i64_]]
+    ; CHECK: RET_ReallyLR implicit $q0
     %0:fpr(<2 x s64>) = COPY $q0
     %1:fpr(<2 x s64>) = COPY $q1
     %2:fpr(<2 x s64>) = G_TRN1 %0, %1
-    RET_ReallyLR
+    $q0 = COPY %2(<2 x s64>)
+    RET_ReallyLR implicit $q0
 
 ...
 ---
@@ -62,11 +66,13 @@ body:             |
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
     ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
     ; CHECK: [[TRN1v4i16_:%[0-9]+]]:fpr64 = TRN1v4i16 [[COPY]], [[COPY1]]
-    ; CHECK: RET_ReallyLR
+    ; CHECK: $d0 = COPY [[TRN1v4i16_]]
+    ; CHECK: RET_ReallyLR implicit $d0
     %0:fpr(<4 x s16>) = COPY $d0
     %1:fpr(<4 x s16>) = COPY $d1
     %2:fpr(<4 x s16>) = G_TRN1 %0, %1
-    RET_ReallyLR
+    $d0 = COPY %2(<4 x s16>)
+    RET_ReallyLR implicit $d0
 
 ...
 ---
@@ -83,11 +89,13 @@ body:             |
     ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
     ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
     ; CHECK: [[TRN1v4i32_:%[0-9]+]]:fpr128 = TRN1v4i32 [[COPY]], [[COPY1]]
-    ; CHECK: RET_ReallyLR
+    ; CHECK: $q0 = COPY [[TRN1v4i32_]]
+    ; CHECK: RET_ReallyLR implicit $q0
     %0:fpr(<4 x s32>) = COPY $q0
     %1:fpr(<4 x s32>) = COPY $q1
     %2:fpr(<4 x s32>) = G_TRN1 %0, %1
-    RET_ReallyLR
+    $q0 = COPY %2(<4 x s32>)
+    RET_ReallyLR implicit $q0
 
 ...
 ---
@@ -104,11 +112,13 @@ body:             |
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
     ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
     ; CHECK: [[TRN1v8i8_:%[0-9]+]]:fpr64 = TRN1v8i8 [[COPY]], [[COPY1]]
-    ; CHECK: RET_ReallyLR
+    ; CHECK: $d0 = COPY [[TRN1v8i8_]]
+    ; CHECK: RET_ReallyLR implicit $d0
     %0:fpr(<8 x s8>) = COPY $d0
     %1:fpr(<8 x s8>) = COPY $d1
     %2:fpr(<8 x s8>) = G_TRN1 %0, %1
-    RET_ReallyLR
+    $d0 = COPY %2(<8 x s8>)
+    RET_ReallyLR implicit $d0
 
 ...
 ---
@@ -125,11 +135,13 @@ body:             |
     ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
     ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
     ; CHECK: [[TRN1v8i16_:%[0-9]+]]:fpr128 = TRN1v8i16 [[COPY]], [[COPY1]]
-    ; CHECK: RET_ReallyLR
+    ; CHECK: $q0 = COPY [[TRN1v8i16_]]
+    ; CHECK: RET_ReallyLR implicit $q0
     %0:fpr(<8 x s16>) = COPY $q0
     %1:fpr(<8 x s16>) = COPY $q1
     %2:fpr(<8 x s16>) = G_TRN1 %0, %1
-    RET_ReallyLR
+    $q0 = COPY %2(<8 x s16>)
+    RET_ReallyLR implicit $q0
 
 ...
 ---
@@ -146,11 +158,13 @@ body:             |
     ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
     ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
     ; CHECK: [[TRN1v16i8_:%[0-9]+]]:fpr128 = TRN1v16i8 [[COPY]], [[COPY1]]
-    ; CHECK: RET_ReallyLR
+    ; CHECK: $q0 = COPY [[TRN1v16i8_]]
+    ; CHECK: RET_ReallyLR implicit $q0
     %0:fpr(<16 x s8>) = COPY $q0
     %1:fpr(<16 x s8>) = COPY $q1
     %2:fpr(<16 x s8>) = G_TRN1 %0, %1
-    RET_ReallyLR
+    $q0 = COPY %2(<16 x s8>)
+    RET_ReallyLR implicit $q0
 
 ...
 ---
@@ -167,11 +181,13 @@ body:             |
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
     ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
     ; CHECK: [[TRN2v2i32_:%[0-9]+]]:fpr64 = TRN2v2i32 [[COPY]], [[COPY1]]
-    ; CHECK: RET_ReallyLR
+    ; CHECK: $d0 = COPY [[TRN2v2i32_]]
+    ; CHECK: RET_ReallyLR implicit $d0
     %0:fpr(<2 x s32>) = COPY $d0
     %1:fpr(<2 x s32>) = COPY $d1
     %2:fpr(<2 x s32>) = G_TRN2 %0, %1
-    RET_ReallyLR
+    $d0 = COPY %2(<2 x s32>)
+    RET_ReallyLR implicit $d0
 
 ...
 ---
@@ -188,11 +204,13 @@ body:             |
     ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
     ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
     ; CHECK: [[TRN2v2i64_:%[0-9]+]]:fpr128 = TRN2v2i64 [[COPY]], [[COPY1]]
-    ; CHECK: RET_ReallyLR
+    ; CHECK: $q0 = COPY [[TRN2v2i64_]]
+    ; CHECK: RET_ReallyLR implicit $q0
     %0:fpr(<2 x s64>) = COPY $q0
     %1:fpr(<2 x s64>) = COPY $q1
     %2:fpr(<2 x s64>) = G_TRN2 %0, %1
-    RET_ReallyLR
+    $q0 = COPY %2(<2 x s64>)
+    RET_ReallyLR implicit $q0
 
 ...
 ---
@@ -209,11 +227,13 @@ body:             |
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
     ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
     ; CHECK: [[TRN2v4i16_:%[0-9]+]]:fpr64 = TRN2v4i16 [[COPY]], [[COPY1]]
-    ; CHECK: RET_ReallyLR
+    ; CHECK: $d0 = COPY [[TRN2v4i16_]]
+    ; CHECK: RET_ReallyLR implicit $d0
     %0:fpr(<4 x s16>) = COPY $d0
     %1:fpr(<4 x s16>) = COPY $d1
     %2:fpr(<4 x s16>) = G_TRN2 %0, %1
-    RET_ReallyLR
+    $d0 = COPY %2(<4 x s16>)
+    RET_ReallyLR implicit $d0
 
 ...
 ---
@@ -230,11 +250,13 @@ body:             |
     ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
     ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
     ; CHECK: [[TRN2v4i32_:%[0-9]+]]:fpr128 = TRN2v4i32 [[COPY]], [[COPY1]]
-    ; CHECK: RET_ReallyLR
+    ; CHECK: $q0 = COPY [[TRN2v4i32_]]
+    ; CHECK: RET_ReallyLR implicit $q0
     %0:fpr(<4 x s32>) = COPY $q0
     %1:fpr(<4 x s32>) = COPY $q1
     %2:fpr(<4 x s32>) = G_TRN2 %0, %1
-    RET_ReallyLR
+    $q0 = COPY %2(<4 x s32>)
+    RET_ReallyLR implicit $q0
 
 ...
 ---
@@ -251,11 +273,13 @@ body:             |
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
     ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
     ; CHECK: [[TRN2v8i8_:%[0-9]+]]:fpr64 = TRN2v8i8 [[COPY]], [[COPY1]]
-    ; CHECK: RET_ReallyLR
+    ; CHECK: $d0 = COPY [[TRN2v8i8_]]
+    ; CHECK: RET_ReallyLR implicit $d0
     %0:fpr(<8 x s8>) = COPY $d0
     %1:fpr(<8 x s8>) = COPY $d1
     %2:fpr(<8 x s8>) = G_TRN2 %0, %1
-    RET_ReallyLR
+    $d0 = COPY %2(<8 x s8>)
+    RET_ReallyLR implicit $d0
 
 ...
 ---
@@ -272,11 +296,13 @@ body:             |
     ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
     ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
     ; CHECK: [[TRN2v8i16_:%[0-9]+]]:fpr128 = TRN2v8i16 [[COPY]], [[COPY1]]
-    ; CHECK: RET_ReallyLR
+    ; CHECK: $q0 = COPY [[TRN2v8i16_]]
+    ; CHECK: RET_ReallyLR implicit $q0
     %0:fpr(<8 x s16>) = COPY $q0
     %1:fpr(<8 x s16>) = COPY $q1
     %2:fpr(<8 x s16>) = G_TRN2 %0, %1
-    RET_ReallyLR
+    $q0 = COPY %2(<8 x s16>)
+    RET_ReallyLR implicit $q0
 
 ...
 ---
@@ -293,8 +319,10 @@ body:             |
     ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
     ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
     ; CHECK: [[TRN2v16i8_:%[0-9]+]]:fpr128 = TRN2v16i8 [[COPY]], [[COPY1]]
-    ; CHECK: RET_ReallyLR
+    ; CHECK: $q0 = COPY [[TRN2v16i8_]]
+    ; CHECK: RET_ReallyLR implicit $q0
     %0:fpr(<16 x s8>) = COPY $q0
     %1:fpr(<16 x s8>) = COPY $q1
     %2:fpr(<16 x s8>) = G_TRN2 %0, %1
-    RET_ReallyLR
+    $q0 = COPY %2(<16 x s8>)
+    RET_ReallyLR implicit $q0