From 30673299d45e667c5a0ffcbc632a78ca53dc1eea Mon Sep 17 00:00:00 2001 From: David Green Date: Sun, 17 Mar 2019 16:00:21 +0000 Subject: [PATCH] [ARM] Add some CBZ constant island tests. NFC llvm-svn: 356335 --- .../CodeGen/Thumb2/constant-islands-cbz.ll | 68 +++++ .../CodeGen/Thumb2/constant-islands-cbz.mir | 280 ++++++++++++++++++ 2 files changed, 348 insertions(+) create mode 100644 llvm/test/CodeGen/Thumb2/constant-islands-cbz.ll create mode 100644 llvm/test/CodeGen/Thumb2/constant-islands-cbz.mir diff --git a/llvm/test/CodeGen/Thumb2/constant-islands-cbz.ll b/llvm/test/CodeGen/Thumb2/constant-islands-cbz.ll new file mode 100644 index 0000000000000..b27815ee50233 --- /dev/null +++ b/llvm/test/CodeGen/Thumb2/constant-islands-cbz.ll @@ -0,0 +1,68 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=thumbv8m.base-none-eabi %s -o - | FileCheck %s --check-prefix=CHECK-T1 +; RUN: llc < %s -mtriple=thumbv8m.main-none-eabi %s -o - | FileCheck %s --check-prefix=CHECK-T2 + +define i32* @test(i32* returned %this, i32 %event_size, i8* %event_pointer) { +; CHECK-T1-LABEL: test: +; CHECK-T1: @ %bb.0: @ %entry +; CHECK-T1-NEXT: .save {r4, lr} +; CHECK-T1-NEXT: push {r4, lr} +; CHECK-T1-NEXT: mov r4, r0 +; CHECK-T1-NEXT: movs r0, #0 +; CHECK-T1-NEXT: str r0, [r4, #4] +; CHECK-T1-NEXT: str r0, [r4, #8] +; CHECK-T1-NEXT: str r0, [r4, #12] +; CHECK-T1-NEXT: str r0, [r4, #16] +; CHECK-T1-NEXT: mov r0, r4 +; CHECK-T1-NEXT: cbz r2, .LBB0_2 +; CHECK-T1-NEXT: @ %bb.1: @ %if.else +; CHECK-T1-NEXT: bl equeue_create_inplace +; CHECK-T1-NEXT: mov r0, r4 +; CHECK-T1-NEXT: pop {r4, pc} +; CHECK-T1-NEXT: .LBB0_2: @ %if.then +; CHECK-T1-NEXT: bl equeue_create +; CHECK-T1-NEXT: mov r0, r4 +; CHECK-T1-NEXT: pop {r4, pc} +; +; CHECK-T2-LABEL: test: +; CHECK-T2: @ %bb.0: @ %entry +; CHECK-T2-NEXT: .save {r4, lr} +; CHECK-T2-NEXT: push {r4, lr} +; CHECK-T2-NEXT: mov r4, r0 +; CHECK-T2-NEXT: movs r0, #0 +; CHECK-T2-NEXT: strd r0, r0, [r4, #4] +; CHECK-T2-NEXT: cmp r2, #0 +; CHECK-T2-NEXT: strd r0, r0, [r4, #12] +; CHECK-T2-NEXT: mov r0, r4 +; CHECK-T2-NEXT: beq .LBB0_2 +; CHECK-T2-NEXT: @ %bb.1: @ %if.else +; CHECK-T2-NEXT: bl equeue_create_inplace +; CHECK-T2-NEXT: mov r0, r4 +; CHECK-T2-NEXT: pop {r4, pc} +; CHECK-T2-NEXT: .LBB0_2: @ %if.then +; CHECK-T2-NEXT: bl equeue_create +; CHECK-T2-NEXT: mov r0, r4 +; CHECK-T2-NEXT: pop {r4, pc} +entry: + %_update = getelementptr inbounds i32, i32* %this, i32 1 + %0 = bitcast i32* %_update to i8* + tail call void @llvm.memset.p0i8.i32(i8* nonnull align 4 %0, i8 0, i32 16, i1 false) #4 + %tobool = icmp eq i8* %event_pointer, null + %_equeue5 = getelementptr inbounds i32, i32* %this, i32 0 + br i1 %tobool, label %if.then, label %if.else + +if.then: ; preds = %entry + %call4 = tail call i32 @equeue_create(i32* %_equeue5, i32 %event_size) #5 + br label %if.end + +if.else: ; preds = %entry + %call6 = tail call i32 @equeue_create_inplace(i32* %_equeue5, i32 %event_size, i8* nonnull %event_pointer) #5 + br label %if.end + +if.end: ; preds = %if.else, %if.then + ret i32* %this +} + +declare dso_local i32 @equeue_create(i32*, i32) local_unnamed_addr #1 +declare dso_local i32 @equeue_create_inplace(i32*, i32, i8*) local_unnamed_addr #1 +declare void @llvm.memset.p0i8.i32(i8* nocapture writeonly, i8, i32, i1 immarg) #2 diff --git a/llvm/test/CodeGen/Thumb2/constant-islands-cbz.mir b/llvm/test/CodeGen/Thumb2/constant-islands-cbz.mir new file mode 100644 index 0000000000000..f94c141e23341 --- /dev/null +++ b/llvm/test/CodeGen/Thumb2/constant-islands-cbz.mir @@ -0,0 +1,280 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=thumbv7m-none-eabi -run-pass=arm-cp-islands -o - %s | FileCheck %s + +--- | + define i32* @test_simple(i32* %x, i32 %y) { ret i32* %x } + define i32* @test_notfirst(i32* %x, i32 %y) { ret i32* %x } + define i32* @test_redefined(i32* %x, i32 %y) { ret i32* %x } + define i32* @test_notredefined(i32* %x, i32 %y) { ret i32* %x } + define i32* @test_notcmp(i32* %x, i32 %y) { ret i32* %x } + define i32* @test_killflag_1(i32* %x, i32 %y) { ret i32* %x } + define i32* @test_killflag_2(i32* %x, i32 %y) { ret i32* %x } + + declare dso_local i32 @c(i32 %x) +... +--- +name: test_simple +tracksRegLiveness: true +liveins: + - { reg: '$r0', virtual-reg: '' } + - { reg: '$r1', virtual-reg: '' } +body: | + ; CHECK-LABEL: name: test_simple + ; CHECK: bb.0: + ; CHECK: successors: %bb.2(0x30000000), %bb.1(0x50000000) + ; CHECK: tCBZ $r0, %bb.2 + ; CHECK: bb.1: + ; CHECK: renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (load 4 from %ir.x) + ; CHECK: tTAILJMPdND @c, 14, $noreg, implicit $sp, implicit $sp, implicit killed $r0 + ; CHECK: bb.2: + ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14, $noreg + ; CHECK: tBX_RET 14, $noreg, implicit killed $r0 + bb.0: + successors: %bb.1(0x30000000), %bb.2(0x50000000) + liveins: $r0, $r1 + + tCMPi8 renamable $r0, 0, 14, $noreg, implicit-def $cpsr + t2Bcc %bb.1, 0, killed $cpsr + + bb.2: + liveins: $r0 + + renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (load 4 from %ir.x) + tTAILJMPdND @c, 14, $noreg, implicit $sp, implicit $sp, implicit killed $r0 + + bb.1: + $r0, dead $cpsr = tMOVi8 0, 14, $noreg + tBX_RET 14, $noreg, implicit killed $r0 + +... +--- +name: test_notfirst +tracksRegLiveness: true +liveins: + - { reg: '$r0', virtual-reg: '' } + - { reg: '$r1', virtual-reg: '' } +body: | + ; CHECK-LABEL: name: test_notfirst + ; CHECK: bb.0: + ; CHECK: successors: %bb.2(0x30000000), %bb.1(0x50000000) + ; CHECK: renamable $r0, $cpsr = tADDrr killed renamable $r0, renamable $r1, 14, $noreg + ; CHECK: tCMPi8 renamable $r0, 0, 14, $noreg, implicit-def $cpsr + ; CHECK: renamable $r1 = t2ADDrs renamable $r0, killed renamable $r1, 18, 14, $noreg, $noreg + ; CHECK: tBcc %bb.2, 0, killed $cpsr + ; CHECK: bb.1: + ; CHECK: renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (load 4 from %ir.x) + ; CHECK: tTAILJMPdND @c, 14, $noreg, implicit $sp, implicit $sp, implicit killed $r0 + ; CHECK: bb.2: + ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14, $noreg + ; CHECK: tBX_RET 14, $noreg, implicit killed $r0 + bb.0: + successors: %bb.1(0x30000000), %bb.2(0x50000000) + liveins: $r0, $r1 + + renamable $r0, $cpsr = tADDrr killed renamable $r0, renamable $r1, 14, $noreg + tCMPi8 renamable $r0, 0, 14, $noreg, implicit-def $cpsr + renamable $r1 = t2ADDrs renamable $r0, killed renamable $r1, 18, 14, $noreg, $noreg + t2Bcc %bb.1, 0, killed $cpsr + + bb.2: + liveins: $r0 + + renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (load 4 from %ir.x) + tTAILJMPdND @c, 14, $noreg, implicit $sp, implicit $sp, implicit killed $r0 + + bb.1: + $r0, dead $cpsr = tMOVi8 0, 14, $noreg + tBX_RET 14, $noreg, implicit killed $r0 + +... +--- +name: test_redefined +tracksRegLiveness: true +liveins: + - { reg: '$r0', virtual-reg: '' } + - { reg: '$r1', virtual-reg: '' } +body: | + ; CHECK-LABEL: name: test_redefined + ; CHECK: bb.0: + ; CHECK: successors: %bb.2(0x30000000), %bb.1(0x50000000) + ; CHECK: tCMPi8 renamable $r0, 0, 14, $noreg, implicit-def $cpsr + ; CHECK: renamable $r0 = t2ADDrs killed renamable $r0, killed renamable $r1, 18, 14, $noreg, $noreg + ; CHECK: tBcc %bb.2, 0, killed $cpsr + ; CHECK: bb.1: + ; CHECK: renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (load 4 from %ir.x) + ; CHECK: tTAILJMPdND @c, 14, $noreg, implicit $sp, implicit $sp, implicit killed $r0 + ; CHECK: bb.2: + ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14, $noreg + ; CHECK: tBX_RET 14, $noreg, implicit killed $r0 + bb.0: + successors: %bb.1(0x30000000), %bb.2(0x50000000) + liveins: $r0, $r1 + + tCMPi8 renamable $r0, 0, 14, $noreg, implicit-def $cpsr + renamable $r0 = t2ADDrs killed renamable $r0, killed renamable $r1, 18, 14, $noreg, $noreg + t2Bcc %bb.1, 0, killed $cpsr + + bb.2: + liveins: $r0 + + renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (load 4 from %ir.x) + tTAILJMPdND @c, 14, $noreg, implicit $sp, implicit $sp, implicit killed $r0 + + bb.1: + $r0, dead $cpsr = tMOVi8 0, 14, $noreg + tBX_RET 14, $noreg, implicit killed $r0 + +... +--- +name: test_notredefined +tracksRegLiveness: true +liveins: + - { reg: '$r0', virtual-reg: '' } + - { reg: '$r1', virtual-reg: '' } +body: | + ; CHECK-LABEL: name: test_notredefined + ; CHECK: bb.0: + ; CHECK: successors: %bb.2(0x30000000), %bb.1(0x50000000) + ; CHECK: tCMPi8 renamable $r0, 0, 14, $noreg, implicit-def $cpsr + ; CHECK: renamable $r1 = t2ADDrs renamable $r0, killed renamable $r1, 18, 14, $noreg, $noreg + ; CHECK: tBcc %bb.2, 0, killed $cpsr + ; CHECK: bb.1: + ; CHECK: renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (load 4 from %ir.x) + ; CHECK: tTAILJMPdND @c, 14, $noreg, implicit $sp, implicit $sp, implicit killed $r0 + ; CHECK: bb.2: + ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14, $noreg + ; CHECK: tBX_RET 14, $noreg, implicit killed $r0 + bb.0: + successors: %bb.1(0x30000000), %bb.2(0x50000000) + liveins: $r0, $r1 + + tCMPi8 renamable $r0, 0, 14, $noreg, implicit-def $cpsr + renamable $r1 = t2ADDrs renamable $r0, killed renamable $r1, 18, 14, $noreg, $noreg + t2Bcc %bb.1, 0, killed $cpsr + + bb.2: + liveins: $r0 + + renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (load 4 from %ir.x) + tTAILJMPdND @c, 14, $noreg, implicit $sp, implicit $sp, implicit killed $r0 + + bb.1: + $r0, dead $cpsr = tMOVi8 0, 14, $noreg + tBX_RET 14, $noreg, implicit killed $r0 + +... +--- +name: test_notcmp +tracksRegLiveness: true +liveins: + - { reg: '$r0', virtual-reg: '' } + - { reg: '$r1', virtual-reg: '' } +body: | + ; CHECK-LABEL: name: test_notcmp + ; CHECK: bb.0: + ; CHECK: successors: %bb.2(0x30000000), %bb.1(0x50000000) + ; CHECK: tCMPi8 renamable $r0, 0, 14, $noreg, implicit-def $cpsr + ; CHECK: renamable $r1, $cpsr = tADDrr renamable $r0, killed renamable $r1, 14, $noreg + ; CHECK: tBcc %bb.2, 0, killed $cpsr + ; CHECK: bb.1: + ; CHECK: renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (load 4 from %ir.x) + ; CHECK: tTAILJMPdND @c, 14, $noreg, implicit $sp, implicit $sp, implicit killed $r0 + ; CHECK: bb.2: + ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14, $noreg + ; CHECK: tBX_RET 14, $noreg, implicit killed $r0 + bb.0: + successors: %bb.1(0x30000000), %bb.2(0x50000000) + liveins: $r0, $r1 + + tCMPi8 renamable $r0, 0, 14, $noreg, implicit-def $cpsr + renamable $r1, $cpsr = tADDrr renamable $r0, killed renamable $r1, 14, $noreg + t2Bcc %bb.1, 0, killed $cpsr + + bb.2: + liveins: $r0 + + renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (load 4 from %ir.x) + tTAILJMPdND @c, 14, $noreg, implicit $sp, implicit $sp, implicit killed $r0 + + bb.1: + $r0, dead $cpsr = tMOVi8 0, 14, $noreg + tBX_RET 14, $noreg, implicit killed $r0 + +... +--- +name: test_killflag_1 +tracksRegLiveness: true +liveins: + - { reg: '$r0', virtual-reg: '' } + - { reg: '$r1', virtual-reg: '' } +body: | + ; CHECK-LABEL: name: test_killflag_1 + ; CHECK: bb.0: + ; CHECK: successors: %bb.2(0x30000000), %bb.1(0x50000000) + ; CHECK: tCMPi8 killed renamable $r1, 0, 14, $noreg, implicit-def $cpsr + ; CHECK: renamable $r0 = t2ADDrs killed renamable $r0, killed renamable $r0, 18, 14, $noreg, $noreg + ; CHECK: tBcc %bb.2, 0, killed $cpsr + ; CHECK: bb.1: + ; CHECK: renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (load 4 from %ir.x) + ; CHECK: tTAILJMPdND @c, 14, $noreg, implicit $sp, implicit $sp, implicit killed $r0 + ; CHECK: bb.2: + ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14, $noreg + ; CHECK: tBX_RET 14, $noreg, implicit killed $r0 + bb.0: + successors: %bb.1(0x30000000), %bb.2(0x50000000) + liveins: $r0, $r1 + + tCMPi8 killed renamable $r1, 0, 14, $noreg, implicit-def $cpsr + renamable $r0 = t2ADDrs killed renamable $r0, killed renamable $r0, 18, 14, $noreg, $noreg + t2Bcc %bb.1, 0, killed $cpsr + + bb.2: + liveins: $r0 + + renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (load 4 from %ir.x) + tTAILJMPdND @c, 14, $noreg, implicit $sp, implicit $sp, implicit killed $r0 + + bb.1: + $r0, dead $cpsr = tMOVi8 0, 14, $noreg + tBX_RET 14, $noreg, implicit killed $r0 + +... +--- +name: test_killflag_2 +tracksRegLiveness: true +liveins: + - { reg: '$r0', virtual-reg: '' } + - { reg: '$r1', virtual-reg: '' } +body: | + ; CHECK-LABEL: name: test_killflag_2 + ; CHECK: bb.0: + ; CHECK: successors: %bb.2(0x30000000), %bb.1(0x50000000) + ; CHECK: tCMPi8 renamable $r1, 0, 14, $noreg, implicit-def $cpsr + ; CHECK: renamable $r0 = t2ADDrs killed renamable $r1, killed renamable $r0, 18, 14, $noreg, $noreg + ; CHECK: tBcc %bb.2, 0, killed $cpsr + ; CHECK: bb.1: + ; CHECK: renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (load 4 from %ir.x) + ; CHECK: tTAILJMPdND @c, 14, $noreg, implicit $sp, implicit $sp, implicit killed $r0 + ; CHECK: bb.2: + ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14, $noreg + ; CHECK: tBX_RET 14, $noreg, implicit killed $r0 + bb.0: + successors: %bb.1(0x30000000), %bb.2(0x50000000) + liveins: $r0, $r1 + + tCMPi8 renamable $r1, 0, 14, $noreg, implicit-def $cpsr + renamable $r0 = t2ADDrs killed renamable $r1, killed renamable $r0, 18, 14, $noreg, $noreg + t2Bcc %bb.1, 0, killed $cpsr + + bb.2: + liveins: $r0 + + renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (load 4 from %ir.x) + tTAILJMPdND @c, 14, $noreg, implicit $sp, implicit $sp, implicit killed $r0 + + bb.1: + $r0, dead $cpsr = tMOVi8 0, 14, $noreg + tBX_RET 14, $noreg, implicit killed $r0 + +... +