diff --git a/llvm/lib/Target/X86/X86FastISel.cpp b/llvm/lib/Target/X86/X86FastISel.cpp index 47361da75994e..147cd1b9b32de 100644 --- a/llvm/lib/Target/X86/X86FastISel.cpp +++ b/llvm/lib/Target/X86/X86FastISel.cpp @@ -497,7 +497,7 @@ bool X86FastISel::X86FastEmitStore(EVT VT, unsigned ValReg, bool ValIsKill, default: return false; case MVT::i1: { // Mask out all but lowest bit. - unsigned AndResult = createResultReg(&X86::GR8RegClass); + Register AndResult = createResultReg(&X86::GR8RegClass); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::AND8ri), AndResult) .addReg(ValReg, getKillRegState(ValIsKill)).addImm(1); @@ -690,7 +690,7 @@ bool X86FastISel::X86FastEmitStore(EVT VT, const Value *Val, } } - unsigned ValReg = getRegForValue(Val); + Register ValReg = getRegForValue(Val); if (ValReg == 0) return false; @@ -1195,7 +1195,7 @@ bool X86FastISel::X86SelectRet(const Instruction *I) { CCInfo.AnalyzeReturn(Outs, RetCC_X86); const Value *RV = Ret->getOperand(0); - unsigned Reg = getRegForValue(RV); + Register Reg = getRegForValue(RV); if (Reg == 0) return false; @@ -1263,7 +1263,7 @@ bool X86FastISel::X86SelectRet(const Instruction *I) { // We saved the argument into a virtual register in the entry block, // so now we copy the value out and into %rax/%eax. if (F.hasStructRetAttr() && CC != CallingConv::Swift) { - unsigned Reg = X86MFInfo->getSRetReturnReg(); + Register Reg = X86MFInfo->getSRetReturnReg(); assert(Reg && "SRetReturnReg should have been set in LowerFormalArguments()!"); unsigned RetReg = Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX; @@ -1391,7 +1391,7 @@ static unsigned X86ChooseCmpImmediateOpcode(EVT VT, const ConstantInt *RHSC) { bool X86FastISel::X86FastEmitCompare(const Value *Op0, const Value *Op1, EVT VT, const DebugLoc &CurDbgLoc) { - unsigned Op0Reg = getRegForValue(Op0); + Register Op0Reg = getRegForValue(Op0); if (Op0Reg == 0) return false; // Handle 'null' like i32/i64 0. @@ -1413,7 +1413,7 @@ bool X86FastISel::X86FastEmitCompare(const Value *Op0, const Value *Op1, EVT VT, unsigned CompareOpc = X86ChooseCmpOpcode(VT, Subtarget); if (CompareOpc == 0) return false; - unsigned Op1Reg = getRegForValue(Op1); + Register Op1Reg = getRegForValue(Op1); if (Op1Reg == 0) return false; BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, CurDbgLoc, TII.get(CompareOpc)) .addReg(Op0Reg) @@ -1486,8 +1486,8 @@ bool X86FastISel::X86SelectCmp(const Instruction *I) { if (!X86FastEmitCompare(LHS, RHS, VT, I->getDebugLoc())) return false; - unsigned FlagReg1 = createResultReg(&X86::GR8RegClass); - unsigned FlagReg2 = createResultReg(&X86::GR8RegClass); + Register FlagReg1 = createResultReg(&X86::GR8RegClass); + Register FlagReg2 = createResultReg(&X86::GR8RegClass); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::SETCCr), FlagReg1).addImm(SETFOpc[0]); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::SETCCr), @@ -1521,7 +1521,7 @@ bool X86FastISel::X86SelectZExt(const Instruction *I) { if (!TLI.isTypeLegal(DstVT)) return false; - unsigned ResultReg = getRegForValue(I->getOperand(0)); + Register ResultReg = getRegForValue(I->getOperand(0)); if (ResultReg == 0) return false; @@ -1547,7 +1547,7 @@ bool X86FastISel::X86SelectZExt(const Instruction *I) { default: llvm_unreachable("Unexpected zext to i64 source type"); } - unsigned Result32 = createResultReg(&X86::GR32RegClass); + Register Result32 = createResultReg(&X86::GR32RegClass); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(MovInst), Result32) .addReg(ResultReg); @@ -1558,7 +1558,7 @@ bool X86FastISel::X86SelectZExt(const Instruction *I) { } else if (DstVT == MVT::i16) { // i8->i16 doesn't exist in the autogenerated isel table. Need to zero // extend to 32-bits and then extract down to 16-bits. - unsigned Result32 = createResultReg(&X86::GR32RegClass); + Register Result32 = createResultReg(&X86::GR32RegClass); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::MOVZX32rr8), Result32).addReg(ResultReg); @@ -1580,7 +1580,7 @@ bool X86FastISel::X86SelectSExt(const Instruction *I) { if (!TLI.isTypeLegal(DstVT)) return false; - unsigned ResultReg = getRegForValue(I->getOperand(0)); + Register ResultReg = getRegForValue(I->getOperand(0)); if (ResultReg == 0) return false; @@ -1588,7 +1588,7 @@ bool X86FastISel::X86SelectSExt(const Instruction *I) { MVT SrcVT = TLI.getSimpleValueType(DL, I->getOperand(0)->getType()); if (SrcVT == MVT::i1) { // Set the high bits to zero. - unsigned ZExtReg = fastEmitZExtFromI1(MVT::i8, ResultReg, + Register ZExtReg = fastEmitZExtFromI1(MVT::i8, ResultReg, /*TODO: Kill=*/false); if (ZExtReg == 0) return false; @@ -1604,7 +1604,7 @@ bool X86FastISel::X86SelectSExt(const Instruction *I) { if (DstVT == MVT::i16) { // i8->i16 doesn't exist in the autogenerated isel table. Need to sign // extend to 32-bits and then extract down to 16-bits. - unsigned Result32 = createResultReg(&X86::GR32RegClass); + Register Result32 = createResultReg(&X86::GR32RegClass); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::MOVSX32rr8), Result32).addReg(ResultReg); @@ -1719,7 +1719,7 @@ bool X86FastISel::X86SelectBranch(const Instruction *I) { case MVT::i64: TestOpc = X86::TEST64ri32; break; } if (TestOpc) { - unsigned OpReg = getRegForValue(TI->getOperand(0)); + Register OpReg = getRegForValue(TI->getOperand(0)); if (OpReg == 0) return false; BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TestOpc)) @@ -1741,7 +1741,7 @@ bool X86FastISel::X86SelectBranch(const Instruction *I) { } else if (foldX86XALUIntrinsic(CC, BI, BI->getCondition())) { // Fake request the condition, otherwise the intrinsic might be completely // optimized away. - unsigned TmpReg = getRegForValue(BI->getCondition()); + Register TmpReg = getRegForValue(BI->getCondition()); if (TmpReg == 0) return false; @@ -1754,7 +1754,7 @@ bool X86FastISel::X86SelectBranch(const Instruction *I) { // Otherwise do a clumsy setcc and re-test it. // Note that i1 essentially gets ANY_EXTEND'ed to i8 where it isn't used // in an explicit cast, so make sure to handle that correctly. - unsigned OpReg = getRegForValue(BI->getCondition()); + Register OpReg = getRegForValue(BI->getCondition()); if (OpReg == 0) return false; // In case OpReg is a K register, COPY to a GPR @@ -1823,10 +1823,10 @@ bool X86FastISel::X86SelectShift(const Instruction *I) { if (!isTypeLegal(I->getType(), VT)) return false; - unsigned Op0Reg = getRegForValue(I->getOperand(0)); + Register Op0Reg = getRegForValue(I->getOperand(0)); if (Op0Reg == 0) return false; - unsigned Op1Reg = getRegForValue(I->getOperand(1)); + Register Op1Reg = getRegForValue(I->getOperand(1)); if (Op1Reg == 0) return false; BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY), CReg).addReg(Op1Reg); @@ -1838,7 +1838,7 @@ bool X86FastISel::X86SelectShift(const Instruction *I) { TII.get(TargetOpcode::KILL), X86::CL) .addReg(CReg, RegState::Kill); - unsigned ResultReg = createResultReg(RC); + Register ResultReg = createResultReg(RC); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(OpReg), ResultReg) .addReg(Op0Reg); updateValueMap(I, ResultReg); @@ -1932,10 +1932,10 @@ bool X86FastISel::X86SelectDivRem(const Instruction *I) { const DivRemEntry &TypeEntry = OpTable[TypeIndex]; const DivRemEntry::DivRemResult &OpEntry = TypeEntry.ResultTable[OpIndex]; - unsigned Op0Reg = getRegForValue(I->getOperand(0)); + Register Op0Reg = getRegForValue(I->getOperand(0)); if (Op0Reg == 0) return false; - unsigned Op1Reg = getRegForValue(I->getOperand(1)); + Register Op1Reg = getRegForValue(I->getOperand(1)); if (Op1Reg == 0) return false; @@ -1948,7 +1948,7 @@ bool X86FastISel::X86SelectDivRem(const Instruction *I) { BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(OpEntry.OpSignExtend)); else { - unsigned Zero32 = createResultReg(&X86::GR32RegClass); + Register Zero32 = createResultReg(&X86::GR32RegClass); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::MOV32r0), Zero32); @@ -1985,8 +1985,8 @@ bool X86FastISel::X86SelectDivRem(const Instruction *I) { if ((I->getOpcode() == Instruction::SRem || I->getOpcode() == Instruction::URem) && OpEntry.DivRemResultReg == X86::AH && Subtarget->is64Bit()) { - unsigned SourceSuperReg = createResultReg(&X86::GR16RegClass); - unsigned ResultSuperReg = createResultReg(&X86::GR16RegClass); + Register SourceSuperReg = createResultReg(&X86::GR16RegClass); + Register ResultSuperReg = createResultReg(&X86::GR16RegClass); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Copy), SourceSuperReg).addReg(X86::AX); @@ -2065,15 +2065,15 @@ bool X86FastISel::X86FastEmitCMoveSelect(MVT RetVT, const Instruction *I) { return false; if (SETFOpc) { - unsigned FlagReg1 = createResultReg(&X86::GR8RegClass); - unsigned FlagReg2 = createResultReg(&X86::GR8RegClass); + Register FlagReg1 = createResultReg(&X86::GR8RegClass); + Register FlagReg2 = createResultReg(&X86::GR8RegClass); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::SETCCr), FlagReg1).addImm(SETFOpc[0]); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::SETCCr), FlagReg2).addImm(SETFOpc[1]); auto const &II = TII.get(SETFOpc[2]); if (II.getNumDefs()) { - unsigned TmpReg = createResultReg(&X86::GR8RegClass); + Register TmpReg = createResultReg(&X86::GR8RegClass); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, TmpReg) .addReg(FlagReg2).addReg(FlagReg1); } else { @@ -2085,7 +2085,7 @@ bool X86FastISel::X86FastEmitCMoveSelect(MVT RetVT, const Instruction *I) { } else if (foldX86XALUIntrinsic(CC, I, Cond)) { // Fake request the condition, otherwise the intrinsic might be completely // optimized away. - unsigned TmpReg = getRegForValue(Cond); + Register TmpReg = getRegForValue(Cond); if (TmpReg == 0) return false; @@ -2098,7 +2098,7 @@ bool X86FastISel::X86FastEmitCMoveSelect(MVT RetVT, const Instruction *I) { // accurate. If we read more than the lsb, we may see non-zero values // whereas lsb is zero. Therefore, we have to truncate Op0Reg to i1 for // the select. This is achieved by performing TEST against 1. - unsigned CondReg = getRegForValue(Cond); + Register CondReg = getRegForValue(Cond); if (CondReg == 0) return false; bool CondIsKill = hasTrivialKill(Cond); @@ -2121,10 +2121,10 @@ bool X86FastISel::X86FastEmitCMoveSelect(MVT RetVT, const Instruction *I) { const Value *LHS = I->getOperand(1); const Value *RHS = I->getOperand(2); - unsigned RHSReg = getRegForValue(RHS); + Register RHSReg = getRegForValue(RHS); bool RHSIsKill = hasTrivialKill(RHS); - unsigned LHSReg = getRegForValue(LHS); + Register LHSReg = getRegForValue(LHS); bool LHSIsKill = hasTrivialKill(LHS); if (!LHSReg || !RHSReg) @@ -2132,7 +2132,7 @@ bool X86FastISel::X86FastEmitCMoveSelect(MVT RetVT, const Instruction *I) { const TargetRegisterInfo &TRI = *Subtarget->getRegisterInfo(); unsigned Opc = X86::getCMovOpcode(TRI.getRegSizeInBits(*RC)/8); - unsigned ResultReg = fastEmitInst_rri(Opc, RC, RHSReg, RHSIsKill, + Register ResultReg = fastEmitInst_rri(Opc, RC, RHSReg, RHSIsKill, LHSReg, LHSIsKill, CC); updateValueMap(I, ResultReg); return true; @@ -2181,16 +2181,16 @@ bool X86FastISel::X86FastEmitSSESelect(MVT RetVT, const Instruction *I) { const Value *LHS = I->getOperand(1); const Value *RHS = I->getOperand(2); - unsigned LHSReg = getRegForValue(LHS); + Register LHSReg = getRegForValue(LHS); bool LHSIsKill = hasTrivialKill(LHS); - unsigned RHSReg = getRegForValue(RHS); + Register RHSReg = getRegForValue(RHS); bool RHSIsKill = hasTrivialKill(RHS); - unsigned CmpLHSReg = getRegForValue(CmpLHS); + Register CmpLHSReg = getRegForValue(CmpLHS); bool CmpLHSIsKill = hasTrivialKill(CmpLHS); - unsigned CmpRHSReg = getRegForValue(CmpRHS); + Register CmpRHSReg = getRegForValue(CmpRHS); bool CmpRHSIsKill = hasTrivialKill(CmpRHS); if (!LHSReg || !RHSReg || !CmpLHSReg || !CmpRHSReg) @@ -2206,12 +2206,12 @@ bool X86FastISel::X86FastEmitSSESelect(MVT RetVT, const Instruction *I) { unsigned CmpOpcode = (RetVT == MVT::f32) ? X86::VCMPSSZrr : X86::VCMPSDZrr; - unsigned CmpReg = fastEmitInst_rri(CmpOpcode, VK1, CmpLHSReg, CmpLHSIsKill, + Register CmpReg = fastEmitInst_rri(CmpOpcode, VK1, CmpLHSReg, CmpLHSIsKill, CmpRHSReg, CmpRHSIsKill, CC); // Need an IMPLICIT_DEF for the input that is used to generate the upper // bits of the result register since its not based on any of the inputs. - unsigned ImplicitDefReg = createResultReg(VR128X); + Register ImplicitDefReg = createResultReg(VR128X); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::IMPLICIT_DEF), ImplicitDefReg); @@ -2240,9 +2240,9 @@ bool X86FastISel::X86FastEmitSSESelect(MVT RetVT, const Instruction *I) { unsigned BlendOpcode = (RetVT == MVT::f32) ? X86::VBLENDVPSrr : X86::VBLENDVPDrr; - unsigned CmpReg = fastEmitInst_rri(CmpOpcode, RC, CmpLHSReg, CmpLHSIsKill, + Register CmpReg = fastEmitInst_rri(CmpOpcode, RC, CmpLHSReg, CmpLHSIsKill, CmpRHSReg, CmpRHSIsKill, CC); - unsigned VBlendReg = fastEmitInst_rrr(BlendOpcode, VR128, RHSReg, RHSIsKill, + Register VBlendReg = fastEmitInst_rrr(BlendOpcode, VR128, RHSReg, RHSIsKill, LHSReg, LHSIsKill, CmpReg, true); ResultReg = createResultReg(RC); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, @@ -2262,13 +2262,13 @@ bool X86FastISel::X86FastEmitSSESelect(MVT RetVT, const Instruction *I) { } const TargetRegisterClass *VR128 = &X86::VR128RegClass; - unsigned CmpReg = fastEmitInst_rri(Opc[0], RC, CmpLHSReg, CmpLHSIsKill, + Register CmpReg = fastEmitInst_rri(Opc[0], RC, CmpLHSReg, CmpLHSIsKill, CmpRHSReg, CmpRHSIsKill, CC); - unsigned AndReg = fastEmitInst_rr(Opc[1], VR128, CmpReg, /*IsKill=*/false, + Register AndReg = fastEmitInst_rr(Opc[1], VR128, CmpReg, /*IsKill=*/false, LHSReg, LHSIsKill); - unsigned AndNReg = fastEmitInst_rr(Opc[2], VR128, CmpReg, /*IsKill=*/true, + Register AndNReg = fastEmitInst_rr(Opc[2], VR128, CmpReg, /*IsKill=*/true, RHSReg, RHSIsKill); - unsigned OrReg = fastEmitInst_rr(Opc[3], VR128, AndNReg, /*IsKill=*/true, + Register OrReg = fastEmitInst_rr(Opc[3], VR128, AndNReg, /*IsKill=*/true, AndReg, /*IsKill=*/true); ResultReg = createResultReg(RC); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, @@ -2316,7 +2316,7 @@ bool X86FastISel::X86FastEmitPseudoSelect(MVT RetVT, const Instruction *I) { if (!X86FastEmitCompare(CmpLHS, CmpRHS, CmpVT, CI->getDebugLoc())) return false; } else { - unsigned CondReg = getRegForValue(Cond); + Register CondReg = getRegForValue(Cond); if (CondReg == 0) return false; bool CondIsKill = hasTrivialKill(Cond); @@ -2339,10 +2339,10 @@ bool X86FastISel::X86FastEmitPseudoSelect(MVT RetVT, const Instruction *I) { const Value *LHS = I->getOperand(1); const Value *RHS = I->getOperand(2); - unsigned LHSReg = getRegForValue(LHS); + Register LHSReg = getRegForValue(LHS); bool LHSIsKill = hasTrivialKill(LHS); - unsigned RHSReg = getRegForValue(RHS); + Register RHSReg = getRegForValue(RHS); bool RHSIsKill = hasTrivialKill(RHS); if (!LHSReg || !RHSReg) @@ -2350,7 +2350,7 @@ bool X86FastISel::X86FastEmitPseudoSelect(MVT RetVT, const Instruction *I) { const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); - unsigned ResultReg = + Register ResultReg = fastEmitInst_rri(Opc, RC, RHSReg, RHSIsKill, LHSReg, LHSIsKill, CC); updateValueMap(I, ResultReg); return true; @@ -2372,12 +2372,12 @@ bool X86FastISel::X86SelectSelect(const Instruction *I) { } // No need for a select anymore - this is an unconditional move. if (Opnd) { - unsigned OpReg = getRegForValue(Opnd); + Register OpReg = getRegForValue(Opnd); if (OpReg == 0) return false; bool OpIsKill = hasTrivialKill(Opnd); const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); - unsigned ResultReg = createResultReg(RC); + Register ResultReg = createResultReg(RC); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY), ResultReg) .addReg(OpReg, getKillRegState(OpIsKill)); @@ -2418,7 +2418,7 @@ bool X86FastISel::X86SelectIntToFP(const Instruction *I, bool IsSigned) { return false; // Select integer to float/double conversion. - unsigned OpReg = getRegForValue(I->getOperand(0)); + Register OpReg = getRegForValue(I->getOperand(0)); if (OpReg == 0) return false; @@ -2447,10 +2447,10 @@ bool X86FastISel::X86SelectIntToFP(const Instruction *I, bool IsSigned) { MVT DstVT = TLI.getValueType(DL, I->getType()).getSimpleVT(); const TargetRegisterClass *RC = TLI.getRegClassFor(DstVT); - unsigned ImplicitDefReg = createResultReg(RC); + Register ImplicitDefReg = createResultReg(RC); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::IMPLICIT_DEF), ImplicitDefReg); - unsigned ResultReg = + Register ResultReg = fastEmitInst_rr(Opcode, RC, ImplicitDefReg, true, OpReg, false); updateValueMap(I, ResultReg); return true; @@ -2473,7 +2473,7 @@ bool X86FastISel::X86SelectFPExtOrFPTrunc(const Instruction *I, "Instruction must be an FPExt or FPTrunc!"); bool HasAVX = Subtarget->hasAVX(); - unsigned OpReg = getRegForValue(I->getOperand(0)); + Register OpReg = getRegForValue(I->getOperand(0)); if (OpReg == 0) return false; @@ -2485,7 +2485,7 @@ bool X86FastISel::X86SelectFPExtOrFPTrunc(const Instruction *I, } - unsigned ResultReg = createResultReg(RC); + Register ResultReg = createResultReg(RC); MachineInstrBuilder MIB; MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpc), ResultReg); @@ -2536,7 +2536,7 @@ bool X86FastISel::X86SelectTrunc(const Instruction *I) { if (!TLI.isTypeLegal(SrcVT)) return false; - unsigned InputReg = getRegForValue(I->getOperand(0)); + Register InputReg = getRegForValue(I->getOperand(0)); if (!InputReg) // Unhandled operand. Halt "fast" selection and bail. return false; @@ -2548,7 +2548,7 @@ bool X86FastISel::X86SelectTrunc(const Instruction *I) { } // Issue an extract_subreg. - unsigned ResultReg = fastEmitInst_extractsubreg(MVT::i8, + Register ResultReg = fastEmitInst_extractsubreg(MVT::i8, InputReg, false, X86::sub_8bit); if (!ResultReg) @@ -2607,7 +2607,7 @@ bool X86FastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) { return false; const Value *Op = II->getArgOperand(0); - unsigned InputReg = getRegForValue(Op); + Register InputReg = getRegForValue(Op); if (InputReg == 0) return false; @@ -2704,7 +2704,7 @@ bool X86FastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) { // Always make a copy of the frame register to a vreg first, so that we // never directly reference the frame register (the TwoAddressInstruction- // Pass doesn't like that). - unsigned SrcReg = createResultReg(RC); + Register SrcReg = createResultReg(RC); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY), SrcReg).addReg(FrameReg); @@ -2834,7 +2834,7 @@ bool X86FastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) { } const Value *SrcVal = II->getArgOperand(0); - unsigned SrcReg = getRegForValue(SrcVal); + Register SrcReg = getRegForValue(SrcVal); if (SrcReg == 0) return false; @@ -2847,7 +2847,7 @@ bool X86FastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) { TII.get(TargetOpcode::IMPLICIT_DEF), ImplicitDefReg); } - unsigned ResultReg = createResultReg(RC); + Register ResultReg = createResultReg(RC); MachineInstrBuilder MIB; MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg); @@ -2907,7 +2907,7 @@ bool X86FastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) { BaseOpc = X86ISD::UMUL; CondCode = X86::COND_O; break; } - unsigned LHSReg = getRegForValue(LHS); + Register LHSReg = getRegForValue(LHS); if (LHSReg == 0) return false; bool LHSIsKill = hasTrivialKill(LHS); @@ -2978,7 +2978,7 @@ bool X86FastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) { return false; // Assign to a GPR since the overflow return value is lowered to a SETcc. - unsigned ResultReg2 = createResultReg(&X86::GR8RegClass); + Register ResultReg2 = createResultReg(&X86::GR8RegClass); assert((ResultReg+1) == ResultReg2 && "Nonconsecutive result registers."); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::SETCCr), ResultReg2).addImm(CondCode); @@ -3045,11 +3045,11 @@ bool X86FastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) { Op = IE->getOperand(0); } - unsigned Reg = getRegForValue(Op); + Register Reg = getRegForValue(Op); if (Reg == 0) return false; - unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); + Register ResultReg = createResultReg(TLI.getRegClassFor(VT)); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) .addReg(Reg); @@ -3143,11 +3143,11 @@ bool X86FastISel::fastLowerArguments() { case MVT::f32: LLVM_FALLTHROUGH; case MVT::f64: SrcReg = XMMArgRegs[FPRIdx++]; break; } - unsigned DstReg = FuncInfo.MF->addLiveIn(SrcReg, RC); + Register DstReg = FuncInfo.MF->addLiveIn(SrcReg, RC); // FIXME: Unfortunately it's necessary to emit a copy from the livein copy. // Without this, EmitLiveInCopies may eliminate the livein if its only // use is a bitcast (which isn't turned into an instruction). - unsigned ResultReg = createResultReg(RC); + Register ResultReg = createResultReg(RC); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY), ResultReg) .addReg(DstReg, getKillRegState(true)); @@ -3551,7 +3551,7 @@ bool X86FastISel::fastLowerCall(CallLoweringInfo &CLI) { CCRetInfo.AnalyzeCallResult(Ins, RetCC_X86); // Copy all of the result registers out of their specified physreg. - unsigned ResultReg = FuncInfo.CreateRegs(CLI.RetTy); + Register ResultReg = FuncInfo.CreateRegs(CLI.RetTy); for (unsigned i = 0; i != RVLocs.size(); ++i) { CCValAssign &VA = RVLocs[i]; EVT CopyVT = VA.getValVT(); @@ -3649,7 +3649,7 @@ X86FastISel::fastSelectInstruction(const Instruction *I) { return X86SelectZExt(I); if (DstVT.bitsLT(SrcVT)) return X86SelectTrunc(I); - unsigned Reg = getRegForValue(I->getOperand(0)); + Register Reg = getRegForValue(I->getOperand(0)); if (Reg == 0) return false; updateValueMap(I, Reg); return true; @@ -3670,7 +3670,7 @@ X86FastISel::fastSelectInstruction(const Instruction *I) { DstVT.getVectorElementType() == MVT::i1) return false; - unsigned Reg = getRegForValue(I->getOperand(0)); + Register Reg = getRegForValue(I->getOperand(0)); if (Reg == 0) return false; @@ -3690,7 +3690,7 @@ unsigned X86FastISel::X86MaterializeInt(const ConstantInt *CI, MVT VT) { uint64_t Imm = CI->getZExtValue(); if (Imm == 0) { - unsigned SrcReg = fastEmitInst_(X86::MOV32r0, &X86::GR32RegClass); + Register SrcReg = fastEmitInst_(X86::MOV32r0, &X86::GR32RegClass); switch (VT.SimpleTy) { default: llvm_unreachable("Unexpected value type"); case MVT::i1: @@ -3703,7 +3703,7 @@ unsigned X86FastISel::X86MaterializeInt(const ConstantInt *CI, MVT VT) { case MVT::i32: return SrcReg; case MVT::i64: { - unsigned ResultReg = createResultReg(&X86::GR64RegClass); + Register ResultReg = createResultReg(&X86::GR64RegClass); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::SUBREG_TO_REG), ResultReg) .addImm(0).addReg(SrcReg).addImm(X86::sub_32bit); @@ -3785,11 +3785,11 @@ unsigned X86FastISel::X86MaterializeFP(const ConstantFP *CFP, MVT VT) { // Create the load from the constant pool. unsigned CPI = MCP.getConstantPoolIndex(CFP, Alignment); - unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT.SimpleTy)); + Register ResultReg = createResultReg(TLI.getRegClassFor(VT.SimpleTy)); // Large code model only applies to 64-bit mode. if (Subtarget->is64Bit() && CM == CodeModel::Large) { - unsigned AddrReg = createResultReg(&X86::GR64RegClass); + Register AddrReg = createResultReg(&X86::GR64RegClass); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::MOV64ri), AddrReg) .addConstantPoolIndex(CPI, 0, OpFlag); @@ -3823,7 +3823,7 @@ unsigned X86FastISel::X86MaterializeGV(const GlobalValue *GV, MVT VT) { AM.IndexReg == 0 && AM.Disp == 0 && AM.GV == nullptr) return AM.Base.Reg; - unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); + Register ResultReg = createResultReg(TLI.getRegClassFor(VT)); if (TM.getRelocationModel() == Reloc::Static && TLI.getPointerTy(DL) == MVT::i64) { // The displacement code could be more than 32 bits away so we need to use @@ -3882,7 +3882,7 @@ unsigned X86FastISel::fastMaterializeAlloca(const AllocaInst *C) { ? (Subtarget->isTarget64BitILP32() ? X86::LEA64_32r : X86::LEA32r) : X86::LEA64r; const TargetRegisterClass *RC = TLI.getRegClassFor(TLI.getPointerTy(DL)); - unsigned ResultReg = createResultReg(RC); + Register ResultReg = createResultReg(RC); addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg), AM); return ResultReg; @@ -3915,7 +3915,7 @@ unsigned X86FastISel::fastMaterializeFloatZero(const ConstantFP *CF) { return 0; } - unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); + Register ResultReg = createResultReg(TLI.getRegClassFor(VT)); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg); return ResultReg; } @@ -3953,7 +3953,7 @@ bool X86FastISel::tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo, if (!MO.isReg() || MO.isDef() || MO.getReg() != AM.IndexReg) continue; // Found the index reg, now try to rewrite it. - unsigned IndexReg = constrainOperandRegClass(Result->getDesc(), + Register IndexReg = constrainOperandRegClass(Result->getDesc(), MO.getReg(), OperandNo); if (IndexReg == MO.getReg()) continue; @@ -3975,7 +3975,7 @@ unsigned X86FastISel::fastEmitInst_rrrr(unsigned MachineInstOpcode, unsigned Op3, bool Op3IsKill) { const MCInstrDesc &II = TII.get(MachineInstOpcode); - unsigned ResultReg = createResultReg(RC); + Register ResultReg = createResultReg(RC); Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); Op2 = constrainOperandRegClass(II, Op2, II.getNumDefs() + 2);