From 4010f894a1e880f88bda78a49a8bece5affaa848 Mon Sep 17 00:00:00 2001 From: paperchalice Date: Tue, 9 Jul 2024 12:09:11 +0800 Subject: [PATCH] [CodeGen][NewPM] Port `SlotIndexes` to new pass manager (#97941) - Add `SlotIndexesAnalysis`. - Add `SlotIndexesPrinterPass`. - Use `SlotIndexesWrapperPass` in legacy pass. --- llvm/include/llvm/CodeGen/SlotIndexes.h | 64 +++++++++++++++++-- llvm/include/llvm/InitializePasses.h | 2 +- .../llvm/Passes/MachinePassRegistry.def | 3 +- llvm/lib/CodeGen/CodeGen.cpp | 2 +- llvm/lib/CodeGen/LiveIntervals.cpp | 8 +-- llvm/lib/CodeGen/LiveStacks.cpp | 6 +- .../lib/CodeGen/MLRegAllocPriorityAdvisor.cpp | 9 +-- llvm/lib/CodeGen/MachineBasicBlock.cpp | 3 +- .../CodeGen/MachineFunctionPrinterPass.cpp | 5 +- llvm/lib/CodeGen/MachineScheduler.cpp | 6 +- llvm/lib/CodeGen/MachineVerifier.cpp | 5 +- llvm/lib/CodeGen/PHIElimination.cpp | 2 +- llvm/lib/CodeGen/RegAllocBasic.cpp | 4 +- llvm/lib/CodeGen/RegAllocGreedy.cpp | 8 +-- llvm/lib/CodeGen/RegAllocPBQP.cpp | 6 +- llvm/lib/CodeGen/RegAllocPriorityAdvisor.cpp | 4 +- llvm/lib/CodeGen/RegisterCoalescer.cpp | 4 +- llvm/lib/CodeGen/RenameIndependentSubregs.cpp | 6 +- llvm/lib/CodeGen/SlotIndexes.cpp | 55 ++++++++++------ llvm/lib/CodeGen/StackColoring.cpp | 6 +- llvm/lib/CodeGen/StackSlotColoring.cpp | 8 +-- .../lib/CodeGen/TwoAddressInstructionPass.cpp | 2 +- llvm/lib/CodeGen/VirtRegMap.cpp | 8 +-- llvm/lib/Passes/PassBuilder.cpp | 1 + .../AMDGPU/AMDGPUMarkLastScratchLoad.cpp | 6 +- .../AMDGPU/GCNRewritePartialRegUses.cpp | 2 +- llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp | 2 +- llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp | 3 +- llvm/lib/Target/AMDGPU/SILowerWWMCopies.cpp | 3 +- llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp | 2 +- .../Target/Hexagon/HexagonCopyHoisting.cpp | 7 +- .../Target/Hexagon/HexagonExpandCondsets.cpp | 4 +- llvm/lib/Target/Hexagon/HexagonTfrCleanup.cpp | 3 +- .../LoongArchDeadRegisterDefinitions.cpp | 2 +- llvm/lib/Target/PowerPC/PPCTLSDynamicCall.cpp | 4 +- llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp | 6 +- .../RISCV/RISCVDeadRegisterDefinitions.cpp | 2 +- llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp | 2 +- .../WebAssemblyMemIntrinsicResults.cpp | 2 +- .../WebAssemblyOptimizeLiveIntervals.cpp | 2 +- .../WebAssembly/WebAssemblyRegStackify.cpp | 2 +- llvm/test/CodeGen/X86/slot-indexes.ll | 11 ++++ 42 files changed, 187 insertions(+), 105 deletions(-) create mode 100644 llvm/test/CodeGen/X86/slot-indexes.ll diff --git a/llvm/include/llvm/CodeGen/SlotIndexes.h b/llvm/include/llvm/CodeGen/SlotIndexes.h index 21a9df22c2e1c..e357d1a898e4f 100644 --- a/llvm/include/llvm/CodeGen/SlotIndexes.h +++ b/llvm/include/llvm/CodeGen/SlotIndexes.h @@ -28,6 +28,7 @@ #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineInstrBundle.h" +#include "llvm/CodeGen/MachinePassManager.h" #include "llvm/Support/Allocator.h" #include #include @@ -293,7 +294,9 @@ class raw_ostream; /// SlotIndexes pass. /// /// This pass assigns indexes to each instruction. - class SlotIndexes : public MachineFunctionPass { + class SlotIndexes { + friend class SlotIndexesWrapperPass; + private: // IndexListEntry allocator. BumpPtrAllocator ileAllocator; @@ -313,6 +316,13 @@ class raw_ostream; /// and MBB id. SmallVector idx2MBBMap; + // For legacy pass manager. + SlotIndexes() = default; + + void clear(); + + void analyze(MachineFunction &MF); + IndexListEntry* createEntry(MachineInstr *mi, unsigned index) { IndexListEntry *entry = static_cast(ileAllocator.Allocate( @@ -327,16 +337,18 @@ class raw_ostream; void renumberIndexes(IndexList::iterator curItr); public: - static char ID; + SlotIndexes(SlotIndexes &&) = default; - SlotIndexes(); + SlotIndexes(MachineFunction &MF) { analyze(MF); } - ~SlotIndexes() override; + ~SlotIndexes(); - void getAnalysisUsage(AnalysisUsage &au) const override; - void releaseMemory() override; + void reanalyze(MachineFunction &MF) { + clear(); + analyze(MF); + } - bool runOnMachineFunction(MachineFunction &fn) override; + void print(raw_ostream &OS) const; /// Dump the indexes. void dump() const; @@ -629,6 +641,44 @@ class raw_ostream; struct IntervalMapInfo : IntervalMapHalfOpenInfo { }; + class SlotIndexesAnalysis : public AnalysisInfoMixin { + friend AnalysisInfoMixin; + static AnalysisKey Key; + + public: + using Result = SlotIndexes; + Result run(MachineFunction &MF, MachineFunctionAnalysisManager &); + }; + + class SlotIndexesPrinterPass : public PassInfoMixin { + raw_ostream &OS; + + public: + explicit SlotIndexesPrinterPass(raw_ostream &OS) : OS(OS) {} + PreservedAnalyses run(MachineFunction &MF, + MachineFunctionAnalysisManager &MFAM); + static bool isRequired() { return true; } + }; + + class SlotIndexesWrapperPass : public MachineFunctionPass { + SlotIndexes SI; + + public: + static char ID; + + SlotIndexesWrapperPass(); + + void getAnalysisUsage(AnalysisUsage &au) const override; + void releaseMemory() override { SI.clear(); } + + bool runOnMachineFunction(MachineFunction &fn) override { + SI.analyze(fn); + return false; + } + + SlotIndexes &getSI() { return SI; } + }; + } // end namespace llvm #endif // LLVM_CODEGEN_SLOTINDEXES_H diff --git a/llvm/include/llvm/InitializePasses.h b/llvm/include/llvm/InitializePasses.h index 0e798e4fd2e1f..9aa55d0ded79a 100644 --- a/llvm/include/llvm/InitializePasses.h +++ b/llvm/include/llvm/InitializePasses.h @@ -279,7 +279,7 @@ void initializeShrinkWrapPass(PassRegistry&); void initializeSingleLoopExtractorPass(PassRegistry&); void initializeSinkingLegacyPassPass(PassRegistry&); void initializeSjLjEHPreparePass(PassRegistry&); -void initializeSlotIndexesPass(PassRegistry&); +void initializeSlotIndexesWrapperPassPass(PassRegistry &); void initializeSpeculativeExecutionLegacyPassPass(PassRegistry&); void initializeSpillPlacementPass(PassRegistry&); void initializeStackColoringPass(PassRegistry&); diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def b/llvm/include/llvm/Passes/MachinePassRegistry.def index 2f838e0d4b3ae..0e8fde7468707 100644 --- a/llvm/include/llvm/Passes/MachinePassRegistry.def +++ b/llvm/include/llvm/Passes/MachinePassRegistry.def @@ -102,8 +102,8 @@ MACHINE_FUNCTION_ANALYSIS("machine-loops", MachineLoopAnalysis()) MACHINE_FUNCTION_ANALYSIS("machine-post-dom-tree", MachinePostDominatorTreeAnalysis()) MACHINE_FUNCTION_ANALYSIS("pass-instrumentation", PassInstrumentationAnalysis(PIC)) +MACHINE_FUNCTION_ANALYSIS("slot-indexes", SlotIndexesAnalysis()) // MACHINE_FUNCTION_ANALYSIS("live-stacks", LiveStacksPass()) -// MACHINE_FUNCTION_ANALYSIS("slot-indexes", SlotIndexesAnalysis()) // MACHINE_FUNCTION_ANALYSIS("edge-bundles", EdgeBundlesAnalysis()) // MACHINE_FUNCTION_ANALYSIS("lazy-machine-bfi", // LazyMachineBlockFrequencyInfoAnalysis()) @@ -140,6 +140,7 @@ MACHINE_FUNCTION_PASS("print", MACHINE_FUNCTION_PASS("print", MachineLoopPrinterPass(dbgs())) MACHINE_FUNCTION_PASS("print", MachinePostDominatorTreePrinterPass(dbgs())) +MACHINE_FUNCTION_PASS("print", SlotIndexesPrinterPass(dbgs())) MACHINE_FUNCTION_PASS("require-all-machine-function-properties", RequireAllMachineFunctionPropertiesPass()) MACHINE_FUNCTION_PASS("trigger-verifier-error", TriggerVerifierErrorPass()) diff --git a/llvm/lib/CodeGen/CodeGen.cpp b/llvm/lib/CodeGen/CodeGen.cpp index 2680f2458cc14..98eebd0d7b5c3 100644 --- a/llvm/lib/CodeGen/CodeGen.cpp +++ b/llvm/lib/CodeGen/CodeGen.cpp @@ -123,7 +123,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) { initializeShadowStackGCLoweringPass(Registry); initializeShrinkWrapPass(Registry); initializeSjLjEHPreparePass(Registry); - initializeSlotIndexesPass(Registry); + initializeSlotIndexesWrapperPassPass(Registry); initializeStackColoringPass(Registry); initializeStackFrameLayoutAnalysisPassPass(Registry); initializeStackMapLivenessPass(Registry); diff --git a/llvm/lib/CodeGen/LiveIntervals.cpp b/llvm/lib/CodeGen/LiveIntervals.cpp index 0fc878a53172a..9742a48a5c3ad 100644 --- a/llvm/lib/CodeGen/LiveIntervals.cpp +++ b/llvm/lib/CodeGen/LiveIntervals.cpp @@ -62,7 +62,7 @@ char &llvm::LiveIntervalsID = LiveIntervals::ID; INITIALIZE_PASS_BEGIN(LiveIntervals, "liveintervals", "Live Interval Analysis", false, false) INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass) -INITIALIZE_PASS_DEPENDENCY(SlotIndexes) +INITIALIZE_PASS_DEPENDENCY(SlotIndexesWrapperPass) INITIALIZE_PASS_END(LiveIntervals, "liveintervals", "Live Interval Analysis", false, false) @@ -89,8 +89,8 @@ void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const { AU.addPreservedID(MachineLoopInfoID); AU.addRequiredTransitiveID(MachineDominatorsID); AU.addPreservedID(MachineDominatorsID); - AU.addPreserved(); - AU.addRequiredTransitive(); + AU.addPreserved(); + AU.addRequiredTransitive(); MachineFunctionPass::getAnalysisUsage(AU); } @@ -122,7 +122,7 @@ bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) { MRI = &MF->getRegInfo(); TRI = MF->getSubtarget().getRegisterInfo(); TII = MF->getSubtarget().getInstrInfo(); - Indexes = &getAnalysis(); + Indexes = &getAnalysis().getSI(); DomTree = &getAnalysis().getDomTree(); if (!LICalc) diff --git a/llvm/lib/CodeGen/LiveStacks.cpp b/llvm/lib/CodeGen/LiveStacks.cpp index 8fc5a929d77b2..ae36b2819a358 100644 --- a/llvm/lib/CodeGen/LiveStacks.cpp +++ b/llvm/lib/CodeGen/LiveStacks.cpp @@ -23,7 +23,7 @@ using namespace llvm; char LiveStacks::ID = 0; INITIALIZE_PASS_BEGIN(LiveStacks, DEBUG_TYPE, "Live Stack Slot Analysis", false, false) -INITIALIZE_PASS_DEPENDENCY(SlotIndexes) +INITIALIZE_PASS_DEPENDENCY(SlotIndexesWrapperPass) INITIALIZE_PASS_END(LiveStacks, DEBUG_TYPE, "Live Stack Slot Analysis", false, false) @@ -31,8 +31,8 @@ char &llvm::LiveStacksID = LiveStacks::ID; void LiveStacks::getAnalysisUsage(AnalysisUsage &AU) const { AU.setPreservesAll(); - AU.addPreserved(); - AU.addRequiredTransitive(); + AU.addPreserved(); + AU.addRequiredTransitive(); MachineFunctionPass::getAnalysisUsage(AU); } diff --git a/llvm/lib/CodeGen/MLRegAllocPriorityAdvisor.cpp b/llvm/lib/CodeGen/MLRegAllocPriorityAdvisor.cpp index 8c1bb41f1430c..9638df81770c1 100644 --- a/llvm/lib/CodeGen/MLRegAllocPriorityAdvisor.cpp +++ b/llvm/lib/CodeGen/MLRegAllocPriorityAdvisor.cpp @@ -134,7 +134,7 @@ class ReleaseModePriorityAdvisorAnalysis final private: void getAnalysisUsage(AnalysisUsage &AU) const override { AU.setPreservesAll(); - AU.addRequired(); + AU.addRequired(); RegAllocPriorityAdvisorAnalysis::getAnalysisUsage(AU); } @@ -151,7 +151,7 @@ class ReleaseModePriorityAdvisorAnalysis final InteractiveChannelBaseName + ".in"); } return std::make_unique( - MF, RA, &getAnalysis(), Runner.get()); + MF, RA, &getAnalysis().getSI(), Runner.get()); } std::unique_ptr Runner; }; @@ -215,7 +215,7 @@ class DevelopmentModePriorityAdvisorAnalysis final private: void getAnalysisUsage(AnalysisUsage &AU) const override { AU.setPreservesAll(); - AU.addRequired(); + AU.addRequired(); RegAllocPriorityAdvisorAnalysis::getAnalysisUsage(AU); } @@ -266,7 +266,8 @@ class DevelopmentModePriorityAdvisorAnalysis final } return std::make_unique( - MF, RA, &getAnalysis(), Runner.get(), Log.get()); + MF, RA, &getAnalysis().getSI(), Runner.get(), + Log.get()); } std::unique_ptr Runner; diff --git a/llvm/lib/CodeGen/MachineBasicBlock.cpp b/llvm/lib/CodeGen/MachineBasicBlock.cpp index 82c833ed97f59..292bfa6c85edc 100644 --- a/llvm/lib/CodeGen/MachineBasicBlock.cpp +++ b/llvm/lib/CodeGen/MachineBasicBlock.cpp @@ -1162,7 +1162,8 @@ MachineBasicBlock *MachineBasicBlock::SplitCriticalEdge( << printMBBReference(*Succ) << '\n'); LiveIntervals *LIS = P.getAnalysisIfAvailable(); - SlotIndexes *Indexes = P.getAnalysisIfAvailable(); + auto *SIWrapper = P.getAnalysisIfAvailable(); + SlotIndexes *Indexes = SIWrapper ? &SIWrapper->getSI() : nullptr; if (LIS) LIS->insertMBBInMaps(NMBB); else if (Indexes) diff --git a/llvm/lib/CodeGen/MachineFunctionPrinterPass.cpp b/llvm/lib/CodeGen/MachineFunctionPrinterPass.cpp index c31c065b19767..0f88a7b741600 100644 --- a/llvm/lib/CodeGen/MachineFunctionPrinterPass.cpp +++ b/llvm/lib/CodeGen/MachineFunctionPrinterPass.cpp @@ -39,7 +39,7 @@ struct MachineFunctionPrinterPass : public MachineFunctionPass { void getAnalysisUsage(AnalysisUsage &AU) const override { AU.setPreservesAll(); - AU.addUsedIfAvailable(); + AU.addUsedIfAvailable(); MachineFunctionPass::getAnalysisUsage(AU); } @@ -47,7 +47,8 @@ struct MachineFunctionPrinterPass : public MachineFunctionPass { if (!isFunctionInPrintList(MF.getName())) return false; OS << "# " << Banner << ":\n"; - MF.print(OS, getAnalysisIfAvailable()); + auto *SIWrapper = getAnalysisIfAvailable(); + MF.print(OS, SIWrapper ? &SIWrapper->getSI() : nullptr); return false; } }; diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp index 84ba703742553..50eac1a570344 100644 --- a/llvm/lib/CodeGen/MachineScheduler.cpp +++ b/llvm/lib/CodeGen/MachineScheduler.cpp @@ -268,7 +268,7 @@ INITIALIZE_PASS_BEGIN(MachineScheduler, DEBUG_TYPE, INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass) INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass) INITIALIZE_PASS_DEPENDENCY(MachineLoopInfoWrapperPass) -INITIALIZE_PASS_DEPENDENCY(SlotIndexes) +INITIALIZE_PASS_DEPENDENCY(SlotIndexesWrapperPass) INITIALIZE_PASS_DEPENDENCY(LiveIntervals) INITIALIZE_PASS_END(MachineScheduler, DEBUG_TYPE, "Machine Instruction Scheduler", false, false) @@ -283,8 +283,8 @@ void MachineScheduler::getAnalysisUsage(AnalysisUsage &AU) const { AU.addRequired(); AU.addRequired(); AU.addRequired(); - AU.addRequired(); - AU.addPreserved(); + AU.addRequired(); + AU.addPreserved(); AU.addRequired(); AU.addPreserved(); MachineFunctionPass::getAnalysisUsage(AU); diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp index 612631acb578e..395f5de34b582 100644 --- a/llvm/lib/CodeGen/MachineVerifier.cpp +++ b/llvm/lib/CodeGen/MachineVerifier.cpp @@ -315,7 +315,7 @@ namespace { void getAnalysisUsage(AnalysisUsage &AU) const override { AU.addUsedIfAvailable(); AU.addUsedIfAvailable(); - AU.addUsedIfAvailable(); + AU.addUsedIfAvailable(); AU.addUsedIfAvailable(); AU.setPreservesAll(); MachineFunctionPass::getAnalysisUsage(AU); @@ -434,7 +434,8 @@ unsigned MachineVerifier::verify(const MachineFunction &MF) { if (!LiveInts) LiveVars = LVWrapper ? &LVWrapper->getLV() : nullptr; LiveStks = PASS->getAnalysisIfAvailable(); - Indexes = PASS->getAnalysisIfAvailable(); + auto *SIWrapper = PASS->getAnalysisIfAvailable(); + Indexes = SIWrapper ? &SIWrapper->getSI() : nullptr; } verifySlotIndexes(); diff --git a/llvm/lib/CodeGen/PHIElimination.cpp b/llvm/lib/CodeGen/PHIElimination.cpp index df51ddad9c2ae..cddbb5b4ed719 100644 --- a/llvm/lib/CodeGen/PHIElimination.cpp +++ b/llvm/lib/CodeGen/PHIElimination.cpp @@ -138,7 +138,7 @@ INITIALIZE_PASS_END(PHIElimination, DEBUG_TYPE, void PHIElimination::getAnalysisUsage(AnalysisUsage &AU) const { AU.addUsedIfAvailable(); AU.addPreserved(); - AU.addPreserved(); + AU.addPreserved(); AU.addPreserved(); AU.addPreserved(); AU.addPreserved(); diff --git a/llvm/lib/CodeGen/RegAllocBasic.cpp b/llvm/lib/CodeGen/RegAllocBasic.cpp index 2062334bd7f4b..133904cdbcf44 100644 --- a/llvm/lib/CodeGen/RegAllocBasic.cpp +++ b/llvm/lib/CodeGen/RegAllocBasic.cpp @@ -130,7 +130,7 @@ char &llvm::RABasicID = RABasic::ID; INITIALIZE_PASS_BEGIN(RABasic, "regallocbasic", "Basic Register Allocator", false, false) INITIALIZE_PASS_DEPENDENCY(LiveDebugVariables) -INITIALIZE_PASS_DEPENDENCY(SlotIndexes) +INITIALIZE_PASS_DEPENDENCY(SlotIndexesWrapperPass) INITIALIZE_PASS_DEPENDENCY(LiveIntervals) INITIALIZE_PASS_DEPENDENCY(RegisterCoalescer) INITIALIZE_PASS_DEPENDENCY(MachineScheduler) @@ -179,7 +179,7 @@ void RABasic::getAnalysisUsage(AnalysisUsage &AU) const { AU.addPreserved(); AU.addRequired(); AU.addPreserved(); - AU.addPreserved(); + AU.addPreserved(); AU.addRequired(); AU.addPreserved(); AU.addRequired(); diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp b/llvm/lib/CodeGen/RegAllocGreedy.cpp index b79b0e54124ce..2fdf63e32fb7c 100644 --- a/llvm/lib/CodeGen/RegAllocGreedy.cpp +++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp @@ -155,7 +155,7 @@ char &llvm::RAGreedyID = RAGreedy::ID; INITIALIZE_PASS_BEGIN(RAGreedy, "greedy", "Greedy Register Allocator", false, false) INITIALIZE_PASS_DEPENDENCY(LiveDebugVariables) -INITIALIZE_PASS_DEPENDENCY(SlotIndexes) +INITIALIZE_PASS_DEPENDENCY(SlotIndexesWrapperPass) INITIALIZE_PASS_DEPENDENCY(LiveIntervals) INITIALIZE_PASS_DEPENDENCY(RegisterCoalescer) INITIALIZE_PASS_DEPENDENCY(MachineScheduler) @@ -207,8 +207,8 @@ void RAGreedy::getAnalysisUsage(AnalysisUsage &AU) const { AU.addPreserved(); AU.addRequired(); AU.addPreserved(); - AU.addRequired(); - AU.addPreserved(); + AU.addRequired(); + AU.addPreserved(); AU.addRequired(); AU.addPreserved(); AU.addRequired(); @@ -2724,7 +2724,7 @@ bool RAGreedy::runOnMachineFunction(MachineFunction &mf) { if (!hasVirtRegAlloc()) return false; - Indexes = &getAnalysis(); + Indexes = &getAnalysis().getSI(); // Renumber to get accurate and consistent results from // SlotIndexes::getApproxInstrDistance. Indexes->packIndexes(); diff --git a/llvm/lib/CodeGen/RegAllocPBQP.cpp b/llvm/lib/CodeGen/RegAllocPBQP.cpp index 293c01b0f1176..dd7bd38060572 100644 --- a/llvm/lib/CodeGen/RegAllocPBQP.cpp +++ b/llvm/lib/CodeGen/RegAllocPBQP.cpp @@ -120,7 +120,7 @@ class RegAllocPBQP : public MachineFunctionPass { /// Construct a PBQP register allocator. RegAllocPBQP(char *cPassID = nullptr) : MachineFunctionPass(ID), customPassID(cPassID) { - initializeSlotIndexesPass(*PassRegistry::getPassRegistry()); + initializeSlotIndexesWrapperPassPass(*PassRegistry::getPassRegistry()); initializeLiveIntervalsPass(*PassRegistry::getPassRegistry()); initializeLiveStacksPass(*PassRegistry::getPassRegistry()); initializeVirtRegMapPass(*PassRegistry::getPassRegistry()); @@ -544,8 +544,8 @@ void RegAllocPBQP::getAnalysisUsage(AnalysisUsage &au) const { au.setPreservesCFG(); au.addRequired(); au.addPreserved(); - au.addRequired(); - au.addPreserved(); + au.addRequired(); + au.addPreserved(); au.addRequired(); au.addPreserved(); //au.addRequiredID(SplitCriticalEdgesID); diff --git a/llvm/lib/CodeGen/RegAllocPriorityAdvisor.cpp b/llvm/lib/CodeGen/RegAllocPriorityAdvisor.cpp index e031019a4c917..0650aaff56ea0 100644 --- a/llvm/lib/CodeGen/RegAllocPriorityAdvisor.cpp +++ b/llvm/lib/CodeGen/RegAllocPriorityAdvisor.cpp @@ -51,13 +51,13 @@ class DefaultPriorityAdvisorAnalysis final private: void getAnalysisUsage(AnalysisUsage &AU) const override { - AU.addRequired(); + AU.addRequired(); RegAllocPriorityAdvisorAnalysis::getAnalysisUsage(AU); } std::unique_ptr getAdvisor(const MachineFunction &MF, const RAGreedy &RA) override { return std::make_unique( - MF, RA, &getAnalysis()); + MF, RA, &getAnalysis().getSI()); } bool doInitialization(Module &M) override { if (NotAsRequested) diff --git a/llvm/lib/CodeGen/RegisterCoalescer.cpp b/llvm/lib/CodeGen/RegisterCoalescer.cpp index 7c7fb8fe0cfe2..c84650b730816 100644 --- a/llvm/lib/CodeGen/RegisterCoalescer.cpp +++ b/llvm/lib/CodeGen/RegisterCoalescer.cpp @@ -407,7 +407,7 @@ char &llvm::RegisterCoalescerID = RegisterCoalescer::ID; INITIALIZE_PASS_BEGIN(RegisterCoalescer, "register-coalescer", "Register Coalescer", false, false) INITIALIZE_PASS_DEPENDENCY(LiveIntervals) -INITIALIZE_PASS_DEPENDENCY(SlotIndexes) +INITIALIZE_PASS_DEPENDENCY(SlotIndexesWrapperPass) INITIALIZE_PASS_DEPENDENCY(MachineLoopInfoWrapperPass) INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass) INITIALIZE_PASS_END(RegisterCoalescer, "register-coalescer", @@ -590,7 +590,7 @@ void RegisterCoalescer::getAnalysisUsage(AnalysisUsage &AU) const { AU.addRequired(); AU.addRequired(); AU.addPreserved(); - AU.addPreserved(); + AU.addPreserved(); AU.addRequired(); AU.addPreserved(); AU.addPreservedID(MachineDominatorsID); diff --git a/llvm/lib/CodeGen/RenameIndependentSubregs.cpp b/llvm/lib/CodeGen/RenameIndependentSubregs.cpp index e888f290df510..2c4a0270172e6 100644 --- a/llvm/lib/CodeGen/RenameIndependentSubregs.cpp +++ b/llvm/lib/CodeGen/RenameIndependentSubregs.cpp @@ -56,8 +56,8 @@ class RenameIndependentSubregs : public MachineFunctionPass { AU.setPreservesCFG(); AU.addRequired(); AU.addPreserved(); - AU.addRequired(); - AU.addPreserved(); + AU.addRequired(); + AU.addPreserved(); MachineFunctionPass::getAnalysisUsage(AU); } @@ -114,7 +114,7 @@ char &llvm::RenameIndependentSubregsID = RenameIndependentSubregs::ID; INITIALIZE_PASS_BEGIN(RenameIndependentSubregs, DEBUG_TYPE, "Rename Independent Subregisters", false, false) -INITIALIZE_PASS_DEPENDENCY(SlotIndexes) +INITIALIZE_PASS_DEPENDENCY(SlotIndexesWrapperPass) INITIALIZE_PASS_DEPENDENCY(LiveIntervals) INITIALIZE_PASS_END(RenameIndependentSubregs, DEBUG_TYPE, "Rename Independent Subregisters", false, false) diff --git a/llvm/lib/CodeGen/SlotIndexes.cpp b/llvm/lib/CodeGen/SlotIndexes.cpp index a038b09c765c0..1b92a5aa59d18 100644 --- a/llvm/lib/CodeGen/SlotIndexes.cpp +++ b/llvm/lib/CodeGen/SlotIndexes.cpp @@ -18,10 +18,25 @@ using namespace llvm; #define DEBUG_TYPE "slotindexes" -char SlotIndexes::ID = 0; +AnalysisKey SlotIndexesAnalysis::Key; -SlotIndexes::SlotIndexes() : MachineFunctionPass(ID) { - initializeSlotIndexesPass(*PassRegistry::getPassRegistry()); +SlotIndexesAnalysis::Result +SlotIndexesAnalysis::run(MachineFunction &MF, + MachineFunctionAnalysisManager &) { + return Result(MF); +} + +PreservedAnalyses +SlotIndexesPrinterPass::run(MachineFunction &MF, + MachineFunctionAnalysisManager &MFAM) { + OS << "Slot indexes in machine function: " << MF.getName() << '\n'; + MFAM.getResult(MF).print(OS); + return PreservedAnalyses::all(); +} +char SlotIndexesWrapperPass::ID = 0; + +SlotIndexesWrapperPass::SlotIndexesWrapperPass() : MachineFunctionPass(ID) { + initializeSlotIndexesWrapperPassPass(*PassRegistry::getPassRegistry()); } SlotIndexes::~SlotIndexes() { @@ -29,17 +44,17 @@ SlotIndexes::~SlotIndexes() { indexList.clear(); } -INITIALIZE_PASS(SlotIndexes, DEBUG_TYPE, - "Slot index numbering", false, false) +INITIALIZE_PASS(SlotIndexesWrapperPass, DEBUG_TYPE, "Slot index numbering", + false, false) STATISTIC(NumLocalRenum, "Number of local renumberings"); -void SlotIndexes::getAnalysisUsage(AnalysisUsage &au) const { +void SlotIndexesWrapperPass::getAnalysisUsage(AnalysisUsage &au) const { au.setPreservesAll(); MachineFunctionPass::getAnalysisUsage(au); } -void SlotIndexes::releaseMemory() { +void SlotIndexes::clear() { mi2iMap.clear(); MBBRanges.clear(); idx2MBBMap.clear(); @@ -47,7 +62,7 @@ void SlotIndexes::releaseMemory() { ileAllocator.Reset(); } -bool SlotIndexes::runOnMachineFunction(MachineFunction &fn) { +void SlotIndexes::analyze(MachineFunction &fn) { // Compute numbering as follows: // Grab an iterator to the start of the index list. @@ -107,9 +122,6 @@ bool SlotIndexes::runOnMachineFunction(MachineFunction &fn) { llvm::sort(idx2MBBMap, less_first()); LLVM_DEBUG(mf->print(dbgs(), this)); - - // And we're done! - return false; } void SlotIndexes::removeMachineInstrFromMaps(MachineInstr &MI, @@ -242,22 +254,23 @@ void SlotIndexes::packIndexes() { Entry.setIndex(Index * SlotIndex::InstrDist); } -#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) -LLVM_DUMP_METHOD void SlotIndexes::dump() const { +void SlotIndexes::print(raw_ostream &OS) const { for (const IndexListEntry &ILE : indexList) { - dbgs() << ILE.getIndex() << " "; + OS << ILE.getIndex() << ' '; - if (ILE.getInstr()) { - dbgs() << *ILE.getInstr(); - } else { - dbgs() << "\n"; - } + if (ILE.getInstr()) + OS << *ILE.getInstr(); + else + OS << '\n'; } for (unsigned i = 0, e = MBBRanges.size(); i != e; ++i) - dbgs() << "%bb." << i << "\t[" << MBBRanges[i].first << ';' - << MBBRanges[i].second << ")\n"; + OS << "%bb." << i << "\t[" << MBBRanges[i].first << ';' + << MBBRanges[i].second << ")\n"; } + +#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) +LLVM_DUMP_METHOD void SlotIndexes::dump() const { print(dbgs()); } #endif // Print a SlotIndex to a raw_ostream. diff --git a/llvm/lib/CodeGen/StackColoring.cpp b/llvm/lib/CodeGen/StackColoring.cpp index 10c69cdc0d87f..341ec629bedd9 100644 --- a/llvm/lib/CodeGen/StackColoring.cpp +++ b/llvm/lib/CodeGen/StackColoring.cpp @@ -517,12 +517,12 @@ char &llvm::StackColoringID = StackColoring::ID; INITIALIZE_PASS_BEGIN(StackColoring, DEBUG_TYPE, "Merge disjoint stack slots", false, false) -INITIALIZE_PASS_DEPENDENCY(SlotIndexes) +INITIALIZE_PASS_DEPENDENCY(SlotIndexesWrapperPass) INITIALIZE_PASS_END(StackColoring, DEBUG_TYPE, "Merge disjoint stack slots", false, false) void StackColoring::getAnalysisUsage(AnalysisUsage &AU) const { - AU.addRequired(); + AU.addRequired(); MachineFunctionPass::getAnalysisUsage(AU); } @@ -1183,7 +1183,7 @@ bool StackColoring::runOnMachineFunction(MachineFunction &Func) { << "********** Function: " << Func.getName() << '\n'); MF = &Func; MFI = &MF->getFrameInfo(); - Indexes = &getAnalysis(); + Indexes = &getAnalysis().getSI(); BlockLiveness.clear(); BasicBlocks.clear(); BasicBlockNumbering.clear(); diff --git a/llvm/lib/CodeGen/StackSlotColoring.cpp b/llvm/lib/CodeGen/StackSlotColoring.cpp index 5f039ea63a823..928ec39ad25a8 100644 --- a/llvm/lib/CodeGen/StackSlotColoring.cpp +++ b/llvm/lib/CodeGen/StackSlotColoring.cpp @@ -148,8 +148,8 @@ namespace { void getAnalysisUsage(AnalysisUsage &AU) const override { AU.setPreservesCFG(); - AU.addRequired(); - AU.addPreserved(); + AU.addRequired(); + AU.addPreserved(); AU.addRequired(); AU.addRequired(); AU.addPreserved(); @@ -185,7 +185,7 @@ char &llvm::StackSlotColoringID = StackSlotColoring::ID; INITIALIZE_PASS_BEGIN(StackSlotColoring, DEBUG_TYPE, "Stack Slot Coloring", false, false) -INITIALIZE_PASS_DEPENDENCY(SlotIndexes) +INITIALIZE_PASS_DEPENDENCY(SlotIndexesWrapperPass) INITIALIZE_PASS_DEPENDENCY(LiveStacks) INITIALIZE_PASS_DEPENDENCY(MachineLoopInfoWrapperPass) INITIALIZE_PASS_END(StackSlotColoring, DEBUG_TYPE, @@ -528,7 +528,7 @@ bool StackSlotColoring::runOnMachineFunction(MachineFunction &MF) { TII = MF.getSubtarget().getInstrInfo(); LS = &getAnalysis(); MBFI = &getAnalysis(); - Indexes = &getAnalysis(); + Indexes = &getAnalysis().getSI(); bool Changed = false; diff --git a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp index bf6d694280aa1..eb6f36892d8e7 100644 --- a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp +++ b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp @@ -197,7 +197,7 @@ class TwoAddressInstructionPass : public MachineFunctionPass { AU.addUsedIfAvailable(); AU.addUsedIfAvailable(); AU.addPreserved(); - AU.addPreserved(); + AU.addPreserved(); AU.addPreserved(); AU.addPreservedID(MachineLoopInfoID); AU.addPreservedID(MachineDominatorsID); diff --git a/llvm/lib/CodeGen/VirtRegMap.cpp b/llvm/lib/CodeGen/VirtRegMap.cpp index 2c778980f5d1e..c2c13ea3a3e7c 100644 --- a/llvm/lib/CodeGen/VirtRegMap.cpp +++ b/llvm/lib/CodeGen/VirtRegMap.cpp @@ -228,7 +228,7 @@ char &llvm::VirtRegRewriterID = VirtRegRewriter::ID; INITIALIZE_PASS_BEGIN(VirtRegRewriter, "virtregrewriter", "Virtual Register Rewriter", false, false) -INITIALIZE_PASS_DEPENDENCY(SlotIndexes) +INITIALIZE_PASS_DEPENDENCY(SlotIndexesWrapperPass) INITIALIZE_PASS_DEPENDENCY(LiveIntervals) INITIALIZE_PASS_DEPENDENCY(LiveDebugVariables) INITIALIZE_PASS_DEPENDENCY(LiveStacks) @@ -240,8 +240,8 @@ void VirtRegRewriter::getAnalysisUsage(AnalysisUsage &AU) const { AU.setPreservesCFG(); AU.addRequired(); AU.addPreserved(); - AU.addRequired(); - AU.addPreserved(); + AU.addRequired(); + AU.addPreserved(); AU.addRequired(); AU.addRequired(); AU.addPreserved(); @@ -258,7 +258,7 @@ bool VirtRegRewriter::runOnMachineFunction(MachineFunction &fn) { TRI = MF->getSubtarget().getRegisterInfo(); TII = MF->getSubtarget().getInstrInfo(); MRI = &MF->getRegInfo(); - Indexes = &getAnalysis(); + Indexes = &getAnalysis().getSI(); LIS = &getAnalysis(); VRM = &getAnalysis(); DebugVars = &getAnalysis(); diff --git a/llvm/lib/Passes/PassBuilder.cpp b/llvm/lib/Passes/PassBuilder.cpp index 4185eac5bc7ad..4f3867826bfa0 100644 --- a/llvm/lib/Passes/PassBuilder.cpp +++ b/llvm/lib/Passes/PassBuilder.cpp @@ -107,6 +107,7 @@ #include "llvm/CodeGen/SelectOptimize.h" #include "llvm/CodeGen/ShadowStackGCLowering.h" #include "llvm/CodeGen/SjLjEHPrepare.h" +#include "llvm/CodeGen/SlotIndexes.h" #include "llvm/CodeGen/StackProtector.h" #include "llvm/CodeGen/TargetPassConfig.h" #include "llvm/CodeGen/TypePromotion.h" diff --git a/llvm/lib/Target/AMDGPU/AMDGPUMarkLastScratchLoad.cpp b/llvm/lib/Target/AMDGPU/AMDGPUMarkLastScratchLoad.cpp index 0692a12a40611..be809fc120637 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUMarkLastScratchLoad.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUMarkLastScratchLoad.cpp @@ -42,7 +42,7 @@ class AMDGPUMarkLastScratchLoad : public MachineFunctionPass { bool runOnMachineFunction(MachineFunction &MF) override; void getAnalysisUsage(AnalysisUsage &AU) const override { - AU.addRequired(); + AU.addRequired(); AU.addRequired(); AU.addRequired(); AU.setPreservesAll(); @@ -66,7 +66,7 @@ bool AMDGPUMarkLastScratchLoad::runOnMachineFunction(MachineFunction &MF) { LS = &getAnalysis(); LIS = &getAnalysis(); - SI = &getAnalysis(); + SI = &getAnalysis().getSI(); SII = ST.getInstrInfo(); SlotIndexes &Slots = *LIS->getSlotIndexes(); @@ -136,7 +136,7 @@ char &llvm::AMDGPUMarkLastScratchLoadID = AMDGPUMarkLastScratchLoad::ID; INITIALIZE_PASS_BEGIN(AMDGPUMarkLastScratchLoad, DEBUG_TYPE, "AMDGPU Mark last scratch load", false, false) -INITIALIZE_PASS_DEPENDENCY(SlotIndexes) +INITIALIZE_PASS_DEPENDENCY(SlotIndexesWrapperPass) INITIALIZE_PASS_DEPENDENCY(LiveStacks) INITIALIZE_PASS_END(AMDGPUMarkLastScratchLoad, DEBUG_TYPE, "AMDGPU Mark last scratch load", false, false) diff --git a/llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.cpp b/llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.cpp index 019b64dd871e2..e6dd3042887b9 100644 --- a/llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.cpp +++ b/llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.cpp @@ -58,7 +58,7 @@ class GCNRewritePartialRegUses : public MachineFunctionPass { void getAnalysisUsage(AnalysisUsage &AU) const override { AU.setPreservesCFG(); AU.addPreserved(); - AU.addPreserved(); + AU.addPreserved(); MachineFunctionPass::getAnalysisUsage(AU); } diff --git a/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp b/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp index ec70099309e66..4bccf2b1ff671 100644 --- a/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp +++ b/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp @@ -150,7 +150,7 @@ class SILowerControlFlow : public MachineFunctionPass { AU.addUsedIfAvailable(); // Should preserve the same set that TwoAddressInstructions does. AU.addPreserved(); - AU.addPreserved(); + AU.addPreserved(); AU.addPreserved(); AU.addPreservedID(LiveVariablesID); MachineFunctionPass::getAnalysisUsage(AU); diff --git a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp index b6a0152f6fa83..1ca419b93c9f5 100644 --- a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp +++ b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp @@ -312,7 +312,8 @@ bool SILowerSGPRSpills::runOnMachineFunction(MachineFunction &MF) { TRI = &TII->getRegisterInfo(); LIS = getAnalysisIfAvailable(); - Indexes = getAnalysisIfAvailable(); + auto *SIWrapper = getAnalysisIfAvailable(); + Indexes = SIWrapper ? &SIWrapper->getSI() : nullptr; assert(SaveBlocks.empty() && RestoreBlocks.empty()); diff --git a/llvm/lib/Target/AMDGPU/SILowerWWMCopies.cpp b/llvm/lib/Target/AMDGPU/SILowerWWMCopies.cpp index 9c3cd1bbd6b0f..c05406b21a45c 100644 --- a/llvm/lib/Target/AMDGPU/SILowerWWMCopies.cpp +++ b/llvm/lib/Target/AMDGPU/SILowerWWMCopies.cpp @@ -103,7 +103,8 @@ bool SILowerWWMCopies::runOnMachineFunction(MachineFunction &MF) { MFI = MF.getInfo(); LIS = getAnalysisIfAvailable(); - Indexes = getAnalysisIfAvailable(); + auto *SIWrapper = getAnalysisIfAvailable(); + Indexes = SIWrapper ? &SIWrapper->getSI() : nullptr; VRM = getAnalysisIfAvailable(); TRI = ST.getRegisterInfo(); MRI = &MF.getRegInfo(); diff --git a/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp b/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp index 742fd397ff9e3..b39f3ba970600 100644 --- a/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp +++ b/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp @@ -237,7 +237,7 @@ class SIWholeQuadMode : public MachineFunctionPass { void getAnalysisUsage(AnalysisUsage &AU) const override { AU.addRequired(); - AU.addPreserved(); + AU.addPreserved(); AU.addPreserved(); AU.addPreserved(); AU.addPreserved(); diff --git a/llvm/lib/Target/Hexagon/HexagonCopyHoisting.cpp b/llvm/lib/Target/Hexagon/HexagonCopyHoisting.cpp index a5c47e67de892..9cfbaf9452587 100644 --- a/llvm/lib/Target/Hexagon/HexagonCopyHoisting.cpp +++ b/llvm/lib/Target/Hexagon/HexagonCopyHoisting.cpp @@ -46,9 +46,9 @@ class HexagonCopyHoisting : public MachineFunctionPass { StringRef getPassName() const override { return "Hexagon Copy Hoisting"; } void getAnalysisUsage(AnalysisUsage &AU) const override { - AU.addRequired(); + AU.addRequired(); AU.addRequired(); - AU.addPreserved(); + AU.addPreserved(); AU.addPreserved(); AU.addRequired(); AU.addPreserved(); @@ -109,8 +109,7 @@ bool HexagonCopyHoisting::runOnMachineFunction(MachineFunction &Fn) { if (Changed) { LiveIntervals &LIS = getAnalysis(); SlotIndexes *SI = LIS.getSlotIndexes(); - SI->releaseMemory(); - SI->runOnMachineFunction(Fn); + SI->reanalyze(Fn); LIS.releaseMemory(); LIS.runOnMachineFunction(Fn); } diff --git a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp index 8a23b7743e839..65093e054dc4e 100644 --- a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp +++ b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp @@ -154,7 +154,7 @@ namespace { void getAnalysisUsage(AnalysisUsage &AU) const override { AU.addRequired(); AU.addPreserved(); - AU.addPreserved(); + AU.addPreserved(); AU.addRequired(); AU.addPreserved(); MachineFunctionPass::getAnalysisUsage(AU); @@ -255,7 +255,7 @@ namespace llvm { INITIALIZE_PASS_BEGIN(HexagonExpandCondsets, "expand-condsets", "Hexagon Expand Condsets", false, false) INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass) -INITIALIZE_PASS_DEPENDENCY(SlotIndexes) +INITIALIZE_PASS_DEPENDENCY(SlotIndexesWrapperPass) INITIALIZE_PASS_DEPENDENCY(LiveIntervals) INITIALIZE_PASS_END(HexagonExpandCondsets, "expand-condsets", "Hexagon Expand Condsets", false, false) diff --git a/llvm/lib/Target/Hexagon/HexagonTfrCleanup.cpp b/llvm/lib/Target/Hexagon/HexagonTfrCleanup.cpp index a4b359af303a3..282e8126146eb 100644 --- a/llvm/lib/Target/Hexagon/HexagonTfrCleanup.cpp +++ b/llvm/lib/Target/Hexagon/HexagonTfrCleanup.cpp @@ -282,7 +282,8 @@ bool HexagonTfrCleanup::runOnMachineFunction(MachineFunction &MF) { // Map: 32-bit register -> immediate value. // 64-bit registers are stored through their subregisters. ImmediateMap IMap; - SlotIndexes *Indexes = this->getAnalysisIfAvailable(); + auto *SIWrapper = getAnalysisIfAvailable(); + SlotIndexes *Indexes = SIWrapper ? &SIWrapper->getSI() : nullptr; auto &HST = MF.getSubtarget(); HII = HST.getInstrInfo(); diff --git a/llvm/lib/Target/LoongArch/LoongArchDeadRegisterDefinitions.cpp b/llvm/lib/Target/LoongArch/LoongArchDeadRegisterDefinitions.cpp index 6ff9b6ac25b7c..eb589dafd4e3f 100644 --- a/llvm/lib/Target/LoongArch/LoongArchDeadRegisterDefinitions.cpp +++ b/llvm/lib/Target/LoongArch/LoongArchDeadRegisterDefinitions.cpp @@ -38,7 +38,7 @@ class LoongArchDeadRegisterDefinitions : public MachineFunctionPass { AU.addRequired(); AU.addPreserved(); AU.addRequired(); - AU.addPreserved(); + AU.addPreserved(); AU.addPreserved(); AU.addPreserved(); MachineFunctionPass::getAnalysisUsage(AU); diff --git a/llvm/lib/Target/PowerPC/PPCTLSDynamicCall.cpp b/llvm/lib/Target/PowerPC/PPCTLSDynamicCall.cpp index 9f680ef5046da..3ad89641d21cc 100644 --- a/llvm/lib/Target/PowerPC/PPCTLSDynamicCall.cpp +++ b/llvm/lib/Target/PowerPC/PPCTLSDynamicCall.cpp @@ -326,7 +326,7 @@ namespace { void getAnalysisUsage(AnalysisUsage &AU) const override { AU.addRequired(); - AU.addRequired(); + AU.addRequired(); MachineFunctionPass::getAnalysisUsage(AU); } }; @@ -335,7 +335,7 @@ namespace { INITIALIZE_PASS_BEGIN(PPCTLSDynamicCall, DEBUG_TYPE, "PowerPC TLS Dynamic Call Fixup", false, false) INITIALIZE_PASS_DEPENDENCY(LiveIntervals) -INITIALIZE_PASS_DEPENDENCY(SlotIndexes) +INITIALIZE_PASS_DEPENDENCY(SlotIndexesWrapperPass) INITIALIZE_PASS_END(PPCTLSDynamicCall, DEBUG_TYPE, "PowerPC TLS Dynamic Call Fixup", false, false) diff --git a/llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp b/llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp index 69e046972f3d4..b1a1f44dc9fe8 100644 --- a/llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp +++ b/llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp @@ -366,8 +366,8 @@ namespace { void getAnalysisUsage(AnalysisUsage &AU) const override { AU.addRequired(); AU.addPreserved(); - AU.addRequired(); - AU.addPreserved(); + AU.addRequired(); + AU.addPreserved(); AU.addRequired(); AU.addPreserved(); MachineFunctionPass::getAnalysisUsage(AU); @@ -378,7 +378,7 @@ namespace { INITIALIZE_PASS_BEGIN(PPCVSXFMAMutate, DEBUG_TYPE, "PowerPC VSX FMA Mutation", false, false) INITIALIZE_PASS_DEPENDENCY(LiveIntervals) -INITIALIZE_PASS_DEPENDENCY(SlotIndexes) +INITIALIZE_PASS_DEPENDENCY(SlotIndexesWrapperPass) INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass) INITIALIZE_PASS_END(PPCVSXFMAMutate, DEBUG_TYPE, "PowerPC VSX FMA Mutation", false, false) diff --git a/llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp b/llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp index 7de48d8218f06..d2c42f98dd893 100644 --- a/llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp +++ b/llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp @@ -38,7 +38,7 @@ class RISCVDeadRegisterDefinitions : public MachineFunctionPass { AU.addRequired(); AU.addPreserved(); AU.addRequired(); - AU.addPreserved(); + AU.addPreserved(); AU.addPreserved(); AU.addPreserved(); MachineFunctionPass::getAnalysisUsage(AU); diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp index 9c76bb15035eb..a92118b1444b8 100644 --- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp +++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp @@ -893,7 +893,7 @@ class RISCVInsertVSETVLI : public MachineFunctionPass { AU.addUsedIfAvailable(); AU.addPreserved(); - AU.addPreserved(); + AU.addPreserved(); AU.addPreserved(); AU.addPreserved(); diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyMemIntrinsicResults.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyMemIntrinsicResults.cpp index 2ab5bcdd838d0..f2aebacebddf3 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyMemIntrinsicResults.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyMemIntrinsicResults.cpp @@ -59,7 +59,7 @@ class WebAssemblyMemIntrinsicResults final : public MachineFunctionPass { AU.addRequired(); AU.addPreserved(); AU.addRequired(); - AU.addPreserved(); + AU.addPreserved(); AU.addPreserved(); AU.addRequired(); MachineFunctionPass::getAnalysisUsage(AU); diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyOptimizeLiveIntervals.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyOptimizeLiveIntervals.cpp index d542ddb45c2e2..affaa454b734f 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyOptimizeLiveIntervals.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyOptimizeLiveIntervals.cpp @@ -42,7 +42,7 @@ class WebAssemblyOptimizeLiveIntervals final : public MachineFunctionPass { AU.setPreservesCFG(); AU.addRequired(); AU.addPreserved(); - AU.addPreserved(); + AU.addPreserved(); AU.addPreserved(); AU.addPreservedID(LiveVariablesID); AU.addPreservedID(MachineDominatorsID); diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp index 87e63a1cebc3b..a53b4d478a20f 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp @@ -52,7 +52,7 @@ class WebAssemblyRegStackify final : public MachineFunctionPass { AU.addRequired(); AU.addRequired(); AU.addPreserved(); - AU.addPreserved(); + AU.addPreserved(); AU.addPreserved(); AU.addPreservedID(LiveVariablesID); AU.addPreserved(); diff --git a/llvm/test/CodeGen/X86/slot-indexes.ll b/llvm/test/CodeGen/X86/slot-indexes.ll new file mode 100644 index 0000000000000..8ca89383813a2 --- /dev/null +++ b/llvm/test/CodeGen/X86/slot-indexes.ll @@ -0,0 +1,11 @@ +; RUN: llc -mtriple=x86_64-pc-linux -stop-after=slotindexes %s -o - | llc -passes='print' -x mir 2>&1 | FileCheck %s + +define void @foo(){ + ret void +} + +; CHECK: Slot indexes in machine function: foo +; CHECK: 0 +; CHECK: 16 RET64 +; CHECK: 32 +; CHECK: %bb.0 [0B;32B)