diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp index 3bb50c08bee047..08f1c9ffb738a3 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp @@ -77,6 +77,12 @@ MCInst RISCVInstrInfo::getNop() const { .addImm(0); } +unsigned RISCVInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, + int &FrameIndex) const { + unsigned Dummy; + return isLoadFromStackSlot(MI, FrameIndex, Dummy); +} + unsigned RISCVInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex, unsigned &MemBytes) const { @@ -112,6 +118,12 @@ unsigned RISCVInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, return 0; } +unsigned RISCVInstrInfo::isStoreToStackSlot(const MachineInstr &MI, + int &FrameIndex) const { + unsigned Dummy; + return isStoreToStackSlot(MI, FrameIndex, Dummy); +} + unsigned RISCVInstrInfo::isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex, unsigned &MemBytes) const { diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h index f0f5fd14922ff4..cc84e9c07d0d6a 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h @@ -49,8 +49,12 @@ class RISCVInstrInfo : public RISCVGenInstrInfo { MCInst getNop() const override; const MCInstrDesc &getBrCond(RISCVCC::CondCode CC) const; + unsigned isLoadFromStackSlot(const MachineInstr &MI, + int &FrameIndex) const override; unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex, unsigned &MemBytes) const override; + unsigned isStoreToStackSlot(const MachineInstr &MI, + int &FrameIndex) const override; unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex, unsigned &MemBytes) const override;