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Followup on Proposal to move MIR physical register namespace to '$' s…
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…igil.

Discussed here:

http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html

In preparation for adding support for named vregs we are changing the sigil for
physical registers in MIR to '$' from '%'. This will prevent name clashes of
named physical register with named vregs.

llvm-svn: 323922
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@plotfi
plotfi committed Jan 31, 2018
1 parent de07acb commit 43e94b1
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Showing 970 changed files with 29,359 additions and 29,350 deletions.
23 changes: 16 additions & 7 deletions llvm/lib/CodeGen/MIRParser/MILexer.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -410,17 +410,26 @@ static bool isRegisterChar(char C) {
return isIdentifierChar(C) && C != '.';
}

static Cursor maybeLexRegister(Cursor C, MIToken &Token) {
if (C.peek() != '%')
static Cursor maybeLexRegister(Cursor C, MIToken &Token,
ErrorCallbackType ErrorCallback) {
if (C.peek() != '%' && C.peek() != '$')
return None;
if (isdigit(C.peek(1)))
return lexVirtualRegister(C, Token);

if (C.peek() == '%') {
if (isdigit(C.peek(1)))
return lexVirtualRegister(C, Token);

// ErrorCallback(Token.location(), "Named vregs are not yet supported.");
return None;
}

assert(C.peek() == '$');
auto Range = C;
C.advance(); // Skip '%'
C.advance(); // Skip '$'
while (isRegisterChar(C.peek()))
C.advance();
Token.reset(MIToken::NamedRegister, Range.upto(C))
.setStringValue(Range.upto(C).drop_front(1)); // Drop the '%'
.setStringValue(Range.upto(C).drop_front(1)); // Drop the '$'
return C;
}

Expand Down Expand Up @@ -642,7 +651,7 @@ StringRef llvm::lexMIToken(StringRef Source, MIToken &Token,
return R.remaining();
if (Cursor R = maybeLexIRValue(C, Token, ErrorCallback))
return R.remaining();
if (Cursor R = maybeLexRegister(C, Token))
if (Cursor R = maybeLexRegister(C, Token, ErrorCallback))
return R.remaining();
if (Cursor R = maybeLexGlobalValue(C, Token, ErrorCallback))
return R.remaining();
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6 changes: 3 additions & 3 deletions llvm/lib/CodeGen/TargetRegisterInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -89,15 +89,15 @@ Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI,
unsigned SubIdx) {
return Printable([Reg, TRI, SubIdx](raw_ostream &OS) {
if (!Reg)
OS << "%noreg";
OS << "$noreg";
else if (TargetRegisterInfo::isStackSlot(Reg))
OS << "SS#" << TargetRegisterInfo::stackSlot2Index(Reg);
else if (TargetRegisterInfo::isVirtualRegister(Reg))
OS << '%' << TargetRegisterInfo::virtReg2Index(Reg);
else if (!TRI)
OS << '%' << "physreg" << Reg;
OS << '$' << "physreg" << Reg;
else if (Reg < TRI->getNumRegs()) {
OS << '%';
OS << '$';
printLowerCase(TRI->getName(Reg), OS);
} else
llvm_unreachable("Register kind is unsupported.");
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv-ios.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -13,9 +13,9 @@ target triple = "aarch64-apple-ios9.0"
; CHECK: [[F_ONE:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
; CHECK: [[TWO:%[0-9]+]]:_(s64) = G_FCONSTANT double 2.000000e+00

; CHECK: %w0 = COPY [[ANSWER]]
; CHECK: %d0 = COPY [[D_ONE]]
; CHECK: %x1 = COPY [[TWELVE]]
; CHECK: $w0 = COPY [[ANSWER]]
; CHECK: $d0 = COPY [[D_ONE]]
; CHECK: $x1 = COPY [[TWELVE]]
; CHECK: G_STORE [[THREE]](s8), {{%[0-9]+}}(p0) :: (store 1 into stack, align 0)
; CHECK: G_STORE [[ONE]](s16), {{%[0-9]+}}(p0) :: (store 2 into stack + 8, align 0)
; CHECK: G_STORE [[FOUR]](s32), {{%[0-9]+}}(p0) :: (store 4 into stack + 16, align 0)
Expand Down
74 changes: 37 additions & 37 deletions llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -4,55 +4,55 @@ target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
target triple = "aarch64-linux-gnu"

; CHECK-LABEL: name: args_i32
; CHECK: %[[ARG0:[0-9]+]]:_(s32) = COPY %w0
; CHECK: %{{[0-9]+}}:_(s32) = COPY %w1
; CHECK: %{{[0-9]+}}:_(s32) = COPY %w2
; CHECK: %{{[0-9]+}}:_(s32) = COPY %w3
; CHECK: %{{[0-9]+}}:_(s32) = COPY %w4
; CHECK: %{{[0-9]+}}:_(s32) = COPY %w5
; CHECK: %{{[0-9]+}}:_(s32) = COPY %w6
; CHECK: %{{[0-9]+}}:_(s32) = COPY %w7
; CHECK: %w0 = COPY %[[ARG0]]
; CHECK: %[[ARG0:[0-9]+]]:_(s32) = COPY $w0
; CHECK: %{{[0-9]+}}:_(s32) = COPY $w1
; CHECK: %{{[0-9]+}}:_(s32) = COPY $w2
; CHECK: %{{[0-9]+}}:_(s32) = COPY $w3
; CHECK: %{{[0-9]+}}:_(s32) = COPY $w4
; CHECK: %{{[0-9]+}}:_(s32) = COPY $w5
; CHECK: %{{[0-9]+}}:_(s32) = COPY $w6
; CHECK: %{{[0-9]+}}:_(s32) = COPY $w7
; CHECK: $w0 = COPY %[[ARG0]]

define i32 @args_i32(i32 %w0, i32 %w1, i32 %w2, i32 %w3,
i32 %w4, i32 %w5, i32 %w6, i32 %w7) {
ret i32 %w0
}

; CHECK-LABEL: name: args_i64
; CHECK: %[[ARG0:[0-9]+]]:_(s64) = COPY %x0
; CHECK: %{{[0-9]+}}:_(s64) = COPY %x1
; CHECK: %{{[0-9]+}}:_(s64) = COPY %x2
; CHECK: %{{[0-9]+}}:_(s64) = COPY %x3
; CHECK: %{{[0-9]+}}:_(s64) = COPY %x4
; CHECK: %{{[0-9]+}}:_(s64) = COPY %x5
; CHECK: %{{[0-9]+}}:_(s64) = COPY %x6
; CHECK: %{{[0-9]+}}:_(s64) = COPY %x7
; CHECK: %x0 = COPY %[[ARG0]]
; CHECK: %[[ARG0:[0-9]+]]:_(s64) = COPY $x0
; CHECK: %{{[0-9]+}}:_(s64) = COPY $x1
; CHECK: %{{[0-9]+}}:_(s64) = COPY $x2
; CHECK: %{{[0-9]+}}:_(s64) = COPY $x3
; CHECK: %{{[0-9]+}}:_(s64) = COPY $x4
; CHECK: %{{[0-9]+}}:_(s64) = COPY $x5
; CHECK: %{{[0-9]+}}:_(s64) = COPY $x6
; CHECK: %{{[0-9]+}}:_(s64) = COPY $x7
; CHECK: $x0 = COPY %[[ARG0]]
define i64 @args_i64(i64 %x0, i64 %x1, i64 %x2, i64 %x3,
i64 %x4, i64 %x5, i64 %x6, i64 %x7) {
ret i64 %x0
}


; CHECK-LABEL: name: args_ptrs
; CHECK: %[[ARG0:[0-9]+]]:_(p0) = COPY %x0
; CHECK: %{{[0-9]+}}:_(p0) = COPY %x1
; CHECK: %{{[0-9]+}}:_(p0) = COPY %x2
; CHECK: %{{[0-9]+}}:_(p0) = COPY %x3
; CHECK: %{{[0-9]+}}:_(p0) = COPY %x4
; CHECK: %{{[0-9]+}}:_(p0) = COPY %x5
; CHECK: %{{[0-9]+}}:_(p0) = COPY %x6
; CHECK: %{{[0-9]+}}:_(p0) = COPY %x7
; CHECK: %x0 = COPY %[[ARG0]]
; CHECK: %[[ARG0:[0-9]+]]:_(p0) = COPY $x0
; CHECK: %{{[0-9]+}}:_(p0) = COPY $x1
; CHECK: %{{[0-9]+}}:_(p0) = COPY $x2
; CHECK: %{{[0-9]+}}:_(p0) = COPY $x3
; CHECK: %{{[0-9]+}}:_(p0) = COPY $x4
; CHECK: %{{[0-9]+}}:_(p0) = COPY $x5
; CHECK: %{{[0-9]+}}:_(p0) = COPY $x6
; CHECK: %{{[0-9]+}}:_(p0) = COPY $x7
; CHECK: $x0 = COPY %[[ARG0]]
define i8* @args_ptrs(i8* %x0, i16* %x1, <2 x i8>* %x2, {i8, i16, i32}* %x3,
[3 x float]* %x4, double* %x5, i8* %x6, i8* %x7) {
ret i8* %x0
}

; CHECK-LABEL: name: args_arr
; CHECK: %[[ARG0:[0-9]+]]:_(s64) = COPY %d0
; CHECK: %d0 = COPY %[[ARG0]]
; CHECK: %[[ARG0:[0-9]+]]:_(s64) = COPY $d0
; CHECK: $d0 = COPY %[[ARG0]]
define [1 x double] @args_arr([1 x double] %d0) {
ret [1 x double] %d0
}
Expand All @@ -67,16 +67,16 @@ define [1 x double] @args_arr([1 x double] %d0) {
; CHECK: [[F_ONE:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
; CHECK: [[TWO:%[0-9]+]]:_(s64) = G_FCONSTANT double 2.000000e+00

; CHECK: %w0 = COPY [[ANSWER]]
; CHECK: %d0 = COPY [[D_ONE]]
; CHECK: %x1 = COPY [[TWELVE]]
; CHECK: $w0 = COPY [[ANSWER]]
; CHECK: $d0 = COPY [[D_ONE]]
; CHECK: $x1 = COPY [[TWELVE]]
; CHECK: [[THREE_TMP:%[0-9]+]]:_(s32) = G_ANYEXT [[THREE]]
; CHECK: %w2 = COPY [[THREE_TMP]](s32)
; CHECK: $w2 = COPY [[THREE_TMP]](s32)
; CHECK: [[ONE_TMP:%[0-9]+]]:_(s32) = G_ANYEXT [[ONE]]
; CHECK: %w3 = COPY [[ONE_TMP]](s32)
; CHECK: %w4 = COPY [[FOUR]](s32)
; CHECK: %s1 = COPY [[F_ONE]](s32)
; CHECK: %d2 = COPY [[TWO]](s64)
; CHECK: $w3 = COPY [[ONE_TMP]](s32)
; CHECK: $w4 = COPY [[FOUR]](s32)
; CHECK: $s1 = COPY [[F_ONE]](s32)
; CHECK: $d2 = COPY [[TWO]](s64)
declare void @varargs(i32, double, i64, ...)
define void @test_varargs() {
call void(i32, double, i64, ...) @varargs(i32 42, double 1.0, i64 12, i8 3, i16 1, i32 4, float 1.0, double 2.0)
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