diff --git a/clang/test/OpenMP/parallel_master_taskloop_firstprivate_codegen.cpp b/clang/test/OpenMP/parallel_master_taskloop_firstprivate_codegen.cpp index 4a2bc4b8d609ad..75b99b1a003183 100644 --- a/clang/test/OpenMP/parallel_master_taskloop_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/parallel_master_taskloop_firstprivate_codegen.cpp @@ -1,17 +1,17 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ -// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=LAMBDA %s -// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=BLOCKS %s -// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=ARRAY %s +// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s +// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=LAMBDA %s +// RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=BLOCKS %s +// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=ARRAY %s -// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s -// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY2 %s -// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY3 %s -// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY4 %s +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY2 %s +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY3 %s +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY4 %s // expected-no-diagnostics #ifndef ARRAY @@ -201,376 +201,356 @@ void array_func(int n, float a[n], St s[2]) { // CHECK-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 16 // CHECK-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 8 // CHECK-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[TTT]]) -// CHECK-NEXT: call void @_ZN1SIdEC1ERKS0_d(%struct.S* noundef nonnull align 8 dereferenceable(8) [[TEST]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[TTT]], double noundef 0.000000e+00) -// CHECK-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* noundef nonnull align 8 dereferenceable(8) [[ARRAYINIT_BEGIN]], double noundef 1.000000e+00) -// CHECK-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* noundef nonnull align 8 dereferenceable(8) [[ARRAYINIT_ELEMENT]], double noundef 2.000000e+00) -// CHECK-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* noundef nonnull align 8 dereferenceable(8) [[VAR]], double noundef 3.000000e+00) -// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4 -// CHECK-NEXT: [[TMP2:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 -// CHECK-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*)* @main.omp_outlined to void (i32*, i32*, ...)*), [2 x i32]* [[VEC]], i64 [[TMP2]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[VAR]]) +// CHECK-NEXT: store i32 0, ptr [[RETVAL]], align 4 +// CHECK-NEXT: call void @_ZN1SIdEC1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[TTT]]) +// CHECK-NEXT: call void @_ZN1SIdEC1ERKS0_d(ptr noundef nonnull align 8 dereferenceable(8) [[TEST]], ptr noundef nonnull align 8 dereferenceable(8) [[TTT]], double noundef 0.000000e+00) +// CHECK-NEXT: store i32 0, ptr [[T_VAR]], align 4 +// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const.main.vec, i64 8, i1 false) +// CHECK-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 0 +// CHECK-NEXT: call void @_ZN1SIdEC1Ed(ptr noundef nonnull align 8 dereferenceable(8) [[ARRAYINIT_BEGIN]], double noundef 1.000000e+00) +// CHECK-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYINIT_BEGIN]], i64 1 +// CHECK-NEXT: call void @_ZN1SIdEC1Ed(ptr noundef nonnull align 8 dereferenceable(8) [[ARRAYINIT_ELEMENT]], double noundef 2.000000e+00) +// CHECK-NEXT: call void @_ZN1SIdEC1Ed(ptr noundef nonnull align 8 dereferenceable(8) [[VAR]], double noundef 3.000000e+00) +// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[T_VAR]], align 4 +// CHECK-NEXT: store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 +// CHECK-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 4, ptr @main.omp_outlined, ptr [[VEC]], i64 [[TMP1]], ptr [[S_ARR]], ptr [[VAR]]) // CHECK-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() -// CHECK-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[VAR]]) #[[ATTR4:[0-9]+]] -// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 +// CHECK-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[VAR]]) #[[ATTR4:[0-9]+]] +// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK: arraydestroy.body: -// CHECK-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP3]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK: arraydestroy.done1: -// CHECK-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[TEST]]) #[[ATTR4]] -// CHECK-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[TTT]]) #[[ATTR4]] -// CHECK-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK-NEXT: ret i32 [[TMP4]] +// CHECK-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[TEST]]) #[[ATTR4]] +// CHECK-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[TTT]]) #[[ATTR4]] +// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[RETVAL]], align 4 +// CHECK-NEXT: ret i32 [[TMP3]] // // // CHECK-LABEL: define {{[^@]+}}@_ZN1SIdEC1Ev -// CHECK-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { +// CHECK-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { // CHECK-NEXT: entry: -// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK-NEXT: call void @_ZN1SIdEC2Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS1]]) +// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// CHECK-NEXT: call void @_ZN1SIdEC2Ev(ptr noundef nonnull align 8 dereferenceable(8) [[THIS1]]) // CHECK-NEXT: ret void // // // CHECK-LABEL: define {{[^@]+}}@_ZN1SIdEC1ERKS0_d -// CHECK-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[S:%.*]], double noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[S:%.*]], double noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK-NEXT: entry: -// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[T_ADDR:%.*]] = alloca double, align 8 -// CHECK-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 -// CHECK-NEXT: store double [[T]], double* [[T_ADDR]], align 8 -// CHECK-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 -// CHECK-NEXT: [[TMP1:%.*]] = load double, double* [[T_ADDR]], align 8 -// CHECK-NEXT: call void @_ZN1SIdEC2ERKS0_d(%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS1]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[TMP0]], double noundef [[TMP1]]) +// CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// CHECK-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 +// CHECK-NEXT: store double [[T]], ptr [[T_ADDR]], align 8 +// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 +// CHECK-NEXT: [[TMP1:%.*]] = load double, ptr [[T_ADDR]], align 8 +// CHECK-NEXT: call void @_ZN1SIdEC2ERKS0_d(ptr noundef nonnull align 8 dereferenceable(8) [[THIS1]], ptr noundef nonnull align 8 dereferenceable(8) [[TMP0]], double noundef [[TMP1]]) // CHECK-NEXT: ret void // // // CHECK-LABEL: define {{[^@]+}}@_ZN1SIdEC1Ed -// CHECK-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], double noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], double noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK-NEXT: entry: -// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[A_ADDR:%.*]] = alloca double, align 8 -// CHECK-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK-NEXT: store double [[A]], double* [[A_ADDR]], align 8 -// CHECK-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK-NEXT: [[TMP0:%.*]] = load double, double* [[A_ADDR]], align 8 -// CHECK-NEXT: call void @_ZN1SIdEC2Ed(%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS1]], double noundef [[TMP0]]) +// CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// CHECK-NEXT: store double [[A]], ptr [[A_ADDR]], align 8 +// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load double, ptr [[A_ADDR]], align 8 +// CHECK-NEXT: call void @_ZN1SIdEC2Ed(ptr noundef nonnull align 8 dereferenceable(8) [[THIS1]], double noundef [[TMP0]]) // CHECK-NEXT: ret void // // // CHECK-LABEL: define {{[^@]+}}@main.omp_outlined -// CHECK-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 8 dereferenceable(16) [[S_ARR:%.*]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[VAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[S_ARR:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[VAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK-NEXT: entry: -// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 -// CHECK-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 8 // CHECK-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 -// CHECK-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 -// CHECK-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* -// CHECK-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 -// CHECK-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) +// CHECK-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 +// CHECK-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 +// CHECK-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 +// CHECK-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 +// CHECK-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 +// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 +// CHECK-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB1]], i32 [[TMP4]]) // CHECK-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0 // CHECK-NEXT: br i1 [[TMP6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] // CHECK: omp_if.then: -// CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 -// CHECK-NEXT: store [2 x %struct.S]* [[TMP1]], [2 x %struct.S]** [[TMP7]], align 8 -// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 -// CHECK-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP8]], align 8 -// CHECK-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) -// CHECK-NEXT: [[TMP9:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]], i32 9, i64 120, i64 16, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*)) -// CHECK-NEXT: [[TMP10:%.*]] = bitcast i8* [[TMP9]] to %struct.kmp_task_t_with_privates* -// CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP10]], i32 0, i32 0 -// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP11]], i32 0, i32 0 -// CHECK-NEXT: [[TMP13:%.*]] = load i8*, i8** [[TMP12]], align 8 -// CHECK-NEXT: [[TMP14:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* -// CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP13]], i8* align 8 [[TMP14]], i64 16, i1 false) -// CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP10]], i32 0, i32 1 -// CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP15]], i32 0, i32 0 -// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP16]], i32 0, i32 0 -// CHECK-NEXT: [[TMP17:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* -// CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP18]] +// CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0 +// CHECK-NEXT: store ptr [[TMP1]], ptr [[TMP7]], align 8 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 1 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[TMP8]], align 8 +// CHECK-NEXT: call void @__kmpc_taskgroup(ptr @[[GLOB1]], i32 [[TMP4]]) +// CHECK-NEXT: [[TMP9:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP4]], i32 9, i64 120, i64 16, ptr @.omp_task_entry.) +// CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP9]], i32 0, i32 0 +// CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP10]], i32 0, i32 0 +// CHECK-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8 +// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP12]], ptr align 8 [[AGG_CAPTURED]], i64 16, i1 false) +// CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP9]], i32 0, i32 1 +// CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP13]], i32 0, i32 0 +// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP14]], i32 0, i32 0 +// CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP15]] // CHECK-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] // CHECK: omp.arraycpy.body: -// CHECK-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP17]], [[OMP_IF_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[OMP_IF_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK-NEXT: call void @_ZN1SIdEC1ERKS0_d(%struct.S* noundef nonnull align 8 dereferenceable(8) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[OMP_ARRAYCPY_SRCELEMENTPAST]], double noundef 0.000000e+00) -// CHECK-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP18]] +// CHECK-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[OMP_IF_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[OMP_IF_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK-NEXT: call void @_ZN1SIdEC1ERKS0_d(ptr noundef nonnull align 8 dereferenceable(8) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 8 dereferenceable(8) [[OMP_ARRAYCPY_SRCELEMENTPAST]], double noundef 0.000000e+00) +// CHECK-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP15]] // CHECK-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]] // CHECK: omp.arraycpy.done1: -// CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP15]], i32 0, i32 1 -// CHECK-NEXT: call void @_ZN1SIdEC1ERKS0_d(%struct.S* noundef nonnull align 8 dereferenceable(8) [[TMP19]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[TMP2]], double noundef 0.000000e+00) -// CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP15]], i32 0, i32 2 -// CHECK-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 4 -// CHECK-NEXT: store i32 [[TMP21]], i32* [[TMP20]], align 8 -// CHECK-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP15]], i32 0, i32 3 -// CHECK-NEXT: [[TMP23:%.*]] = bitcast [2 x i32]* [[TMP22]] to i8* -// CHECK-NEXT: [[TMP24:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP23]], i8* align 4 [[TMP24]], i64 8, i1 false) -// CHECK-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP15]], i32 0, i32 4 -// CHECK-NEXT: [[TMP26:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK-NEXT: store i32 [[TMP26]], i32* [[TMP25]], align 4 -// CHECK-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP11]], i32 0, i32 3 -// CHECK-NEXT: [[TMP28:%.*]] = bitcast %union.kmp_cmplrdata_t* [[TMP27]] to i32 (i32, i8*)** -// CHECK-NEXT: store i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_destructor. to i32 (i32, i8*)*), i32 (i32, i8*)** [[TMP28]], align 8 -// CHECK-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP11]], i32 0, i32 5 -// CHECK-NEXT: store i64 0, i64* [[TMP29]], align 8 -// CHECK-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP11]], i32 0, i32 6 -// CHECK-NEXT: store i64 9, i64* [[TMP30]], align 8 -// CHECK-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP11]], i32 0, i32 7 -// CHECK-NEXT: store i64 1, i64* [[TMP31]], align 8 -// CHECK-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP11]], i32 0, i32 9 -// CHECK-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i8* -// CHECK-NEXT: call void @llvm.memset.p0i8.i64(i8* align 8 [[TMP33]], i8 0, i64 8, i1 false) -// CHECK-NEXT: [[TMP34:%.*]] = load i64, i64* [[TMP31]], align 8 -// CHECK-NEXT: call void @__kmpc_taskloop(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]], i8* [[TMP9]], i32 1, i64* [[TMP29]], i64* [[TMP30]], i64 [[TMP34]], i32 1, i32 0, i64 0, i8* bitcast (void (%struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates*, i32)* @.omp_task_dup. to i8*)) -// CHECK-NEXT: call void @__kmpc_end_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) -// CHECK-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) +// CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP13]], i32 0, i32 1 +// CHECK-NEXT: call void @_ZN1SIdEC1ERKS0_d(ptr noundef nonnull align 8 dereferenceable(8) [[TMP16]], ptr noundef nonnull align 8 dereferenceable(8) [[TMP2]], double noundef 0.000000e+00) +// CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP13]], i32 0, i32 2 +// CHECK-NEXT: [[TMP18:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 +// CHECK-NEXT: store i32 [[TMP18]], ptr [[TMP17]], align 8 +// CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP13]], i32 0, i32 3 +// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP19]], ptr align 4 [[TMP0]], i64 8, i1 false) +// CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP13]], i32 0, i32 4 +// CHECK-NEXT: [[TMP21:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4 +// CHECK-NEXT: store i32 [[TMP21]], ptr [[TMP20]], align 4 +// CHECK-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP10]], i32 0, i32 3 +// CHECK-NEXT: store ptr @.omp_task_destructor., ptr [[TMP22]], align 8 +// CHECK-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP10]], i32 0, i32 5 +// CHECK-NEXT: store i64 0, ptr [[TMP23]], align 8 +// CHECK-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP10]], i32 0, i32 6 +// CHECK-NEXT: store i64 9, ptr [[TMP24]], align 8 +// CHECK-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP10]], i32 0, i32 7 +// CHECK-NEXT: store i64 1, ptr [[TMP25]], align 8 +// CHECK-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP10]], i32 0, i32 9 +// CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP26]], i8 0, i64 8, i1 false) +// CHECK-NEXT: [[TMP27:%.*]] = load i64, ptr [[TMP25]], align 8 +// CHECK-NEXT: call void @__kmpc_taskloop(ptr @[[GLOB1]], i32 [[TMP4]], ptr [[TMP9]], i32 1, ptr [[TMP23]], ptr [[TMP24]], i64 [[TMP27]], i32 1, i32 0, i64 0, ptr @.omp_task_dup.) +// CHECK-NEXT: call void @__kmpc_end_taskgroup(ptr @[[GLOB1]], i32 [[TMP4]]) +// CHECK-NEXT: call void @__kmpc_end_master(ptr @[[GLOB1]], i32 [[TMP4]]) // CHECK-NEXT: br label [[OMP_IF_END]] // CHECK: omp_if.end: // CHECK-NEXT: ret void // // // CHECK-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], %struct.S** noalias noundef [[TMP1:%.*]], i32** noalias noundef [[TMP2:%.*]], [2 x %struct.S]** noalias noundef [[TMP3:%.*]], [2 x i32]** noalias noundef [[TMP4:%.*]], i32** noalias noundef [[TMP5:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]], ptr noalias noundef [[TMP3:%.*]], ptr noalias noundef [[TMP4:%.*]], ptr noalias noundef [[TMP5:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK-NEXT: entry: -// CHECK-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 -// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca %struct.S**, align 8 -// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca i32**, align 8 -// CHECK-NEXT: [[DOTADDR3:%.*]] = alloca [2 x %struct.S]**, align 8 -// CHECK-NEXT: [[DOTADDR4:%.*]] = alloca [2 x i32]**, align 8 -// CHECK-NEXT: [[DOTADDR5:%.*]] = alloca i32**, align 8 -// CHECK-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8 -// CHECK-NEXT: store %struct.S** [[TMP1]], %struct.S*** [[DOTADDR1]], align 8 -// CHECK-NEXT: store i32** [[TMP2]], i32*** [[DOTADDR2]], align 8 -// CHECK-NEXT: store [2 x %struct.S]** [[TMP3]], [2 x %struct.S]*** [[DOTADDR3]], align 8 -// CHECK-NEXT: store [2 x i32]** [[TMP4]], [2 x i32]*** [[DOTADDR4]], align 8 -// CHECK-NEXT: store i32** [[TMP5]], i32*** [[DOTADDR5]], align 8 -// CHECK-NEXT: [[TMP6:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8 -// CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP6]], i32 0, i32 0 -// CHECK-NEXT: [[TMP8:%.*]] = load [2 x %struct.S]**, [2 x %struct.S]*** [[DOTADDR3]], align 8 -// CHECK-NEXT: store [2 x %struct.S]* [[TMP7]], [2 x %struct.S]** [[TMP8]], align 8 -// CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP6]], i32 0, i32 1 -// CHECK-NEXT: [[TMP10:%.*]] = load %struct.S**, %struct.S*** [[DOTADDR1]], align 8 -// CHECK-NEXT: store %struct.S* [[TMP9]], %struct.S** [[TMP10]], align 8 -// CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP6]], i32 0, i32 2 -// CHECK-NEXT: [[TMP12:%.*]] = load i32**, i32*** [[DOTADDR2]], align 8 -// CHECK-NEXT: store i32* [[TMP11]], i32** [[TMP12]], align 8 -// CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP6]], i32 0, i32 3 -// CHECK-NEXT: [[TMP14:%.*]] = load [2 x i32]**, [2 x i32]*** [[DOTADDR4]], align 8 -// CHECK-NEXT: store [2 x i32]* [[TMP13]], [2 x i32]** [[TMP14]], align 8 -// CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP6]], i32 0, i32 4 -// CHECK-NEXT: [[TMP16:%.*]] = load i32**, i32*** [[DOTADDR5]], align 8 -// CHECK-NEXT: store i32* [[TMP15]], i32** [[TMP16]], align 8 +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTADDR5:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 +// CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2]], align 8 +// CHECK-NEXT: store ptr [[TMP3]], ptr [[DOTADDR3]], align 8 +// CHECK-NEXT: store ptr [[TMP4]], ptr [[DOTADDR4]], align 8 +// CHECK-NEXT: store ptr [[TMP5]], ptr [[DOTADDR5]], align 8 +// CHECK-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTADDR]], align 8 +// CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP6]], i32 0, i32 0 +// CHECK-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTADDR3]], align 8 +// CHECK-NEXT: store ptr [[TMP7]], ptr [[TMP8]], align 8 +// CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP6]], i32 0, i32 1 +// CHECK-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 +// CHECK-NEXT: store ptr [[TMP9]], ptr [[TMP10]], align 8 +// CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP6]], i32 0, i32 2 +// CHECK-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTADDR2]], align 8 +// CHECK-NEXT: store ptr [[TMP11]], ptr [[TMP12]], align 8 +// CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP6]], i32 0, i32 3 +// CHECK-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTADDR4]], align 8 +// CHECK-NEXT: store ptr [[TMP13]], ptr [[TMP14]], align 8 +// CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP6]], i32 0, i32 4 +// CHECK-NEXT: [[TMP16:%.*]] = load ptr, ptr [[DOTADDR5]], align 8 +// CHECK-NEXT: store ptr [[TMP15]], ptr [[TMP16]], align 8 // CHECK-NEXT: ret void // // // CHECK-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { +// CHECK-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 -// CHECK-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 -// CHECK-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[DOTLB__ADDR_I:%.*]] = alloca i64, align 8 // CHECK-NEXT: [[DOTUB__ADDR_I:%.*]] = alloca i64, align 8 // CHECK-NEXT: [[DOTST__ADDR_I:%.*]] = alloca i64, align 8 // CHECK-NEXT: [[DOTLITER__ADDR_I:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 -// CHECK-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca %struct.S*, align 8 -// CHECK-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca i32*, align 8 -// CHECK-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [2 x %struct.S]*, align 8 -// CHECK-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [2 x i32]*, align 8 -// CHECK-NEXT: [[DOTFIRSTPRIV_PTR_ADDR4_I:%.*]] = alloca i32*, align 8 +// CHECK-NEXT: [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTFIRSTPRIV_PTR_ADDR4_I:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[I_I:%.*]] = alloca i32, align 4 // CHECK-NEXT: [[DOTOMP_IV_I:%.*]] = alloca i32, align 4 // CHECK-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 -// CHECK-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 -// CHECK-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 -// CHECK-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 -// CHECK-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 -// CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 -// CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 -// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 -// CHECK-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 -// CHECK-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* -// CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 -// CHECK-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* -// CHECK-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* -// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 5 -// CHECK-NEXT: [[TMP13:%.*]] = load i64, i64* [[TMP12]], align 8 -// CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 6 -// CHECK-NEXT: [[TMP15:%.*]] = load i64, i64* [[TMP14]], align 8 -// CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 7 -// CHECK-NEXT: [[TMP17:%.*]] = load i64, i64* [[TMP16]], align 8 -// CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 8 -// CHECK-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 8 -// CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 9 -// CHECK-NEXT: [[TMP21:%.*]] = load i8*, i8** [[TMP20]], align 8 +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 +// CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 1 +// CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 5 +// CHECK-NEXT: [[TMP10:%.*]] = load i64, ptr [[TMP9]], align 8 +// CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 6 +// CHECK-NEXT: [[TMP12:%.*]] = load i64, ptr [[TMP11]], align 8 +// CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 7 +// CHECK-NEXT: [[TMP14:%.*]] = load i64, ptr [[TMP13]], align 8 +// CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 8 +// CHECK-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 8 +// CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 9 +// CHECK-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8 // CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]]) // CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]]) // CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]]) // CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]]) // CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]]) -// CHECK-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14 -// CHECK-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !14 -// CHECK-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14 -// CHECK-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, %struct.S**, i32**, [2 x %struct.S]**, [2 x i32]**, i32**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14 -// CHECK-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !14 -// CHECK-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !14 -// CHECK-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !14 -// CHECK-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !14 -// CHECK-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !14 -// CHECK-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !14 -// CHECK-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14 -// CHECK-NEXT: [[TMP22:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14 -// CHECK-NEXT: [[TMP23:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14 -// CHECK-NEXT: [[TMP24:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14 -// CHECK-NEXT: [[TMP25:%.*]] = bitcast void (i8*, ...)* [[TMP23]] to void (i8*, %struct.S**, i32**, [2 x %struct.S]**, [2 x i32]**, i32**)* -// CHECK-NEXT: call void [[TMP25]](i8* [[TMP24]], %struct.S** [[DOTFIRSTPRIV_PTR_ADDR_I]], i32** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [2 x %struct.S]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [2 x i32]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], i32** [[DOTFIRSTPRIV_PTR_ADDR4_I]]) #[[ATTR4]] -// CHECK-NEXT: [[TMP26:%.*]] = load %struct.S*, %struct.S** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !14 -// CHECK-NEXT: [[TMP27:%.*]] = load i32*, i32** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !14 -// CHECK-NEXT: [[TMP28:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !14 -// CHECK-NEXT: [[TMP29:%.*]] = load [2 x i32]*, [2 x i32]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !14 -// CHECK-NEXT: [[TMP30:%.*]] = load i32*, i32** [[DOTFIRSTPRIV_PTR_ADDR4_I]], align 8, !noalias !14 -// CHECK-NEXT: [[TMP31:%.*]] = load i64, i64* [[DOTLB__ADDR_I]], align 8, !noalias !14 -// CHECK-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP31]] to i32 -// CHECK-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14 +// CHECK-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14 +// CHECK-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias !14 +// CHECK-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14 +// CHECK-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14 +// CHECK-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias !14 +// CHECK-NEXT: store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias !14 +// CHECK-NEXT: store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias !14 +// CHECK-NEXT: store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias !14 +// CHECK-NEXT: store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias !14 +// CHECK-NEXT: store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !14 +// CHECK-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias !14 +// CHECK-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias !14 +// CHECK-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14 +// CHECK-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14 +// CHECK-NEXT: call void [[TMP20]](ptr [[TMP21]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR4_I]]) #[[ATTR4]] +// CHECK-NEXT: [[TMP22:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !14 +// CHECK-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !14 +// CHECK-NEXT: [[TMP24:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !14 +// CHECK-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !14 +// CHECK-NEXT: [[TMP26:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR4_I]], align 8, !noalias !14 +// CHECK-NEXT: [[TMP27:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias !14 +// CHECK-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP27]] to i32 +// CHECK-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias !14 // CHECK-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]] // CHECK: omp.inner.for.cond.i: -// CHECK-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IV_I]], align 4, !noalias !14 -// CHECK-NEXT: [[CONV5_I:%.*]] = sext i32 [[TMP32]] to i64 -// CHECK-NEXT: [[TMP33:%.*]] = load i64, i64* [[DOTUB__ADDR_I]], align 8, !noalias !14 -// CHECK-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV5_I]], [[TMP33]] +// CHECK-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias !14 +// CHECK-NEXT: [[CONV5_I:%.*]] = sext i32 [[TMP28]] to i64 +// CHECK-NEXT: [[TMP29:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias !14 +// CHECK-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV5_I]], [[TMP29]] // CHECK-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]] // CHECK: omp.inner.for.body.i: -// CHECK-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_IV_I]], align 4, !noalias !14 -// CHECK-NEXT: store i32 [[TMP34]], i32* [[I_I]], align 4, !noalias !14 -// CHECK-NEXT: [[TMP35:%.*]] = load i32, i32* [[TMP27]], align 4 -// CHECK-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[TMP29]], i64 0, i64 0 -// CHECK-NEXT: store i32 [[TMP35]], i32* [[ARRAYIDX_I]], align 4 -// CHECK-NEXT: [[ARRAYIDX6_I:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP28]], i64 0, i64 0 -// CHECK-NEXT: [[TMP36:%.*]] = bitcast %struct.S* [[ARRAYIDX6_I]] to i8* -// CHECK-NEXT: [[TMP37:%.*]] = bitcast %struct.S* [[TMP26]] to i8* -// CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP36]], i8* align 8 [[TMP37]], i64 8, i1 false) -// CHECK-NEXT: store i32 33, i32* [[TMP30]], align 4 -// CHECK-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTOMP_IV_I]], align 4, !noalias !14 -// CHECK-NEXT: [[ADD7_I:%.*]] = add nsw i32 [[TMP38]], 1 -// CHECK-NEXT: store i32 [[ADD7_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14 +// CHECK-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias !14 +// CHECK-NEXT: store i32 [[TMP30]], ptr [[I_I]], align 4, !noalias !14 +// CHECK-NEXT: [[TMP31:%.*]] = load i32, ptr [[TMP23]], align 4 +// CHECK-NEXT: store i32 [[TMP31]], ptr [[TMP25]], align 4 +// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 16 [[TMP24]], ptr align 8 [[TMP22]], i64 8, i1 false) +// CHECK-NEXT: store i32 33, ptr [[TMP26]], align 4 +// CHECK-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias !14 +// CHECK-NEXT: [[ADD7_I:%.*]] = add nsw i32 [[TMP32]], 1 +// CHECK-NEXT: store i32 [[ADD7_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias !14 // CHECK-NEXT: br label [[OMP_INNER_FOR_COND_I]] // CHECK: .omp_outlined..exit: // CHECK-NEXT: ret i32 0 // // // CHECK-LABEL: define {{[^@]+}}@.omp_task_dup. -// CHECK-SAME: (%struct.kmp_task_t_with_privates* noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noundef [[TMP1:%.*]], i32 noundef [[TMP2:%.*]]) #[[ATTR7]] { +// CHECK-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], i32 noundef [[TMP2:%.*]]) #[[ATTR7]] { // CHECK-NEXT: entry: -// CHECK-NEXT: [[DOTADDR:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 -// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[DOTADDR2:%.*]] = alloca i32, align 4 -// CHECK-NEXT: store %struct.kmp_task_t_with_privates* [[TMP0]], %struct.kmp_task_t_with_privates** [[DOTADDR]], align 8 -// CHECK-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 -// CHECK-NEXT: store i32 [[TMP2]], i32* [[DOTADDR2]], align 4 -// CHECK-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR]], align 8 -// CHECK-NEXT: [[TMP4:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 -// CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP4]], i32 0, i32 0 -// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP5]], i32 0, i32 0 -// CHECK-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 -// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 -// CHECK-NEXT: [[TMP9:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* -// CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP8]], i32 0, i32 0 -// CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP9]], i32 0, i32 0 -// CHECK-NEXT: [[TMP12:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[TMP11]], align 8 -// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP10]], i32 0, i32 0 -// CHECK-NEXT: [[TMP13:%.*]] = bitcast [2 x %struct.S]* [[TMP12]] to %struct.S* -// CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP14]] +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 +// CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK-NEXT: store i32 [[TMP2]], ptr [[DOTADDR2]], align 4 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 +// CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP4]], i32 0, i32 0 +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP5]], i32 0, i32 0 +// CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 1 +// CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP8]], i32 0, i32 0 +// CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP7]], i32 0, i32 0 +// CHECK-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP10]], align 8 +// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP9]], i32 0, i32 0 +// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP12]] // CHECK-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] // CHECK: omp.arraycpy.body: -// CHECK-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK-NEXT: call void @_ZN1SIdEC1ERKS0_d(%struct.S* noundef nonnull align 8 dereferenceable(8) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[OMP_ARRAYCPY_SRCELEMENTPAST]], double noundef 0.000000e+00) -// CHECK-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP14]] +// CHECK-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP11]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK-NEXT: call void @_ZN1SIdEC1ERKS0_d(ptr noundef nonnull align 8 dereferenceable(8) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 8 dereferenceable(8) [[OMP_ARRAYCPY_SRCELEMENTPAST]], double noundef 0.000000e+00) +// CHECK-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP12]] // CHECK-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] // CHECK: omp.arraycpy.done3: -// CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP8]], i32 0, i32 1 -// CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP9]], i32 0, i32 1 -// CHECK-NEXT: [[TMP17:%.*]] = load %struct.S*, %struct.S** [[TMP16]], align 8 -// CHECK-NEXT: call void @_ZN1SIdEC1ERKS0_d(%struct.S* noundef nonnull align 8 dereferenceable(8) [[TMP15]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[TMP17]], double noundef 0.000000e+00) +// CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP8]], i32 0, i32 1 +// CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP7]], i32 0, i32 1 +// CHECK-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP14]], align 8 +// CHECK-NEXT: call void @_ZN1SIdEC1ERKS0_d(ptr noundef nonnull align 8 dereferenceable(8) [[TMP13]], ptr noundef nonnull align 8 dereferenceable(8) [[TMP15]], double noundef 0.000000e+00) // CHECK-NEXT: ret void // // // CHECK-LABEL: define {{[^@]+}}@.omp_task_destructor. -// CHECK-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR7]] { +// CHECK-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR7]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 -// CHECK-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 -// CHECK-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 -// CHECK-NEXT: [[TMP2:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 -// CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP2]], i32 0, i32 1 -// CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP3]], i32 0, i32 0 -// CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP3]], i32 0, i32 1 -// CHECK-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[TMP5]]) #[[ATTR4]] -// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP4]], i32 0, i32 0 -// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP2]], i32 0, i32 1 +// CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP3]], i32 0, i32 1 +// CHECK-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[TMP5]]) #[[ATTR4]] +// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP4]], i32 0, i32 0 +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK: arraydestroy.body: -// CHECK-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP6]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP6]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK: arraydestroy.done2: -// CHECK-NEXT: [[TMP7:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK-NEXT: ret i32 [[TMP7]] // // // CHECK-LABEL: define {{[^@]+}}@_ZN1SIdED1Ev -// CHECK-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK-NEXT: entry: -// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK-NEXT: call void @_ZN1SIdED2Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS1]]) #[[ATTR4]] +// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// CHECK-NEXT: call void @_ZN1SIdED2Ev(ptr noundef nonnull align 8 dereferenceable(8) [[THIS1]]) #[[ATTR4]] // CHECK-NEXT: ret void // // @@ -585,471 +565,451 @@ void array_func(int n, float a[n], St s[2]) { // CHECK-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TTT]]) -// CHECK-NEXT: call void @_ZN1SIiEC1ERKS0_i(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TTT]], i32 noundef 0) -// CHECK-NEXT: store i32 0, i32* [[T_VAR]], align 128 -// CHECK-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef 1) -// CHECK-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) -// CHECK-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]], i32 noundef 3) -// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 128 -// CHECK-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4 -// CHECK-NEXT: [[TMP2:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 -// CHECK-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @_Z5tmainIiET_v.omp_outlined to void (i32*, i32*, ...)*), [2 x i32]* [[VEC]], i64 [[TMP2]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[VAR]]) -// CHECK-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TTT]]) +// CHECK-NEXT: call void @_ZN1SIiEC1ERKS0_i(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]], ptr noundef nonnull align 4 dereferenceable(4) [[TTT]], i32 noundef 0) +// CHECK-NEXT: store i32 0, ptr [[T_VAR]], align 128 +// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false) +// CHECK-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 0 +// CHECK-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYINIT_BEGIN]], i64 1 +// CHECK-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]], i32 noundef 3) +// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[T_VAR]], align 128 +// CHECK-NEXT: store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 +// CHECK-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 4, ptr @_Z5tmainIiET_v.omp_outlined, ptr [[VEC]], i64 [[TMP1]], ptr [[S_ARR]], ptr [[VAR]]) +// CHECK-NEXT: store i32 0, ptr [[RETVAL]], align 4 +// CHECK-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK: arraydestroy.body: -// CHECK-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK: arraydestroy.done1: -// CHECK-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TTT]]) #[[ATTR4]] -// CHECK-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK-NEXT: ret i32 [[TMP4]] +// CHECK-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TTT]]) #[[ATTR4]] +// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[RETVAL]], align 4 +// CHECK-NEXT: ret i32 [[TMP3]] // // // CHECK-LABEL: define {{[^@]+}}@_ZN1SIdEC2Ev -// CHECK-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK-NEXT: entry: -// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK-NEXT: store double 0.000000e+00, double* [[F]], align 8 +// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// CHECK-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 +// CHECK-NEXT: store double 0.000000e+00, ptr [[F]], align 8 // CHECK-NEXT: ret void // // // CHECK-LABEL: define {{[^@]+}}@_ZN1SIdEC2ERKS0_d -// CHECK-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[S:%.*]], double noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[S:%.*]], double noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK-NEXT: entry: -// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[T_ADDR:%.*]] = alloca double, align 8 -// CHECK-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 -// CHECK-NEXT: store double [[T]], double* [[T_ADDR]], align 8 -// CHECK-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 -// CHECK-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0 -// CHECK-NEXT: [[TMP1:%.*]] = load double, double* [[F2]], align 8 -// CHECK-NEXT: [[TMP2:%.*]] = load double, double* [[T_ADDR]], align 8 +// CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// CHECK-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 +// CHECK-NEXT: store double [[T]], ptr [[T_ADDR]], align 8 +// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// CHECK-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 +// CHECK-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0 +// CHECK-NEXT: [[TMP1:%.*]] = load double, ptr [[F2]], align 8 +// CHECK-NEXT: [[TMP2:%.*]] = load double, ptr [[T_ADDR]], align 8 // CHECK-NEXT: [[ADD:%.*]] = fadd double [[TMP1]], [[TMP2]] -// CHECK-NEXT: store double [[ADD]], double* [[F]], align 8 +// CHECK-NEXT: store double [[ADD]], ptr [[F]], align 8 // CHECK-NEXT: ret void // // // CHECK-LABEL: define {{[^@]+}}@_ZN1SIdEC2Ed -// CHECK-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], double noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], double noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK-NEXT: entry: -// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[A_ADDR:%.*]] = alloca double, align 8 -// CHECK-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK-NEXT: store double [[A]], double* [[A_ADDR]], align 8 -// CHECK-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK-NEXT: [[TMP0:%.*]] = load double, double* [[A_ADDR]], align 8 -// CHECK-NEXT: store double [[TMP0]], double* [[F]], align 8 +// CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// CHECK-NEXT: store double [[A]], ptr [[A_ADDR]], align 8 +// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// CHECK-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 +// CHECK-NEXT: [[TMP0:%.*]] = load double, ptr [[A_ADDR]], align 8 +// CHECK-NEXT: store double [[TMP0]], ptr [[F]], align 8 // CHECK-NEXT: ret void // // // CHECK-LABEL: define {{[^@]+}}@_ZN1SIdED2Ev -// CHECK-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK-NEXT: entry: -// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: ret void // // // CHECK-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK-NEXT: entry: -// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) +// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// CHECK-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK-NEXT: ret void // // // CHECK-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_i -// CHECK-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], i32 noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], i32 noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK-NEXT: entry: -// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[T_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 -// CHECK-NEXT: store i32 [[T]], i32* [[T_ADDR]], align 4 -// CHECK-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 -// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_ADDR]], align 4 -// CHECK-NEXT: call void @_ZN1SIiEC2ERKS0_i(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], i32 noundef [[TMP1]]) +// CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// CHECK-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 +// CHECK-NEXT: store i32 [[T]], ptr [[T_ADDR]], align 4 +// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 +// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_ADDR]], align 4 +// CHECK-NEXT: call void @_ZN1SIiEC2ERKS0_i(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], i32 noundef [[TMP1]]) // CHECK-NEXT: ret void // // // CHECK-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK-NEXT: entry: -// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]) +// CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// CHECK-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 +// CHECK-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]) // CHECK-NEXT: ret void // // // CHECK-LABEL: define {{[^@]+}}@_Z5tmainIiET_v.omp_outlined -// CHECK-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK-NEXT: entry: -// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 -// CHECK-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON_1:%.*]], align 8 // CHECK-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 -// CHECK-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* -// CHECK-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) +// CHECK-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 +// CHECK-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 +// CHECK-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 +// CHECK-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 +// CHECK-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 +// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 +// CHECK-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB1]], i32 [[TMP4]]) // CHECK-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0 // CHECK-NEXT: br i1 [[TMP6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] // CHECK: omp_if.then: -// CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1* [[AGG_CAPTURED]], i32 0, i32 0 -// CHECK-NEXT: store [2 x %struct.S.0]* [[TMP1]], [2 x %struct.S.0]** [[TMP7]], align 8 -// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1* [[AGG_CAPTURED]], i32 0, i32 1 -// CHECK-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP8]], align 8 -// CHECK-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) -// CHECK-NEXT: [[TMP9:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]], i32 9, i64 256, i64 16, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.2*)* @.omp_task_entry..3 to i32 (i32, i8*)*)) -// CHECK-NEXT: [[TMP10:%.*]] = bitcast i8* [[TMP9]] to %struct.kmp_task_t_with_privates.2* -// CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2:%.*]], %struct.kmp_task_t_with_privates.2* [[TMP10]], i32 0, i32 0 -// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP11]], i32 0, i32 0 -// CHECK-NEXT: [[TMP13:%.*]] = load i8*, i8** [[TMP12]], align 128 -// CHECK-NEXT: [[TMP14:%.*]] = bitcast %struct.anon.1* [[AGG_CAPTURED]] to i8* -// CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP13]], i8* align 8 [[TMP14]], i64 16, i1 false) -// CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2]], %struct.kmp_task_t_with_privates.2* [[TMP10]], i32 0, i32 2 -// CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3:%.*]], %struct..kmp_privates.t.3* [[TMP15]], i32 0, i32 0 -// CHECK-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 4 -// CHECK-NEXT: store i32 [[TMP17]], i32* [[TMP16]], align 128 -// CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3]], %struct..kmp_privates.t.3* [[TMP15]], i32 0, i32 1 -// CHECK-NEXT: [[TMP19:%.*]] = bitcast [2 x i32]* [[TMP18]] to i8* -// CHECK-NEXT: [[TMP20:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i64 8, i1 false) -// CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3]], %struct..kmp_privates.t.3* [[TMP15]], i32 0, i32 2 -// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP21]], i32 0, i32 0 -// CHECK-NEXT: [[TMP22:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0* -// CHECK-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP23]] +// CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[AGG_CAPTURED]], i32 0, i32 0 +// CHECK-NEXT: store ptr [[TMP1]], ptr [[TMP7]], align 8 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[AGG_CAPTURED]], i32 0, i32 1 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[TMP8]], align 8 +// CHECK-NEXT: call void @__kmpc_taskgroup(ptr @[[GLOB1]], i32 [[TMP4]]) +// CHECK-NEXT: [[TMP9:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP4]], i32 9, i64 256, i64 16, ptr @.omp_task_entry..3) +// CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2:%.*]], ptr [[TMP9]], i32 0, i32 0 +// CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP10]], i32 0, i32 0 +// CHECK-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 128 +// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP12]], ptr align 8 [[AGG_CAPTURED]], i64 16, i1 false) +// CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2]], ptr [[TMP9]], i32 0, i32 2 +// CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3:%.*]], ptr [[TMP13]], i32 0, i32 0 +// CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 +// CHECK-NEXT: store i32 [[TMP15]], ptr [[TMP14]], align 128 +// CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3]], ptr [[TMP13]], i32 0, i32 1 +// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP16]], ptr align 4 [[TMP0]], i64 8, i1 false) +// CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3]], ptr [[TMP13]], i32 0, i32 2 +// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP17]], i32 0, i32 0 +// CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP18]] // CHECK-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] // CHECK: omp.arraycpy.body: -// CHECK-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP22]], [[OMP_IF_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[OMP_IF_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK-NEXT: call void @_ZN1SIiEC1ERKS0_i(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 noundef 0) -// CHECK-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP23]] +// CHECK-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[OMP_IF_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[OMP_IF_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK-NEXT: call void @_ZN1SIiEC1ERKS0_i(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 noundef 0) +// CHECK-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP18]] // CHECK-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]] // CHECK: omp.arraycpy.done1: -// CHECK-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3]], %struct..kmp_privates.t.3* [[TMP15]], i32 0, i32 3 -// CHECK-NEXT: call void @_ZN1SIiEC1ERKS0_i(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP24]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP2]], i32 noundef 0) -// CHECK-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP11]], i32 0, i32 3 -// CHECK-NEXT: [[TMP26:%.*]] = bitcast %union.kmp_cmplrdata_t* [[TMP25]] to i32 (i32, i8*)** -// CHECK-NEXT: store i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.2*)* @.omp_task_destructor..5 to i32 (i32, i8*)*), i32 (i32, i8*)** [[TMP26]], align 8 -// CHECK-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP11]], i32 0, i32 5 -// CHECK-NEXT: store i64 0, i64* [[TMP27]], align 8 -// CHECK-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP11]], i32 0, i32 6 -// CHECK-NEXT: store i64 9, i64* [[TMP28]], align 16 -// CHECK-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP11]], i32 0, i32 7 -// CHECK-NEXT: store i64 1, i64* [[TMP29]], align 8 -// CHECK-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP11]], i32 0, i32 9 -// CHECK-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i8* -// CHECK-NEXT: call void @llvm.memset.p0i8.i64(i8* align 8 [[TMP31]], i8 0, i64 8, i1 false) -// CHECK-NEXT: [[TMP32:%.*]] = load i64, i64* [[TMP29]], align 8 -// CHECK-NEXT: call void @__kmpc_taskloop(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]], i8* [[TMP9]], i32 1, i64* [[TMP27]], i64* [[TMP28]], i64 [[TMP32]], i32 1, i32 0, i64 0, i8* bitcast (void (%struct.kmp_task_t_with_privates.2*, %struct.kmp_task_t_with_privates.2*, i32)* @.omp_task_dup..4 to i8*)) -// CHECK-NEXT: call void @__kmpc_end_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) -// CHECK-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) +// CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3]], ptr [[TMP13]], i32 0, i32 3 +// CHECK-NEXT: call void @_ZN1SIiEC1ERKS0_i(ptr noundef nonnull align 4 dereferenceable(4) [[TMP19]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], i32 noundef 0) +// CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP10]], i32 0, i32 3 +// CHECK-NEXT: store ptr @.omp_task_destructor..5, ptr [[TMP20]], align 8 +// CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP10]], i32 0, i32 5 +// CHECK-NEXT: store i64 0, ptr [[TMP21]], align 8 +// CHECK-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP10]], i32 0, i32 6 +// CHECK-NEXT: store i64 9, ptr [[TMP22]], align 16 +// CHECK-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP10]], i32 0, i32 7 +// CHECK-NEXT: store i64 1, ptr [[TMP23]], align 8 +// CHECK-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP10]], i32 0, i32 9 +// CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP24]], i8 0, i64 8, i1 false) +// CHECK-NEXT: [[TMP25:%.*]] = load i64, ptr [[TMP23]], align 8 +// CHECK-NEXT: call void @__kmpc_taskloop(ptr @[[GLOB1]], i32 [[TMP4]], ptr [[TMP9]], i32 1, ptr [[TMP21]], ptr [[TMP22]], i64 [[TMP25]], i32 1, i32 0, i64 0, ptr @.omp_task_dup..4) +// CHECK-NEXT: call void @__kmpc_end_taskgroup(ptr @[[GLOB1]], i32 [[TMP4]]) +// CHECK-NEXT: call void @__kmpc_end_master(ptr @[[GLOB1]], i32 [[TMP4]]) // CHECK-NEXT: br label [[OMP_IF_END]] // CHECK: omp_if.end: // CHECK-NEXT: ret void // // // CHECK-LABEL: define {{[^@]+}}@.omp_task_privates_map..2 -// CHECK-SAME: (%struct..kmp_privates.t.3* noalias noundef [[TMP0:%.*]], i32** noalias noundef [[TMP1:%.*]], [2 x i32]** noalias noundef [[TMP2:%.*]], [2 x %struct.S.0]** noalias noundef [[TMP3:%.*]], %struct.S.0** noalias noundef [[TMP4:%.*]]) #[[ATTR6]] { +// CHECK-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]], ptr noalias noundef [[TMP3:%.*]], ptr noalias noundef [[TMP4:%.*]]) #[[ATTR6]] { // CHECK-NEXT: entry: -// CHECK-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t.3*, align 8 -// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32**, align 8 -// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca [2 x i32]**, align 8 -// CHECK-NEXT: [[DOTADDR3:%.*]] = alloca [2 x %struct.S.0]**, align 8 -// CHECK-NEXT: [[DOTADDR4:%.*]] = alloca %struct.S.0**, align 8 -// CHECK-NEXT: store %struct..kmp_privates.t.3* [[TMP0]], %struct..kmp_privates.t.3** [[DOTADDR]], align 8 -// CHECK-NEXT: store i32** [[TMP1]], i32*** [[DOTADDR1]], align 8 -// CHECK-NEXT: store [2 x i32]** [[TMP2]], [2 x i32]*** [[DOTADDR2]], align 8 -// CHECK-NEXT: store [2 x %struct.S.0]** [[TMP3]], [2 x %struct.S.0]*** [[DOTADDR3]], align 8 -// CHECK-NEXT: store %struct.S.0** [[TMP4]], %struct.S.0*** [[DOTADDR4]], align 8 -// CHECK-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t.3*, %struct..kmp_privates.t.3** [[DOTADDR]], align 8 -// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3:%.*]], %struct..kmp_privates.t.3* [[TMP5]], i32 0, i32 0 -// CHECK-NEXT: [[TMP7:%.*]] = load i32**, i32*** [[DOTADDR1]], align 8 -// CHECK-NEXT: store i32* [[TMP6]], i32** [[TMP7]], align 8 -// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3]], %struct..kmp_privates.t.3* [[TMP5]], i32 0, i32 1 -// CHECK-NEXT: [[TMP9:%.*]] = load [2 x i32]**, [2 x i32]*** [[DOTADDR2]], align 8 -// CHECK-NEXT: store [2 x i32]* [[TMP8]], [2 x i32]** [[TMP9]], align 8 -// CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3]], %struct..kmp_privates.t.3* [[TMP5]], i32 0, i32 2 -// CHECK-NEXT: [[TMP11:%.*]] = load [2 x %struct.S.0]**, [2 x %struct.S.0]*** [[DOTADDR3]], align 8 -// CHECK-NEXT: store [2 x %struct.S.0]* [[TMP10]], [2 x %struct.S.0]** [[TMP11]], align 8 -// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3]], %struct..kmp_privates.t.3* [[TMP5]], i32 0, i32 3 -// CHECK-NEXT: [[TMP13:%.*]] = load %struct.S.0**, %struct.S.0*** [[DOTADDR4]], align 8 -// CHECK-NEXT: store %struct.S.0* [[TMP12]], %struct.S.0** [[TMP13]], align 8 +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 +// CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2]], align 8 +// CHECK-NEXT: store ptr [[TMP3]], ptr [[DOTADDR3]], align 8 +// CHECK-NEXT: store ptr [[TMP4]], ptr [[DOTADDR4]], align 8 +// CHECK-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR]], align 8 +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3:%.*]], ptr [[TMP5]], i32 0, i32 0 +// CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 +// CHECK-NEXT: store ptr [[TMP6]], ptr [[TMP7]], align 8 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3]], ptr [[TMP5]], i32 0, i32 1 +// CHECK-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTADDR2]], align 8 +// CHECK-NEXT: store ptr [[TMP8]], ptr [[TMP9]], align 8 +// CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3]], ptr [[TMP5]], i32 0, i32 2 +// CHECK-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTADDR3]], align 8 +// CHECK-NEXT: store ptr [[TMP10]], ptr [[TMP11]], align 8 +// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3]], ptr [[TMP5]], i32 0, i32 3 +// CHECK-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTADDR4]], align 8 +// CHECK-NEXT: store ptr [[TMP12]], ptr [[TMP13]], align 8 // CHECK-NEXT: ret void // // // CHECK-LABEL: define {{[^@]+}}@.omp_task_entry..3 -// CHECK-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.2* noalias noundef [[TMP1:%.*]]) #[[ATTR7]] { +// CHECK-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR7]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 -// CHECK-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 -// CHECK-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[DOTLB__ADDR_I:%.*]] = alloca i64, align 8 // CHECK-NEXT: [[DOTUB__ADDR_I:%.*]] = alloca i64, align 8 // CHECK-NEXT: [[DOTST__ADDR_I:%.*]] = alloca i64, align 8 // CHECK-NEXT: [[DOTLITER__ADDR_I:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon.1*, align 8 -// CHECK-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i32*, align 8 -// CHECK-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [2 x i32]*, align 8 -// CHECK-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [2 x %struct.S.0]*, align 8 -// CHECK-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca %struct.S.0*, align 8 +// CHECK-NEXT: [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[I_I:%.*]] = alloca i32, align 4 // CHECK-NEXT: [[DOTOMP_IV_I:%.*]] = alloca i32, align 4 // CHECK-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates.2*, align 8 -// CHECK-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 -// CHECK-NEXT: store %struct.kmp_task_t_with_privates.2* [[TMP1]], %struct.kmp_task_t_with_privates.2** [[DOTADDR1]], align 8 -// CHECK-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 -// CHECK-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates.2*, %struct.kmp_task_t_with_privates.2** [[DOTADDR1]], align 8 -// CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2:%.*]], %struct.kmp_task_t_with_privates.2* [[TMP3]], i32 0, i32 0 -// CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 -// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 -// CHECK-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 128 -// CHECK-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon.1* -// CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2]], %struct.kmp_task_t_with_privates.2* [[TMP3]], i32 0, i32 2 -// CHECK-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t.3* [[TMP9]] to i8* -// CHECK-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates.2* [[TMP3]] to i8* -// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 5 -// CHECK-NEXT: [[TMP13:%.*]] = load i64, i64* [[TMP12]], align 8 -// CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 6 -// CHECK-NEXT: [[TMP15:%.*]] = load i64, i64* [[TMP14]], align 16 -// CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 7 -// CHECK-NEXT: [[TMP17:%.*]] = load i64, i64* [[TMP16]], align 8 -// CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 8 -// CHECK-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 64 -// CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 9 -// CHECK-NEXT: [[TMP21:%.*]] = load i8*, i8** [[TMP20]], align 8 +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 +// CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 128 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2]], ptr [[TMP3]], i32 0, i32 2 +// CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 5 +// CHECK-NEXT: [[TMP10:%.*]] = load i64, ptr [[TMP9]], align 8 +// CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 6 +// CHECK-NEXT: [[TMP12:%.*]] = load i64, ptr [[TMP11]], align 16 +// CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 7 +// CHECK-NEXT: [[TMP14:%.*]] = load i64, ptr [[TMP13]], align 8 +// CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 8 +// CHECK-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 64 +// CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 9 +// CHECK-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8 // CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]]) // CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) // CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]]) // CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]]) // CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META26:![0-9]+]]) -// CHECK-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !28 -// CHECK-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !28 -// CHECK-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !28 -// CHECK-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t.3*, i32**, [2 x i32]**, [2 x %struct.S.0]**, %struct.S.0**)* @.omp_task_privates_map..2 to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !28 -// CHECK-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !28 -// CHECK-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !28 -// CHECK-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !28 -// CHECK-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !28 -// CHECK-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !28 -// CHECK-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !28 -// CHECK-NEXT: store %struct.anon.1* [[TMP8]], %struct.anon.1** [[__CONTEXT_ADDR_I]], align 8, !noalias !28 -// CHECK-NEXT: [[TMP22:%.*]] = load %struct.anon.1*, %struct.anon.1** [[__CONTEXT_ADDR_I]], align 8, !noalias !28 -// CHECK-NEXT: [[TMP23:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !28 -// CHECK-NEXT: [[TMP24:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !28 -// CHECK-NEXT: [[TMP25:%.*]] = bitcast void (i8*, ...)* [[TMP23]] to void (i8*, i32**, [2 x i32]**, [2 x %struct.S.0]**, %struct.S.0**)* -// CHECK-NEXT: call void [[TMP25]](i8* [[TMP24]], i32** [[DOTFIRSTPRIV_PTR_ADDR_I]], [2 x i32]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [2 x %struct.S.0]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], %struct.S.0** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]] -// CHECK-NEXT: [[TMP26:%.*]] = load i32*, i32** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !28 -// CHECK-NEXT: [[TMP27:%.*]] = load [2 x i32]*, [2 x i32]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !28 -// CHECK-NEXT: [[TMP28:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !28 -// CHECK-NEXT: [[TMP29:%.*]] = load %struct.S.0*, %struct.S.0** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !28 -// CHECK-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTLB__ADDR_I]], align 8, !noalias !28 -// CHECK-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP30]] to i32 -// CHECK-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !28 +// CHECK-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !28 +// CHECK-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias !28 +// CHECK-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias !28 +// CHECK-NEXT: store ptr @.omp_task_privates_map..2, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !28 +// CHECK-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias !28 +// CHECK-NEXT: store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias !28 +// CHECK-NEXT: store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias !28 +// CHECK-NEXT: store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias !28 +// CHECK-NEXT: store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias !28 +// CHECK-NEXT: store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !28 +// CHECK-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias !28 +// CHECK-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias !28 +// CHECK-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !28 +// CHECK-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias !28 +// CHECK-NEXT: call void [[TMP20]](ptr [[TMP21]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]] +// CHECK-NEXT: [[TMP22:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !28 +// CHECK-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !28 +// CHECK-NEXT: [[TMP24:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !28 +// CHECK-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !28 +// CHECK-NEXT: [[TMP26:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias !28 +// CHECK-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP26]] to i32 +// CHECK-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias !28 // CHECK-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]] // CHECK: omp.inner.for.cond.i: -// CHECK-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV_I]], align 4, !noalias !28 -// CHECK-NEXT: [[CONV4_I:%.*]] = sext i32 [[TMP31]] to i64 -// CHECK-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTUB__ADDR_I]], align 8, !noalias !28 -// CHECK-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV4_I]], [[TMP32]] +// CHECK-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias !28 +// CHECK-NEXT: [[CONV4_I:%.*]] = sext i32 [[TMP27]] to i64 +// CHECK-NEXT: [[TMP28:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias !28 +// CHECK-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV4_I]], [[TMP28]] // CHECK-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] // CHECK: omp.inner.for.body.i: -// CHECK-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_IV_I]], align 4, !noalias !28 -// CHECK-NEXT: store i32 [[TMP33]], i32* [[I_I]], align 4, !noalias !28 -// CHECK-NEXT: [[TMP34:%.*]] = load i32, i32* [[TMP26]], align 128 -// CHECK-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[TMP27]], i64 0, i64 0 -// CHECK-NEXT: store i32 [[TMP34]], i32* [[ARRAYIDX_I]], align 4 -// CHECK-NEXT: [[ARRAYIDX5_I:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP28]], i64 0, i64 0 -// CHECK-NEXT: [[TMP35:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5_I]] to i8* -// CHECK-NEXT: [[TMP36:%.*]] = bitcast %struct.S.0* [[TMP29]] to i8* -// CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP35]], i8* align 4 [[TMP36]], i64 4, i1 false) -// CHECK-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTOMP_IV_I]], align 4, !noalias !28 -// CHECK-NEXT: [[ADD6_I:%.*]] = add nsw i32 [[TMP37]], 1 -// CHECK-NEXT: store i32 [[ADD6_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !28 +// CHECK-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias !28 +// CHECK-NEXT: store i32 [[TMP29]], ptr [[I_I]], align 4, !noalias !28 +// CHECK-NEXT: [[TMP30:%.*]] = load i32, ptr [[TMP22]], align 128 +// CHECK-NEXT: store i32 [[TMP30]], ptr [[TMP23]], align 4 +// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP24]], ptr align 4 [[TMP25]], i64 4, i1 false) +// CHECK-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias !28 +// CHECK-NEXT: [[ADD6_I:%.*]] = add nsw i32 [[TMP31]], 1 +// CHECK-NEXT: store i32 [[ADD6_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias !28 // CHECK-NEXT: br label [[OMP_INNER_FOR_COND_I]] // CHECK: .omp_outlined..1.exit: // CHECK-NEXT: ret i32 0 // // // CHECK-LABEL: define {{[^@]+}}@.omp_task_dup..4 -// CHECK-SAME: (%struct.kmp_task_t_with_privates.2* noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.2* noundef [[TMP1:%.*]], i32 noundef [[TMP2:%.*]]) #[[ATTR7]] { +// CHECK-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], i32 noundef [[TMP2:%.*]]) #[[ATTR7]] { // CHECK-NEXT: entry: -// CHECK-NEXT: [[DOTADDR:%.*]] = alloca %struct.kmp_task_t_with_privates.2*, align 8 -// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates.2*, align 8 +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[DOTADDR2:%.*]] = alloca i32, align 4 -// CHECK-NEXT: store %struct.kmp_task_t_with_privates.2* [[TMP0]], %struct.kmp_task_t_with_privates.2** [[DOTADDR]], align 8 -// CHECK-NEXT: store %struct.kmp_task_t_with_privates.2* [[TMP1]], %struct.kmp_task_t_with_privates.2** [[DOTADDR1]], align 8 -// CHECK-NEXT: store i32 [[TMP2]], i32* [[DOTADDR2]], align 4 -// CHECK-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates.2*, %struct.kmp_task_t_with_privates.2** [[DOTADDR]], align 8 -// CHECK-NEXT: [[TMP4:%.*]] = load %struct.kmp_task_t_with_privates.2*, %struct.kmp_task_t_with_privates.2** [[DOTADDR1]], align 8 -// CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2:%.*]], %struct.kmp_task_t_with_privates.2* [[TMP4]], i32 0, i32 0 -// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP5]], i32 0, i32 0 -// CHECK-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 128 -// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2]], %struct.kmp_task_t_with_privates.2* [[TMP3]], i32 0, i32 2 -// CHECK-NEXT: [[TMP9:%.*]] = bitcast i8* [[TMP7]] to %struct.anon.1* -// CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3:%.*]], %struct..kmp_privates.t.3* [[TMP8]], i32 0, i32 2 -// CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_ANON_1:%.*]], %struct.anon.1* [[TMP9]], i32 0, i32 0 -// CHECK-NEXT: [[TMP12:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[TMP11]], align 8 -// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP10]], i32 0, i32 0 -// CHECK-NEXT: [[TMP13:%.*]] = bitcast [2 x %struct.S.0]* [[TMP12]] to %struct.S.0* -// CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP14]] +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 +// CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK-NEXT: store i32 [[TMP2]], ptr [[DOTADDR2]], align 4 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 +// CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2:%.*]], ptr [[TMP4]], i32 0, i32 0 +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP5]], i32 0, i32 0 +// CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 128 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2]], ptr [[TMP3]], i32 0, i32 2 +// CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3:%.*]], ptr [[TMP8]], i32 0, i32 2 +// CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_ANON_1:%.*]], ptr [[TMP7]], i32 0, i32 0 +// CHECK-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP10]], align 8 +// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP9]], i32 0, i32 0 +// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP12]] // CHECK-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] // CHECK: omp.arraycpy.body: -// CHECK-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK-NEXT: call void @_ZN1SIiEC1ERKS0_i(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 noundef 0) -// CHECK-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP14]] +// CHECK-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP11]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK-NEXT: call void @_ZN1SIiEC1ERKS0_i(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 noundef 0) +// CHECK-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP12]] // CHECK-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] // CHECK: omp.arraycpy.done3: -// CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3]], %struct..kmp_privates.t.3* [[TMP8]], i32 0, i32 3 -// CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1* [[TMP9]], i32 0, i32 1 -// CHECK-NEXT: [[TMP17:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP16]], align 8 -// CHECK-NEXT: call void @_ZN1SIiEC1ERKS0_i(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP15]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP17]], i32 noundef 0) +// CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3]], ptr [[TMP8]], i32 0, i32 3 +// CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[TMP7]], i32 0, i32 1 +// CHECK-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP14]], align 8 +// CHECK-NEXT: call void @_ZN1SIiEC1ERKS0_i(ptr noundef nonnull align 4 dereferenceable(4) [[TMP13]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP15]], i32 noundef 0) // CHECK-NEXT: ret void // // // CHECK-LABEL: define {{[^@]+}}@.omp_task_destructor..5 -// CHECK-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.2* noalias noundef [[TMP1:%.*]]) #[[ATTR7]] { +// CHECK-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR7]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates.2*, align 8 -// CHECK-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 -// CHECK-NEXT: store %struct.kmp_task_t_with_privates.2* [[TMP1]], %struct.kmp_task_t_with_privates.2** [[DOTADDR1]], align 8 -// CHECK-NEXT: [[TMP2:%.*]] = load %struct.kmp_task_t_with_privates.2*, %struct.kmp_task_t_with_privates.2** [[DOTADDR1]], align 8 -// CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2:%.*]], %struct.kmp_task_t_with_privates.2* [[TMP2]], i32 0, i32 2 -// CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3:%.*]], %struct..kmp_privates.t.3* [[TMP3]], i32 0, i32 2 -// CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3]], %struct..kmp_privates.t.3* [[TMP3]], i32 0, i32 3 -// CHECK-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP5]]) #[[ATTR4]] -// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP4]], i32 0, i32 0 -// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2:%.*]], ptr [[TMP2]], i32 0, i32 2 +// CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3:%.*]], ptr [[TMP3]], i32 0, i32 2 +// CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3]], ptr [[TMP3]], i32 0, i32 3 +// CHECK-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP5]]) #[[ATTR4]] +// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP4]], i32 0, i32 0 +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK: arraydestroy.body: -// CHECK-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP6]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP6]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK: arraydestroy.done2: -// CHECK-NEXT: [[TMP7:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK-NEXT: ret i32 [[TMP7]] // // // CHECK-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK-NEXT: entry: -// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// CHECK-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK-NEXT: ret void // // // CHECK-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK-NEXT: entry: -// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK-NEXT: store i32 0, i32* [[F]], align 4 +// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// CHECK-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 +// CHECK-NEXT: store i32 0, ptr [[F]], align 4 // CHECK-NEXT: ret void // // // CHECK-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_i -// CHECK-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], i32 noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], i32 noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK-NEXT: entry: -// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[T_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 -// CHECK-NEXT: store i32 [[T]], i32* [[T_ADDR]], align 4 -// CHECK-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 -// CHECK-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0 -// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4 -// CHECK-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_ADDR]], align 4 +// CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// CHECK-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 +// CHECK-NEXT: store i32 [[T]], ptr [[T_ADDR]], align 4 +// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// CHECK-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 +// CHECK-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0 +// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4 +// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[T_ADDR]], align 4 // CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] -// CHECK-NEXT: store i32 [[ADD]], i32* [[F]], align 4 +// CHECK-NEXT: store i32 [[ADD]], ptr [[F]], align 4 // CHECK-NEXT: ret void // // // CHECK-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK-NEXT: entry: -// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 +// CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// CHECK-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// CHECK-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 +// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 +// CHECK-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // CHECK-NEXT: ret void // // // CHECK-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK-NEXT: entry: -// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: ret void // // @@ -1058,119 +1018,114 @@ void array_func(int n, float a[n], St s[2]) { // LAMBDA-NEXT: entry: // LAMBDA-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // LAMBDA-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// LAMBDA-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// LAMBDA-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef nonnull align 1 dereferenceable(1) [[REF_TMP]]) +// LAMBDA-NEXT: store i32 0, ptr [[RETVAL]], align 4 +// LAMBDA-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]]) // LAMBDA-NEXT: ret i32 0 // // // LAMBDA-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// LAMBDA-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], double** noalias noundef [[TMP1:%.*]], i32** noalias noundef [[TMP2:%.*]]) #[[ATTR5:[0-9]+]] { +// LAMBDA-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]]) #[[ATTR5:[0-9]+]] { // LAMBDA-NEXT: entry: -// LAMBDA-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 -// LAMBDA-NEXT: [[DOTADDR1:%.*]] = alloca double**, align 8 -// LAMBDA-NEXT: [[DOTADDR2:%.*]] = alloca i32**, align 8 -// LAMBDA-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8 -// LAMBDA-NEXT: store double** [[TMP1]], double*** [[DOTADDR1]], align 8 -// LAMBDA-NEXT: store i32** [[TMP2]], i32*** [[DOTADDR2]], align 8 -// LAMBDA-NEXT: [[TMP3:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8 -// LAMBDA-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP3]], i32 0, i32 0 -// LAMBDA-NEXT: [[TMP5:%.*]] = load double**, double*** [[DOTADDR1]], align 8 -// LAMBDA-NEXT: store double* [[TMP4]], double** [[TMP5]], align 8 -// LAMBDA-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP3]], i32 0, i32 1 -// LAMBDA-NEXT: [[TMP7:%.*]] = load i32**, i32*** [[DOTADDR2]], align 8 -// LAMBDA-NEXT: store i32* [[TMP6]], i32** [[TMP7]], align 8 +// LAMBDA-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 +// LAMBDA-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// LAMBDA-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8 +// LAMBDA-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 +// LAMBDA-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// LAMBDA-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2]], align 8 +// LAMBDA-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR]], align 8 +// LAMBDA-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP3]], i32 0, i32 0 +// LAMBDA-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 +// LAMBDA-NEXT: store ptr [[TMP4]], ptr [[TMP5]], align 8 +// LAMBDA-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP3]], i32 0, i32 1 +// LAMBDA-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTADDR2]], align 8 +// LAMBDA-NEXT: store ptr [[TMP6]], ptr [[TMP7]], align 8 // LAMBDA-NEXT: ret void // // // LAMBDA-LABEL: define {{[^@]+}}@.omp_task_entry. -// LAMBDA-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { +// LAMBDA-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { // LAMBDA-NEXT: entry: // LAMBDA-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 -// LAMBDA-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 -// LAMBDA-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 -// LAMBDA-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 -// LAMBDA-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 +// LAMBDA-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8 +// LAMBDA-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8 +// LAMBDA-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8 +// LAMBDA-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8 // LAMBDA-NEXT: [[DOTLB__ADDR_I:%.*]] = alloca i64, align 8 // LAMBDA-NEXT: [[DOTUB__ADDR_I:%.*]] = alloca i64, align 8 // LAMBDA-NEXT: [[DOTST__ADDR_I:%.*]] = alloca i64, align 8 // LAMBDA-NEXT: [[DOTLITER__ADDR_I:%.*]] = alloca i32, align 4 -// LAMBDA-NEXT: [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca i8*, align 8 -// LAMBDA-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 -// LAMBDA-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca double*, align 8 -// LAMBDA-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca i32*, align 8 +// LAMBDA-NEXT: [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca ptr, align 8 +// LAMBDA-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8 +// LAMBDA-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca ptr, align 8 +// LAMBDA-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca ptr, align 8 // LAMBDA-NEXT: [[I_I:%.*]] = alloca i32, align 4 // LAMBDA-NEXT: [[DOTOMP_IV_I:%.*]] = alloca i32, align 4 // LAMBDA-NEXT: [[REF_TMP_I:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 // LAMBDA-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 -// LAMBDA-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 -// LAMBDA-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 -// LAMBDA-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 -// LAMBDA-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 -// LAMBDA-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 -// LAMBDA-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 -// LAMBDA-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 -// LAMBDA-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 -// LAMBDA-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 -// LAMBDA-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* -// LAMBDA-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 -// LAMBDA-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* -// LAMBDA-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* -// LAMBDA-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 5 -// LAMBDA-NEXT: [[TMP13:%.*]] = load i64, i64* [[TMP12]], align 8 -// LAMBDA-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 6 -// LAMBDA-NEXT: [[TMP15:%.*]] = load i64, i64* [[TMP14]], align 8 -// LAMBDA-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 7 -// LAMBDA-NEXT: [[TMP17:%.*]] = load i64, i64* [[TMP16]], align 8 -// LAMBDA-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 8 -// LAMBDA-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 8 -// LAMBDA-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 9 -// LAMBDA-NEXT: [[TMP21:%.*]] = load i8*, i8** [[TMP20]], align 8 +// LAMBDA-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// LAMBDA-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 +// LAMBDA-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// LAMBDA-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 +// LAMBDA-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 +// LAMBDA-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0 +// LAMBDA-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 +// LAMBDA-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 +// LAMBDA-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// LAMBDA-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 1 +// LAMBDA-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 5 +// LAMBDA-NEXT: [[TMP10:%.*]] = load i64, ptr [[TMP9]], align 8 +// LAMBDA-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 6 +// LAMBDA-NEXT: [[TMP12:%.*]] = load i64, ptr [[TMP11]], align 8 +// LAMBDA-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 7 +// LAMBDA-NEXT: [[TMP14:%.*]] = load i64, ptr [[TMP13]], align 8 +// LAMBDA-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 8 +// LAMBDA-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 8 +// LAMBDA-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 9 +// LAMBDA-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8 // LAMBDA-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]]) // LAMBDA-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]]) // LAMBDA-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]]) // LAMBDA-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]]) // LAMBDA-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]]) -// LAMBDA-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14 -// LAMBDA-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !14 -// LAMBDA-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14 -// LAMBDA-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, double**, i32**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14 -// LAMBDA-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !14 -// LAMBDA-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !14 -// LAMBDA-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !14 -// LAMBDA-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !14 -// LAMBDA-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !14 -// LAMBDA-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !14 -// LAMBDA-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14 -// LAMBDA-NEXT: [[TMP22:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14 -// LAMBDA-NEXT: [[TMP23:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14 -// LAMBDA-NEXT: [[TMP24:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14 -// LAMBDA-NEXT: [[TMP25:%.*]] = bitcast void (i8*, ...)* [[TMP23]] to void (i8*, double**, i32**)* -// LAMBDA-NEXT: call void [[TMP25]](i8* [[TMP24]], double** [[DOTFIRSTPRIV_PTR_ADDR_I]], i32** [[DOTFIRSTPRIV_PTR_ADDR1_I]]) #[[ATTR3:[0-9]+]] -// LAMBDA-NEXT: [[TMP26:%.*]] = load double*, double** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !14 -// LAMBDA-NEXT: [[TMP27:%.*]] = load i32*, i32** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !14 -// LAMBDA-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTLB__ADDR_I]], align 8, !noalias !14 -// LAMBDA-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP28]] to i32 -// LAMBDA-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14 +// LAMBDA-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14 +// LAMBDA-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias !14 +// LAMBDA-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14 +// LAMBDA-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14 +// LAMBDA-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias !14 +// LAMBDA-NEXT: store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias !14 +// LAMBDA-NEXT: store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias !14 +// LAMBDA-NEXT: store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias !14 +// LAMBDA-NEXT: store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias !14 +// LAMBDA-NEXT: store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !14 +// LAMBDA-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias !14 +// LAMBDA-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias !14 +// LAMBDA-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14 +// LAMBDA-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14 +// LAMBDA-NEXT: call void [[TMP20]](ptr [[TMP21]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]]) #[[ATTR3:[0-9]+]] +// LAMBDA-NEXT: [[TMP22:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !14 +// LAMBDA-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !14 +// LAMBDA-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias !14 +// LAMBDA-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP24]] to i32 +// LAMBDA-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias !14 // LAMBDA-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]] // LAMBDA: omp.inner.for.cond.i: -// LAMBDA-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV_I]], align 4, !noalias !14 -// LAMBDA-NEXT: [[CONV2_I:%.*]] = sext i32 [[TMP29]] to i64 -// LAMBDA-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTUB__ADDR_I]], align 8, !noalias !14 -// LAMBDA-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV2_I]], [[TMP30]] +// LAMBDA-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias !14 +// LAMBDA-NEXT: [[CONV2_I:%.*]] = sext i32 [[TMP25]] to i64 +// LAMBDA-NEXT: [[TMP26:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias !14 +// LAMBDA-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV2_I]], [[TMP26]] // LAMBDA-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]] // LAMBDA: omp.inner.for.body.i: -// LAMBDA-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV_I]], align 4, !noalias !14 -// LAMBDA-NEXT: store i32 [[TMP31]], i32* [[I_I]], align 4, !noalias !14 -// LAMBDA-NEXT: store double 1.000000e+00, double* [[TMP26]], align 8 -// LAMBDA-NEXT: store i32 11, i32* [[TMP27]], align 4 -// LAMBDA-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP_I]], i32 0, i32 0 -// LAMBDA-NEXT: store double* [[TMP26]], double** [[TMP32]], align 8, !noalias !14 -// LAMBDA-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP_I]], i32 0, i32 1 -// LAMBDA-NEXT: store i32* [[TMP27]], i32** [[TMP33]], align 8, !noalias !14 -// LAMBDA-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef nonnull align 8 dereferenceable(16) [[REF_TMP_I]]) -// LAMBDA-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_IV_I]], align 4, !noalias !14 -// LAMBDA-NEXT: [[ADD3_I:%.*]] = add nsw i32 [[TMP34]], 1 -// LAMBDA-NEXT: store i32 [[ADD3_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14 +// LAMBDA-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias !14 +// LAMBDA-NEXT: store i32 [[TMP27]], ptr [[I_I]], align 4, !noalias !14 +// LAMBDA-NEXT: store double 1.000000e+00, ptr [[TMP22]], align 8 +// LAMBDA-NEXT: store i32 11, ptr [[TMP23]], align 4 +// LAMBDA-NEXT: store ptr [[TMP22]], ptr [[REF_TMP_I]], align 8, !noalias !14 +// LAMBDA-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP_I]], i32 0, i32 1 +// LAMBDA-NEXT: store ptr [[TMP23]], ptr [[TMP28]], align 8, !noalias !14 +// LAMBDA-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(16) [[REF_TMP_I]]) +// LAMBDA-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias !14 +// LAMBDA-NEXT: [[ADD3_I:%.*]] = add nsw i32 [[TMP29]], 1 +// LAMBDA-NEXT: store i32 [[ADD3_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias !14 // LAMBDA-NEXT: br label [[OMP_INNER_FOR_COND_I]] // LAMBDA: .omp_outlined..exit: // LAMBDA-NEXT: ret i32 0 @@ -1180,391 +1135,369 @@ void array_func(int n, float a[n], St s[2]) { // BLOCKS-SAME: () #[[ATTR1:[0-9]+]] { // BLOCKS-NEXT: entry: // BLOCKS-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// BLOCKS-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// BLOCKS-NEXT: [[TMP0:%.*]] = load i8*, i8** getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to %struct.__block_literal_generic*), i32 0, i32 3), align 8 -// BLOCKS-NEXT: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to void (i8*)* -// BLOCKS-NEXT: call void [[TMP1]](i8* noundef bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to i8*)) +// BLOCKS-NEXT: store i32 0, ptr [[RETVAL]], align 4 +// BLOCKS-NEXT: [[TMP0:%.*]] = load ptr, ptr getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr @__block_literal_global, i32 0, i32 3), align 8 +// BLOCKS-NEXT: call void [[TMP0]](ptr noundef @__block_literal_global) // BLOCKS-NEXT: ret i32 0 // // // BLOCKS-LABEL: define {{[^@]+}}@__main_block_invoke -// BLOCKS-SAME: (i8* noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] { +// BLOCKS-SAME: (ptr noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] { // BLOCKS-NEXT: entry: -// BLOCKS-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// BLOCKS-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*, align 8 -// BLOCKS-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// BLOCKS-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* -// BLOCKS-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>** [[BLOCK_ADDR]], align 8 -// BLOCKS-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @__main_block_invoke.omp_outlined to void (i32*, i32*, ...)*)) +// BLOCKS-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 8 +// BLOCKS-NEXT: [[BLOCK_ADDR:%.*]] = alloca ptr, align 8 +// BLOCKS-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 +// BLOCKS-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 8 +// BLOCKS-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 0, ptr @__main_block_invoke.omp_outlined) // BLOCKS-NEXT: ret void // // // BLOCKS-LABEL: define {{[^@]+}}@__main_block_invoke.omp_outlined -// BLOCKS-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { +// BLOCKS-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { // BLOCKS-NEXT: entry: -// BLOCKS-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// BLOCKS-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// BLOCKS-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 +// BLOCKS-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 // BLOCKS-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 // BLOCKS-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// BLOCKS-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// BLOCKS-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// BLOCKS-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// BLOCKS-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// BLOCKS-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// BLOCKS-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// BLOCKS-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 +// BLOCKS-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// BLOCKS-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 +// BLOCKS-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB1]], i32 [[TMP1]]) // BLOCKS-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 // BLOCKS-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] // BLOCKS: omp_if.then: -// BLOCKS-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// BLOCKS-NEXT: [[TMP4:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i64 96, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*)) -// BLOCKS-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to %struct.kmp_task_t_with_privates* -// BLOCKS-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP5]], i32 0, i32 0 -// BLOCKS-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP5]], i32 0, i32 1 -// BLOCKS-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP7]], i32 0, i32 0 -// BLOCKS-NEXT: [[TMP9:%.*]] = load volatile double, double* @g, align 8 -// BLOCKS-NEXT: store volatile double [[TMP9]], double* [[TMP8]], align 8 -// BLOCKS-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP7]], i32 0, i32 1 -// BLOCKS-NEXT: [[TMP11:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// BLOCKS-NEXT: store i32 [[TMP11]], i32* [[TMP10]], align 8 -// BLOCKS-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP6]], i32 0, i32 5 -// BLOCKS-NEXT: store i64 0, i64* [[TMP12]], align 8 -// BLOCKS-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP6]], i32 0, i32 6 -// BLOCKS-NEXT: store i64 9, i64* [[TMP13]], align 8 -// BLOCKS-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP6]], i32 0, i32 7 -// BLOCKS-NEXT: store i64 1, i64* [[TMP14]], align 8 -// BLOCKS-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP6]], i32 0, i32 9 -// BLOCKS-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i8* -// BLOCKS-NEXT: call void @llvm.memset.p0i8.i64(i8* align 8 [[TMP16]], i8 0, i64 8, i1 false) -// BLOCKS-NEXT: [[TMP17:%.*]] = load i64, i64* [[TMP14]], align 8 -// BLOCKS-NEXT: call void @__kmpc_taskloop(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* [[TMP4]], i32 1, i64* [[TMP12]], i64* [[TMP13]], i64 [[TMP17]], i32 1, i32 0, i64 0, i8* null) -// BLOCKS-NEXT: call void @__kmpc_end_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// BLOCKS-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// BLOCKS-NEXT: call void @__kmpc_taskgroup(ptr @[[GLOB1]], i32 [[TMP1]]) +// BLOCKS-NEXT: [[TMP4:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i64 96, i64 1, ptr @.omp_task_entry.) +// BLOCKS-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP4]], i32 0, i32 0 +// BLOCKS-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP4]], i32 0, i32 1 +// BLOCKS-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP6]], i32 0, i32 0 +// BLOCKS-NEXT: [[TMP8:%.*]] = load volatile double, ptr @g, align 8 +// BLOCKS-NEXT: store volatile double [[TMP8]], ptr [[TMP7]], align 8 +// BLOCKS-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP6]], i32 0, i32 1 +// BLOCKS-NEXT: [[TMP10:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4 +// BLOCKS-NEXT: store i32 [[TMP10]], ptr [[TMP9]], align 8 +// BLOCKS-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP5]], i32 0, i32 5 +// BLOCKS-NEXT: store i64 0, ptr [[TMP11]], align 8 +// BLOCKS-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP5]], i32 0, i32 6 +// BLOCKS-NEXT: store i64 9, ptr [[TMP12]], align 8 +// BLOCKS-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP5]], i32 0, i32 7 +// BLOCKS-NEXT: store i64 1, ptr [[TMP13]], align 8 +// BLOCKS-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP5]], i32 0, i32 9 +// BLOCKS-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP14]], i8 0, i64 8, i1 false) +// BLOCKS-NEXT: [[TMP15:%.*]] = load i64, ptr [[TMP13]], align 8 +// BLOCKS-NEXT: call void @__kmpc_taskloop(ptr @[[GLOB1]], i32 [[TMP1]], ptr [[TMP4]], i32 1, ptr [[TMP11]], ptr [[TMP12]], i64 [[TMP15]], i32 1, i32 0, i64 0, ptr null) +// BLOCKS-NEXT: call void @__kmpc_end_taskgroup(ptr @[[GLOB1]], i32 [[TMP1]]) +// BLOCKS-NEXT: call void @__kmpc_end_master(ptr @[[GLOB1]], i32 [[TMP1]]) // BLOCKS-NEXT: br label [[OMP_IF_END]] // BLOCKS: omp_if.end: // BLOCKS-NEXT: ret void // // // BLOCKS-LABEL: define {{[^@]+}}@_block_invoke -// BLOCKS-SAME: (i8* noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { +// BLOCKS-SAME: (ptr noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { // BLOCKS-NEXT: entry: -// BLOCKS-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// BLOCKS-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>*, align 8 -// BLOCKS-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// BLOCKS-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* -// BLOCKS-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>** [[BLOCK_ADDR]], align 8 -// BLOCKS-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK]], i32 0, i32 5 -// BLOCKS-NEXT: store double 2.000000e+00, double* [[BLOCK_CAPTURE_ADDR]], align 8 -// BLOCKS-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK]], i32 0, i32 6 -// BLOCKS-NEXT: store i32 22, i32* [[BLOCK_CAPTURE_ADDR1]], align 8 +// BLOCKS-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 8 +// BLOCKS-NEXT: [[BLOCK_ADDR:%.*]] = alloca ptr, align 8 +// BLOCKS-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 +// BLOCKS-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 8 +// BLOCKS-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 5 +// BLOCKS-NEXT: store double 2.000000e+00, ptr [[BLOCK_CAPTURE_ADDR]], align 8 +// BLOCKS-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 6 +// BLOCKS-NEXT: store i32 22, ptr [[BLOCK_CAPTURE_ADDR1]], align 8 // BLOCKS-NEXT: ret void // // // BLOCKS-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// BLOCKS-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], double** noalias noundef [[TMP1:%.*]], i32** noalias noundef [[TMP2:%.*]]) #[[ATTR6:[0-9]+]] { +// BLOCKS-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]]) #[[ATTR6:[0-9]+]] { // BLOCKS-NEXT: entry: -// BLOCKS-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 -// BLOCKS-NEXT: [[DOTADDR1:%.*]] = alloca double**, align 8 -// BLOCKS-NEXT: [[DOTADDR2:%.*]] = alloca i32**, align 8 -// BLOCKS-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8 -// BLOCKS-NEXT: store double** [[TMP1]], double*** [[DOTADDR1]], align 8 -// BLOCKS-NEXT: store i32** [[TMP2]], i32*** [[DOTADDR2]], align 8 -// BLOCKS-NEXT: [[TMP3:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8 -// BLOCKS-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP3]], i32 0, i32 0 -// BLOCKS-NEXT: [[TMP5:%.*]] = load double**, double*** [[DOTADDR1]], align 8 -// BLOCKS-NEXT: store double* [[TMP4]], double** [[TMP5]], align 8 -// BLOCKS-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP3]], i32 0, i32 1 -// BLOCKS-NEXT: [[TMP7:%.*]] = load i32**, i32*** [[DOTADDR2]], align 8 -// BLOCKS-NEXT: store i32* [[TMP6]], i32** [[TMP7]], align 8 +// BLOCKS-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 +// BLOCKS-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// BLOCKS-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8 +// BLOCKS-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 +// BLOCKS-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// BLOCKS-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2]], align 8 +// BLOCKS-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR]], align 8 +// BLOCKS-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP3]], i32 0, i32 0 +// BLOCKS-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 +// BLOCKS-NEXT: store ptr [[TMP4]], ptr [[TMP5]], align 8 +// BLOCKS-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP3]], i32 0, i32 1 +// BLOCKS-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTADDR2]], align 8 +// BLOCKS-NEXT: store ptr [[TMP6]], ptr [[TMP7]], align 8 // BLOCKS-NEXT: ret void // // // BLOCKS-LABEL: define {{[^@]+}}@.omp_task_entry. -// BLOCKS-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { +// BLOCKS-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { // BLOCKS-NEXT: entry: // BLOCKS-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 -// BLOCKS-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 -// BLOCKS-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 -// BLOCKS-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 -// BLOCKS-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 +// BLOCKS-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8 +// BLOCKS-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8 +// BLOCKS-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8 +// BLOCKS-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8 // BLOCKS-NEXT: [[DOTLB__ADDR_I:%.*]] = alloca i64, align 8 // BLOCKS-NEXT: [[DOTUB__ADDR_I:%.*]] = alloca i64, align 8 // BLOCKS-NEXT: [[DOTST__ADDR_I:%.*]] = alloca i64, align 8 // BLOCKS-NEXT: [[DOTLITER__ADDR_I:%.*]] = alloca i32, align 4 -// BLOCKS-NEXT: [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca i8*, align 8 -// BLOCKS-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 -// BLOCKS-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca double*, align 8 -// BLOCKS-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca i32*, align 8 +// BLOCKS-NEXT: [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca ptr, align 8 +// BLOCKS-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8 +// BLOCKS-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca ptr, align 8 +// BLOCKS-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca ptr, align 8 // BLOCKS-NEXT: [[I_I:%.*]] = alloca i32, align 4 // BLOCKS-NEXT: [[DOTOMP_IV_I:%.*]] = alloca i32, align 4 -// BLOCKS-NEXT: [[BLOCK_I:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, align 8 +// BLOCKS-NEXT: [[BLOCK_I:%.*]] = alloca <{ ptr, i32, i32, ptr, ptr, double, i32 }>, align 8 // BLOCKS-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 -// BLOCKS-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 -// BLOCKS-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 -// BLOCKS-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 -// BLOCKS-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 -// BLOCKS-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 -// BLOCKS-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 -// BLOCKS-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 -// BLOCKS-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 -// BLOCKS-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 -// BLOCKS-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* -// BLOCKS-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 -// BLOCKS-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* -// BLOCKS-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* -// BLOCKS-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 5 -// BLOCKS-NEXT: [[TMP13:%.*]] = load i64, i64* [[TMP12]], align 8 -// BLOCKS-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 6 -// BLOCKS-NEXT: [[TMP15:%.*]] = load i64, i64* [[TMP14]], align 8 -// BLOCKS-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 7 -// BLOCKS-NEXT: [[TMP17:%.*]] = load i64, i64* [[TMP16]], align 8 -// BLOCKS-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 8 -// BLOCKS-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 8 -// BLOCKS-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 9 -// BLOCKS-NEXT: [[TMP21:%.*]] = load i8*, i8** [[TMP20]], align 8 +// BLOCKS-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// BLOCKS-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 +// BLOCKS-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// BLOCKS-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 +// BLOCKS-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 +// BLOCKS-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0 +// BLOCKS-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 +// BLOCKS-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 +// BLOCKS-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// BLOCKS-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 1 +// BLOCKS-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 5 +// BLOCKS-NEXT: [[TMP10:%.*]] = load i64, ptr [[TMP9]], align 8 +// BLOCKS-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 6 +// BLOCKS-NEXT: [[TMP12:%.*]] = load i64, ptr [[TMP11]], align 8 +// BLOCKS-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 7 +// BLOCKS-NEXT: [[TMP14:%.*]] = load i64, ptr [[TMP13]], align 8 +// BLOCKS-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 8 +// BLOCKS-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 8 +// BLOCKS-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 9 +// BLOCKS-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8 // BLOCKS-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]]) // BLOCKS-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]]) // BLOCKS-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]]) // BLOCKS-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]]) // BLOCKS-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]]) -// BLOCKS-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14 -// BLOCKS-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !14 -// BLOCKS-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14 -// BLOCKS-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, double**, i32**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14 -// BLOCKS-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !14 -// BLOCKS-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !14 -// BLOCKS-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !14 -// BLOCKS-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !14 -// BLOCKS-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !14 -// BLOCKS-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !14 -// BLOCKS-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14 -// BLOCKS-NEXT: [[TMP22:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14 -// BLOCKS-NEXT: [[TMP23:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14 -// BLOCKS-NEXT: [[TMP24:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14 -// BLOCKS-NEXT: [[TMP25:%.*]] = bitcast void (i8*, ...)* [[TMP23]] to void (i8*, double**, i32**)* -// BLOCKS-NEXT: call void [[TMP25]](i8* [[TMP24]], double** [[DOTFIRSTPRIV_PTR_ADDR_I]], i32** [[DOTFIRSTPRIV_PTR_ADDR1_I]]) #[[ATTR4:[0-9]+]] -// BLOCKS-NEXT: [[TMP26:%.*]] = load double*, double** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !14 -// BLOCKS-NEXT: [[TMP27:%.*]] = load i32*, i32** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !14 -// BLOCKS-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTLB__ADDR_I]], align 8, !noalias !14 -// BLOCKS-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP28]] to i32 -// BLOCKS-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14 +// BLOCKS-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14 +// BLOCKS-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias !14 +// BLOCKS-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14 +// BLOCKS-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14 +// BLOCKS-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias !14 +// BLOCKS-NEXT: store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias !14 +// BLOCKS-NEXT: store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias !14 +// BLOCKS-NEXT: store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias !14 +// BLOCKS-NEXT: store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias !14 +// BLOCKS-NEXT: store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !14 +// BLOCKS-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias !14 +// BLOCKS-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias !14 +// BLOCKS-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14 +// BLOCKS-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14 +// BLOCKS-NEXT: call void [[TMP20]](ptr [[TMP21]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]]) #[[ATTR4:[0-9]+]] +// BLOCKS-NEXT: [[TMP22:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !14 +// BLOCKS-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !14 +// BLOCKS-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias !14 +// BLOCKS-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP24]] to i32 +// BLOCKS-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias !14 // BLOCKS-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]] // BLOCKS: omp.inner.for.cond.i: -// BLOCKS-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV_I]], align 4, !noalias !14 -// BLOCKS-NEXT: [[CONV2_I:%.*]] = sext i32 [[TMP29]] to i64 -// BLOCKS-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTUB__ADDR_I]], align 8, !noalias !14 -// BLOCKS-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV2_I]], [[TMP30]] +// BLOCKS-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias !14 +// BLOCKS-NEXT: [[CONV2_I:%.*]] = sext i32 [[TMP25]] to i64 +// BLOCKS-NEXT: [[TMP26:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias !14 +// BLOCKS-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV2_I]], [[TMP26]] // BLOCKS-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]] // BLOCKS: omp.inner.for.body.i: -// BLOCKS-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV_I]], align 4, !noalias !14 -// BLOCKS-NEXT: store i32 [[TMP31]], i32* [[I_I]], align 4, !noalias !14 -// BLOCKS-NEXT: store double 1.000000e+00, double* [[TMP26]], align 8 -// BLOCKS-NEXT: store i32 11, i32* [[TMP27]], align 4 -// BLOCKS-NEXT: [[BLOCK_ISA_I:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK_I]], i32 0, i32 0 -// BLOCKS-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA_I]], align 8, !noalias !14 -// BLOCKS-NEXT: [[BLOCK_FLAGS_I:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK_I]], i32 0, i32 1 -// BLOCKS-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS_I]], align 8, !noalias !14 -// BLOCKS-NEXT: [[BLOCK_RESERVED_I:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK_I]], i32 0, i32 2 -// BLOCKS-NEXT: store i32 0, i32* [[BLOCK_RESERVED_I]], align 4, !noalias !14 -// BLOCKS-NEXT: [[BLOCK_INVOKE_I:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK_I]], i32 0, i32 3 -// BLOCKS-NEXT: store i8* bitcast (void (i8*)* @_block_invoke to i8*), i8** [[BLOCK_INVOKE_I]], align 8, !noalias !14 -// BLOCKS-NEXT: [[BLOCK_DESCRIPTOR_I:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK_I]], i32 0, i32 4 -// BLOCKS-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.1 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR_I]], align 8, !noalias !14 -// BLOCKS-NEXT: [[BLOCK_CAPTURED_I:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK_I]], i32 0, i32 5 -// BLOCKS-NEXT: [[TMP32:%.*]] = load volatile double, double* [[TMP26]], align 8 -// BLOCKS-NEXT: store volatile double [[TMP32]], double* [[BLOCK_CAPTURED_I]], align 8, !noalias !14 -// BLOCKS-NEXT: [[BLOCK_CAPTURED3_I:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK_I]], i32 0, i32 6 -// BLOCKS-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP27]], align 4 -// BLOCKS-NEXT: store i32 [[TMP33]], i32* [[BLOCK_CAPTURED3_I]], align 8, !noalias !14 -// BLOCKS-NEXT: [[TMP34:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK_I]] to void ()* -// BLOCKS-NEXT: [[BLOCK_LITERAL_I:%.*]] = bitcast void ()* [[TMP34]] to %struct.__block_literal_generic* -// BLOCKS-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL_I]], i32 0, i32 3 -// BLOCKS-NEXT: [[TMP36:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL_I]] to i8* -// BLOCKS-NEXT: [[TMP37:%.*]] = load i8*, i8** [[TMP35]], align 8, !noalias !14 -// BLOCKS-NEXT: [[TMP38:%.*]] = bitcast i8* [[TMP37]] to void (i8*)* -// BLOCKS-NEXT: call void [[TMP38]](i8* noundef [[TMP36]]) #[[ATTR4]] -// BLOCKS-NEXT: [[TMP39:%.*]] = load i32, i32* [[DOTOMP_IV_I]], align 4, !noalias !14 -// BLOCKS-NEXT: [[ADD4_I:%.*]] = add nsw i32 [[TMP39]], 1 -// BLOCKS-NEXT: store i32 [[ADD4_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14 +// BLOCKS-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias !14 +// BLOCKS-NEXT: store i32 [[TMP27]], ptr [[I_I]], align 4, !noalias !14 +// BLOCKS-NEXT: store double 1.000000e+00, ptr [[TMP22]], align 8 +// BLOCKS-NEXT: store i32 11, ptr [[TMP23]], align 4 +// BLOCKS-NEXT: store ptr @_NSConcreteStackBlock, ptr [[BLOCK_I]], align 8, !noalias !14 +// BLOCKS-NEXT: [[BLOCK_FLAGS_I:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK_I]], i32 0, i32 1 +// BLOCKS-NEXT: store i32 1073741824, ptr [[BLOCK_FLAGS_I]], align 8, !noalias !14 +// BLOCKS-NEXT: [[BLOCK_RESERVED_I:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK_I]], i32 0, i32 2 +// BLOCKS-NEXT: store i32 0, ptr [[BLOCK_RESERVED_I]], align 4, !noalias !14 +// BLOCKS-NEXT: [[BLOCK_INVOKE_I:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK_I]], i32 0, i32 3 +// BLOCKS-NEXT: store ptr @_block_invoke, ptr [[BLOCK_INVOKE_I]], align 8, !noalias !14 +// BLOCKS-NEXT: [[BLOCK_DESCRIPTOR_I:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK_I]], i32 0, i32 4 +// BLOCKS-NEXT: store ptr @__block_descriptor_tmp.1, ptr [[BLOCK_DESCRIPTOR_I]], align 8, !noalias !14 +// BLOCKS-NEXT: [[BLOCK_CAPTURED_I:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK_I]], i32 0, i32 5 +// BLOCKS-NEXT: [[TMP28:%.*]] = load volatile double, ptr [[TMP22]], align 8 +// BLOCKS-NEXT: store volatile double [[TMP28]], ptr [[BLOCK_CAPTURED_I]], align 8, !noalias !14 +// BLOCKS-NEXT: [[BLOCK_CAPTURED3_I:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK_I]], i32 0, i32 6 +// BLOCKS-NEXT: [[TMP29:%.*]] = load i32, ptr [[TMP23]], align 4 +// BLOCKS-NEXT: store i32 [[TMP29]], ptr [[BLOCK_CAPTURED3_I]], align 8, !noalias !14 +// BLOCKS-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr [[BLOCK_I]], i32 0, i32 3 +// BLOCKS-NEXT: [[TMP31:%.*]] = load ptr, ptr [[TMP30]], align 8, !noalias !14 +// BLOCKS-NEXT: call void [[TMP31]](ptr noundef [[BLOCK_I]]) #[[ATTR4]] +// BLOCKS-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias !14 +// BLOCKS-NEXT: [[ADD4_I:%.*]] = add nsw i32 [[TMP32]], 1 +// BLOCKS-NEXT: store i32 [[ADD4_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias !14 // BLOCKS-NEXT: br label [[OMP_INNER_FOR_COND_I]] // BLOCKS: .omp_outlined..exit: // BLOCKS-NEXT: ret i32 0 // // // ARRAY-LABEL: define {{[^@]+}}@_Z10array_funciPfP2St -// ARRAY-SAME: (i32 noundef [[N:%.*]], float* noundef [[A:%.*]], %struct.St* noundef [[S:%.*]]) #[[ATTR0:[0-9]+]] { +// ARRAY-SAME: (i32 noundef [[N:%.*]], ptr noundef [[A:%.*]], ptr noundef [[S:%.*]]) #[[ATTR0:[0-9]+]] { // ARRAY-NEXT: entry: // ARRAY-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// ARRAY-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// ARRAY-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 -// ARRAY-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// ARRAY-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// ARRAY-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 -// ARRAY-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// ARRAY-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 +// ARRAY-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 +// ARRAY-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// ARRAY-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 +// ARRAY-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 +// ARRAY-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // ARRAY-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// ARRAY-NEXT: [[TMP2:%.*]] = load float*, float** [[A_ADDR]], align 8 -// ARRAY-NEXT: [[TMP3:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 -// ARRAY-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, float*, %struct.St*)* @_Z10array_funciPfP2St.omp_outlined to void (i32*, i32*, ...)*), i64 [[TMP1]], float* [[TMP2]], %struct.St* [[TMP3]]) +// ARRAY-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// ARRAY-NEXT: [[TMP3:%.*]] = load ptr, ptr [[S_ADDR]], align 8 +// ARRAY-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 3, ptr @_Z10array_funciPfP2St.omp_outlined, i64 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]]) // ARRAY-NEXT: ret void // // // ARRAY-LABEL: define {{[^@]+}}@_Z10array_funciPfP2St.omp_outlined -// ARRAY-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], float* noundef [[A:%.*]], %struct.St* noundef [[S:%.*]]) #[[ATTR1:[0-9]+]] { +// ARRAY-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], ptr noundef [[A:%.*]], ptr noundef [[S:%.*]]) #[[ATTR1:[0-9]+]] { // ARRAY-NEXT: entry: -// ARRAY-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// ARRAY-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// ARRAY-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 +// ARRAY-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 // ARRAY-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// ARRAY-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// ARRAY-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 +// ARRAY-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 +// ARRAY-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // ARRAY-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 8 // ARRAY-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// ARRAY-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// ARRAY-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// ARRAY-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// ARRAY-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// ARRAY-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 -// ARRAY-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// ARRAY-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// ARRAY-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// ARRAY-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// ARRAY-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// ARRAY-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 +// ARRAY-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 +// ARRAY-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 +// ARRAY-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 +// ARRAY-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 +// ARRAY-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// ARRAY-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// ARRAY-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB1]], i32 [[TMP2]]) // ARRAY-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 // ARRAY-NEXT: br i1 [[TMP4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] // ARRAY: omp_if.then: -// ARRAY-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 -// ARRAY-NEXT: store i64 [[TMP0]], i64* [[TMP5]], align 8 -// ARRAY-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// ARRAY-NEXT: [[TMP6:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1, i64 96, i64 8, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*)) -// ARRAY-NEXT: [[TMP7:%.*]] = bitcast i8* [[TMP6]] to %struct.kmp_task_t_with_privates* -// ARRAY-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP7]], i32 0, i32 0 -// ARRAY-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP8]], i32 0, i32 0 -// ARRAY-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 -// ARRAY-NEXT: [[TMP11:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* -// ARRAY-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP10]], i8* align 8 [[TMP11]], i64 8, i1 false) -// ARRAY-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP7]], i32 0, i32 1 -// ARRAY-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP12]], i32 0, i32 0 -// ARRAY-NEXT: [[TMP14:%.*]] = load float*, float** [[A_ADDR]], align 8 -// ARRAY-NEXT: store float* [[TMP14]], float** [[TMP13]], align 8 -// ARRAY-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP12]], i32 0, i32 1 -// ARRAY-NEXT: [[TMP16:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 -// ARRAY-NEXT: store %struct.St* [[TMP16]], %struct.St** [[TMP15]], align 8 -// ARRAY-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP8]], i32 0, i32 5 -// ARRAY-NEXT: store i64 0, i64* [[TMP17]], align 8 -// ARRAY-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP8]], i32 0, i32 6 -// ARRAY-NEXT: store i64 9, i64* [[TMP18]], align 8 -// ARRAY-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP8]], i32 0, i32 7 -// ARRAY-NEXT: store i64 1, i64* [[TMP19]], align 8 -// ARRAY-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP8]], i32 0, i32 9 -// ARRAY-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i8* -// ARRAY-NEXT: call void @llvm.memset.p0i8.i64(i8* align 8 [[TMP21]], i8 0, i64 8, i1 false) -// ARRAY-NEXT: [[TMP22:%.*]] = load i64, i64* [[TMP19]], align 8 -// ARRAY-NEXT: call void @__kmpc_taskloop(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i8* [[TMP6]], i32 1, i64* [[TMP17]], i64* [[TMP18]], i64 [[TMP22]], i32 1, i32 0, i64 0, i8* null) -// ARRAY-NEXT: call void @__kmpc_end_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// ARRAY-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// ARRAY-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0 +// ARRAY-NEXT: store i64 [[TMP0]], ptr [[TMP5]], align 8 +// ARRAY-NEXT: call void @__kmpc_taskgroup(ptr @[[GLOB1]], i32 [[TMP2]]) +// ARRAY-NEXT: [[TMP6:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP2]], i32 1, i64 96, i64 8, ptr @.omp_task_entry.) +// ARRAY-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP6]], i32 0, i32 0 +// ARRAY-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP7]], i32 0, i32 0 +// ARRAY-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 +// ARRAY-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP9]], ptr align 8 [[AGG_CAPTURED]], i64 8, i1 false) +// ARRAY-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP6]], i32 0, i32 1 +// ARRAY-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP10]], i32 0, i32 0 +// ARRAY-NEXT: [[TMP12:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// ARRAY-NEXT: store ptr [[TMP12]], ptr [[TMP11]], align 8 +// ARRAY-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP10]], i32 0, i32 1 +// ARRAY-NEXT: [[TMP14:%.*]] = load ptr, ptr [[S_ADDR]], align 8 +// ARRAY-NEXT: store ptr [[TMP14]], ptr [[TMP13]], align 8 +// ARRAY-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP7]], i32 0, i32 5 +// ARRAY-NEXT: store i64 0, ptr [[TMP15]], align 8 +// ARRAY-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP7]], i32 0, i32 6 +// ARRAY-NEXT: store i64 9, ptr [[TMP16]], align 8 +// ARRAY-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP7]], i32 0, i32 7 +// ARRAY-NEXT: store i64 1, ptr [[TMP17]], align 8 +// ARRAY-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP7]], i32 0, i32 9 +// ARRAY-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP18]], i8 0, i64 8, i1 false) +// ARRAY-NEXT: [[TMP19:%.*]] = load i64, ptr [[TMP17]], align 8 +// ARRAY-NEXT: call void @__kmpc_taskloop(ptr @[[GLOB1]], i32 [[TMP2]], ptr [[TMP6]], i32 1, ptr [[TMP15]], ptr [[TMP16]], i64 [[TMP19]], i32 1, i32 0, i64 0, ptr null) +// ARRAY-NEXT: call void @__kmpc_end_taskgroup(ptr @[[GLOB1]], i32 [[TMP2]]) +// ARRAY-NEXT: call void @__kmpc_end_master(ptr @[[GLOB1]], i32 [[TMP2]]) // ARRAY-NEXT: br label [[OMP_IF_END]] // ARRAY: omp_if.end: // ARRAY-NEXT: ret void // // // ARRAY-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// ARRAY-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], float*** noalias noundef [[TMP1:%.*]], %struct.St*** noalias noundef [[TMP2:%.*]]) #[[ATTR4:[0-9]+]] { +// ARRAY-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]]) #[[ATTR4:[0-9]+]] { // ARRAY-NEXT: entry: -// ARRAY-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 -// ARRAY-NEXT: [[DOTADDR1:%.*]] = alloca float***, align 8 -// ARRAY-NEXT: [[DOTADDR2:%.*]] = alloca %struct.St***, align 8 -// ARRAY-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8 -// ARRAY-NEXT: store float*** [[TMP1]], float**** [[DOTADDR1]], align 8 -// ARRAY-NEXT: store %struct.St*** [[TMP2]], %struct.St**** [[DOTADDR2]], align 8 -// ARRAY-NEXT: [[TMP3:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8 -// ARRAY-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP3]], i32 0, i32 0 -// ARRAY-NEXT: [[TMP5:%.*]] = load float***, float**** [[DOTADDR1]], align 8 -// ARRAY-NEXT: store float** [[TMP4]], float*** [[TMP5]], align 8 -// ARRAY-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP3]], i32 0, i32 1 -// ARRAY-NEXT: [[TMP7:%.*]] = load %struct.St***, %struct.St**** [[DOTADDR2]], align 8 -// ARRAY-NEXT: store %struct.St** [[TMP6]], %struct.St*** [[TMP7]], align 8 +// ARRAY-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 +// ARRAY-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// ARRAY-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8 +// ARRAY-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 +// ARRAY-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// ARRAY-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2]], align 8 +// ARRAY-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR]], align 8 +// ARRAY-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP3]], i32 0, i32 0 +// ARRAY-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 +// ARRAY-NEXT: store ptr [[TMP4]], ptr [[TMP5]], align 8 +// ARRAY-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP3]], i32 0, i32 1 +// ARRAY-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTADDR2]], align 8 +// ARRAY-NEXT: store ptr [[TMP6]], ptr [[TMP7]], align 8 // ARRAY-NEXT: ret void // // // ARRAY-LABEL: define {{[^@]+}}@.omp_task_entry. -// ARRAY-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// ARRAY-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { // ARRAY-NEXT: entry: // ARRAY-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 -// ARRAY-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 -// ARRAY-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 -// ARRAY-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 -// ARRAY-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 +// ARRAY-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8 +// ARRAY-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8 +// ARRAY-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8 +// ARRAY-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8 // ARRAY-NEXT: [[DOTLB__ADDR_I:%.*]] = alloca i64, align 8 // ARRAY-NEXT: [[DOTUB__ADDR_I:%.*]] = alloca i64, align 8 // ARRAY-NEXT: [[DOTST__ADDR_I:%.*]] = alloca i64, align 8 // ARRAY-NEXT: [[DOTLITER__ADDR_I:%.*]] = alloca i32, align 4 -// ARRAY-NEXT: [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca i8*, align 8 -// ARRAY-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 -// ARRAY-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca float**, align 8 -// ARRAY-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca %struct.St**, align 8 +// ARRAY-NEXT: [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca ptr, align 8 +// ARRAY-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8 +// ARRAY-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca ptr, align 8 +// ARRAY-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca ptr, align 8 // ARRAY-NEXT: [[I_I:%.*]] = alloca i32, align 4 // ARRAY-NEXT: [[DOTOMP_IV_I:%.*]] = alloca i32, align 4 // ARRAY-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 -// ARRAY-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 -// ARRAY-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 -// ARRAY-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 -// ARRAY-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 -// ARRAY-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 -// ARRAY-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 -// ARRAY-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 -// ARRAY-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 -// ARRAY-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 -// ARRAY-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* -// ARRAY-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 -// ARRAY-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* -// ARRAY-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* -// ARRAY-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 5 -// ARRAY-NEXT: [[TMP13:%.*]] = load i64, i64* [[TMP12]], align 8 -// ARRAY-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 6 -// ARRAY-NEXT: [[TMP15:%.*]] = load i64, i64* [[TMP14]], align 8 -// ARRAY-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 7 -// ARRAY-NEXT: [[TMP17:%.*]] = load i64, i64* [[TMP16]], align 8 -// ARRAY-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 8 -// ARRAY-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 8 -// ARRAY-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 9 -// ARRAY-NEXT: [[TMP21:%.*]] = load i8*, i8** [[TMP20]], align 8 +// ARRAY-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// ARRAY-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 +// ARRAY-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// ARRAY-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 +// ARRAY-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 +// ARRAY-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0 +// ARRAY-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 +// ARRAY-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 +// ARRAY-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// ARRAY-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 1 +// ARRAY-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 5 +// ARRAY-NEXT: [[TMP10:%.*]] = load i64, ptr [[TMP9]], align 8 +// ARRAY-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 6 +// ARRAY-NEXT: [[TMP12:%.*]] = load i64, ptr [[TMP11]], align 8 +// ARRAY-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 7 +// ARRAY-NEXT: [[TMP14:%.*]] = load i64, ptr [[TMP13]], align 8 +// ARRAY-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 8 +// ARRAY-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 8 +// ARRAY-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 9 +// ARRAY-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8 // ARRAY-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]]) // ARRAY-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]]) // ARRAY-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]]) // ARRAY-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]]) // ARRAY-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]]) -// ARRAY-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14 -// ARRAY-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !14 -// ARRAY-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14 -// ARRAY-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, float***, %struct.St***)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14 -// ARRAY-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !14 -// ARRAY-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !14 -// ARRAY-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !14 -// ARRAY-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !14 -// ARRAY-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !14 -// ARRAY-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !14 -// ARRAY-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14 -// ARRAY-NEXT: [[TMP22:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14 -// ARRAY-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP22]], i32 0, i32 0 -// ARRAY-NEXT: [[TMP24:%.*]] = load i64, i64* [[TMP23]], align 8 -// ARRAY-NEXT: [[TMP25:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14 -// ARRAY-NEXT: [[TMP26:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14 -// ARRAY-NEXT: [[TMP27:%.*]] = bitcast void (i8*, ...)* [[TMP25]] to void (i8*, float***, %struct.St***)* -// ARRAY-NEXT: call void [[TMP27]](i8* [[TMP26]], float*** [[DOTFIRSTPRIV_PTR_ADDR_I]], %struct.St*** [[DOTFIRSTPRIV_PTR_ADDR1_I]]) #[[ATTR2:[0-9]+]] -// ARRAY-NEXT: [[TMP28:%.*]] = load float**, float*** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !14 -// ARRAY-NEXT: [[TMP29:%.*]] = load %struct.St**, %struct.St*** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !14 -// ARRAY-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTLB__ADDR_I]], align 8, !noalias !14 -// ARRAY-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP30]] to i32 -// ARRAY-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14 +// ARRAY-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14 +// ARRAY-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias !14 +// ARRAY-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14 +// ARRAY-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14 +// ARRAY-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias !14 +// ARRAY-NEXT: store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias !14 +// ARRAY-NEXT: store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias !14 +// ARRAY-NEXT: store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias !14 +// ARRAY-NEXT: store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias !14 +// ARRAY-NEXT: store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !14 +// ARRAY-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias !14 +// ARRAY-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias !14 +// ARRAY-NEXT: [[TMP20:%.*]] = load i64, ptr [[TMP19]], align 8 +// ARRAY-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14 +// ARRAY-NEXT: [[TMP22:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14 +// ARRAY-NEXT: call void [[TMP21]](ptr [[TMP22]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]]) #[[ATTR2:[0-9]+]] +// ARRAY-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !14 +// ARRAY-NEXT: [[TMP24:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !14 +// ARRAY-NEXT: [[TMP25:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias !14 +// ARRAY-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP25]] to i32 +// ARRAY-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias !14 // ARRAY-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]] // ARRAY: omp.inner.for.cond.i: -// ARRAY-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV_I]], align 4, !noalias !14 -// ARRAY-NEXT: [[CONV2_I:%.*]] = sext i32 [[TMP31]] to i64 -// ARRAY-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTUB__ADDR_I]], align 8, !noalias !14 -// ARRAY-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV2_I]], [[TMP32]] +// ARRAY-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias !14 +// ARRAY-NEXT: [[CONV2_I:%.*]] = sext i32 [[TMP26]] to i64 +// ARRAY-NEXT: [[TMP27:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias !14 +// ARRAY-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV2_I]], [[TMP27]] // ARRAY-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]] // ARRAY: omp.inner.for.body.i: -// ARRAY-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_IV_I]], align 4, !noalias !14 -// ARRAY-NEXT: store i32 [[TMP33]], i32* [[I_I]], align 4, !noalias !14 -// ARRAY-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_IV_I]], align 4, !noalias !14 -// ARRAY-NEXT: [[ADD3_I:%.*]] = add nsw i32 [[TMP34]], 1 -// ARRAY-NEXT: store i32 [[ADD3_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14 +// ARRAY-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias !14 +// ARRAY-NEXT: store i32 [[TMP28]], ptr [[I_I]], align 4, !noalias !14 +// ARRAY-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias !14 +// ARRAY-NEXT: [[ADD3_I:%.*]] = add nsw i32 [[TMP29]], 1 +// ARRAY-NEXT: store i32 [[ADD3_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias !14 // ARRAY-NEXT: br label [[OMP_INNER_FOR_COND_I]] // ARRAY: .omp_outlined..exit: // ARRAY-NEXT: ret i32 0 @@ -1581,94 +1514,91 @@ void array_func(int n, float a[n], St s[2]) { // SIMD-ONLY0-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 16 // SIMD-ONLY0-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 8 // SIMD-ONLY0-NEXT: [[I:%.*]] = alloca i32, align 4 -// SIMD-ONLY0-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// SIMD-ONLY0-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[TTT]]) -// SIMD-ONLY0-NEXT: call void @_ZN1SIdEC1ERKS0_d(%struct.S* noundef nonnull align 8 dereferenceable(8) [[TEST]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[TTT]], double noundef 0.000000e+00) -// SIMD-ONLY0-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// SIMD-ONLY0-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// SIMD-ONLY0-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// SIMD-ONLY0-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* noundef nonnull align 8 dereferenceable(8) [[ARRAYINIT_BEGIN]], double noundef 1.000000e+00) -// SIMD-ONLY0-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// SIMD-ONLY0-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* noundef nonnull align 8 dereferenceable(8) [[ARRAYINIT_ELEMENT]], double noundef 2.000000e+00) -// SIMD-ONLY0-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* noundef nonnull align 8 dereferenceable(8) [[VAR]], double noundef 3.000000e+00) -// SIMD-ONLY0-NEXT: store i32 0, i32* [[I]], align 4 +// SIMD-ONLY0-NEXT: store i32 0, ptr [[RETVAL]], align 4 +// SIMD-ONLY0-NEXT: call void @_ZN1SIdEC1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[TTT]]) +// SIMD-ONLY0-NEXT: call void @_ZN1SIdEC1ERKS0_d(ptr noundef nonnull align 8 dereferenceable(8) [[TEST]], ptr noundef nonnull align 8 dereferenceable(8) [[TTT]], double noundef 0.000000e+00) +// SIMD-ONLY0-NEXT: store i32 0, ptr [[T_VAR]], align 4 +// SIMD-ONLY0-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const.main.vec, i64 8, i1 false) +// SIMD-ONLY0-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 0 +// SIMD-ONLY0-NEXT: call void @_ZN1SIdEC1Ed(ptr noundef nonnull align 8 dereferenceable(8) [[ARRAYINIT_BEGIN]], double noundef 1.000000e+00) +// SIMD-ONLY0-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYINIT_BEGIN]], i64 1 +// SIMD-ONLY0-NEXT: call void @_ZN1SIdEC1Ed(ptr noundef nonnull align 8 dereferenceable(8) [[ARRAYINIT_ELEMENT]], double noundef 2.000000e+00) +// SIMD-ONLY0-NEXT: call void @_ZN1SIdEC1Ed(ptr noundef nonnull align 8 dereferenceable(8) [[VAR]], double noundef 3.000000e+00) +// SIMD-ONLY0-NEXT: store i32 0, ptr [[I]], align 4 // SIMD-ONLY0-NEXT: br label [[FOR_COND:%.*]] // SIMD-ONLY0: for.cond: -// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// SIMD-ONLY0-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 10 +// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load i32, ptr [[I]], align 4 +// SIMD-ONLY0-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 // SIMD-ONLY0-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] // SIMD-ONLY0: for.body: -// SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// SIMD-ONLY0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// SIMD-ONLY0-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// SIMD-ONLY0-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// SIMD-ONLY0-NEXT: [[TMP3:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// SIMD-ONLY0-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// SIMD-ONLY0-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP3]], i8* align 8 [[TMP4]], i64 8, i1 false) -// SIMD-ONLY0-NEXT: store i32 33, i32* @_ZZ4mainE5sivar, align 4 +// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4 +// SIMD-ONLY0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 0 +// SIMD-ONLY0-NEXT: store i32 [[TMP1]], ptr [[ARRAYIDX]], align 4 +// SIMD-ONLY0-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 0 +// SIMD-ONLY0-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 16 [[ARRAYIDX1]], ptr align 8 [[VAR]], i64 8, i1 false) +// SIMD-ONLY0-NEXT: store i32 33, ptr @_ZZ4mainE5sivar, align 4 // SIMD-ONLY0-NEXT: br label [[FOR_INC:%.*]] // SIMD-ONLY0: for.inc: -// SIMD-ONLY0-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// SIMD-ONLY0-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 -// SIMD-ONLY0-NEXT: store i32 [[INC]], i32* [[I]], align 4 +// SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load i32, ptr [[I]], align 4 +// SIMD-ONLY0-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 +// SIMD-ONLY0-NEXT: store i32 [[INC]], ptr [[I]], align 4 // SIMD-ONLY0-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] // SIMD-ONLY0: for.end: // SIMD-ONLY0-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() -// SIMD-ONLY0-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// SIMD-ONLY0-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[VAR]]) #[[ATTR4:[0-9]+]] -// SIMD-ONLY0-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// SIMD-ONLY0-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// SIMD-ONLY0-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 +// SIMD-ONLY0-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[VAR]]) #[[ATTR4:[0-9]+]] +// SIMD-ONLY0-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// SIMD-ONLY0-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // SIMD-ONLY0-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // SIMD-ONLY0: arraydestroy.body: -// SIMD-ONLY0-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP6]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// SIMD-ONLY0-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// SIMD-ONLY0-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// SIMD-ONLY0-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// SIMD-ONLY0-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP3]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// SIMD-ONLY0-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// SIMD-ONLY0-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// SIMD-ONLY0-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // SIMD-ONLY0-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // SIMD-ONLY0: arraydestroy.done2: -// SIMD-ONLY0-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[TEST]]) #[[ATTR4]] -// SIMD-ONLY0-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[TTT]]) #[[ATTR4]] -// SIMD-ONLY0-NEXT: [[TMP7:%.*]] = load i32, i32* [[RETVAL]], align 4 -// SIMD-ONLY0-NEXT: ret i32 [[TMP7]] +// SIMD-ONLY0-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[TEST]]) #[[ATTR4]] +// SIMD-ONLY0-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[TTT]]) #[[ATTR4]] +// SIMD-ONLY0-NEXT: [[TMP4:%.*]] = load i32, ptr [[RETVAL]], align 4 +// SIMD-ONLY0-NEXT: ret i32 [[TMP4]] // // // SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIdEC1Ev -// SIMD-ONLY0-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { +// SIMD-ONLY0-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { // SIMD-ONLY0-NEXT: entry: -// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// SIMD-ONLY0-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// SIMD-ONLY0-NEXT: call void @_ZN1SIdEC2Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS1]]) +// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY0-NEXT: call void @_ZN1SIdEC2Ev(ptr noundef nonnull align 8 dereferenceable(8) [[THIS1]]) // SIMD-ONLY0-NEXT: ret void // // // SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIdEC1ERKS0_d -// SIMD-ONLY0-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[S:%.*]], double noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY0-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[S:%.*]], double noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY0-NEXT: entry: -// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// SIMD-ONLY0-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 +// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// SIMD-ONLY0-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY0-NEXT: [[T_ADDR:%.*]] = alloca double, align 8 -// SIMD-ONLY0-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// SIMD-ONLY0-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 -// SIMD-ONLY0-NEXT: store double [[T]], double* [[T_ADDR]], align 8 -// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 -// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load double, double* [[T_ADDR]], align 8 -// SIMD-ONLY0-NEXT: call void @_ZN1SIdEC2ERKS0_d(%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS1]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[TMP0]], double noundef [[TMP1]]) +// SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY0-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 +// SIMD-ONLY0-NEXT: store double [[T]], ptr [[T_ADDR]], align 8 +// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 +// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load double, ptr [[T_ADDR]], align 8 +// SIMD-ONLY0-NEXT: call void @_ZN1SIdEC2ERKS0_d(ptr noundef nonnull align 8 dereferenceable(8) [[THIS1]], ptr noundef nonnull align 8 dereferenceable(8) [[TMP0]], double noundef [[TMP1]]) // SIMD-ONLY0-NEXT: ret void // // // SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIdEC1Ed -// SIMD-ONLY0-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], double noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY0-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], double noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY0-NEXT: entry: -// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY0-NEXT: [[A_ADDR:%.*]] = alloca double, align 8 -// SIMD-ONLY0-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// SIMD-ONLY0-NEXT: store double [[A]], double* [[A_ADDR]], align 8 -// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load double, double* [[A_ADDR]], align 8 -// SIMD-ONLY0-NEXT: call void @_ZN1SIdEC2Ed(%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS1]], double noundef [[TMP0]]) +// SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY0-NEXT: store double [[A]], ptr [[A_ADDR]], align 8 +// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load double, ptr [[A_ADDR]], align 8 +// SIMD-ONLY0-NEXT: call void @_ZN1SIdEC2Ed(ptr noundef nonnull align 8 dereferenceable(8) [[THIS1]], double noundef [[TMP0]]) // SIMD-ONLY0-NEXT: ret void // // @@ -1683,219 +1613,216 @@ void array_func(int n, float a[n], St s[2]) { // SIMD-ONLY0-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 // SIMD-ONLY0-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // SIMD-ONLY0-NEXT: [[I:%.*]] = alloca i32, align 4 -// SIMD-ONLY0-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TTT]]) -// SIMD-ONLY0-NEXT: call void @_ZN1SIiEC1ERKS0_i(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TTT]], i32 noundef 0) -// SIMD-ONLY0-NEXT: store i32 0, i32* [[T_VAR]], align 128 -// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// SIMD-ONLY0-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// SIMD-ONLY0-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// SIMD-ONLY0-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef 1) -// SIMD-ONLY0-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// SIMD-ONLY0-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) -// SIMD-ONLY0-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]], i32 noundef 3) -// SIMD-ONLY0-NEXT: store i32 0, i32* [[I]], align 4 +// SIMD-ONLY0-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TTT]]) +// SIMD-ONLY0-NEXT: call void @_ZN1SIiEC1ERKS0_i(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]], ptr noundef nonnull align 4 dereferenceable(4) [[TTT]], i32 noundef 0) +// SIMD-ONLY0-NEXT: store i32 0, ptr [[T_VAR]], align 128 +// SIMD-ONLY0-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false) +// SIMD-ONLY0-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 0 +// SIMD-ONLY0-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef 1) +// SIMD-ONLY0-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYINIT_BEGIN]], i64 1 +// SIMD-ONLY0-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// SIMD-ONLY0-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]], i32 noundef 3) +// SIMD-ONLY0-NEXT: store i32 0, ptr [[I]], align 4 // SIMD-ONLY0-NEXT: br label [[FOR_COND:%.*]] // SIMD-ONLY0: for.cond: -// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// SIMD-ONLY0-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 10 +// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load i32, ptr [[I]], align 4 +// SIMD-ONLY0-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 // SIMD-ONLY0-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] // SIMD-ONLY0: for.body: -// SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 128 -// SIMD-ONLY0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// SIMD-ONLY0-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// SIMD-ONLY0-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// SIMD-ONLY0-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* -// SIMD-ONLY0-NEXT: [[TMP4:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* -// SIMD-ONLY0-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 4, i1 false) +// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 128 +// SIMD-ONLY0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 0 +// SIMD-ONLY0-NEXT: store i32 [[TMP1]], ptr [[ARRAYIDX]], align 4 +// SIMD-ONLY0-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 0 +// SIMD-ONLY0-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX1]], ptr align 4 [[VAR]], i64 4, i1 false) // SIMD-ONLY0-NEXT: br label [[FOR_INC:%.*]] // SIMD-ONLY0: for.inc: -// SIMD-ONLY0-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// SIMD-ONLY0-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 -// SIMD-ONLY0-NEXT: store i32 [[INC]], i32* [[I]], align 4 +// SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load i32, ptr [[I]], align 4 +// SIMD-ONLY0-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 +// SIMD-ONLY0-NEXT: store i32 [[INC]], ptr [[I]], align 4 // SIMD-ONLY0-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // SIMD-ONLY0: for.end: -// SIMD-ONLY0-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// SIMD-ONLY0-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// SIMD-ONLY0-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// SIMD-ONLY0-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// SIMD-ONLY0-NEXT: store i32 0, ptr [[RETVAL]], align 4 +// SIMD-ONLY0-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] +// SIMD-ONLY0-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// SIMD-ONLY0-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // SIMD-ONLY0-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // SIMD-ONLY0: arraydestroy.body: -// SIMD-ONLY0-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP6]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// SIMD-ONLY0-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// SIMD-ONLY0-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// SIMD-ONLY0-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// SIMD-ONLY0-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP3]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// SIMD-ONLY0-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// SIMD-ONLY0-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// SIMD-ONLY0-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // SIMD-ONLY0-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // SIMD-ONLY0: arraydestroy.done2: -// SIMD-ONLY0-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// SIMD-ONLY0-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TTT]]) #[[ATTR4]] -// SIMD-ONLY0-NEXT: [[TMP7:%.*]] = load i32, i32* [[RETVAL]], align 4 -// SIMD-ONLY0-NEXT: ret i32 [[TMP7]] +// SIMD-ONLY0-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// SIMD-ONLY0-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TTT]]) #[[ATTR4]] +// SIMD-ONLY0-NEXT: [[TMP4:%.*]] = load i32, ptr [[RETVAL]], align 4 +// SIMD-ONLY0-NEXT: ret i32 [[TMP4]] // // // SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIdED1Ev -// SIMD-ONLY0-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY0-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY0-NEXT: entry: -// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// SIMD-ONLY0-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// SIMD-ONLY0-NEXT: call void @_ZN1SIdED2Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS1]]) #[[ATTR4]] +// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY0-NEXT: call void @_ZN1SIdED2Ev(ptr noundef nonnull align 8 dereferenceable(8) [[THIS1]]) #[[ATTR4]] // SIMD-ONLY0-NEXT: ret void // // // SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIdEC2Ev -// SIMD-ONLY0-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY0-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY0-NEXT: entry: -// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// SIMD-ONLY0-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// SIMD-ONLY0-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// SIMD-ONLY0-NEXT: store double 0.000000e+00, double* [[F]], align 8 +// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY0-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 +// SIMD-ONLY0-NEXT: store double 0.000000e+00, ptr [[F]], align 8 // SIMD-ONLY0-NEXT: ret void // // // SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIdED2Ev -// SIMD-ONLY0-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY0-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY0-NEXT: entry: -// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// SIMD-ONLY0-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // SIMD-ONLY0-NEXT: ret void // // // SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIdEC2ERKS0_d -// SIMD-ONLY0-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[S:%.*]], double noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY0-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[S:%.*]], double noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY0-NEXT: entry: -// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// SIMD-ONLY0-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 +// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// SIMD-ONLY0-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY0-NEXT: [[T_ADDR:%.*]] = alloca double, align 8 -// SIMD-ONLY0-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// SIMD-ONLY0-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 -// SIMD-ONLY0-NEXT: store double [[T]], double* [[T_ADDR]], align 8 -// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// SIMD-ONLY0-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 -// SIMD-ONLY0-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0 -// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load double, double* [[F2]], align 8 -// SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load double, double* [[T_ADDR]], align 8 +// SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY0-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 +// SIMD-ONLY0-NEXT: store double [[T]], ptr [[T_ADDR]], align 8 +// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY0-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 +// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 +// SIMD-ONLY0-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0 +// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load double, ptr [[F2]], align 8 +// SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load double, ptr [[T_ADDR]], align 8 // SIMD-ONLY0-NEXT: [[ADD:%.*]] = fadd double [[TMP1]], [[TMP2]] -// SIMD-ONLY0-NEXT: store double [[ADD]], double* [[F]], align 8 +// SIMD-ONLY0-NEXT: store double [[ADD]], ptr [[F]], align 8 // SIMD-ONLY0-NEXT: ret void // // // SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIdEC2Ed -// SIMD-ONLY0-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], double noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY0-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], double noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY0-NEXT: entry: -// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY0-NEXT: [[A_ADDR:%.*]] = alloca double, align 8 -// SIMD-ONLY0-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// SIMD-ONLY0-NEXT: store double [[A]], double* [[A_ADDR]], align 8 -// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// SIMD-ONLY0-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load double, double* [[A_ADDR]], align 8 -// SIMD-ONLY0-NEXT: store double [[TMP0]], double* [[F]], align 8 +// SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY0-NEXT: store double [[A]], ptr [[A_ADDR]], align 8 +// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY0-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 +// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load double, ptr [[A_ADDR]], align 8 +// SIMD-ONLY0-NEXT: store double [[TMP0]], ptr [[F]], align 8 // SIMD-ONLY0-NEXT: ret void // // // SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// SIMD-ONLY0-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY0-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY0-NEXT: entry: -// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// SIMD-ONLY0-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// SIMD-ONLY0-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) +// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY0-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // SIMD-ONLY0-NEXT: ret void // // // SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_i -// SIMD-ONLY0-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], i32 noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY0-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], i32 noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY0-NEXT: entry: -// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// SIMD-ONLY0-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// SIMD-ONLY0-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY0-NEXT: [[T_ADDR:%.*]] = alloca i32, align 4 -// SIMD-ONLY0-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// SIMD-ONLY0-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 -// SIMD-ONLY0-NEXT: store i32 [[T]], i32* [[T_ADDR]], align 4 -// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 -// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_ADDR]], align 4 -// SIMD-ONLY0-NEXT: call void @_ZN1SIiEC2ERKS0_i(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], i32 noundef [[TMP1]]) +// SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY0-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 +// SIMD-ONLY0-NEXT: store i32 [[T]], ptr [[T_ADDR]], align 4 +// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 +// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_ADDR]], align 4 +// SIMD-ONLY0-NEXT: call void @_ZN1SIiEC2ERKS0_i(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], i32 noundef [[TMP1]]) // SIMD-ONLY0-NEXT: ret void // // // SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// SIMD-ONLY0-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY0-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY0-NEXT: entry: -// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY0-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// SIMD-ONLY0-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// SIMD-ONLY0-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// SIMD-ONLY0-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]) +// SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY0-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 +// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 +// SIMD-ONLY0-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]) // SIMD-ONLY0-NEXT: ret void // // // SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// SIMD-ONLY0-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY0-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY0-NEXT: entry: -// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// SIMD-ONLY0-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// SIMD-ONLY0-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY0-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // SIMD-ONLY0-NEXT: ret void // // // SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// SIMD-ONLY0-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY0-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY0-NEXT: entry: -// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// SIMD-ONLY0-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// SIMD-ONLY0-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// SIMD-ONLY0-NEXT: store i32 0, i32* [[F]], align 4 +// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY0-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 +// SIMD-ONLY0-NEXT: store i32 0, ptr [[F]], align 4 // SIMD-ONLY0-NEXT: ret void // // // SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_i -// SIMD-ONLY0-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], i32 noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY0-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], i32 noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY0-NEXT: entry: -// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// SIMD-ONLY0-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// SIMD-ONLY0-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY0-NEXT: [[T_ADDR:%.*]] = alloca i32, align 4 -// SIMD-ONLY0-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// SIMD-ONLY0-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 -// SIMD-ONLY0-NEXT: store i32 [[T]], i32* [[T_ADDR]], align 4 -// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// SIMD-ONLY0-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 -// SIMD-ONLY0-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0 -// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4 -// SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_ADDR]], align 4 +// SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY0-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 +// SIMD-ONLY0-NEXT: store i32 [[T]], ptr [[T_ADDR]], align 4 +// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY0-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 +// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 +// SIMD-ONLY0-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0 +// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4 +// SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load i32, ptr [[T_ADDR]], align 4 // SIMD-ONLY0-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] -// SIMD-ONLY0-NEXT: store i32 [[ADD]], i32* [[F]], align 4 +// SIMD-ONLY0-NEXT: store i32 [[ADD]], ptr [[F]], align 4 // SIMD-ONLY0-NEXT: ret void // // // SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// SIMD-ONLY0-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY0-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY0-NEXT: entry: -// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY0-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// SIMD-ONLY0-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// SIMD-ONLY0-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// SIMD-ONLY0-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// SIMD-ONLY0-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 +// SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY0-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 +// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY0-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 +// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 +// SIMD-ONLY0-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // SIMD-ONLY0-NEXT: ret void // // // SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// SIMD-ONLY0-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY0-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY0-NEXT: entry: -// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// SIMD-ONLY0-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // SIMD-ONLY0-NEXT: ret void // // @@ -1910,94 +1837,91 @@ void array_func(int n, float a[n], St s[2]) { // SIMD-ONLY1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 16 // SIMD-ONLY1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 8 // SIMD-ONLY1-NEXT: [[I:%.*]] = alloca i32, align 4 -// SIMD-ONLY1-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// SIMD-ONLY1-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[TTT]]) -// SIMD-ONLY1-NEXT: call void @_ZN1SIdEC1ERKS0_d(%struct.S* noundef nonnull align 8 dereferenceable(8) [[TEST]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[TTT]], double noundef 0.000000e+00) -// SIMD-ONLY1-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// SIMD-ONLY1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// SIMD-ONLY1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// SIMD-ONLY1-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* noundef nonnull align 8 dereferenceable(8) [[ARRAYINIT_BEGIN]], double noundef 1.000000e+00) -// SIMD-ONLY1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// SIMD-ONLY1-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* noundef nonnull align 8 dereferenceable(8) [[ARRAYINIT_ELEMENT]], double noundef 2.000000e+00) -// SIMD-ONLY1-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* noundef nonnull align 8 dereferenceable(8) [[VAR]], double noundef 3.000000e+00) -// SIMD-ONLY1-NEXT: store i32 0, i32* [[I]], align 4 +// SIMD-ONLY1-NEXT: store i32 0, ptr [[RETVAL]], align 4 +// SIMD-ONLY1-NEXT: call void @_ZN1SIdEC1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[TTT]]) +// SIMD-ONLY1-NEXT: call void @_ZN1SIdEC1ERKS0_d(ptr noundef nonnull align 8 dereferenceable(8) [[TEST]], ptr noundef nonnull align 8 dereferenceable(8) [[TTT]], double noundef 0.000000e+00) +// SIMD-ONLY1-NEXT: store i32 0, ptr [[T_VAR]], align 4 +// SIMD-ONLY1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const.main.vec, i64 8, i1 false) +// SIMD-ONLY1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 0 +// SIMD-ONLY1-NEXT: call void @_ZN1SIdEC1Ed(ptr noundef nonnull align 8 dereferenceable(8) [[ARRAYINIT_BEGIN]], double noundef 1.000000e+00) +// SIMD-ONLY1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYINIT_BEGIN]], i64 1 +// SIMD-ONLY1-NEXT: call void @_ZN1SIdEC1Ed(ptr noundef nonnull align 8 dereferenceable(8) [[ARRAYINIT_ELEMENT]], double noundef 2.000000e+00) +// SIMD-ONLY1-NEXT: call void @_ZN1SIdEC1Ed(ptr noundef nonnull align 8 dereferenceable(8) [[VAR]], double noundef 3.000000e+00) +// SIMD-ONLY1-NEXT: store i32 0, ptr [[I]], align 4 // SIMD-ONLY1-NEXT: br label [[FOR_COND:%.*]] // SIMD-ONLY1: for.cond: -// SIMD-ONLY1-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// SIMD-ONLY1-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 10 +// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load i32, ptr [[I]], align 4 +// SIMD-ONLY1-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 // SIMD-ONLY1-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] // SIMD-ONLY1: for.body: -// SIMD-ONLY1-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// SIMD-ONLY1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// SIMD-ONLY1-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// SIMD-ONLY1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// SIMD-ONLY1-NEXT: [[TMP3:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* -// SIMD-ONLY1-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// SIMD-ONLY1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP3]], i8* align 8 [[TMP4]], i64 8, i1 false) -// SIMD-ONLY1-NEXT: store i32 33, i32* @_ZZ4mainE5sivar, align 4 +// SIMD-ONLY1-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4 +// SIMD-ONLY1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 0 +// SIMD-ONLY1-NEXT: store i32 [[TMP1]], ptr [[ARRAYIDX]], align 4 +// SIMD-ONLY1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 0 +// SIMD-ONLY1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 16 [[ARRAYIDX1]], ptr align 8 [[VAR]], i64 8, i1 false) +// SIMD-ONLY1-NEXT: store i32 33, ptr @_ZZ4mainE5sivar, align 4 // SIMD-ONLY1-NEXT: br label [[FOR_INC:%.*]] // SIMD-ONLY1: for.inc: -// SIMD-ONLY1-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// SIMD-ONLY1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 -// SIMD-ONLY1-NEXT: store i32 [[INC]], i32* [[I]], align 4 +// SIMD-ONLY1-NEXT: [[TMP2:%.*]] = load i32, ptr [[I]], align 4 +// SIMD-ONLY1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 +// SIMD-ONLY1-NEXT: store i32 [[INC]], ptr [[I]], align 4 // SIMD-ONLY1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] // SIMD-ONLY1: for.end: // SIMD-ONLY1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() -// SIMD-ONLY1-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// SIMD-ONLY1-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[VAR]]) #[[ATTR4:[0-9]+]] -// SIMD-ONLY1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// SIMD-ONLY1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// SIMD-ONLY1-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 +// SIMD-ONLY1-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[VAR]]) #[[ATTR4:[0-9]+]] +// SIMD-ONLY1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// SIMD-ONLY1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // SIMD-ONLY1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // SIMD-ONLY1: arraydestroy.body: -// SIMD-ONLY1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP6]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// SIMD-ONLY1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// SIMD-ONLY1-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// SIMD-ONLY1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// SIMD-ONLY1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP3]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// SIMD-ONLY1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// SIMD-ONLY1-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// SIMD-ONLY1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // SIMD-ONLY1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // SIMD-ONLY1: arraydestroy.done2: -// SIMD-ONLY1-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[TEST]]) #[[ATTR4]] -// SIMD-ONLY1-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[TTT]]) #[[ATTR4]] -// SIMD-ONLY1-NEXT: [[TMP7:%.*]] = load i32, i32* [[RETVAL]], align 4 -// SIMD-ONLY1-NEXT: ret i32 [[TMP7]] +// SIMD-ONLY1-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[TEST]]) #[[ATTR4]] +// SIMD-ONLY1-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[TTT]]) #[[ATTR4]] +// SIMD-ONLY1-NEXT: [[TMP4:%.*]] = load i32, ptr [[RETVAL]], align 4 +// SIMD-ONLY1-NEXT: ret i32 [[TMP4]] // // // SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIdEC1Ev -// SIMD-ONLY1-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { +// SIMD-ONLY1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { // SIMD-ONLY1-NEXT: entry: -// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// SIMD-ONLY1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// SIMD-ONLY1-NEXT: call void @_ZN1SIdEC2Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS1]]) +// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// SIMD-ONLY1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY1-NEXT: call void @_ZN1SIdEC2Ev(ptr noundef nonnull align 8 dereferenceable(8) [[THIS1]]) // SIMD-ONLY1-NEXT: ret void // // // SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIdEC1ERKS0_d -// SIMD-ONLY1-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[S:%.*]], double noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[S:%.*]], double noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY1-NEXT: entry: -// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// SIMD-ONLY1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 +// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// SIMD-ONLY1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY1-NEXT: [[T_ADDR:%.*]] = alloca double, align 8 -// SIMD-ONLY1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// SIMD-ONLY1-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 -// SIMD-ONLY1-NEXT: store double [[T]], double* [[T_ADDR]], align 8 -// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 -// SIMD-ONLY1-NEXT: [[TMP1:%.*]] = load double, double* [[T_ADDR]], align 8 -// SIMD-ONLY1-NEXT: call void @_ZN1SIdEC2ERKS0_d(%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS1]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[TMP0]], double noundef [[TMP1]]) +// SIMD-ONLY1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 +// SIMD-ONLY1-NEXT: store double [[T]], ptr [[T_ADDR]], align 8 +// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 +// SIMD-ONLY1-NEXT: [[TMP1:%.*]] = load double, ptr [[T_ADDR]], align 8 +// SIMD-ONLY1-NEXT: call void @_ZN1SIdEC2ERKS0_d(ptr noundef nonnull align 8 dereferenceable(8) [[THIS1]], ptr noundef nonnull align 8 dereferenceable(8) [[TMP0]], double noundef [[TMP1]]) // SIMD-ONLY1-NEXT: ret void // // // SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIdEC1Ed -// SIMD-ONLY1-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], double noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], double noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY1-NEXT: entry: -// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY1-NEXT: [[A_ADDR:%.*]] = alloca double, align 8 -// SIMD-ONLY1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// SIMD-ONLY1-NEXT: store double [[A]], double* [[A_ADDR]], align 8 -// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load double, double* [[A_ADDR]], align 8 -// SIMD-ONLY1-NEXT: call void @_ZN1SIdEC2Ed(%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS1]], double noundef [[TMP0]]) +// SIMD-ONLY1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY1-NEXT: store double [[A]], ptr [[A_ADDR]], align 8 +// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load double, ptr [[A_ADDR]], align 8 +// SIMD-ONLY1-NEXT: call void @_ZN1SIdEC2Ed(ptr noundef nonnull align 8 dereferenceable(8) [[THIS1]], double noundef [[TMP0]]) // SIMD-ONLY1-NEXT: ret void // // @@ -2012,219 +1936,216 @@ void array_func(int n, float a[n], St s[2]) { // SIMD-ONLY1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 // SIMD-ONLY1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // SIMD-ONLY1-NEXT: [[I:%.*]] = alloca i32, align 4 -// SIMD-ONLY1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TTT]]) -// SIMD-ONLY1-NEXT: call void @_ZN1SIiEC1ERKS0_i(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TTT]], i32 noundef 0) -// SIMD-ONLY1-NEXT: store i32 0, i32* [[T_VAR]], align 128 -// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// SIMD-ONLY1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// SIMD-ONLY1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// SIMD-ONLY1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef 1) -// SIMD-ONLY1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// SIMD-ONLY1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) -// SIMD-ONLY1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]], i32 noundef 3) -// SIMD-ONLY1-NEXT: store i32 0, i32* [[I]], align 4 +// SIMD-ONLY1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TTT]]) +// SIMD-ONLY1-NEXT: call void @_ZN1SIiEC1ERKS0_i(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]], ptr noundef nonnull align 4 dereferenceable(4) [[TTT]], i32 noundef 0) +// SIMD-ONLY1-NEXT: store i32 0, ptr [[T_VAR]], align 128 +// SIMD-ONLY1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false) +// SIMD-ONLY1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 0 +// SIMD-ONLY1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef 1) +// SIMD-ONLY1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYINIT_BEGIN]], i64 1 +// SIMD-ONLY1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// SIMD-ONLY1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]], i32 noundef 3) +// SIMD-ONLY1-NEXT: store i32 0, ptr [[I]], align 4 // SIMD-ONLY1-NEXT: br label [[FOR_COND:%.*]] // SIMD-ONLY1: for.cond: -// SIMD-ONLY1-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 -// SIMD-ONLY1-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 10 +// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load i32, ptr [[I]], align 4 +// SIMD-ONLY1-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 // SIMD-ONLY1-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] // SIMD-ONLY1: for.body: -// SIMD-ONLY1-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 128 -// SIMD-ONLY1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// SIMD-ONLY1-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// SIMD-ONLY1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// SIMD-ONLY1-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* -// SIMD-ONLY1-NEXT: [[TMP4:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* -// SIMD-ONLY1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 4, i1 false) +// SIMD-ONLY1-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 128 +// SIMD-ONLY1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 0 +// SIMD-ONLY1-NEXT: store i32 [[TMP1]], ptr [[ARRAYIDX]], align 4 +// SIMD-ONLY1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 0 +// SIMD-ONLY1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX1]], ptr align 4 [[VAR]], i64 4, i1 false) // SIMD-ONLY1-NEXT: br label [[FOR_INC:%.*]] // SIMD-ONLY1: for.inc: -// SIMD-ONLY1-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 -// SIMD-ONLY1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 -// SIMD-ONLY1-NEXT: store i32 [[INC]], i32* [[I]], align 4 +// SIMD-ONLY1-NEXT: [[TMP2:%.*]] = load i32, ptr [[I]], align 4 +// SIMD-ONLY1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 +// SIMD-ONLY1-NEXT: store i32 [[INC]], ptr [[I]], align 4 // SIMD-ONLY1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // SIMD-ONLY1: for.end: -// SIMD-ONLY1-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// SIMD-ONLY1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// SIMD-ONLY1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// SIMD-ONLY1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// SIMD-ONLY1-NEXT: store i32 0, ptr [[RETVAL]], align 4 +// SIMD-ONLY1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] +// SIMD-ONLY1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// SIMD-ONLY1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // SIMD-ONLY1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // SIMD-ONLY1: arraydestroy.body: -// SIMD-ONLY1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP6]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// SIMD-ONLY1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// SIMD-ONLY1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// SIMD-ONLY1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// SIMD-ONLY1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP3]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// SIMD-ONLY1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// SIMD-ONLY1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// SIMD-ONLY1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // SIMD-ONLY1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // SIMD-ONLY1: arraydestroy.done2: -// SIMD-ONLY1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// SIMD-ONLY1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TTT]]) #[[ATTR4]] -// SIMD-ONLY1-NEXT: [[TMP7:%.*]] = load i32, i32* [[RETVAL]], align 4 -// SIMD-ONLY1-NEXT: ret i32 [[TMP7]] +// SIMD-ONLY1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// SIMD-ONLY1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TTT]]) #[[ATTR4]] +// SIMD-ONLY1-NEXT: [[TMP4:%.*]] = load i32, ptr [[RETVAL]], align 4 +// SIMD-ONLY1-NEXT: ret i32 [[TMP4]] // // // SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIdED1Ev -// SIMD-ONLY1-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY1-NEXT: entry: -// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// SIMD-ONLY1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// SIMD-ONLY1-NEXT: call void @_ZN1SIdED2Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS1]]) #[[ATTR4]] +// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// SIMD-ONLY1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY1-NEXT: call void @_ZN1SIdED2Ev(ptr noundef nonnull align 8 dereferenceable(8) [[THIS1]]) #[[ATTR4]] // SIMD-ONLY1-NEXT: ret void // // // SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIdEC2Ev -// SIMD-ONLY1-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY1-NEXT: entry: -// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// SIMD-ONLY1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// SIMD-ONLY1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// SIMD-ONLY1-NEXT: store double 0.000000e+00, double* [[F]], align 8 +// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// SIMD-ONLY1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 +// SIMD-ONLY1-NEXT: store double 0.000000e+00, ptr [[F]], align 8 // SIMD-ONLY1-NEXT: ret void // // // SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIdED2Ev -// SIMD-ONLY1-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY1-NEXT: entry: -// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// SIMD-ONLY1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// SIMD-ONLY1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // SIMD-ONLY1-NEXT: ret void // // // SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIdEC2ERKS0_d -// SIMD-ONLY1-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[S:%.*]], double noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[S:%.*]], double noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY1-NEXT: entry: -// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// SIMD-ONLY1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 +// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// SIMD-ONLY1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY1-NEXT: [[T_ADDR:%.*]] = alloca double, align 8 -// SIMD-ONLY1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// SIMD-ONLY1-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 -// SIMD-ONLY1-NEXT: store double [[T]], double* [[T_ADDR]], align 8 -// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// SIMD-ONLY1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 -// SIMD-ONLY1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0 -// SIMD-ONLY1-NEXT: [[TMP1:%.*]] = load double, double* [[F2]], align 8 -// SIMD-ONLY1-NEXT: [[TMP2:%.*]] = load double, double* [[T_ADDR]], align 8 +// SIMD-ONLY1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 +// SIMD-ONLY1-NEXT: store double [[T]], ptr [[T_ADDR]], align 8 +// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 +// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 +// SIMD-ONLY1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0 +// SIMD-ONLY1-NEXT: [[TMP1:%.*]] = load double, ptr [[F2]], align 8 +// SIMD-ONLY1-NEXT: [[TMP2:%.*]] = load double, ptr [[T_ADDR]], align 8 // SIMD-ONLY1-NEXT: [[ADD:%.*]] = fadd double [[TMP1]], [[TMP2]] -// SIMD-ONLY1-NEXT: store double [[ADD]], double* [[F]], align 8 +// SIMD-ONLY1-NEXT: store double [[ADD]], ptr [[F]], align 8 // SIMD-ONLY1-NEXT: ret void // // // SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIdEC2Ed -// SIMD-ONLY1-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], double noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], double noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY1-NEXT: entry: -// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY1-NEXT: [[A_ADDR:%.*]] = alloca double, align 8 -// SIMD-ONLY1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// SIMD-ONLY1-NEXT: store double [[A]], double* [[A_ADDR]], align 8 -// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// SIMD-ONLY1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load double, double* [[A_ADDR]], align 8 -// SIMD-ONLY1-NEXT: store double [[TMP0]], double* [[F]], align 8 +// SIMD-ONLY1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY1-NEXT: store double [[A]], ptr [[A_ADDR]], align 8 +// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 +// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load double, ptr [[A_ADDR]], align 8 +// SIMD-ONLY1-NEXT: store double [[TMP0]], ptr [[F]], align 8 // SIMD-ONLY1-NEXT: ret void // // // SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// SIMD-ONLY1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY1-NEXT: entry: -// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// SIMD-ONLY1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// SIMD-ONLY1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) +// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// SIMD-ONLY1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY1-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // SIMD-ONLY1-NEXT: ret void // // // SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_i -// SIMD-ONLY1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], i32 noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], i32 noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY1-NEXT: entry: -// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// SIMD-ONLY1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// SIMD-ONLY1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY1-NEXT: [[T_ADDR:%.*]] = alloca i32, align 4 -// SIMD-ONLY1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// SIMD-ONLY1-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 -// SIMD-ONLY1-NEXT: store i32 [[T]], i32* [[T_ADDR]], align 4 -// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 -// SIMD-ONLY1-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_ADDR]], align 4 -// SIMD-ONLY1-NEXT: call void @_ZN1SIiEC2ERKS0_i(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], i32 noundef [[TMP1]]) +// SIMD-ONLY1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 +// SIMD-ONLY1-NEXT: store i32 [[T]], ptr [[T_ADDR]], align 4 +// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 +// SIMD-ONLY1-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_ADDR]], align 4 +// SIMD-ONLY1-NEXT: call void @_ZN1SIiEC2ERKS0_i(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], i32 noundef [[TMP1]]) // SIMD-ONLY1-NEXT: ret void // // // SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// SIMD-ONLY1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY1-NEXT: entry: -// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// SIMD-ONLY1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// SIMD-ONLY1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// SIMD-ONLY1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]) +// SIMD-ONLY1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 +// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 +// SIMD-ONLY1-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]) // SIMD-ONLY1-NEXT: ret void // // // SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// SIMD-ONLY1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY1-NEXT: entry: -// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// SIMD-ONLY1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// SIMD-ONLY1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// SIMD-ONLY1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // SIMD-ONLY1-NEXT: ret void // // // SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// SIMD-ONLY1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY1-NEXT: entry: -// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// SIMD-ONLY1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// SIMD-ONLY1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// SIMD-ONLY1-NEXT: store i32 0, i32* [[F]], align 4 +// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// SIMD-ONLY1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 +// SIMD-ONLY1-NEXT: store i32 0, ptr [[F]], align 4 // SIMD-ONLY1-NEXT: ret void // // // SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_i -// SIMD-ONLY1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], i32 noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], i32 noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY1-NEXT: entry: -// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// SIMD-ONLY1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// SIMD-ONLY1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY1-NEXT: [[T_ADDR:%.*]] = alloca i32, align 4 -// SIMD-ONLY1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// SIMD-ONLY1-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 -// SIMD-ONLY1-NEXT: store i32 [[T]], i32* [[T_ADDR]], align 4 -// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// SIMD-ONLY1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 -// SIMD-ONLY1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0 -// SIMD-ONLY1-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4 -// SIMD-ONLY1-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_ADDR]], align 4 +// SIMD-ONLY1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 +// SIMD-ONLY1-NEXT: store i32 [[T]], ptr [[T_ADDR]], align 4 +// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 +// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 +// SIMD-ONLY1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0 +// SIMD-ONLY1-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4 +// SIMD-ONLY1-NEXT: [[TMP2:%.*]] = load i32, ptr [[T_ADDR]], align 4 // SIMD-ONLY1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] -// SIMD-ONLY1-NEXT: store i32 [[ADD]], i32* [[F]], align 4 +// SIMD-ONLY1-NEXT: store i32 [[ADD]], ptr [[F]], align 4 // SIMD-ONLY1-NEXT: ret void // // // SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// SIMD-ONLY1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY1-NEXT: entry: -// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// SIMD-ONLY1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// SIMD-ONLY1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// SIMD-ONLY1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// SIMD-ONLY1-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 +// SIMD-ONLY1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 +// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 +// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 +// SIMD-ONLY1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // SIMD-ONLY1-NEXT: ret void // // // SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// SIMD-ONLY1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY1-NEXT: entry: -// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// SIMD-ONLY1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// SIMD-ONLY1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // SIMD-ONLY1-NEXT: ret void // // @@ -2233,8 +2154,8 @@ void array_func(int n, float a[n], St s[2]) { // SIMD-ONLY2-NEXT: entry: // SIMD-ONLY2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // SIMD-ONLY2-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// SIMD-ONLY2-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// SIMD-ONLY2-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef nonnull align 1 dereferenceable(1) [[REF_TMP]]) +// SIMD-ONLY2-NEXT: store i32 0, ptr [[RETVAL]], align 4 +// SIMD-ONLY2-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]]) // SIMD-ONLY2-NEXT: ret i32 0 // // @@ -2242,104 +2163,97 @@ void array_func(int n, float a[n], St s[2]) { // SIMD-ONLY3-SAME: () #[[ATTR1:[0-9]+]] { // SIMD-ONLY3-NEXT: entry: // SIMD-ONLY3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// SIMD-ONLY3-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// SIMD-ONLY3-NEXT: [[TMP0:%.*]] = load i8*, i8** getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to %struct.__block_literal_generic*), i32 0, i32 3), align 8 -// SIMD-ONLY3-NEXT: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to void (i8*)* -// SIMD-ONLY3-NEXT: call void [[TMP1]](i8* noundef bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to i8*)) +// SIMD-ONLY3-NEXT: store i32 0, ptr [[RETVAL]], align 4 +// SIMD-ONLY3-NEXT: [[TMP0:%.*]] = load ptr, ptr getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr @__block_literal_global, i32 0, i32 3), align 8 +// SIMD-ONLY3-NEXT: call void [[TMP0]](ptr noundef @__block_literal_global) // SIMD-ONLY3-NEXT: ret i32 0 // // // SIMD-ONLY3-LABEL: define {{[^@]+}}@__main_block_invoke -// SIMD-ONLY3-SAME: (i8* noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] { +// SIMD-ONLY3-SAME: (ptr noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] { // SIMD-ONLY3-NEXT: entry: -// SIMD-ONLY3-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// SIMD-ONLY3-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*, align 8 +// SIMD-ONLY3-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 8 +// SIMD-ONLY3-NEXT: [[BLOCK_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY3-NEXT: [[I:%.*]] = alloca i32, align 4 -// SIMD-ONLY3-NEXT: [[BLOCK1:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, align 8 -// SIMD-ONLY3-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// SIMD-ONLY3-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* -// SIMD-ONLY3-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>** [[BLOCK_ADDR]], align 8 -// SIMD-ONLY3-NEXT: store i32 0, i32* [[I]], align 4 +// SIMD-ONLY3-NEXT: [[BLOCK:%.*]] = alloca <{ ptr, i32, i32, ptr, ptr, double, i32 }>, align 8 +// SIMD-ONLY3-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 +// SIMD-ONLY3-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 8 +// SIMD-ONLY3-NEXT: store i32 0, ptr [[I]], align 4 // SIMD-ONLY3-NEXT: br label [[FOR_COND:%.*]] // SIMD-ONLY3: for.cond: -// SIMD-ONLY3-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 +// SIMD-ONLY3-NEXT: [[TMP0:%.*]] = load i32, ptr [[I]], align 4 // SIMD-ONLY3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 // SIMD-ONLY3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] // SIMD-ONLY3: for.body: -// SIMD-ONLY3-NEXT: store double 1.000000e+00, double* @g, align 8 -// SIMD-ONLY3-NEXT: store i32 11, i32* @_ZZ4mainE5sivar, align 4 -// SIMD-ONLY3-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK1]], i32 0, i32 0 -// SIMD-ONLY3-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 -// SIMD-ONLY3-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK1]], i32 0, i32 1 -// SIMD-ONLY3-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 -// SIMD-ONLY3-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK1]], i32 0, i32 2 -// SIMD-ONLY3-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 -// SIMD-ONLY3-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK1]], i32 0, i32 3 -// SIMD-ONLY3-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke_2 to i8*), i8** [[BLOCK_INVOKE]], align 8 -// SIMD-ONLY3-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK1]], i32 0, i32 4 -// SIMD-ONLY3-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.1 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 -// SIMD-ONLY3-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK1]], i32 0, i32 5 -// SIMD-ONLY3-NEXT: [[TMP1:%.*]] = load volatile double, double* @g, align 8 -// SIMD-ONLY3-NEXT: store volatile double [[TMP1]], double* [[BLOCK_CAPTURED]], align 8 -// SIMD-ONLY3-NEXT: [[BLOCK_CAPTURED2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK1]], i32 0, i32 6 -// SIMD-ONLY3-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// SIMD-ONLY3-NEXT: store i32 [[TMP2]], i32* [[BLOCK_CAPTURED2]], align 8 -// SIMD-ONLY3-NEXT: [[TMP3:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK1]] to void ()* -// SIMD-ONLY3-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP3]] to %struct.__block_literal_generic* -// SIMD-ONLY3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// SIMD-ONLY3-NEXT: [[TMP5:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// SIMD-ONLY3-NEXT: [[TMP6:%.*]] = load i8*, i8** [[TMP4]], align 8 -// SIMD-ONLY3-NEXT: [[TMP7:%.*]] = bitcast i8* [[TMP6]] to void (i8*)* -// SIMD-ONLY3-NEXT: call void [[TMP7]](i8* noundef [[TMP5]]) +// SIMD-ONLY3-NEXT: store double 1.000000e+00, ptr @g, align 8 +// SIMD-ONLY3-NEXT: store i32 11, ptr @_ZZ4mainE5sivar, align 4 +// SIMD-ONLY3-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK]], i32 0, i32 0 +// SIMD-ONLY3-NEXT: store ptr @_NSConcreteStackBlock, ptr [[BLOCK_ISA]], align 8 +// SIMD-ONLY3-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK]], i32 0, i32 1 +// SIMD-ONLY3-NEXT: store i32 1073741824, ptr [[BLOCK_FLAGS]], align 8 +// SIMD-ONLY3-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK]], i32 0, i32 2 +// SIMD-ONLY3-NEXT: store i32 0, ptr [[BLOCK_RESERVED]], align 4 +// SIMD-ONLY3-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK]], i32 0, i32 3 +// SIMD-ONLY3-NEXT: store ptr @__main_block_invoke_2, ptr [[BLOCK_INVOKE]], align 8 +// SIMD-ONLY3-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK]], i32 0, i32 4 +// SIMD-ONLY3-NEXT: store ptr @__block_descriptor_tmp.1, ptr [[BLOCK_DESCRIPTOR]], align 8 +// SIMD-ONLY3-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK]], i32 0, i32 5 +// SIMD-ONLY3-NEXT: [[TMP1:%.*]] = load volatile double, ptr @g, align 8 +// SIMD-ONLY3-NEXT: store volatile double [[TMP1]], ptr [[BLOCK_CAPTURED]], align 8 +// SIMD-ONLY3-NEXT: [[BLOCK_CAPTURED1:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK]], i32 0, i32 6 +// SIMD-ONLY3-NEXT: [[TMP2:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4 +// SIMD-ONLY3-NEXT: store i32 [[TMP2]], ptr [[BLOCK_CAPTURED1]], align 8 +// SIMD-ONLY3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr [[BLOCK]], i32 0, i32 3 +// SIMD-ONLY3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 8 +// SIMD-ONLY3-NEXT: call void [[TMP4]](ptr noundef [[BLOCK]]) // SIMD-ONLY3-NEXT: br label [[FOR_INC:%.*]] // SIMD-ONLY3: for.inc: -// SIMD-ONLY3-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 -// SIMD-ONLY3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 -// SIMD-ONLY3-NEXT: store i32 [[INC]], i32* [[I]], align 4 +// SIMD-ONLY3-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4 +// SIMD-ONLY3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 +// SIMD-ONLY3-NEXT: store i32 [[INC]], ptr [[I]], align 4 // SIMD-ONLY3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] // SIMD-ONLY3: for.end: // SIMD-ONLY3-NEXT: ret void // // // SIMD-ONLY3-LABEL: define {{[^@]+}}@__main_block_invoke_2 -// SIMD-ONLY3-SAME: (i8* noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { +// SIMD-ONLY3-SAME: (ptr noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { // SIMD-ONLY3-NEXT: entry: -// SIMD-ONLY3-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// SIMD-ONLY3-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>*, align 8 -// SIMD-ONLY3-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// SIMD-ONLY3-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* -// SIMD-ONLY3-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>** [[BLOCK_ADDR]], align 8 -// SIMD-ONLY3-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK]], i32 0, i32 5 -// SIMD-ONLY3-NEXT: store double 2.000000e+00, double* [[BLOCK_CAPTURE_ADDR]], align 8 -// SIMD-ONLY3-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK]], i32 0, i32 6 -// SIMD-ONLY3-NEXT: store i32 22, i32* [[BLOCK_CAPTURE_ADDR1]], align 8 +// SIMD-ONLY3-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 8 +// SIMD-ONLY3-NEXT: [[BLOCK_ADDR:%.*]] = alloca ptr, align 8 +// SIMD-ONLY3-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 +// SIMD-ONLY3-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 8 +// SIMD-ONLY3-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 5 +// SIMD-ONLY3-NEXT: store double 2.000000e+00, ptr [[BLOCK_CAPTURE_ADDR]], align 8 +// SIMD-ONLY3-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 6 +// SIMD-ONLY3-NEXT: store i32 22, ptr [[BLOCK_CAPTURE_ADDR1]], align 8 // SIMD-ONLY3-NEXT: ret void // // // SIMD-ONLY4-LABEL: define {{[^@]+}}@_Z10array_funciPfP2St -// SIMD-ONLY4-SAME: (i32 noundef [[N:%.*]], float* noundef [[A:%.*]], %struct.St* noundef [[S:%.*]]) #[[ATTR0:[0-9]+]] { +// SIMD-ONLY4-SAME: (i32 noundef [[N:%.*]], ptr noundef [[A:%.*]], ptr noundef [[S:%.*]]) #[[ATTR0:[0-9]+]] { // SIMD-ONLY4-NEXT: entry: // SIMD-ONLY4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// SIMD-ONLY4-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// SIMD-ONLY4-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 +// SIMD-ONLY4-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 +// SIMD-ONLY4-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY4-NEXT: [[I:%.*]] = alloca i32, align 4 -// SIMD-ONLY4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// SIMD-ONLY4-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// SIMD-ONLY4-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 -// SIMD-ONLY4-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// SIMD-ONLY4-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// SIMD-ONLY4-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 +// SIMD-ONLY4-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 +// SIMD-ONLY4-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY4-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// SIMD-ONLY4-NEXT: store i32 0, i32* [[I]], align 4 +// SIMD-ONLY4-NEXT: store i32 0, ptr [[I]], align 4 // SIMD-ONLY4-NEXT: br label [[FOR_COND:%.*]] // SIMD-ONLY4: for.cond: -// SIMD-ONLY4-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 +// SIMD-ONLY4-NEXT: [[TMP2:%.*]] = load i32, ptr [[I]], align 4 // SIMD-ONLY4-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], 10 // SIMD-ONLY4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] // SIMD-ONLY4: for.body: // SIMD-ONLY4-NEXT: br label [[FOR_INC:%.*]] // SIMD-ONLY4: for.inc: -// SIMD-ONLY4-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 +// SIMD-ONLY4-NEXT: [[TMP3:%.*]] = load i32, ptr [[I]], align 4 // SIMD-ONLY4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1 -// SIMD-ONLY4-NEXT: store i32 [[INC]], i32* [[I]], align 4 +// SIMD-ONLY4-NEXT: store i32 [[INC]], ptr [[I]], align 4 // SIMD-ONLY4-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] // SIMD-ONLY4: for.end: // SIMD-ONLY4-NEXT: ret void diff --git a/clang/test/OpenMP/parallel_master_taskloop_simd_firstprivate_codegen.cpp b/clang/test/OpenMP/parallel_master_taskloop_simd_firstprivate_codegen.cpp index 9a426cb2e24bc9..b938758b051a26 100644 --- a/clang/test/OpenMP/parallel_master_taskloop_simd_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/parallel_master_taskloop_simd_firstprivate_codegen.cpp @@ -1,17 +1,17 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ -// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=LAMBDA %s -// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=BLOCKS %s -// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=ARRAY %s +// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s +// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=LAMBDA %s +// RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=BLOCKS %s +// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=ARRAY %s -// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s -// RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s -// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY2 %s -// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY3 %s -// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY4 %s +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY2 %s +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY3 %s +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY4 %s // expected-no-diagnostics #ifndef ARRAY @@ -201,376 +201,356 @@ void array_func(int n, float a[n], St s[2]) { // CHECK-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 16 // CHECK-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 8 // CHECK-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[TTT]]) -// CHECK-NEXT: call void @_ZN1SIdEC1ERKS0_d(%struct.S* noundef nonnull align 8 dereferenceable(8) [[TEST]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[TTT]], double noundef 0.000000e+00) -// CHECK-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// CHECK-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// CHECK-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// CHECK-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* noundef nonnull align 8 dereferenceable(8) [[ARRAYINIT_BEGIN]], double noundef 1.000000e+00) -// CHECK-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* noundef nonnull align 8 dereferenceable(8) [[ARRAYINIT_ELEMENT]], double noundef 2.000000e+00) -// CHECK-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* noundef nonnull align 8 dereferenceable(8) [[VAR]], double noundef 3.000000e+00) -// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 -// CHECK-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4 -// CHECK-NEXT: [[TMP2:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 -// CHECK-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*)* @main.omp_outlined to void (i32*, i32*, ...)*), [2 x i32]* [[VEC]], i64 [[TMP2]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[VAR]]) +// CHECK-NEXT: store i32 0, ptr [[RETVAL]], align 4 +// CHECK-NEXT: call void @_ZN1SIdEC1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[TTT]]) +// CHECK-NEXT: call void @_ZN1SIdEC1ERKS0_d(ptr noundef nonnull align 8 dereferenceable(8) [[TEST]], ptr noundef nonnull align 8 dereferenceable(8) [[TTT]], double noundef 0.000000e+00) +// CHECK-NEXT: store i32 0, ptr [[T_VAR]], align 4 +// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const.main.vec, i64 8, i1 false) +// CHECK-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 0 +// CHECK-NEXT: call void @_ZN1SIdEC1Ed(ptr noundef nonnull align 8 dereferenceable(8) [[ARRAYINIT_BEGIN]], double noundef 1.000000e+00) +// CHECK-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYINIT_BEGIN]], i64 1 +// CHECK-NEXT: call void @_ZN1SIdEC1Ed(ptr noundef nonnull align 8 dereferenceable(8) [[ARRAYINIT_ELEMENT]], double noundef 2.000000e+00) +// CHECK-NEXT: call void @_ZN1SIdEC1Ed(ptr noundef nonnull align 8 dereferenceable(8) [[VAR]], double noundef 3.000000e+00) +// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[T_VAR]], align 4 +// CHECK-NEXT: store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 +// CHECK-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 4, ptr @main.omp_outlined, ptr [[VEC]], i64 [[TMP1]], ptr [[S_ARR]], ptr [[VAR]]) // CHECK-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() -// CHECK-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// CHECK-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[VAR]]) #[[ATTR4:[0-9]+]] -// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 +// CHECK-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[VAR]]) #[[ATTR4:[0-9]+]] +// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK: arraydestroy.body: -// CHECK-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP3]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK: arraydestroy.done1: -// CHECK-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[TEST]]) #[[ATTR4]] -// CHECK-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[TTT]]) #[[ATTR4]] -// CHECK-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK-NEXT: ret i32 [[TMP4]] +// CHECK-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[TEST]]) #[[ATTR4]] +// CHECK-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[TTT]]) #[[ATTR4]] +// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[RETVAL]], align 4 +// CHECK-NEXT: ret i32 [[TMP3]] // // // CHECK-LABEL: define {{[^@]+}}@_ZN1SIdEC1Ev -// CHECK-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { +// CHECK-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { // CHECK-NEXT: entry: -// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK-NEXT: call void @_ZN1SIdEC2Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS1]]) +// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// CHECK-NEXT: call void @_ZN1SIdEC2Ev(ptr noundef nonnull align 8 dereferenceable(8) [[THIS1]]) // CHECK-NEXT: ret void // // // CHECK-LABEL: define {{[^@]+}}@_ZN1SIdEC1ERKS0_d -// CHECK-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[S:%.*]], double noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[S:%.*]], double noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK-NEXT: entry: -// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[T_ADDR:%.*]] = alloca double, align 8 -// CHECK-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 -// CHECK-NEXT: store double [[T]], double* [[T_ADDR]], align 8 -// CHECK-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 -// CHECK-NEXT: [[TMP1:%.*]] = load double, double* [[T_ADDR]], align 8 -// CHECK-NEXT: call void @_ZN1SIdEC2ERKS0_d(%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS1]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[TMP0]], double noundef [[TMP1]]) +// CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// CHECK-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 +// CHECK-NEXT: store double [[T]], ptr [[T_ADDR]], align 8 +// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 +// CHECK-NEXT: [[TMP1:%.*]] = load double, ptr [[T_ADDR]], align 8 +// CHECK-NEXT: call void @_ZN1SIdEC2ERKS0_d(ptr noundef nonnull align 8 dereferenceable(8) [[THIS1]], ptr noundef nonnull align 8 dereferenceable(8) [[TMP0]], double noundef [[TMP1]]) // CHECK-NEXT: ret void // // // CHECK-LABEL: define {{[^@]+}}@_ZN1SIdEC1Ed -// CHECK-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], double noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], double noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK-NEXT: entry: -// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[A_ADDR:%.*]] = alloca double, align 8 -// CHECK-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK-NEXT: store double [[A]], double* [[A_ADDR]], align 8 -// CHECK-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK-NEXT: [[TMP0:%.*]] = load double, double* [[A_ADDR]], align 8 -// CHECK-NEXT: call void @_ZN1SIdEC2Ed(%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS1]], double noundef [[TMP0]]) +// CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// CHECK-NEXT: store double [[A]], ptr [[A_ADDR]], align 8 +// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load double, ptr [[A_ADDR]], align 8 +// CHECK-NEXT: call void @_ZN1SIdEC2Ed(ptr noundef nonnull align 8 dereferenceable(8) [[THIS1]], double noundef [[TMP0]]) // CHECK-NEXT: ret void // // // CHECK-LABEL: define {{[^@]+}}@main.omp_outlined -// CHECK-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 8 dereferenceable(16) [[S_ARR:%.*]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[VAR:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[S_ARR:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[VAR:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK-NEXT: entry: -// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 -// CHECK-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 8 // CHECK-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 -// CHECK-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 -// CHECK-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* -// CHECK-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 -// CHECK-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 -// CHECK-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) +// CHECK-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 +// CHECK-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 +// CHECK-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 +// CHECK-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 +// CHECK-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 +// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 +// CHECK-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB1]], i32 [[TMP4]]) // CHECK-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0 // CHECK-NEXT: br i1 [[TMP6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] // CHECK: omp_if.then: -// CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 -// CHECK-NEXT: store [2 x %struct.S]* [[TMP1]], [2 x %struct.S]** [[TMP7]], align 8 -// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 -// CHECK-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP8]], align 8 -// CHECK-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) -// CHECK-NEXT: [[TMP9:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]], i32 9, i64 120, i64 16, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*)) -// CHECK-NEXT: [[TMP10:%.*]] = bitcast i8* [[TMP9]] to %struct.kmp_task_t_with_privates* -// CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP10]], i32 0, i32 0 -// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP11]], i32 0, i32 0 -// CHECK-NEXT: [[TMP13:%.*]] = load i8*, i8** [[TMP12]], align 8 -// CHECK-NEXT: [[TMP14:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* -// CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP13]], i8* align 8 [[TMP14]], i64 16, i1 false) -// CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP10]], i32 0, i32 1 -// CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP15]], i32 0, i32 0 -// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP16]], i32 0, i32 0 -// CHECK-NEXT: [[TMP17:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* -// CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP18]] +// CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0 +// CHECK-NEXT: store ptr [[TMP1]], ptr [[TMP7]], align 8 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 1 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[TMP8]], align 8 +// CHECK-NEXT: call void @__kmpc_taskgroup(ptr @[[GLOB1]], i32 [[TMP4]]) +// CHECK-NEXT: [[TMP9:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP4]], i32 9, i64 120, i64 16, ptr @.omp_task_entry.) +// CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP9]], i32 0, i32 0 +// CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP10]], i32 0, i32 0 +// CHECK-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8 +// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP12]], ptr align 8 [[AGG_CAPTURED]], i64 16, i1 false) +// CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP9]], i32 0, i32 1 +// CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP13]], i32 0, i32 0 +// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP14]], i32 0, i32 0 +// CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP15]] // CHECK-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] // CHECK: omp.arraycpy.body: -// CHECK-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP17]], [[OMP_IF_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[OMP_IF_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK-NEXT: call void @_ZN1SIdEC1ERKS0_d(%struct.S* noundef nonnull align 8 dereferenceable(8) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[OMP_ARRAYCPY_SRCELEMENTPAST]], double noundef 0.000000e+00) -// CHECK-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP18]] +// CHECK-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[OMP_IF_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[OMP_IF_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK-NEXT: call void @_ZN1SIdEC1ERKS0_d(ptr noundef nonnull align 8 dereferenceable(8) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 8 dereferenceable(8) [[OMP_ARRAYCPY_SRCELEMENTPAST]], double noundef 0.000000e+00) +// CHECK-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP15]] // CHECK-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]] // CHECK: omp.arraycpy.done1: -// CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP15]], i32 0, i32 1 -// CHECK-NEXT: call void @_ZN1SIdEC1ERKS0_d(%struct.S* noundef nonnull align 8 dereferenceable(8) [[TMP19]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[TMP2]], double noundef 0.000000e+00) -// CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP15]], i32 0, i32 2 -// CHECK-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 4 -// CHECK-NEXT: store i32 [[TMP21]], i32* [[TMP20]], align 8 -// CHECK-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP15]], i32 0, i32 3 -// CHECK-NEXT: [[TMP23:%.*]] = bitcast [2 x i32]* [[TMP22]] to i8* -// CHECK-NEXT: [[TMP24:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP23]], i8* align 4 [[TMP24]], i64 8, i1 false) -// CHECK-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP15]], i32 0, i32 4 -// CHECK-NEXT: [[TMP26:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// CHECK-NEXT: store i32 [[TMP26]], i32* [[TMP25]], align 4 -// CHECK-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP11]], i32 0, i32 3 -// CHECK-NEXT: [[TMP28:%.*]] = bitcast %union.kmp_cmplrdata_t* [[TMP27]] to i32 (i32, i8*)** -// CHECK-NEXT: store i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_destructor. to i32 (i32, i8*)*), i32 (i32, i8*)** [[TMP28]], align 8 -// CHECK-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP11]], i32 0, i32 5 -// CHECK-NEXT: store i64 0, i64* [[TMP29]], align 8 -// CHECK-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP11]], i32 0, i32 6 -// CHECK-NEXT: store i64 9, i64* [[TMP30]], align 8 -// CHECK-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP11]], i32 0, i32 7 -// CHECK-NEXT: store i64 1, i64* [[TMP31]], align 8 -// CHECK-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP11]], i32 0, i32 9 -// CHECK-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i8* -// CHECK-NEXT: call void @llvm.memset.p0i8.i64(i8* align 8 [[TMP33]], i8 0, i64 8, i1 false) -// CHECK-NEXT: [[TMP34:%.*]] = load i64, i64* [[TMP31]], align 8 -// CHECK-NEXT: call void @__kmpc_taskloop(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]], i8* [[TMP9]], i32 1, i64* [[TMP29]], i64* [[TMP30]], i64 [[TMP34]], i32 1, i32 0, i64 0, i8* bitcast (void (%struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates*, i32)* @.omp_task_dup. to i8*)) -// CHECK-NEXT: call void @__kmpc_end_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) -// CHECK-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) +// CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP13]], i32 0, i32 1 +// CHECK-NEXT: call void @_ZN1SIdEC1ERKS0_d(ptr noundef nonnull align 8 dereferenceable(8) [[TMP16]], ptr noundef nonnull align 8 dereferenceable(8) [[TMP2]], double noundef 0.000000e+00) +// CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP13]], i32 0, i32 2 +// CHECK-NEXT: [[TMP18:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 +// CHECK-NEXT: store i32 [[TMP18]], ptr [[TMP17]], align 8 +// CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP13]], i32 0, i32 3 +// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP19]], ptr align 4 [[TMP0]], i64 8, i1 false) +// CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP13]], i32 0, i32 4 +// CHECK-NEXT: [[TMP21:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4 +// CHECK-NEXT: store i32 [[TMP21]], ptr [[TMP20]], align 4 +// CHECK-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP10]], i32 0, i32 3 +// CHECK-NEXT: store ptr @.omp_task_destructor., ptr [[TMP22]], align 8 +// CHECK-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP10]], i32 0, i32 5 +// CHECK-NEXT: store i64 0, ptr [[TMP23]], align 8 +// CHECK-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP10]], i32 0, i32 6 +// CHECK-NEXT: store i64 9, ptr [[TMP24]], align 8 +// CHECK-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP10]], i32 0, i32 7 +// CHECK-NEXT: store i64 1, ptr [[TMP25]], align 8 +// CHECK-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP10]], i32 0, i32 9 +// CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP26]], i8 0, i64 8, i1 false) +// CHECK-NEXT: [[TMP27:%.*]] = load i64, ptr [[TMP25]], align 8 +// CHECK-NEXT: call void @__kmpc_taskloop(ptr @[[GLOB1]], i32 [[TMP4]], ptr [[TMP9]], i32 1, ptr [[TMP23]], ptr [[TMP24]], i64 [[TMP27]], i32 1, i32 0, i64 0, ptr @.omp_task_dup.) +// CHECK-NEXT: call void @__kmpc_end_taskgroup(ptr @[[GLOB1]], i32 [[TMP4]]) +// CHECK-NEXT: call void @__kmpc_end_master(ptr @[[GLOB1]], i32 [[TMP4]]) // CHECK-NEXT: br label [[OMP_IF_END]] // CHECK: omp_if.end: // CHECK-NEXT: ret void // // // CHECK-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// CHECK-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], %struct.S** noalias noundef [[TMP1:%.*]], i32** noalias noundef [[TMP2:%.*]], [2 x %struct.S]** noalias noundef [[TMP3:%.*]], [2 x i32]** noalias noundef [[TMP4:%.*]], i32** noalias noundef [[TMP5:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]], ptr noalias noundef [[TMP3:%.*]], ptr noalias noundef [[TMP4:%.*]], ptr noalias noundef [[TMP5:%.*]]) #[[ATTR6:[0-9]+]] { // CHECK-NEXT: entry: -// CHECK-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 -// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca %struct.S**, align 8 -// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca i32**, align 8 -// CHECK-NEXT: [[DOTADDR3:%.*]] = alloca [2 x %struct.S]**, align 8 -// CHECK-NEXT: [[DOTADDR4:%.*]] = alloca [2 x i32]**, align 8 -// CHECK-NEXT: [[DOTADDR5:%.*]] = alloca i32**, align 8 -// CHECK-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8 -// CHECK-NEXT: store %struct.S** [[TMP1]], %struct.S*** [[DOTADDR1]], align 8 -// CHECK-NEXT: store i32** [[TMP2]], i32*** [[DOTADDR2]], align 8 -// CHECK-NEXT: store [2 x %struct.S]** [[TMP3]], [2 x %struct.S]*** [[DOTADDR3]], align 8 -// CHECK-NEXT: store [2 x i32]** [[TMP4]], [2 x i32]*** [[DOTADDR4]], align 8 -// CHECK-NEXT: store i32** [[TMP5]], i32*** [[DOTADDR5]], align 8 -// CHECK-NEXT: [[TMP6:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8 -// CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP6]], i32 0, i32 0 -// CHECK-NEXT: [[TMP8:%.*]] = load [2 x %struct.S]**, [2 x %struct.S]*** [[DOTADDR3]], align 8 -// CHECK-NEXT: store [2 x %struct.S]* [[TMP7]], [2 x %struct.S]** [[TMP8]], align 8 -// CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP6]], i32 0, i32 1 -// CHECK-NEXT: [[TMP10:%.*]] = load %struct.S**, %struct.S*** [[DOTADDR1]], align 8 -// CHECK-NEXT: store %struct.S* [[TMP9]], %struct.S** [[TMP10]], align 8 -// CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP6]], i32 0, i32 2 -// CHECK-NEXT: [[TMP12:%.*]] = load i32**, i32*** [[DOTADDR2]], align 8 -// CHECK-NEXT: store i32* [[TMP11]], i32** [[TMP12]], align 8 -// CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP6]], i32 0, i32 3 -// CHECK-NEXT: [[TMP14:%.*]] = load [2 x i32]**, [2 x i32]*** [[DOTADDR4]], align 8 -// CHECK-NEXT: store [2 x i32]* [[TMP13]], [2 x i32]** [[TMP14]], align 8 -// CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP6]], i32 0, i32 4 -// CHECK-NEXT: [[TMP16:%.*]] = load i32**, i32*** [[DOTADDR5]], align 8 -// CHECK-NEXT: store i32* [[TMP15]], i32** [[TMP16]], align 8 +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTADDR5:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 +// CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2]], align 8 +// CHECK-NEXT: store ptr [[TMP3]], ptr [[DOTADDR3]], align 8 +// CHECK-NEXT: store ptr [[TMP4]], ptr [[DOTADDR4]], align 8 +// CHECK-NEXT: store ptr [[TMP5]], ptr [[DOTADDR5]], align 8 +// CHECK-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTADDR]], align 8 +// CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP6]], i32 0, i32 0 +// CHECK-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTADDR3]], align 8 +// CHECK-NEXT: store ptr [[TMP7]], ptr [[TMP8]], align 8 +// CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP6]], i32 0, i32 1 +// CHECK-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 +// CHECK-NEXT: store ptr [[TMP9]], ptr [[TMP10]], align 8 +// CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP6]], i32 0, i32 2 +// CHECK-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTADDR2]], align 8 +// CHECK-NEXT: store ptr [[TMP11]], ptr [[TMP12]], align 8 +// CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP6]], i32 0, i32 3 +// CHECK-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTADDR4]], align 8 +// CHECK-NEXT: store ptr [[TMP13]], ptr [[TMP14]], align 8 +// CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP6]], i32 0, i32 4 +// CHECK-NEXT: [[TMP16:%.*]] = load ptr, ptr [[DOTADDR5]], align 8 +// CHECK-NEXT: store ptr [[TMP15]], ptr [[TMP16]], align 8 // CHECK-NEXT: ret void // // // CHECK-LABEL: define {{[^@]+}}@.omp_task_entry. -// CHECK-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { +// CHECK-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 -// CHECK-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 -// CHECK-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[DOTLB__ADDR_I:%.*]] = alloca i64, align 8 // CHECK-NEXT: [[DOTUB__ADDR_I:%.*]] = alloca i64, align 8 // CHECK-NEXT: [[DOTST__ADDR_I:%.*]] = alloca i64, align 8 // CHECK-NEXT: [[DOTLITER__ADDR_I:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 -// CHECK-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca %struct.S*, align 8 -// CHECK-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca i32*, align 8 -// CHECK-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [2 x %struct.S]*, align 8 -// CHECK-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [2 x i32]*, align 8 -// CHECK-NEXT: [[DOTFIRSTPRIV_PTR_ADDR4_I:%.*]] = alloca i32*, align 8 +// CHECK-NEXT: [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTFIRSTPRIV_PTR_ADDR4_I:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[I_I:%.*]] = alloca i32, align 4 // CHECK-NEXT: [[DOTOMP_IV_I:%.*]] = alloca i32, align 4 // CHECK-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 -// CHECK-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 -// CHECK-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 -// CHECK-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 -// CHECK-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 -// CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 -// CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 -// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 -// CHECK-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 -// CHECK-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* -// CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 -// CHECK-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* -// CHECK-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* -// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 5 -// CHECK-NEXT: [[TMP13:%.*]] = load i64, i64* [[TMP12]], align 8 -// CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 6 -// CHECK-NEXT: [[TMP15:%.*]] = load i64, i64* [[TMP14]], align 8 -// CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 7 -// CHECK-NEXT: [[TMP17:%.*]] = load i64, i64* [[TMP16]], align 8 -// CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 8 -// CHECK-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 8 -// CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 9 -// CHECK-NEXT: [[TMP21:%.*]] = load i8*, i8** [[TMP20]], align 8 +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 +// CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 1 +// CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 5 +// CHECK-NEXT: [[TMP10:%.*]] = load i64, ptr [[TMP9]], align 8 +// CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 6 +// CHECK-NEXT: [[TMP12:%.*]] = load i64, ptr [[TMP11]], align 8 +// CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 7 +// CHECK-NEXT: [[TMP14:%.*]] = load i64, ptr [[TMP13]], align 8 +// CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 8 +// CHECK-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 8 +// CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 9 +// CHECK-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8 // CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]]) // CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]]) // CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]]) // CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]]) // CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]]) -// CHECK-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14 -// CHECK-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !14 -// CHECK-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14 -// CHECK-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, %struct.S**, i32**, [2 x %struct.S]**, [2 x i32]**, i32**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14 -// CHECK-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !14 -// CHECK-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !14 -// CHECK-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !14 -// CHECK-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !14 -// CHECK-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !14 -// CHECK-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !14 -// CHECK-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14 -// CHECK-NEXT: [[TMP22:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14 -// CHECK-NEXT: [[TMP23:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14 -// CHECK-NEXT: [[TMP24:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14 -// CHECK-NEXT: [[TMP25:%.*]] = bitcast void (i8*, ...)* [[TMP23]] to void (i8*, %struct.S**, i32**, [2 x %struct.S]**, [2 x i32]**, i32**)* -// CHECK-NEXT: call void [[TMP25]](i8* [[TMP24]], %struct.S** [[DOTFIRSTPRIV_PTR_ADDR_I]], i32** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [2 x %struct.S]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [2 x i32]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], i32** [[DOTFIRSTPRIV_PTR_ADDR4_I]]) #[[ATTR4]] -// CHECK-NEXT: [[TMP26:%.*]] = load %struct.S*, %struct.S** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !14 -// CHECK-NEXT: [[TMP27:%.*]] = load i32*, i32** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !14 -// CHECK-NEXT: [[TMP28:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !14 -// CHECK-NEXT: [[TMP29:%.*]] = load [2 x i32]*, [2 x i32]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !14 -// CHECK-NEXT: [[TMP30:%.*]] = load i32*, i32** [[DOTFIRSTPRIV_PTR_ADDR4_I]], align 8, !noalias !14 -// CHECK-NEXT: [[TMP31:%.*]] = load i64, i64* [[DOTLB__ADDR_I]], align 8, !noalias !14 -// CHECK-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP31]] to i32 -// CHECK-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14 +// CHECK-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14 +// CHECK-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias !14 +// CHECK-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14 +// CHECK-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14 +// CHECK-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias !14 +// CHECK-NEXT: store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias !14 +// CHECK-NEXT: store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias !14 +// CHECK-NEXT: store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias !14 +// CHECK-NEXT: store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias !14 +// CHECK-NEXT: store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !14 +// CHECK-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias !14 +// CHECK-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias !14 +// CHECK-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14 +// CHECK-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14 +// CHECK-NEXT: call void [[TMP20]](ptr [[TMP21]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR4_I]]) #[[ATTR4]] +// CHECK-NEXT: [[TMP22:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !14 +// CHECK-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !14 +// CHECK-NEXT: [[TMP24:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !14 +// CHECK-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !14 +// CHECK-NEXT: [[TMP26:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR4_I]], align 8, !noalias !14 +// CHECK-NEXT: [[TMP27:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias !14 +// CHECK-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP27]] to i32 +// CHECK-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias !14 // CHECK-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]] // CHECK: omp.inner.for.cond.i: -// CHECK-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group [[ACC_GRP15:![0-9]+]] -// CHECK-NEXT: [[CONV5_I:%.*]] = sext i32 [[TMP32]] to i64 -// CHECK-NEXT: [[TMP33:%.*]] = load i64, i64* [[DOTUB__ADDR_I]], align 8, !noalias !14, !llvm.access.group [[ACC_GRP15]] -// CHECK-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV5_I]], [[TMP33]] +// CHECK-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group [[ACC_GRP15:![0-9]+]] +// CHECK-NEXT: [[CONV5_I:%.*]] = sext i32 [[TMP28]] to i64 +// CHECK-NEXT: [[TMP29:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias !14, !llvm.access.group [[ACC_GRP15]] +// CHECK-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV5_I]], [[TMP29]] // CHECK-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]] // CHECK: omp.inner.for.body.i: -// CHECK-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group [[ACC_GRP15]] -// CHECK-NEXT: store i32 [[TMP34]], i32* [[I_I]], align 4, !noalias !14, !llvm.access.group [[ACC_GRP15]] -// CHECK-NEXT: [[TMP35:%.*]] = load i32, i32* [[TMP27]], align 4, !llvm.access.group [[ACC_GRP15]] -// CHECK-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[TMP29]], i64 0, i64 0 -// CHECK-NEXT: store i32 [[TMP35]], i32* [[ARRAYIDX_I]], align 4, !llvm.access.group [[ACC_GRP15]] -// CHECK-NEXT: [[ARRAYIDX6_I:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP28]], i64 0, i64 0 -// CHECK-NEXT: [[TMP36:%.*]] = bitcast %struct.S* [[ARRAYIDX6_I]] to i8* -// CHECK-NEXT: [[TMP37:%.*]] = bitcast %struct.S* [[TMP26]] to i8* -// CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP36]], i8* align 8 [[TMP37]], i64 8, i1 false), !llvm.access.group [[ACC_GRP15]] -// CHECK-NEXT: store i32 33, i32* [[TMP30]], align 4, !llvm.access.group [[ACC_GRP15]] -// CHECK-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group [[ACC_GRP15]] -// CHECK-NEXT: [[ADD7_I:%.*]] = add nsw i32 [[TMP38]], 1 -// CHECK-NEXT: store i32 [[ADD7_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group [[ACC_GRP15]] +// CHECK-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group [[ACC_GRP15]] +// CHECK-NEXT: store i32 [[TMP30]], ptr [[I_I]], align 4, !noalias !14, !llvm.access.group [[ACC_GRP15]] +// CHECK-NEXT: [[TMP31:%.*]] = load i32, ptr [[TMP23]], align 4, !llvm.access.group [[ACC_GRP15]] +// CHECK-NEXT: store i32 [[TMP31]], ptr [[TMP25]], align 4, !llvm.access.group [[ACC_GRP15]] +// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 16 [[TMP24]], ptr align 8 [[TMP22]], i64 8, i1 false), !llvm.access.group [[ACC_GRP15]] +// CHECK-NEXT: store i32 33, ptr [[TMP26]], align 4, !llvm.access.group [[ACC_GRP15]] +// CHECK-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group [[ACC_GRP15]] +// CHECK-NEXT: [[ADD7_I:%.*]] = add nsw i32 [[TMP32]], 1 +// CHECK-NEXT: store i32 [[ADD7_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group [[ACC_GRP15]] // CHECK-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP16:![0-9]+]] // CHECK: .omp_outlined..exit: // CHECK-NEXT: ret i32 0 // // // CHECK-LABEL: define {{[^@]+}}@.omp_task_dup. -// CHECK-SAME: (%struct.kmp_task_t_with_privates* noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noundef [[TMP1:%.*]], i32 noundef [[TMP2:%.*]]) #[[ATTR7]] { +// CHECK-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], i32 noundef [[TMP2:%.*]]) #[[ATTR7]] { // CHECK-NEXT: entry: -// CHECK-NEXT: [[DOTADDR:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 -// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[DOTADDR2:%.*]] = alloca i32, align 4 -// CHECK-NEXT: store %struct.kmp_task_t_with_privates* [[TMP0]], %struct.kmp_task_t_with_privates** [[DOTADDR]], align 8 -// CHECK-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 -// CHECK-NEXT: store i32 [[TMP2]], i32* [[DOTADDR2]], align 4 -// CHECK-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR]], align 8 -// CHECK-NEXT: [[TMP4:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 -// CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP4]], i32 0, i32 0 -// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP5]], i32 0, i32 0 -// CHECK-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 -// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 -// CHECK-NEXT: [[TMP9:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* -// CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP8]], i32 0, i32 0 -// CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP9]], i32 0, i32 0 -// CHECK-NEXT: [[TMP12:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[TMP11]], align 8 -// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP10]], i32 0, i32 0 -// CHECK-NEXT: [[TMP13:%.*]] = bitcast [2 x %struct.S]* [[TMP12]] to %struct.S* -// CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAY_BEGIN]], i64 2 -// CHECK-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP14]] +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 +// CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK-NEXT: store i32 [[TMP2]], ptr [[DOTADDR2]], align 4 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 +// CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP4]], i32 0, i32 0 +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP5]], i32 0, i32 0 +// CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 1 +// CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP8]], i32 0, i32 0 +// CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP7]], i32 0, i32 0 +// CHECK-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP10]], align 8 +// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP9]], i32 0, i32 0 +// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP12]] // CHECK-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] // CHECK: omp.arraycpy.body: -// CHECK-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK-NEXT: call void @_ZN1SIdEC1ERKS0_d(%struct.S* noundef nonnull align 8 dereferenceable(8) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[OMP_ARRAYCPY_SRCELEMENTPAST]], double noundef 0.000000e+00) -// CHECK-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP14]] +// CHECK-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP11]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK-NEXT: call void @_ZN1SIdEC1ERKS0_d(ptr noundef nonnull align 8 dereferenceable(8) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 8 dereferenceable(8) [[OMP_ARRAYCPY_SRCELEMENTPAST]], double noundef 0.000000e+00) +// CHECK-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP12]] // CHECK-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] // CHECK: omp.arraycpy.done3: -// CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP8]], i32 0, i32 1 -// CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP9]], i32 0, i32 1 -// CHECK-NEXT: [[TMP17:%.*]] = load %struct.S*, %struct.S** [[TMP16]], align 8 -// CHECK-NEXT: call void @_ZN1SIdEC1ERKS0_d(%struct.S* noundef nonnull align 8 dereferenceable(8) [[TMP15]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[TMP17]], double noundef 0.000000e+00) +// CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP8]], i32 0, i32 1 +// CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP7]], i32 0, i32 1 +// CHECK-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP14]], align 8 +// CHECK-NEXT: call void @_ZN1SIdEC1ERKS0_d(ptr noundef nonnull align 8 dereferenceable(8) [[TMP13]], ptr noundef nonnull align 8 dereferenceable(8) [[TMP15]], double noundef 0.000000e+00) // CHECK-NEXT: ret void // // // CHECK-LABEL: define {{[^@]+}}@.omp_task_destructor. -// CHECK-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR7]] { +// CHECK-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR7]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 -// CHECK-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 -// CHECK-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 -// CHECK-NEXT: [[TMP2:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 -// CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP2]], i32 0, i32 1 -// CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP3]], i32 0, i32 0 -// CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP3]], i32 0, i32 1 -// CHECK-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[TMP5]]) #[[ATTR4]] -// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP4]], i32 0, i32 0 -// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP2]], i32 0, i32 1 +// CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP3]], i32 0, i32 1 +// CHECK-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[TMP5]]) #[[ATTR4]] +// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP4]], i32 0, i32 0 +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK: arraydestroy.body: -// CHECK-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP6]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP6]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK: arraydestroy.done2: -// CHECK-NEXT: [[TMP7:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK-NEXT: ret i32 [[TMP7]] // // // CHECK-LABEL: define {{[^@]+}}@_ZN1SIdED1Ev -// CHECK-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK-NEXT: entry: -// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK-NEXT: call void @_ZN1SIdED2Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS1]]) #[[ATTR4]] +// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// CHECK-NEXT: call void @_ZN1SIdED2Ev(ptr noundef nonnull align 8 dereferenceable(8) [[THIS1]]) #[[ATTR4]] // CHECK-NEXT: ret void // // @@ -585,471 +565,451 @@ void array_func(int n, float a[n], St s[2]) { // CHECK-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 // CHECK-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 -// CHECK-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TTT]]) -// CHECK-NEXT: call void @_ZN1SIiEC1ERKS0_i(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TTT]], i32 noundef 0) -// CHECK-NEXT: store i32 0, i32* [[T_VAR]], align 128 -// CHECK-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// CHECK-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// CHECK-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef 1) -// CHECK-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// CHECK-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) -// CHECK-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]], i32 noundef 3) -// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 128 -// CHECK-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* -// CHECK-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4 -// CHECK-NEXT: [[TMP2:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 -// CHECK-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @_Z5tmainIiET_v.omp_outlined to void (i32*, i32*, ...)*), [2 x i32]* [[VEC]], i64 [[TMP2]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[VAR]]) -// CHECK-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// CHECK-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TTT]]) +// CHECK-NEXT: call void @_ZN1SIiEC1ERKS0_i(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]], ptr noundef nonnull align 4 dereferenceable(4) [[TTT]], i32 noundef 0) +// CHECK-NEXT: store i32 0, ptr [[T_VAR]], align 128 +// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false) +// CHECK-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 0 +// CHECK-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef 1) +// CHECK-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYINIT_BEGIN]], i64 1 +// CHECK-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// CHECK-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]], i32 noundef 3) +// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[T_VAR]], align 128 +// CHECK-NEXT: store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 +// CHECK-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 4, ptr @_Z5tmainIiET_v.omp_outlined, ptr [[VEC]], i64 [[TMP1]], ptr [[S_ARR]], ptr [[VAR]]) +// CHECK-NEXT: store i32 0, ptr [[RETVAL]], align 4 +// CHECK-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK: arraydestroy.body: -// CHECK-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK: arraydestroy.done1: -// CHECK-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TTT]]) #[[ATTR4]] -// CHECK-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 -// CHECK-NEXT: ret i32 [[TMP4]] +// CHECK-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TTT]]) #[[ATTR4]] +// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[RETVAL]], align 4 +// CHECK-NEXT: ret i32 [[TMP3]] // // // CHECK-LABEL: define {{[^@]+}}@_ZN1SIdEC2Ev -// CHECK-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK-NEXT: entry: -// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK-NEXT: store double 0.000000e+00, double* [[F]], align 8 +// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// CHECK-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 +// CHECK-NEXT: store double 0.000000e+00, ptr [[F]], align 8 // CHECK-NEXT: ret void // // // CHECK-LABEL: define {{[^@]+}}@_ZN1SIdEC2ERKS0_d -// CHECK-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[S:%.*]], double noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[S:%.*]], double noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK-NEXT: entry: -// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[T_ADDR:%.*]] = alloca double, align 8 -// CHECK-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 -// CHECK-NEXT: store double [[T]], double* [[T_ADDR]], align 8 -// CHECK-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 -// CHECK-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0 -// CHECK-NEXT: [[TMP1:%.*]] = load double, double* [[F2]], align 8 -// CHECK-NEXT: [[TMP2:%.*]] = load double, double* [[T_ADDR]], align 8 +// CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// CHECK-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 +// CHECK-NEXT: store double [[T]], ptr [[T_ADDR]], align 8 +// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// CHECK-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 +// CHECK-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0 +// CHECK-NEXT: [[TMP1:%.*]] = load double, ptr [[F2]], align 8 +// CHECK-NEXT: [[TMP2:%.*]] = load double, ptr [[T_ADDR]], align 8 // CHECK-NEXT: [[ADD:%.*]] = fadd double [[TMP1]], [[TMP2]] -// CHECK-NEXT: store double [[ADD]], double* [[F]], align 8 +// CHECK-NEXT: store double [[ADD]], ptr [[F]], align 8 // CHECK-NEXT: ret void // // // CHECK-LABEL: define {{[^@]+}}@_ZN1SIdEC2Ed -// CHECK-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], double noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], double noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK-NEXT: entry: -// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[A_ADDR:%.*]] = alloca double, align 8 -// CHECK-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK-NEXT: store double [[A]], double* [[A_ADDR]], align 8 -// CHECK-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// CHECK-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// CHECK-NEXT: [[TMP0:%.*]] = load double, double* [[A_ADDR]], align 8 -// CHECK-NEXT: store double [[TMP0]], double* [[F]], align 8 +// CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// CHECK-NEXT: store double [[A]], ptr [[A_ADDR]], align 8 +// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// CHECK-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 +// CHECK-NEXT: [[TMP0:%.*]] = load double, ptr [[A_ADDR]], align 8 +// CHECK-NEXT: store double [[TMP0]], ptr [[F]], align 8 // CHECK-NEXT: ret void // // // CHECK-LABEL: define {{[^@]+}}@_ZN1SIdED2Ev -// CHECK-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK-NEXT: entry: -// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// CHECK-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// CHECK-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: ret void // // // CHECK-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK-NEXT: entry: -// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) +// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// CHECK-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // CHECK-NEXT: ret void // // // CHECK-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_i -// CHECK-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], i32 noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], i32 noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK-NEXT: entry: -// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[T_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 -// CHECK-NEXT: store i32 [[T]], i32* [[T_ADDR]], align 4 -// CHECK-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 -// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_ADDR]], align 4 -// CHECK-NEXT: call void @_ZN1SIiEC2ERKS0_i(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], i32 noundef [[TMP1]]) +// CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// CHECK-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 +// CHECK-NEXT: store i32 [[T]], ptr [[T_ADDR]], align 4 +// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 +// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_ADDR]], align 4 +// CHECK-NEXT: call void @_ZN1SIiEC2ERKS0_i(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], i32 noundef [[TMP1]]) // CHECK-NEXT: ret void // // // CHECK-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK-NEXT: entry: -// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]) +// CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// CHECK-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 +// CHECK-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]) // CHECK-NEXT: ret void // // // CHECK-LABEL: define {{[^@]+}}@_Z5tmainIiET_v.omp_outlined -// CHECK-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { +// CHECK-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { // CHECK-NEXT: entry: -// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 -// CHECK-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 +// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 -// CHECK-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 -// CHECK-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON_1:%.*]], align 8 // CHECK-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// CHECK-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 -// CHECK-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 -// CHECK-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* -// CHECK-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 -// CHECK-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 -// CHECK-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 -// CHECK-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) +// CHECK-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 +// CHECK-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 +// CHECK-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 +// CHECK-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 +// CHECK-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 +// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 +// CHECK-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB1]], i32 [[TMP4]]) // CHECK-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0 // CHECK-NEXT: br i1 [[TMP6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] // CHECK: omp_if.then: -// CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1* [[AGG_CAPTURED]], i32 0, i32 0 -// CHECK-NEXT: store [2 x %struct.S.0]* [[TMP1]], [2 x %struct.S.0]** [[TMP7]], align 8 -// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1* [[AGG_CAPTURED]], i32 0, i32 1 -// CHECK-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP8]], align 8 -// CHECK-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) -// CHECK-NEXT: [[TMP9:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]], i32 9, i64 256, i64 16, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.2*)* @.omp_task_entry..3 to i32 (i32, i8*)*)) -// CHECK-NEXT: [[TMP10:%.*]] = bitcast i8* [[TMP9]] to %struct.kmp_task_t_with_privates.2* -// CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2:%.*]], %struct.kmp_task_t_with_privates.2* [[TMP10]], i32 0, i32 0 -// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP11]], i32 0, i32 0 -// CHECK-NEXT: [[TMP13:%.*]] = load i8*, i8** [[TMP12]], align 128 -// CHECK-NEXT: [[TMP14:%.*]] = bitcast %struct.anon.1* [[AGG_CAPTURED]] to i8* -// CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP13]], i8* align 8 [[TMP14]], i64 16, i1 false) -// CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2]], %struct.kmp_task_t_with_privates.2* [[TMP10]], i32 0, i32 2 -// CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3:%.*]], %struct..kmp_privates.t.3* [[TMP15]], i32 0, i32 0 -// CHECK-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 4 -// CHECK-NEXT: store i32 [[TMP17]], i32* [[TMP16]], align 128 -// CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3]], %struct..kmp_privates.t.3* [[TMP15]], i32 0, i32 1 -// CHECK-NEXT: [[TMP19:%.*]] = bitcast [2 x i32]* [[TMP18]] to i8* -// CHECK-NEXT: [[TMP20:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* -// CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i64 8, i1 false) -// CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3]], %struct..kmp_privates.t.3* [[TMP15]], i32 0, i32 2 -// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP21]], i32 0, i32 0 -// CHECK-NEXT: [[TMP22:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0* -// CHECK-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP23]] +// CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[AGG_CAPTURED]], i32 0, i32 0 +// CHECK-NEXT: store ptr [[TMP1]], ptr [[TMP7]], align 8 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[AGG_CAPTURED]], i32 0, i32 1 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[TMP8]], align 8 +// CHECK-NEXT: call void @__kmpc_taskgroup(ptr @[[GLOB1]], i32 [[TMP4]]) +// CHECK-NEXT: [[TMP9:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP4]], i32 9, i64 256, i64 16, ptr @.omp_task_entry..3) +// CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2:%.*]], ptr [[TMP9]], i32 0, i32 0 +// CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP10]], i32 0, i32 0 +// CHECK-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 128 +// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP12]], ptr align 8 [[AGG_CAPTURED]], i64 16, i1 false) +// CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2]], ptr [[TMP9]], i32 0, i32 2 +// CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3:%.*]], ptr [[TMP13]], i32 0, i32 0 +// CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 +// CHECK-NEXT: store i32 [[TMP15]], ptr [[TMP14]], align 128 +// CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3]], ptr [[TMP13]], i32 0, i32 1 +// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP16]], ptr align 4 [[TMP0]], i64 8, i1 false) +// CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3]], ptr [[TMP13]], i32 0, i32 2 +// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP17]], i32 0, i32 0 +// CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP18]] // CHECK-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] // CHECK: omp.arraycpy.body: -// CHECK-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP22]], [[OMP_IF_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[OMP_IF_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK-NEXT: call void @_ZN1SIiEC1ERKS0_i(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 noundef 0) -// CHECK-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP23]] +// CHECK-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[OMP_IF_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[OMP_IF_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK-NEXT: call void @_ZN1SIiEC1ERKS0_i(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 noundef 0) +// CHECK-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP18]] // CHECK-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]] // CHECK: omp.arraycpy.done1: -// CHECK-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3]], %struct..kmp_privates.t.3* [[TMP15]], i32 0, i32 3 -// CHECK-NEXT: call void @_ZN1SIiEC1ERKS0_i(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP24]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP2]], i32 noundef 0) -// CHECK-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP11]], i32 0, i32 3 -// CHECK-NEXT: [[TMP26:%.*]] = bitcast %union.kmp_cmplrdata_t* [[TMP25]] to i32 (i32, i8*)** -// CHECK-NEXT: store i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.2*)* @.omp_task_destructor..5 to i32 (i32, i8*)*), i32 (i32, i8*)** [[TMP26]], align 8 -// CHECK-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP11]], i32 0, i32 5 -// CHECK-NEXT: store i64 0, i64* [[TMP27]], align 8 -// CHECK-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP11]], i32 0, i32 6 -// CHECK-NEXT: store i64 9, i64* [[TMP28]], align 16 -// CHECK-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP11]], i32 0, i32 7 -// CHECK-NEXT: store i64 1, i64* [[TMP29]], align 8 -// CHECK-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP11]], i32 0, i32 9 -// CHECK-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i8* -// CHECK-NEXT: call void @llvm.memset.p0i8.i64(i8* align 8 [[TMP31]], i8 0, i64 8, i1 false) -// CHECK-NEXT: [[TMP32:%.*]] = load i64, i64* [[TMP29]], align 8 -// CHECK-NEXT: call void @__kmpc_taskloop(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]], i8* [[TMP9]], i32 1, i64* [[TMP27]], i64* [[TMP28]], i64 [[TMP32]], i32 1, i32 0, i64 0, i8* bitcast (void (%struct.kmp_task_t_with_privates.2*, %struct.kmp_task_t_with_privates.2*, i32)* @.omp_task_dup..4 to i8*)) -// CHECK-NEXT: call void @__kmpc_end_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) -// CHECK-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) +// CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3]], ptr [[TMP13]], i32 0, i32 3 +// CHECK-NEXT: call void @_ZN1SIiEC1ERKS0_i(ptr noundef nonnull align 4 dereferenceable(4) [[TMP19]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], i32 noundef 0) +// CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP10]], i32 0, i32 3 +// CHECK-NEXT: store ptr @.omp_task_destructor..5, ptr [[TMP20]], align 8 +// CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP10]], i32 0, i32 5 +// CHECK-NEXT: store i64 0, ptr [[TMP21]], align 8 +// CHECK-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP10]], i32 0, i32 6 +// CHECK-NEXT: store i64 9, ptr [[TMP22]], align 16 +// CHECK-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP10]], i32 0, i32 7 +// CHECK-NEXT: store i64 1, ptr [[TMP23]], align 8 +// CHECK-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP10]], i32 0, i32 9 +// CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP24]], i8 0, i64 8, i1 false) +// CHECK-NEXT: [[TMP25:%.*]] = load i64, ptr [[TMP23]], align 8 +// CHECK-NEXT: call void @__kmpc_taskloop(ptr @[[GLOB1]], i32 [[TMP4]], ptr [[TMP9]], i32 1, ptr [[TMP21]], ptr [[TMP22]], i64 [[TMP25]], i32 1, i32 0, i64 0, ptr @.omp_task_dup..4) +// CHECK-NEXT: call void @__kmpc_end_taskgroup(ptr @[[GLOB1]], i32 [[TMP4]]) +// CHECK-NEXT: call void @__kmpc_end_master(ptr @[[GLOB1]], i32 [[TMP4]]) // CHECK-NEXT: br label [[OMP_IF_END]] // CHECK: omp_if.end: // CHECK-NEXT: ret void // // // CHECK-LABEL: define {{[^@]+}}@.omp_task_privates_map..2 -// CHECK-SAME: (%struct..kmp_privates.t.3* noalias noundef [[TMP0:%.*]], i32** noalias noundef [[TMP1:%.*]], [2 x i32]** noalias noundef [[TMP2:%.*]], [2 x %struct.S.0]** noalias noundef [[TMP3:%.*]], %struct.S.0** noalias noundef [[TMP4:%.*]]) #[[ATTR6]] { +// CHECK-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]], ptr noalias noundef [[TMP3:%.*]], ptr noalias noundef [[TMP4:%.*]]) #[[ATTR6]] { // CHECK-NEXT: entry: -// CHECK-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t.3*, align 8 -// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32**, align 8 -// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca [2 x i32]**, align 8 -// CHECK-NEXT: [[DOTADDR3:%.*]] = alloca [2 x %struct.S.0]**, align 8 -// CHECK-NEXT: [[DOTADDR4:%.*]] = alloca %struct.S.0**, align 8 -// CHECK-NEXT: store %struct..kmp_privates.t.3* [[TMP0]], %struct..kmp_privates.t.3** [[DOTADDR]], align 8 -// CHECK-NEXT: store i32** [[TMP1]], i32*** [[DOTADDR1]], align 8 -// CHECK-NEXT: store [2 x i32]** [[TMP2]], [2 x i32]*** [[DOTADDR2]], align 8 -// CHECK-NEXT: store [2 x %struct.S.0]** [[TMP3]], [2 x %struct.S.0]*** [[DOTADDR3]], align 8 -// CHECK-NEXT: store %struct.S.0** [[TMP4]], %struct.S.0*** [[DOTADDR4]], align 8 -// CHECK-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t.3*, %struct..kmp_privates.t.3** [[DOTADDR]], align 8 -// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3:%.*]], %struct..kmp_privates.t.3* [[TMP5]], i32 0, i32 0 -// CHECK-NEXT: [[TMP7:%.*]] = load i32**, i32*** [[DOTADDR1]], align 8 -// CHECK-NEXT: store i32* [[TMP6]], i32** [[TMP7]], align 8 -// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3]], %struct..kmp_privates.t.3* [[TMP5]], i32 0, i32 1 -// CHECK-NEXT: [[TMP9:%.*]] = load [2 x i32]**, [2 x i32]*** [[DOTADDR2]], align 8 -// CHECK-NEXT: store [2 x i32]* [[TMP8]], [2 x i32]** [[TMP9]], align 8 -// CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3]], %struct..kmp_privates.t.3* [[TMP5]], i32 0, i32 2 -// CHECK-NEXT: [[TMP11:%.*]] = load [2 x %struct.S.0]**, [2 x %struct.S.0]*** [[DOTADDR3]], align 8 -// CHECK-NEXT: store [2 x %struct.S.0]* [[TMP10]], [2 x %struct.S.0]** [[TMP11]], align 8 -// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3]], %struct..kmp_privates.t.3* [[TMP5]], i32 0, i32 3 -// CHECK-NEXT: [[TMP13:%.*]] = load %struct.S.0**, %struct.S.0*** [[DOTADDR4]], align 8 -// CHECK-NEXT: store %struct.S.0* [[TMP12]], %struct.S.0** [[TMP13]], align 8 +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 +// CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2]], align 8 +// CHECK-NEXT: store ptr [[TMP3]], ptr [[DOTADDR3]], align 8 +// CHECK-NEXT: store ptr [[TMP4]], ptr [[DOTADDR4]], align 8 +// CHECK-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR]], align 8 +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3:%.*]], ptr [[TMP5]], i32 0, i32 0 +// CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 +// CHECK-NEXT: store ptr [[TMP6]], ptr [[TMP7]], align 8 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3]], ptr [[TMP5]], i32 0, i32 1 +// CHECK-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTADDR2]], align 8 +// CHECK-NEXT: store ptr [[TMP8]], ptr [[TMP9]], align 8 +// CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3]], ptr [[TMP5]], i32 0, i32 2 +// CHECK-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTADDR3]], align 8 +// CHECK-NEXT: store ptr [[TMP10]], ptr [[TMP11]], align 8 +// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3]], ptr [[TMP5]], i32 0, i32 3 +// CHECK-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTADDR4]], align 8 +// CHECK-NEXT: store ptr [[TMP12]], ptr [[TMP13]], align 8 // CHECK-NEXT: ret void // // // CHECK-LABEL: define {{[^@]+}}@.omp_task_entry..3 -// CHECK-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.2* noalias noundef [[TMP1:%.*]]) #[[ATTR7]] { +// CHECK-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR7]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 -// CHECK-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 -// CHECK-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 +// CHECK-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[DOTLB__ADDR_I:%.*]] = alloca i64, align 8 // CHECK-NEXT: [[DOTUB__ADDR_I:%.*]] = alloca i64, align 8 // CHECK-NEXT: [[DOTST__ADDR_I:%.*]] = alloca i64, align 8 // CHECK-NEXT: [[DOTLITER__ADDR_I:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca i8*, align 8 -// CHECK-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon.1*, align 8 -// CHECK-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i32*, align 8 -// CHECK-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [2 x i32]*, align 8 -// CHECK-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [2 x %struct.S.0]*, align 8 -// CHECK-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca %struct.S.0*, align 8 +// CHECK-NEXT: [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[I_I:%.*]] = alloca i32, align 4 // CHECK-NEXT: [[DOTOMP_IV_I:%.*]] = alloca i32, align 4 // CHECK-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates.2*, align 8 -// CHECK-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 -// CHECK-NEXT: store %struct.kmp_task_t_with_privates.2* [[TMP1]], %struct.kmp_task_t_with_privates.2** [[DOTADDR1]], align 8 -// CHECK-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 -// CHECK-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates.2*, %struct.kmp_task_t_with_privates.2** [[DOTADDR1]], align 8 -// CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2:%.*]], %struct.kmp_task_t_with_privates.2* [[TMP3]], i32 0, i32 0 -// CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 -// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 -// CHECK-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 128 -// CHECK-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon.1* -// CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2]], %struct.kmp_task_t_with_privates.2* [[TMP3]], i32 0, i32 2 -// CHECK-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t.3* [[TMP9]] to i8* -// CHECK-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates.2* [[TMP3]] to i8* -// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 5 -// CHECK-NEXT: [[TMP13:%.*]] = load i64, i64* [[TMP12]], align 8 -// CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 6 -// CHECK-NEXT: [[TMP15:%.*]] = load i64, i64* [[TMP14]], align 16 -// CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 7 -// CHECK-NEXT: [[TMP17:%.*]] = load i64, i64* [[TMP16]], align 8 -// CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 8 -// CHECK-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 64 -// CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 9 -// CHECK-NEXT: [[TMP21:%.*]] = load i8*, i8** [[TMP20]], align 8 +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 +// CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 128 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2]], ptr [[TMP3]], i32 0, i32 2 +// CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 5 +// CHECK-NEXT: [[TMP10:%.*]] = load i64, ptr [[TMP9]], align 8 +// CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 6 +// CHECK-NEXT: [[TMP12:%.*]] = load i64, ptr [[TMP11]], align 16 +// CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 7 +// CHECK-NEXT: [[TMP14:%.*]] = load i64, ptr [[TMP13]], align 8 +// CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 8 +// CHECK-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 64 +// CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 9 +// CHECK-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8 // CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]]) // CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]]) // CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META26:![0-9]+]]) // CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META28:![0-9]+]]) // CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META30:![0-9]+]]) -// CHECK-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !32 -// CHECK-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !32 -// CHECK-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !32 -// CHECK-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t.3*, i32**, [2 x i32]**, [2 x %struct.S.0]**, %struct.S.0**)* @.omp_task_privates_map..2 to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !32 -// CHECK-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !32 -// CHECK-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !32 -// CHECK-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !32 -// CHECK-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !32 -// CHECK-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !32 -// CHECK-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !32 -// CHECK-NEXT: store %struct.anon.1* [[TMP8]], %struct.anon.1** [[__CONTEXT_ADDR_I]], align 8, !noalias !32 -// CHECK-NEXT: [[TMP22:%.*]] = load %struct.anon.1*, %struct.anon.1** [[__CONTEXT_ADDR_I]], align 8, !noalias !32 -// CHECK-NEXT: [[TMP23:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !32 -// CHECK-NEXT: [[TMP24:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !32 -// CHECK-NEXT: [[TMP25:%.*]] = bitcast void (i8*, ...)* [[TMP23]] to void (i8*, i32**, [2 x i32]**, [2 x %struct.S.0]**, %struct.S.0**)* -// CHECK-NEXT: call void [[TMP25]](i8* [[TMP24]], i32** [[DOTFIRSTPRIV_PTR_ADDR_I]], [2 x i32]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [2 x %struct.S.0]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], %struct.S.0** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]] -// CHECK-NEXT: [[TMP26:%.*]] = load i32*, i32** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !32 -// CHECK-NEXT: [[TMP27:%.*]] = load [2 x i32]*, [2 x i32]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !32 -// CHECK-NEXT: [[TMP28:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !32 -// CHECK-NEXT: [[TMP29:%.*]] = load %struct.S.0*, %struct.S.0** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !32 -// CHECK-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTLB__ADDR_I]], align 8, !noalias !32 -// CHECK-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP30]] to i32 -// CHECK-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !32 +// CHECK-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !32 +// CHECK-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias !32 +// CHECK-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias !32 +// CHECK-NEXT: store ptr @.omp_task_privates_map..2, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !32 +// CHECK-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias !32 +// CHECK-NEXT: store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias !32 +// CHECK-NEXT: store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias !32 +// CHECK-NEXT: store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias !32 +// CHECK-NEXT: store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias !32 +// CHECK-NEXT: store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !32 +// CHECK-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias !32 +// CHECK-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias !32 +// CHECK-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !32 +// CHECK-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias !32 +// CHECK-NEXT: call void [[TMP20]](ptr [[TMP21]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]] +// CHECK-NEXT: [[TMP22:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !32 +// CHECK-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !32 +// CHECK-NEXT: [[TMP24:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !32 +// CHECK-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !32 +// CHECK-NEXT: [[TMP26:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias !32 +// CHECK-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP26]] to i32 +// CHECK-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias !32 // CHECK-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]] // CHECK: omp.inner.for.cond.i: -// CHECK-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV_I]], align 4, !noalias !32, !llvm.access.group [[ACC_GRP33:![0-9]+]] -// CHECK-NEXT: [[CONV4_I:%.*]] = sext i32 [[TMP31]] to i64 -// CHECK-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTUB__ADDR_I]], align 8, !noalias !32, !llvm.access.group [[ACC_GRP33]] -// CHECK-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV4_I]], [[TMP32]] +// CHECK-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias !32, !llvm.access.group [[ACC_GRP33:![0-9]+]] +// CHECK-NEXT: [[CONV4_I:%.*]] = sext i32 [[TMP27]] to i64 +// CHECK-NEXT: [[TMP28:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias !32, !llvm.access.group [[ACC_GRP33]] +// CHECK-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV4_I]], [[TMP28]] // CHECK-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] // CHECK: omp.inner.for.body.i: -// CHECK-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_IV_I]], align 4, !noalias !32, !llvm.access.group [[ACC_GRP33]] -// CHECK-NEXT: store i32 [[TMP33]], i32* [[I_I]], align 4, !noalias !32, !llvm.access.group [[ACC_GRP33]] -// CHECK-NEXT: [[TMP34:%.*]] = load i32, i32* [[TMP26]], align 128, !llvm.access.group [[ACC_GRP33]] -// CHECK-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[TMP27]], i64 0, i64 0 -// CHECK-NEXT: store i32 [[TMP34]], i32* [[ARRAYIDX_I]], align 4, !llvm.access.group [[ACC_GRP33]] -// CHECK-NEXT: [[ARRAYIDX5_I:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP28]], i64 0, i64 0 -// CHECK-NEXT: [[TMP35:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5_I]] to i8* -// CHECK-NEXT: [[TMP36:%.*]] = bitcast %struct.S.0* [[TMP29]] to i8* -// CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP35]], i8* align 4 [[TMP36]], i64 4, i1 false), !llvm.access.group [[ACC_GRP33]] -// CHECK-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTOMP_IV_I]], align 4, !noalias !32, !llvm.access.group [[ACC_GRP33]] -// CHECK-NEXT: [[ADD6_I:%.*]] = add nsw i32 [[TMP37]], 1 -// CHECK-NEXT: store i32 [[ADD6_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !32, !llvm.access.group [[ACC_GRP33]] +// CHECK-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias !32, !llvm.access.group [[ACC_GRP33]] +// CHECK-NEXT: store i32 [[TMP29]], ptr [[I_I]], align 4, !noalias !32, !llvm.access.group [[ACC_GRP33]] +// CHECK-NEXT: [[TMP30:%.*]] = load i32, ptr [[TMP22]], align 128, !llvm.access.group [[ACC_GRP33]] +// CHECK-NEXT: store i32 [[TMP30]], ptr [[TMP23]], align 4, !llvm.access.group [[ACC_GRP33]] +// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP24]], ptr align 4 [[TMP25]], i64 4, i1 false), !llvm.access.group [[ACC_GRP33]] +// CHECK-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias !32, !llvm.access.group [[ACC_GRP33]] +// CHECK-NEXT: [[ADD6_I:%.*]] = add nsw i32 [[TMP31]], 1 +// CHECK-NEXT: store i32 [[ADD6_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias !32, !llvm.access.group [[ACC_GRP33]] // CHECK-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP34:![0-9]+]] // CHECK: .omp_outlined..1.exit: // CHECK-NEXT: ret i32 0 // // // CHECK-LABEL: define {{[^@]+}}@.omp_task_dup..4 -// CHECK-SAME: (%struct.kmp_task_t_with_privates.2* noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.2* noundef [[TMP1:%.*]], i32 noundef [[TMP2:%.*]]) #[[ATTR7]] { +// CHECK-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], i32 noundef [[TMP2:%.*]]) #[[ATTR7]] { // CHECK-NEXT: entry: -// CHECK-NEXT: [[DOTADDR:%.*]] = alloca %struct.kmp_task_t_with_privates.2*, align 8 -// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates.2*, align 8 +// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[DOTADDR2:%.*]] = alloca i32, align 4 -// CHECK-NEXT: store %struct.kmp_task_t_with_privates.2* [[TMP0]], %struct.kmp_task_t_with_privates.2** [[DOTADDR]], align 8 -// CHECK-NEXT: store %struct.kmp_task_t_with_privates.2* [[TMP1]], %struct.kmp_task_t_with_privates.2** [[DOTADDR1]], align 8 -// CHECK-NEXT: store i32 [[TMP2]], i32* [[DOTADDR2]], align 4 -// CHECK-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates.2*, %struct.kmp_task_t_with_privates.2** [[DOTADDR]], align 8 -// CHECK-NEXT: [[TMP4:%.*]] = load %struct.kmp_task_t_with_privates.2*, %struct.kmp_task_t_with_privates.2** [[DOTADDR1]], align 8 -// CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2:%.*]], %struct.kmp_task_t_with_privates.2* [[TMP4]], i32 0, i32 0 -// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP5]], i32 0, i32 0 -// CHECK-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 128 -// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2]], %struct.kmp_task_t_with_privates.2* [[TMP3]], i32 0, i32 2 -// CHECK-NEXT: [[TMP9:%.*]] = bitcast i8* [[TMP7]] to %struct.anon.1* -// CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3:%.*]], %struct..kmp_privates.t.3* [[TMP8]], i32 0, i32 2 -// CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_ANON_1:%.*]], %struct.anon.1* [[TMP9]], i32 0, i32 0 -// CHECK-NEXT: [[TMP12:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[TMP11]], align 8 -// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP10]], i32 0, i32 0 -// CHECK-NEXT: [[TMP13:%.*]] = bitcast [2 x %struct.S.0]* [[TMP12]] to %struct.S.0* -// CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 -// CHECK-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP14]] +// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 +// CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK-NEXT: store i32 [[TMP2]], ptr [[DOTADDR2]], align 4 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 +// CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2:%.*]], ptr [[TMP4]], i32 0, i32 0 +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP5]], i32 0, i32 0 +// CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 128 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2]], ptr [[TMP3]], i32 0, i32 2 +// CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3:%.*]], ptr [[TMP8]], i32 0, i32 2 +// CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_ANON_1:%.*]], ptr [[TMP7]], i32 0, i32 0 +// CHECK-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP10]], align 8 +// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP9]], i32 0, i32 0 +// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP12]] // CHECK-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] // CHECK: omp.arraycpy.body: -// CHECK-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK-NEXT: call void @_ZN1SIiEC1ERKS0_i(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 noundef 0) -// CHECK-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP14]] +// CHECK-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP11]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// CHECK-NEXT: call void @_ZN1SIiEC1ERKS0_i(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 noundef 0) +// CHECK-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 +// CHECK-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 +// CHECK-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP12]] // CHECK-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] // CHECK: omp.arraycpy.done3: -// CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3]], %struct..kmp_privates.t.3* [[TMP8]], i32 0, i32 3 -// CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1* [[TMP9]], i32 0, i32 1 -// CHECK-NEXT: [[TMP17:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP16]], align 8 -// CHECK-NEXT: call void @_ZN1SIiEC1ERKS0_i(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP15]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP17]], i32 noundef 0) +// CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3]], ptr [[TMP8]], i32 0, i32 3 +// CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], ptr [[TMP7]], i32 0, i32 1 +// CHECK-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP14]], align 8 +// CHECK-NEXT: call void @_ZN1SIiEC1ERKS0_i(ptr noundef nonnull align 4 dereferenceable(4) [[TMP13]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP15]], i32 noundef 0) // CHECK-NEXT: ret void // // // CHECK-LABEL: define {{[^@]+}}@.omp_task_destructor..5 -// CHECK-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.2* noalias noundef [[TMP1:%.*]]) #[[ATTR7]] { +// CHECK-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR7]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates.2*, align 8 -// CHECK-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 -// CHECK-NEXT: store %struct.kmp_task_t_with_privates.2* [[TMP1]], %struct.kmp_task_t_with_privates.2** [[DOTADDR1]], align 8 -// CHECK-NEXT: [[TMP2:%.*]] = load %struct.kmp_task_t_with_privates.2*, %struct.kmp_task_t_with_privates.2** [[DOTADDR1]], align 8 -// CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2:%.*]], %struct.kmp_task_t_with_privates.2* [[TMP2]], i32 0, i32 2 -// CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3:%.*]], %struct..kmp_privates.t.3* [[TMP3]], i32 0, i32 2 -// CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3]], %struct..kmp_privates.t.3* [[TMP3]], i32 0, i32 3 -// CHECK-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP5]]) #[[ATTR4]] -// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP4]], i32 0, i32 0 -// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2:%.*]], ptr [[TMP2]], i32 0, i32 2 +// CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3:%.*]], ptr [[TMP3]], i32 0, i32 2 +// CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3]], ptr [[TMP3]], i32 0, i32 3 +// CHECK-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP5]]) #[[ATTR4]] +// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP4]], i32 0, i32 0 +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK: arraydestroy.body: -// CHECK-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP6]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// CHECK-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// CHECK-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP6]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK: arraydestroy.done2: -// CHECK-NEXT: [[TMP7:%.*]] = load i32, i32* [[RETVAL]], align 4 +// CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK-NEXT: ret i32 [[TMP7]] // // // CHECK-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK-NEXT: entry: -// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// CHECK-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK-NEXT: ret void // // // CHECK-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK-NEXT: entry: -// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK-NEXT: store i32 0, i32* [[F]], align 4 +// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// CHECK-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 +// CHECK-NEXT: store i32 0, ptr [[F]], align 4 // CHECK-NEXT: ret void // // // CHECK-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_i -// CHECK-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], i32 noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], i32 noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK-NEXT: entry: -// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[T_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 -// CHECK-NEXT: store i32 [[T]], i32* [[T_ADDR]], align 4 -// CHECK-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 -// CHECK-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0 -// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4 -// CHECK-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_ADDR]], align 4 +// CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// CHECK-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 +// CHECK-NEXT: store i32 [[T]], ptr [[T_ADDR]], align 4 +// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// CHECK-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 +// CHECK-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0 +// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4 +// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[T_ADDR]], align 4 // CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] -// CHECK-NEXT: store i32 [[ADD]], i32* [[F]], align 4 +// CHECK-NEXT: store i32 [[ADD]], ptr [[F]], align 4 // CHECK-NEXT: ret void // // // CHECK-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK-NEXT: entry: -// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 +// CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// CHECK-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// CHECK-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 +// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 +// CHECK-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // CHECK-NEXT: ret void // // // CHECK-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK-NEXT: entry: -// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// CHECK-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// CHECK-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: ret void // // @@ -1058,119 +1018,114 @@ void array_func(int n, float a[n], St s[2]) { // LAMBDA-NEXT: entry: // LAMBDA-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // LAMBDA-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// LAMBDA-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// LAMBDA-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef nonnull align 1 dereferenceable(1) [[REF_TMP]]) +// LAMBDA-NEXT: store i32 0, ptr [[RETVAL]], align 4 +// LAMBDA-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]]) // LAMBDA-NEXT: ret i32 0 // // // LAMBDA-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// LAMBDA-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], double** noalias noundef [[TMP1:%.*]], i32** noalias noundef [[TMP2:%.*]]) #[[ATTR5:[0-9]+]] { +// LAMBDA-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]]) #[[ATTR5:[0-9]+]] { // LAMBDA-NEXT: entry: -// LAMBDA-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 -// LAMBDA-NEXT: [[DOTADDR1:%.*]] = alloca double**, align 8 -// LAMBDA-NEXT: [[DOTADDR2:%.*]] = alloca i32**, align 8 -// LAMBDA-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8 -// LAMBDA-NEXT: store double** [[TMP1]], double*** [[DOTADDR1]], align 8 -// LAMBDA-NEXT: store i32** [[TMP2]], i32*** [[DOTADDR2]], align 8 -// LAMBDA-NEXT: [[TMP3:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8 -// LAMBDA-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP3]], i32 0, i32 0 -// LAMBDA-NEXT: [[TMP5:%.*]] = load double**, double*** [[DOTADDR1]], align 8 -// LAMBDA-NEXT: store double* [[TMP4]], double** [[TMP5]], align 8 -// LAMBDA-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP3]], i32 0, i32 1 -// LAMBDA-NEXT: [[TMP7:%.*]] = load i32**, i32*** [[DOTADDR2]], align 8 -// LAMBDA-NEXT: store i32* [[TMP6]], i32** [[TMP7]], align 8 +// LAMBDA-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 +// LAMBDA-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// LAMBDA-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8 +// LAMBDA-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 +// LAMBDA-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// LAMBDA-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2]], align 8 +// LAMBDA-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR]], align 8 +// LAMBDA-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP3]], i32 0, i32 0 +// LAMBDA-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 +// LAMBDA-NEXT: store ptr [[TMP4]], ptr [[TMP5]], align 8 +// LAMBDA-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP3]], i32 0, i32 1 +// LAMBDA-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTADDR2]], align 8 +// LAMBDA-NEXT: store ptr [[TMP6]], ptr [[TMP7]], align 8 // LAMBDA-NEXT: ret void // // // LAMBDA-LABEL: define {{[^@]+}}@.omp_task_entry. -// LAMBDA-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { +// LAMBDA-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { // LAMBDA-NEXT: entry: // LAMBDA-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 -// LAMBDA-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 -// LAMBDA-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 -// LAMBDA-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 -// LAMBDA-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 +// LAMBDA-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8 +// LAMBDA-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8 +// LAMBDA-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8 +// LAMBDA-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8 // LAMBDA-NEXT: [[DOTLB__ADDR_I:%.*]] = alloca i64, align 8 // LAMBDA-NEXT: [[DOTUB__ADDR_I:%.*]] = alloca i64, align 8 // LAMBDA-NEXT: [[DOTST__ADDR_I:%.*]] = alloca i64, align 8 // LAMBDA-NEXT: [[DOTLITER__ADDR_I:%.*]] = alloca i32, align 4 -// LAMBDA-NEXT: [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca i8*, align 8 -// LAMBDA-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 -// LAMBDA-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca double*, align 8 -// LAMBDA-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca i32*, align 8 +// LAMBDA-NEXT: [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca ptr, align 8 +// LAMBDA-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8 +// LAMBDA-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca ptr, align 8 +// LAMBDA-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca ptr, align 8 // LAMBDA-NEXT: [[I_I:%.*]] = alloca i32, align 4 // LAMBDA-NEXT: [[DOTOMP_IV_I:%.*]] = alloca i32, align 4 // LAMBDA-NEXT: [[REF_TMP_I:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 // LAMBDA-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 -// LAMBDA-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 -// LAMBDA-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 -// LAMBDA-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 -// LAMBDA-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 -// LAMBDA-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 -// LAMBDA-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 -// LAMBDA-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 -// LAMBDA-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 -// LAMBDA-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 -// LAMBDA-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* -// LAMBDA-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 -// LAMBDA-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* -// LAMBDA-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* -// LAMBDA-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 5 -// LAMBDA-NEXT: [[TMP13:%.*]] = load i64, i64* [[TMP12]], align 8 -// LAMBDA-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 6 -// LAMBDA-NEXT: [[TMP15:%.*]] = load i64, i64* [[TMP14]], align 8 -// LAMBDA-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 7 -// LAMBDA-NEXT: [[TMP17:%.*]] = load i64, i64* [[TMP16]], align 8 -// LAMBDA-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 8 -// LAMBDA-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 8 -// LAMBDA-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 9 -// LAMBDA-NEXT: [[TMP21:%.*]] = load i8*, i8** [[TMP20]], align 8 +// LAMBDA-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// LAMBDA-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 +// LAMBDA-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// LAMBDA-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 +// LAMBDA-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 +// LAMBDA-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0 +// LAMBDA-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 +// LAMBDA-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 +// LAMBDA-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// LAMBDA-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 1 +// LAMBDA-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 5 +// LAMBDA-NEXT: [[TMP10:%.*]] = load i64, ptr [[TMP9]], align 8 +// LAMBDA-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 6 +// LAMBDA-NEXT: [[TMP12:%.*]] = load i64, ptr [[TMP11]], align 8 +// LAMBDA-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 7 +// LAMBDA-NEXT: [[TMP14:%.*]] = load i64, ptr [[TMP13]], align 8 +// LAMBDA-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 8 +// LAMBDA-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 8 +// LAMBDA-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 9 +// LAMBDA-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8 // LAMBDA-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]]) // LAMBDA-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]]) // LAMBDA-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]]) // LAMBDA-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]]) // LAMBDA-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]]) -// LAMBDA-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14 -// LAMBDA-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !14 -// LAMBDA-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14 -// LAMBDA-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, double**, i32**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14 -// LAMBDA-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !14 -// LAMBDA-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !14 -// LAMBDA-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !14 -// LAMBDA-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !14 -// LAMBDA-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !14 -// LAMBDA-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !14 -// LAMBDA-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14 -// LAMBDA-NEXT: [[TMP22:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14 -// LAMBDA-NEXT: [[TMP23:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14 -// LAMBDA-NEXT: [[TMP24:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14 -// LAMBDA-NEXT: [[TMP25:%.*]] = bitcast void (i8*, ...)* [[TMP23]] to void (i8*, double**, i32**)* -// LAMBDA-NEXT: call void [[TMP25]](i8* [[TMP24]], double** [[DOTFIRSTPRIV_PTR_ADDR_I]], i32** [[DOTFIRSTPRIV_PTR_ADDR1_I]]) #[[ATTR3:[0-9]+]] -// LAMBDA-NEXT: [[TMP26:%.*]] = load double*, double** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !14 -// LAMBDA-NEXT: [[TMP27:%.*]] = load i32*, i32** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !14 -// LAMBDA-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTLB__ADDR_I]], align 8, !noalias !14 -// LAMBDA-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP28]] to i32 -// LAMBDA-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14 +// LAMBDA-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14 +// LAMBDA-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias !14 +// LAMBDA-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14 +// LAMBDA-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14 +// LAMBDA-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias !14 +// LAMBDA-NEXT: store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias !14 +// LAMBDA-NEXT: store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias !14 +// LAMBDA-NEXT: store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias !14 +// LAMBDA-NEXT: store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias !14 +// LAMBDA-NEXT: store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !14 +// LAMBDA-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias !14 +// LAMBDA-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias !14 +// LAMBDA-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14 +// LAMBDA-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14 +// LAMBDA-NEXT: call void [[TMP20]](ptr [[TMP21]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]]) #[[ATTR3:[0-9]+]] +// LAMBDA-NEXT: [[TMP22:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !14 +// LAMBDA-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !14 +// LAMBDA-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias !14 +// LAMBDA-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP24]] to i32 +// LAMBDA-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias !14 // LAMBDA-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]] // LAMBDA: omp.inner.for.cond.i: -// LAMBDA-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group [[ACC_GRP15:![0-9]+]] -// LAMBDA-NEXT: [[CONV2_I:%.*]] = sext i32 [[TMP29]] to i64 -// LAMBDA-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTUB__ADDR_I]], align 8, !noalias !14, !llvm.access.group [[ACC_GRP15]] -// LAMBDA-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV2_I]], [[TMP30]] +// LAMBDA-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group [[ACC_GRP15:![0-9]+]] +// LAMBDA-NEXT: [[CONV2_I:%.*]] = sext i32 [[TMP25]] to i64 +// LAMBDA-NEXT: [[TMP26:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias !14, !llvm.access.group [[ACC_GRP15]] +// LAMBDA-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV2_I]], [[TMP26]] // LAMBDA-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]] // LAMBDA: omp.inner.for.body.i: -// LAMBDA-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group [[ACC_GRP15]] -// LAMBDA-NEXT: store i32 [[TMP31]], i32* [[I_I]], align 4, !noalias !14, !llvm.access.group [[ACC_GRP15]] -// LAMBDA-NEXT: store double 1.000000e+00, double* [[TMP26]], align 8, !llvm.access.group [[ACC_GRP15]] -// LAMBDA-NEXT: store i32 11, i32* [[TMP27]], align 4, !llvm.access.group [[ACC_GRP15]] -// LAMBDA-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP_I]], i32 0, i32 0 -// LAMBDA-NEXT: store double* [[TMP26]], double** [[TMP32]], align 8, !noalias !14, !llvm.access.group [[ACC_GRP15]] -// LAMBDA-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP_I]], i32 0, i32 1 -// LAMBDA-NEXT: store i32* [[TMP27]], i32** [[TMP33]], align 8, !noalias !14, !llvm.access.group [[ACC_GRP15]] -// LAMBDA-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef nonnull align 8 dereferenceable(16) [[REF_TMP_I]]), !llvm.access.group [[ACC_GRP15]] -// LAMBDA-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group [[ACC_GRP15]] -// LAMBDA-NEXT: [[ADD3_I:%.*]] = add nsw i32 [[TMP34]], 1 -// LAMBDA-NEXT: store i32 [[ADD3_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group [[ACC_GRP15]] +// LAMBDA-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group [[ACC_GRP15]] +// LAMBDA-NEXT: store i32 [[TMP27]], ptr [[I_I]], align 4, !noalias !14, !llvm.access.group [[ACC_GRP15]] +// LAMBDA-NEXT: store double 1.000000e+00, ptr [[TMP22]], align 8, !llvm.access.group [[ACC_GRP15]] +// LAMBDA-NEXT: store i32 11, ptr [[TMP23]], align 4, !llvm.access.group [[ACC_GRP15]] +// LAMBDA-NEXT: store ptr [[TMP22]], ptr [[REF_TMP_I]], align 8, !noalias !14, !llvm.access.group [[ACC_GRP15]] +// LAMBDA-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP_I]], i32 0, i32 1 +// LAMBDA-NEXT: store ptr [[TMP23]], ptr [[TMP28]], align 8, !noalias !14, !llvm.access.group [[ACC_GRP15]] +// LAMBDA-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(16) [[REF_TMP_I]]), !llvm.access.group [[ACC_GRP15]] +// LAMBDA-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group [[ACC_GRP15]] +// LAMBDA-NEXT: [[ADD3_I:%.*]] = add nsw i32 [[TMP29]], 1 +// LAMBDA-NEXT: store i32 [[ADD3_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group [[ACC_GRP15]] // LAMBDA-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP16:![0-9]+]] // LAMBDA: .omp_outlined..exit: // LAMBDA-NEXT: ret i32 0 @@ -1180,391 +1135,369 @@ void array_func(int n, float a[n], St s[2]) { // BLOCKS-SAME: () #[[ATTR1:[0-9]+]] { // BLOCKS-NEXT: entry: // BLOCKS-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// BLOCKS-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// BLOCKS-NEXT: [[TMP0:%.*]] = load i8*, i8** getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to %struct.__block_literal_generic*), i32 0, i32 3), align 8 -// BLOCKS-NEXT: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to void (i8*)* -// BLOCKS-NEXT: call void [[TMP1]](i8* noundef bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to i8*)) +// BLOCKS-NEXT: store i32 0, ptr [[RETVAL]], align 4 +// BLOCKS-NEXT: [[TMP0:%.*]] = load ptr, ptr getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr @__block_literal_global, i32 0, i32 3), align 8 +// BLOCKS-NEXT: call void [[TMP0]](ptr noundef @__block_literal_global) // BLOCKS-NEXT: ret i32 0 // // // BLOCKS-LABEL: define {{[^@]+}}@__main_block_invoke -// BLOCKS-SAME: (i8* noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] { +// BLOCKS-SAME: (ptr noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] { // BLOCKS-NEXT: entry: -// BLOCKS-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// BLOCKS-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*, align 8 -// BLOCKS-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// BLOCKS-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* -// BLOCKS-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>** [[BLOCK_ADDR]], align 8 -// BLOCKS-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @__main_block_invoke.omp_outlined to void (i32*, i32*, ...)*)) +// BLOCKS-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 8 +// BLOCKS-NEXT: [[BLOCK_ADDR:%.*]] = alloca ptr, align 8 +// BLOCKS-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 +// BLOCKS-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 8 +// BLOCKS-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 0, ptr @__main_block_invoke.omp_outlined) // BLOCKS-NEXT: ret void // // // BLOCKS-LABEL: define {{[^@]+}}@__main_block_invoke.omp_outlined -// BLOCKS-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { +// BLOCKS-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { // BLOCKS-NEXT: entry: -// BLOCKS-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// BLOCKS-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// BLOCKS-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 +// BLOCKS-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 // BLOCKS-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 // BLOCKS-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// BLOCKS-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// BLOCKS-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// BLOCKS-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// BLOCKS-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 -// BLOCKS-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// BLOCKS-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// BLOCKS-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 +// BLOCKS-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// BLOCKS-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 +// BLOCKS-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB1]], i32 [[TMP1]]) // BLOCKS-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 // BLOCKS-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] // BLOCKS: omp_if.then: -// BLOCKS-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// BLOCKS-NEXT: [[TMP4:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i64 96, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*)) -// BLOCKS-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to %struct.kmp_task_t_with_privates* -// BLOCKS-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP5]], i32 0, i32 0 -// BLOCKS-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP5]], i32 0, i32 1 -// BLOCKS-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP7]], i32 0, i32 0 -// BLOCKS-NEXT: [[TMP9:%.*]] = load volatile double, double* @g, align 8 -// BLOCKS-NEXT: store volatile double [[TMP9]], double* [[TMP8]], align 8 -// BLOCKS-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP7]], i32 0, i32 1 -// BLOCKS-NEXT: [[TMP11:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 -// BLOCKS-NEXT: store i32 [[TMP11]], i32* [[TMP10]], align 8 -// BLOCKS-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP6]], i32 0, i32 5 -// BLOCKS-NEXT: store i64 0, i64* [[TMP12]], align 8 -// BLOCKS-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP6]], i32 0, i32 6 -// BLOCKS-NEXT: store i64 9, i64* [[TMP13]], align 8 -// BLOCKS-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP6]], i32 0, i32 7 -// BLOCKS-NEXT: store i64 1, i64* [[TMP14]], align 8 -// BLOCKS-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP6]], i32 0, i32 9 -// BLOCKS-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i8* -// BLOCKS-NEXT: call void @llvm.memset.p0i8.i64(i8* align 8 [[TMP16]], i8 0, i64 8, i1 false) -// BLOCKS-NEXT: [[TMP17:%.*]] = load i64, i64* [[TMP14]], align 8 -// BLOCKS-NEXT: call void @__kmpc_taskloop(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* [[TMP4]], i32 1, i64* [[TMP12]], i64* [[TMP13]], i64 [[TMP17]], i32 1, i32 0, i64 0, i8* null) -// BLOCKS-NEXT: call void @__kmpc_end_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) -// BLOCKS-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) +// BLOCKS-NEXT: call void @__kmpc_taskgroup(ptr @[[GLOB1]], i32 [[TMP1]]) +// BLOCKS-NEXT: [[TMP4:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i64 96, i64 1, ptr @.omp_task_entry.) +// BLOCKS-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP4]], i32 0, i32 0 +// BLOCKS-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP4]], i32 0, i32 1 +// BLOCKS-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP6]], i32 0, i32 0 +// BLOCKS-NEXT: [[TMP8:%.*]] = load volatile double, ptr @g, align 8 +// BLOCKS-NEXT: store volatile double [[TMP8]], ptr [[TMP7]], align 8 +// BLOCKS-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP6]], i32 0, i32 1 +// BLOCKS-NEXT: [[TMP10:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4 +// BLOCKS-NEXT: store i32 [[TMP10]], ptr [[TMP9]], align 8 +// BLOCKS-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP5]], i32 0, i32 5 +// BLOCKS-NEXT: store i64 0, ptr [[TMP11]], align 8 +// BLOCKS-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP5]], i32 0, i32 6 +// BLOCKS-NEXT: store i64 9, ptr [[TMP12]], align 8 +// BLOCKS-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP5]], i32 0, i32 7 +// BLOCKS-NEXT: store i64 1, ptr [[TMP13]], align 8 +// BLOCKS-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP5]], i32 0, i32 9 +// BLOCKS-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP14]], i8 0, i64 8, i1 false) +// BLOCKS-NEXT: [[TMP15:%.*]] = load i64, ptr [[TMP13]], align 8 +// BLOCKS-NEXT: call void @__kmpc_taskloop(ptr @[[GLOB1]], i32 [[TMP1]], ptr [[TMP4]], i32 1, ptr [[TMP11]], ptr [[TMP12]], i64 [[TMP15]], i32 1, i32 0, i64 0, ptr null) +// BLOCKS-NEXT: call void @__kmpc_end_taskgroup(ptr @[[GLOB1]], i32 [[TMP1]]) +// BLOCKS-NEXT: call void @__kmpc_end_master(ptr @[[GLOB1]], i32 [[TMP1]]) // BLOCKS-NEXT: br label [[OMP_IF_END]] // BLOCKS: omp_if.end: // BLOCKS-NEXT: ret void // // // BLOCKS-LABEL: define {{[^@]+}}@_block_invoke -// BLOCKS-SAME: (i8* noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { +// BLOCKS-SAME: (ptr noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { // BLOCKS-NEXT: entry: -// BLOCKS-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// BLOCKS-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>*, align 8 -// BLOCKS-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// BLOCKS-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* -// BLOCKS-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>** [[BLOCK_ADDR]], align 8 -// BLOCKS-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK]], i32 0, i32 5 -// BLOCKS-NEXT: store double 2.000000e+00, double* [[BLOCK_CAPTURE_ADDR]], align 8 -// BLOCKS-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK]], i32 0, i32 6 -// BLOCKS-NEXT: store i32 22, i32* [[BLOCK_CAPTURE_ADDR1]], align 8 +// BLOCKS-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 8 +// BLOCKS-NEXT: [[BLOCK_ADDR:%.*]] = alloca ptr, align 8 +// BLOCKS-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 +// BLOCKS-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 8 +// BLOCKS-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 5 +// BLOCKS-NEXT: store double 2.000000e+00, ptr [[BLOCK_CAPTURE_ADDR]], align 8 +// BLOCKS-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 6 +// BLOCKS-NEXT: store i32 22, ptr [[BLOCK_CAPTURE_ADDR1]], align 8 // BLOCKS-NEXT: ret void // // // BLOCKS-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// BLOCKS-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], double** noalias noundef [[TMP1:%.*]], i32** noalias noundef [[TMP2:%.*]]) #[[ATTR6:[0-9]+]] { +// BLOCKS-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]]) #[[ATTR6:[0-9]+]] { // BLOCKS-NEXT: entry: -// BLOCKS-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 -// BLOCKS-NEXT: [[DOTADDR1:%.*]] = alloca double**, align 8 -// BLOCKS-NEXT: [[DOTADDR2:%.*]] = alloca i32**, align 8 -// BLOCKS-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8 -// BLOCKS-NEXT: store double** [[TMP1]], double*** [[DOTADDR1]], align 8 -// BLOCKS-NEXT: store i32** [[TMP2]], i32*** [[DOTADDR2]], align 8 -// BLOCKS-NEXT: [[TMP3:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8 -// BLOCKS-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP3]], i32 0, i32 0 -// BLOCKS-NEXT: [[TMP5:%.*]] = load double**, double*** [[DOTADDR1]], align 8 -// BLOCKS-NEXT: store double* [[TMP4]], double** [[TMP5]], align 8 -// BLOCKS-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP3]], i32 0, i32 1 -// BLOCKS-NEXT: [[TMP7:%.*]] = load i32**, i32*** [[DOTADDR2]], align 8 -// BLOCKS-NEXT: store i32* [[TMP6]], i32** [[TMP7]], align 8 +// BLOCKS-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 +// BLOCKS-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// BLOCKS-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8 +// BLOCKS-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 +// BLOCKS-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// BLOCKS-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2]], align 8 +// BLOCKS-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR]], align 8 +// BLOCKS-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP3]], i32 0, i32 0 +// BLOCKS-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 +// BLOCKS-NEXT: store ptr [[TMP4]], ptr [[TMP5]], align 8 +// BLOCKS-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP3]], i32 0, i32 1 +// BLOCKS-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTADDR2]], align 8 +// BLOCKS-NEXT: store ptr [[TMP6]], ptr [[TMP7]], align 8 // BLOCKS-NEXT: ret void // // // BLOCKS-LABEL: define {{[^@]+}}@.omp_task_entry. -// BLOCKS-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { +// BLOCKS-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { // BLOCKS-NEXT: entry: // BLOCKS-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 -// BLOCKS-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 -// BLOCKS-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 -// BLOCKS-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 -// BLOCKS-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 +// BLOCKS-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8 +// BLOCKS-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8 +// BLOCKS-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8 +// BLOCKS-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8 // BLOCKS-NEXT: [[DOTLB__ADDR_I:%.*]] = alloca i64, align 8 // BLOCKS-NEXT: [[DOTUB__ADDR_I:%.*]] = alloca i64, align 8 // BLOCKS-NEXT: [[DOTST__ADDR_I:%.*]] = alloca i64, align 8 // BLOCKS-NEXT: [[DOTLITER__ADDR_I:%.*]] = alloca i32, align 4 -// BLOCKS-NEXT: [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca i8*, align 8 -// BLOCKS-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 -// BLOCKS-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca double*, align 8 -// BLOCKS-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca i32*, align 8 +// BLOCKS-NEXT: [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca ptr, align 8 +// BLOCKS-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8 +// BLOCKS-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca ptr, align 8 +// BLOCKS-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca ptr, align 8 // BLOCKS-NEXT: [[I_I:%.*]] = alloca i32, align 4 // BLOCKS-NEXT: [[DOTOMP_IV_I:%.*]] = alloca i32, align 4 -// BLOCKS-NEXT: [[BLOCK_I:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, align 8 +// BLOCKS-NEXT: [[BLOCK_I:%.*]] = alloca <{ ptr, i32, i32, ptr, ptr, double, i32 }>, align 8 // BLOCKS-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 -// BLOCKS-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 -// BLOCKS-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 -// BLOCKS-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 -// BLOCKS-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 -// BLOCKS-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 -// BLOCKS-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 -// BLOCKS-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 -// BLOCKS-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 -// BLOCKS-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 -// BLOCKS-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* -// BLOCKS-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 -// BLOCKS-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* -// BLOCKS-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* -// BLOCKS-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 5 -// BLOCKS-NEXT: [[TMP13:%.*]] = load i64, i64* [[TMP12]], align 8 -// BLOCKS-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 6 -// BLOCKS-NEXT: [[TMP15:%.*]] = load i64, i64* [[TMP14]], align 8 -// BLOCKS-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 7 -// BLOCKS-NEXT: [[TMP17:%.*]] = load i64, i64* [[TMP16]], align 8 -// BLOCKS-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 8 -// BLOCKS-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 8 -// BLOCKS-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 9 -// BLOCKS-NEXT: [[TMP21:%.*]] = load i8*, i8** [[TMP20]], align 8 +// BLOCKS-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// BLOCKS-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 +// BLOCKS-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// BLOCKS-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 +// BLOCKS-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 +// BLOCKS-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0 +// BLOCKS-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 +// BLOCKS-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 +// BLOCKS-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// BLOCKS-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 1 +// BLOCKS-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 5 +// BLOCKS-NEXT: [[TMP10:%.*]] = load i64, ptr [[TMP9]], align 8 +// BLOCKS-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 6 +// BLOCKS-NEXT: [[TMP12:%.*]] = load i64, ptr [[TMP11]], align 8 +// BLOCKS-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 7 +// BLOCKS-NEXT: [[TMP14:%.*]] = load i64, ptr [[TMP13]], align 8 +// BLOCKS-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 8 +// BLOCKS-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 8 +// BLOCKS-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 9 +// BLOCKS-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8 // BLOCKS-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]]) // BLOCKS-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]]) // BLOCKS-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]]) // BLOCKS-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]]) // BLOCKS-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]]) -// BLOCKS-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14 -// BLOCKS-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !14 -// BLOCKS-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14 -// BLOCKS-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, double**, i32**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14 -// BLOCKS-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !14 -// BLOCKS-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !14 -// BLOCKS-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !14 -// BLOCKS-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !14 -// BLOCKS-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !14 -// BLOCKS-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !14 -// BLOCKS-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14 -// BLOCKS-NEXT: [[TMP22:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14 -// BLOCKS-NEXT: [[TMP23:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14 -// BLOCKS-NEXT: [[TMP24:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14 -// BLOCKS-NEXT: [[TMP25:%.*]] = bitcast void (i8*, ...)* [[TMP23]] to void (i8*, double**, i32**)* -// BLOCKS-NEXT: call void [[TMP25]](i8* [[TMP24]], double** [[DOTFIRSTPRIV_PTR_ADDR_I]], i32** [[DOTFIRSTPRIV_PTR_ADDR1_I]]) #[[ATTR4:[0-9]+]] -// BLOCKS-NEXT: [[TMP26:%.*]] = load double*, double** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !14 -// BLOCKS-NEXT: [[TMP27:%.*]] = load i32*, i32** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !14 -// BLOCKS-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTLB__ADDR_I]], align 8, !noalias !14 -// BLOCKS-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP28]] to i32 -// BLOCKS-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14 +// BLOCKS-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14 +// BLOCKS-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias !14 +// BLOCKS-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14 +// BLOCKS-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14 +// BLOCKS-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias !14 +// BLOCKS-NEXT: store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias !14 +// BLOCKS-NEXT: store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias !14 +// BLOCKS-NEXT: store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias !14 +// BLOCKS-NEXT: store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias !14 +// BLOCKS-NEXT: store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !14 +// BLOCKS-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias !14 +// BLOCKS-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias !14 +// BLOCKS-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14 +// BLOCKS-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14 +// BLOCKS-NEXT: call void [[TMP20]](ptr [[TMP21]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]]) #[[ATTR4:[0-9]+]] +// BLOCKS-NEXT: [[TMP22:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !14 +// BLOCKS-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !14 +// BLOCKS-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias !14 +// BLOCKS-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP24]] to i32 +// BLOCKS-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias !14 // BLOCKS-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]] // BLOCKS: omp.inner.for.cond.i: -// BLOCKS-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group [[ACC_GRP15:![0-9]+]] -// BLOCKS-NEXT: [[CONV2_I:%.*]] = sext i32 [[TMP29]] to i64 -// BLOCKS-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTUB__ADDR_I]], align 8, !noalias !14, !llvm.access.group [[ACC_GRP15]] -// BLOCKS-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV2_I]], [[TMP30]] +// BLOCKS-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group [[ACC_GRP15:![0-9]+]] +// BLOCKS-NEXT: [[CONV2_I:%.*]] = sext i32 [[TMP25]] to i64 +// BLOCKS-NEXT: [[TMP26:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias !14, !llvm.access.group [[ACC_GRP15]] +// BLOCKS-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV2_I]], [[TMP26]] // BLOCKS-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]] // BLOCKS: omp.inner.for.body.i: -// BLOCKS-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group [[ACC_GRP15]] -// BLOCKS-NEXT: store i32 [[TMP31]], i32* [[I_I]], align 4, !noalias !14, !llvm.access.group [[ACC_GRP15]] -// BLOCKS-NEXT: store double 1.000000e+00, double* [[TMP26]], align 8, !llvm.access.group [[ACC_GRP15]] -// BLOCKS-NEXT: store i32 11, i32* [[TMP27]], align 4, !llvm.access.group [[ACC_GRP15]] -// BLOCKS-NEXT: [[BLOCK_ISA_I:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK_I]], i32 0, i32 0 -// BLOCKS-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA_I]], align 8, !noalias !14, !llvm.access.group [[ACC_GRP15]] -// BLOCKS-NEXT: [[BLOCK_FLAGS_I:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK_I]], i32 0, i32 1 -// BLOCKS-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS_I]], align 8, !noalias !14, !llvm.access.group [[ACC_GRP15]] -// BLOCKS-NEXT: [[BLOCK_RESERVED_I:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK_I]], i32 0, i32 2 -// BLOCKS-NEXT: store i32 0, i32* [[BLOCK_RESERVED_I]], align 4, !noalias !14, !llvm.access.group [[ACC_GRP15]] -// BLOCKS-NEXT: [[BLOCK_INVOKE_I:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK_I]], i32 0, i32 3 -// BLOCKS-NEXT: store i8* bitcast (void (i8*)* @_block_invoke to i8*), i8** [[BLOCK_INVOKE_I]], align 8, !noalias !14, !llvm.access.group [[ACC_GRP15]] -// BLOCKS-NEXT: [[BLOCK_DESCRIPTOR_I:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK_I]], i32 0, i32 4 -// BLOCKS-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.1 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR_I]], align 8, !noalias !14, !llvm.access.group [[ACC_GRP15]] -// BLOCKS-NEXT: [[BLOCK_CAPTURED_I:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK_I]], i32 0, i32 5 -// BLOCKS-NEXT: [[TMP32:%.*]] = load volatile double, double* [[TMP26]], align 8, !llvm.access.group [[ACC_GRP15]] -// BLOCKS-NEXT: store volatile double [[TMP32]], double* [[BLOCK_CAPTURED_I]], align 8, !noalias !14, !llvm.access.group [[ACC_GRP15]] -// BLOCKS-NEXT: [[BLOCK_CAPTURED3_I:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK_I]], i32 0, i32 6 -// BLOCKS-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP27]], align 4, !llvm.access.group [[ACC_GRP15]] -// BLOCKS-NEXT: store i32 [[TMP33]], i32* [[BLOCK_CAPTURED3_I]], align 8, !noalias !14, !llvm.access.group [[ACC_GRP15]] -// BLOCKS-NEXT: [[TMP34:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK_I]] to void ()* -// BLOCKS-NEXT: [[BLOCK_LITERAL_I:%.*]] = bitcast void ()* [[TMP34]] to %struct.__block_literal_generic* -// BLOCKS-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL_I]], i32 0, i32 3 -// BLOCKS-NEXT: [[TMP36:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL_I]] to i8* -// BLOCKS-NEXT: [[TMP37:%.*]] = load i8*, i8** [[TMP35]], align 8, !noalias !14, !llvm.access.group [[ACC_GRP15]] -// BLOCKS-NEXT: [[TMP38:%.*]] = bitcast i8* [[TMP37]] to void (i8*)* -// BLOCKS-NEXT: call void [[TMP38]](i8* noundef [[TMP36]]) #[[ATTR4]], !llvm.access.group [[ACC_GRP15]] -// BLOCKS-NEXT: [[TMP39:%.*]] = load i32, i32* [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group [[ACC_GRP15]] -// BLOCKS-NEXT: [[ADD4_I:%.*]] = add nsw i32 [[TMP39]], 1 -// BLOCKS-NEXT: store i32 [[ADD4_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group [[ACC_GRP15]] +// BLOCKS-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group [[ACC_GRP15]] +// BLOCKS-NEXT: store i32 [[TMP27]], ptr [[I_I]], align 4, !noalias !14, !llvm.access.group [[ACC_GRP15]] +// BLOCKS-NEXT: store double 1.000000e+00, ptr [[TMP22]], align 8, !llvm.access.group [[ACC_GRP15]] +// BLOCKS-NEXT: store i32 11, ptr [[TMP23]], align 4, !llvm.access.group [[ACC_GRP15]] +// BLOCKS-NEXT: store ptr @_NSConcreteStackBlock, ptr [[BLOCK_I]], align 8, !noalias !14, !llvm.access.group [[ACC_GRP15]] +// BLOCKS-NEXT: [[BLOCK_FLAGS_I:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK_I]], i32 0, i32 1 +// BLOCKS-NEXT: store i32 1073741824, ptr [[BLOCK_FLAGS_I]], align 8, !noalias !14, !llvm.access.group [[ACC_GRP15]] +// BLOCKS-NEXT: [[BLOCK_RESERVED_I:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK_I]], i32 0, i32 2 +// BLOCKS-NEXT: store i32 0, ptr [[BLOCK_RESERVED_I]], align 4, !noalias !14, !llvm.access.group [[ACC_GRP15]] +// BLOCKS-NEXT: [[BLOCK_INVOKE_I:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK_I]], i32 0, i32 3 +// BLOCKS-NEXT: store ptr @_block_invoke, ptr [[BLOCK_INVOKE_I]], align 8, !noalias !14, !llvm.access.group [[ACC_GRP15]] +// BLOCKS-NEXT: [[BLOCK_DESCRIPTOR_I:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK_I]], i32 0, i32 4 +// BLOCKS-NEXT: store ptr @__block_descriptor_tmp.1, ptr [[BLOCK_DESCRIPTOR_I]], align 8, !noalias !14, !llvm.access.group [[ACC_GRP15]] +// BLOCKS-NEXT: [[BLOCK_CAPTURED_I:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK_I]], i32 0, i32 5 +// BLOCKS-NEXT: [[TMP28:%.*]] = load volatile double, ptr [[TMP22]], align 8, !llvm.access.group [[ACC_GRP15]] +// BLOCKS-NEXT: store volatile double [[TMP28]], ptr [[BLOCK_CAPTURED_I]], align 8, !noalias !14, !llvm.access.group [[ACC_GRP15]] +// BLOCKS-NEXT: [[BLOCK_CAPTURED3_I:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK_I]], i32 0, i32 6 +// BLOCKS-NEXT: [[TMP29:%.*]] = load i32, ptr [[TMP23]], align 4, !llvm.access.group [[ACC_GRP15]] +// BLOCKS-NEXT: store i32 [[TMP29]], ptr [[BLOCK_CAPTURED3_I]], align 8, !noalias !14, !llvm.access.group [[ACC_GRP15]] +// BLOCKS-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr [[BLOCK_I]], i32 0, i32 3 +// BLOCKS-NEXT: [[TMP31:%.*]] = load ptr, ptr [[TMP30]], align 8, !noalias !14, !llvm.access.group [[ACC_GRP15]] +// BLOCKS-NEXT: call void [[TMP31]](ptr noundef [[BLOCK_I]]) #[[ATTR4]], !llvm.access.group [[ACC_GRP15]] +// BLOCKS-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group [[ACC_GRP15]] +// BLOCKS-NEXT: [[ADD4_I:%.*]] = add nsw i32 [[TMP32]], 1 +// BLOCKS-NEXT: store i32 [[ADD4_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group [[ACC_GRP15]] // BLOCKS-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP16:![0-9]+]] // BLOCKS: .omp_outlined..exit: // BLOCKS-NEXT: ret i32 0 // // // ARRAY-LABEL: define {{[^@]+}}@_Z10array_funciPfP2St -// ARRAY-SAME: (i32 noundef [[N:%.*]], float* noundef [[A:%.*]], %struct.St* noundef [[S:%.*]]) #[[ATTR0:[0-9]+]] { +// ARRAY-SAME: (i32 noundef [[N:%.*]], ptr noundef [[A:%.*]], ptr noundef [[S:%.*]]) #[[ATTR0:[0-9]+]] { // ARRAY-NEXT: entry: // ARRAY-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// ARRAY-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// ARRAY-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 -// ARRAY-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// ARRAY-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// ARRAY-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 -// ARRAY-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// ARRAY-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 +// ARRAY-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 +// ARRAY-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// ARRAY-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 +// ARRAY-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 +// ARRAY-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // ARRAY-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// ARRAY-NEXT: [[TMP2:%.*]] = load float*, float** [[A_ADDR]], align 8 -// ARRAY-NEXT: [[TMP3:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 -// ARRAY-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, float*, %struct.St*)* @_Z10array_funciPfP2St.omp_outlined to void (i32*, i32*, ...)*), i64 [[TMP1]], float* [[TMP2]], %struct.St* [[TMP3]]) +// ARRAY-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// ARRAY-NEXT: [[TMP3:%.*]] = load ptr, ptr [[S_ADDR]], align 8 +// ARRAY-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 3, ptr @_Z10array_funciPfP2St.omp_outlined, i64 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]]) // ARRAY-NEXT: ret void // // // ARRAY-LABEL: define {{[^@]+}}@_Z10array_funciPfP2St.omp_outlined -// ARRAY-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], float* noundef [[A:%.*]], %struct.St* noundef [[S:%.*]]) #[[ATTR1:[0-9]+]] { +// ARRAY-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], ptr noundef [[A:%.*]], ptr noundef [[S:%.*]]) #[[ATTR1:[0-9]+]] { // ARRAY-NEXT: entry: -// ARRAY-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 -// ARRAY-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 +// ARRAY-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 +// ARRAY-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 // ARRAY-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// ARRAY-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// ARRAY-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 +// ARRAY-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 +// ARRAY-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // ARRAY-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 8 // ARRAY-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// ARRAY-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// ARRAY-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 -// ARRAY-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// ARRAY-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// ARRAY-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 -// ARRAY-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// ARRAY-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 -// ARRAY-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 -// ARRAY-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// ARRAY-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// ARRAY-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 +// ARRAY-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 +// ARRAY-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 +// ARRAY-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 +// ARRAY-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 +// ARRAY-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// ARRAY-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// ARRAY-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB1]], i32 [[TMP2]]) // ARRAY-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 // ARRAY-NEXT: br i1 [[TMP4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] // ARRAY: omp_if.then: -// ARRAY-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 -// ARRAY-NEXT: store i64 [[TMP0]], i64* [[TMP5]], align 8 -// ARRAY-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// ARRAY-NEXT: [[TMP6:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1, i64 96, i64 8, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*)) -// ARRAY-NEXT: [[TMP7:%.*]] = bitcast i8* [[TMP6]] to %struct.kmp_task_t_with_privates* -// ARRAY-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP7]], i32 0, i32 0 -// ARRAY-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP8]], i32 0, i32 0 -// ARRAY-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 -// ARRAY-NEXT: [[TMP11:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* -// ARRAY-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP10]], i8* align 8 [[TMP11]], i64 8, i1 false) -// ARRAY-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP7]], i32 0, i32 1 -// ARRAY-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP12]], i32 0, i32 0 -// ARRAY-NEXT: [[TMP14:%.*]] = load float*, float** [[A_ADDR]], align 8 -// ARRAY-NEXT: store float* [[TMP14]], float** [[TMP13]], align 8 -// ARRAY-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP12]], i32 0, i32 1 -// ARRAY-NEXT: [[TMP16:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 -// ARRAY-NEXT: store %struct.St* [[TMP16]], %struct.St** [[TMP15]], align 8 -// ARRAY-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP8]], i32 0, i32 5 -// ARRAY-NEXT: store i64 0, i64* [[TMP17]], align 8 -// ARRAY-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP8]], i32 0, i32 6 -// ARRAY-NEXT: store i64 9, i64* [[TMP18]], align 8 -// ARRAY-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP8]], i32 0, i32 7 -// ARRAY-NEXT: store i64 1, i64* [[TMP19]], align 8 -// ARRAY-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP8]], i32 0, i32 9 -// ARRAY-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i8* -// ARRAY-NEXT: call void @llvm.memset.p0i8.i64(i8* align 8 [[TMP21]], i8 0, i64 8, i1 false) -// ARRAY-NEXT: [[TMP22:%.*]] = load i64, i64* [[TMP19]], align 8 -// ARRAY-NEXT: call void @__kmpc_taskloop(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i8* [[TMP6]], i32 1, i64* [[TMP17]], i64* [[TMP18]], i64 [[TMP22]], i32 1, i32 0, i64 0, i8* null) -// ARRAY-NEXT: call void @__kmpc_end_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) -// ARRAY-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) +// ARRAY-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0 +// ARRAY-NEXT: store i64 [[TMP0]], ptr [[TMP5]], align 8 +// ARRAY-NEXT: call void @__kmpc_taskgroup(ptr @[[GLOB1]], i32 [[TMP2]]) +// ARRAY-NEXT: [[TMP6:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP2]], i32 1, i64 96, i64 8, ptr @.omp_task_entry.) +// ARRAY-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP6]], i32 0, i32 0 +// ARRAY-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP7]], i32 0, i32 0 +// ARRAY-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 +// ARRAY-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP9]], ptr align 8 [[AGG_CAPTURED]], i64 8, i1 false) +// ARRAY-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP6]], i32 0, i32 1 +// ARRAY-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP10]], i32 0, i32 0 +// ARRAY-NEXT: [[TMP12:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// ARRAY-NEXT: store ptr [[TMP12]], ptr [[TMP11]], align 8 +// ARRAY-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP10]], i32 0, i32 1 +// ARRAY-NEXT: [[TMP14:%.*]] = load ptr, ptr [[S_ADDR]], align 8 +// ARRAY-NEXT: store ptr [[TMP14]], ptr [[TMP13]], align 8 +// ARRAY-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP7]], i32 0, i32 5 +// ARRAY-NEXT: store i64 0, ptr [[TMP15]], align 8 +// ARRAY-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP7]], i32 0, i32 6 +// ARRAY-NEXT: store i64 9, ptr [[TMP16]], align 8 +// ARRAY-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP7]], i32 0, i32 7 +// ARRAY-NEXT: store i64 1, ptr [[TMP17]], align 8 +// ARRAY-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP7]], i32 0, i32 9 +// ARRAY-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP18]], i8 0, i64 8, i1 false) +// ARRAY-NEXT: [[TMP19:%.*]] = load i64, ptr [[TMP17]], align 8 +// ARRAY-NEXT: call void @__kmpc_taskloop(ptr @[[GLOB1]], i32 [[TMP2]], ptr [[TMP6]], i32 1, ptr [[TMP15]], ptr [[TMP16]], i64 [[TMP19]], i32 1, i32 0, i64 0, ptr null) +// ARRAY-NEXT: call void @__kmpc_end_taskgroup(ptr @[[GLOB1]], i32 [[TMP2]]) +// ARRAY-NEXT: call void @__kmpc_end_master(ptr @[[GLOB1]], i32 [[TMP2]]) // ARRAY-NEXT: br label [[OMP_IF_END]] // ARRAY: omp_if.end: // ARRAY-NEXT: ret void // // // ARRAY-LABEL: define {{[^@]+}}@.omp_task_privates_map. -// ARRAY-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], float*** noalias noundef [[TMP1:%.*]], %struct.St*** noalias noundef [[TMP2:%.*]]) #[[ATTR4:[0-9]+]] { +// ARRAY-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]]) #[[ATTR4:[0-9]+]] { // ARRAY-NEXT: entry: -// ARRAY-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 -// ARRAY-NEXT: [[DOTADDR1:%.*]] = alloca float***, align 8 -// ARRAY-NEXT: [[DOTADDR2:%.*]] = alloca %struct.St***, align 8 -// ARRAY-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8 -// ARRAY-NEXT: store float*** [[TMP1]], float**** [[DOTADDR1]], align 8 -// ARRAY-NEXT: store %struct.St*** [[TMP2]], %struct.St**** [[DOTADDR2]], align 8 -// ARRAY-NEXT: [[TMP3:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8 -// ARRAY-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP3]], i32 0, i32 0 -// ARRAY-NEXT: [[TMP5:%.*]] = load float***, float**** [[DOTADDR1]], align 8 -// ARRAY-NEXT: store float** [[TMP4]], float*** [[TMP5]], align 8 -// ARRAY-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP3]], i32 0, i32 1 -// ARRAY-NEXT: [[TMP7:%.*]] = load %struct.St***, %struct.St**** [[DOTADDR2]], align 8 -// ARRAY-NEXT: store %struct.St** [[TMP6]], %struct.St*** [[TMP7]], align 8 +// ARRAY-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 +// ARRAY-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// ARRAY-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8 +// ARRAY-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 +// ARRAY-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// ARRAY-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2]], align 8 +// ARRAY-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR]], align 8 +// ARRAY-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP3]], i32 0, i32 0 +// ARRAY-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 +// ARRAY-NEXT: store ptr [[TMP4]], ptr [[TMP5]], align 8 +// ARRAY-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP3]], i32 0, i32 1 +// ARRAY-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTADDR2]], align 8 +// ARRAY-NEXT: store ptr [[TMP6]], ptr [[TMP7]], align 8 // ARRAY-NEXT: ret void // // // ARRAY-LABEL: define {{[^@]+}}@.omp_task_entry. -// ARRAY-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// ARRAY-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { // ARRAY-NEXT: entry: // ARRAY-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 -// ARRAY-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 -// ARRAY-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 -// ARRAY-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 -// ARRAY-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 +// ARRAY-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8 +// ARRAY-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8 +// ARRAY-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8 +// ARRAY-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8 // ARRAY-NEXT: [[DOTLB__ADDR_I:%.*]] = alloca i64, align 8 // ARRAY-NEXT: [[DOTUB__ADDR_I:%.*]] = alloca i64, align 8 // ARRAY-NEXT: [[DOTST__ADDR_I:%.*]] = alloca i64, align 8 // ARRAY-NEXT: [[DOTLITER__ADDR_I:%.*]] = alloca i32, align 4 -// ARRAY-NEXT: [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca i8*, align 8 -// ARRAY-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 -// ARRAY-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca float**, align 8 -// ARRAY-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca %struct.St**, align 8 +// ARRAY-NEXT: [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca ptr, align 8 +// ARRAY-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8 +// ARRAY-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca ptr, align 8 +// ARRAY-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca ptr, align 8 // ARRAY-NEXT: [[I_I:%.*]] = alloca i32, align 4 // ARRAY-NEXT: [[DOTOMP_IV_I:%.*]] = alloca i32, align 4 // ARRAY-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 -// ARRAY-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 -// ARRAY-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 -// ARRAY-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 -// ARRAY-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 -// ARRAY-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 -// ARRAY-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 -// ARRAY-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 -// ARRAY-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 -// ARRAY-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 -// ARRAY-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* -// ARRAY-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 -// ARRAY-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* -// ARRAY-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* -// ARRAY-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 5 -// ARRAY-NEXT: [[TMP13:%.*]] = load i64, i64* [[TMP12]], align 8 -// ARRAY-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 6 -// ARRAY-NEXT: [[TMP15:%.*]] = load i64, i64* [[TMP14]], align 8 -// ARRAY-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 7 -// ARRAY-NEXT: [[TMP17:%.*]] = load i64, i64* [[TMP16]], align 8 -// ARRAY-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 8 -// ARRAY-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 8 -// ARRAY-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 9 -// ARRAY-NEXT: [[TMP21:%.*]] = load i8*, i8** [[TMP20]], align 8 +// ARRAY-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// ARRAY-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 +// ARRAY-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// ARRAY-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 +// ARRAY-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 +// ARRAY-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0 +// ARRAY-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 +// ARRAY-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 +// ARRAY-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// ARRAY-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 1 +// ARRAY-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 5 +// ARRAY-NEXT: [[TMP10:%.*]] = load i64, ptr [[TMP9]], align 8 +// ARRAY-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 6 +// ARRAY-NEXT: [[TMP12:%.*]] = load i64, ptr [[TMP11]], align 8 +// ARRAY-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 7 +// ARRAY-NEXT: [[TMP14:%.*]] = load i64, ptr [[TMP13]], align 8 +// ARRAY-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 8 +// ARRAY-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 8 +// ARRAY-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 9 +// ARRAY-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8 // ARRAY-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]]) // ARRAY-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]]) // ARRAY-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]]) // ARRAY-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]]) // ARRAY-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]]) -// ARRAY-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14 -// ARRAY-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !14 -// ARRAY-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14 -// ARRAY-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, float***, %struct.St***)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14 -// ARRAY-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !14 -// ARRAY-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !14 -// ARRAY-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !14 -// ARRAY-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !14 -// ARRAY-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !14 -// ARRAY-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !14 -// ARRAY-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14 -// ARRAY-NEXT: [[TMP22:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14 -// ARRAY-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP22]], i32 0, i32 0 -// ARRAY-NEXT: [[TMP24:%.*]] = load i64, i64* [[TMP23]], align 8 -// ARRAY-NEXT: [[TMP25:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14 -// ARRAY-NEXT: [[TMP26:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14 -// ARRAY-NEXT: [[TMP27:%.*]] = bitcast void (i8*, ...)* [[TMP25]] to void (i8*, float***, %struct.St***)* -// ARRAY-NEXT: call void [[TMP27]](i8* [[TMP26]], float*** [[DOTFIRSTPRIV_PTR_ADDR_I]], %struct.St*** [[DOTFIRSTPRIV_PTR_ADDR1_I]]) #[[ATTR2:[0-9]+]] -// ARRAY-NEXT: [[TMP28:%.*]] = load float**, float*** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !14 -// ARRAY-NEXT: [[TMP29:%.*]] = load %struct.St**, %struct.St*** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !14 -// ARRAY-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTLB__ADDR_I]], align 8, !noalias !14 -// ARRAY-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP30]] to i32 -// ARRAY-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14 +// ARRAY-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14 +// ARRAY-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias !14 +// ARRAY-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14 +// ARRAY-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14 +// ARRAY-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias !14 +// ARRAY-NEXT: store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias !14 +// ARRAY-NEXT: store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias !14 +// ARRAY-NEXT: store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias !14 +// ARRAY-NEXT: store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias !14 +// ARRAY-NEXT: store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !14 +// ARRAY-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias !14 +// ARRAY-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias !14 +// ARRAY-NEXT: [[TMP20:%.*]] = load i64, ptr [[TMP19]], align 8 +// ARRAY-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14 +// ARRAY-NEXT: [[TMP22:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14 +// ARRAY-NEXT: call void [[TMP21]](ptr [[TMP22]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]]) #[[ATTR2:[0-9]+]] +// ARRAY-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !14 +// ARRAY-NEXT: [[TMP24:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !14 +// ARRAY-NEXT: [[TMP25:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias !14 +// ARRAY-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP25]] to i32 +// ARRAY-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias !14 // ARRAY-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]] // ARRAY: omp.inner.for.cond.i: -// ARRAY-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group [[ACC_GRP15:![0-9]+]] -// ARRAY-NEXT: [[CONV2_I:%.*]] = sext i32 [[TMP31]] to i64 -// ARRAY-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTUB__ADDR_I]], align 8, !noalias !14, !llvm.access.group [[ACC_GRP15]] -// ARRAY-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV2_I]], [[TMP32]] +// ARRAY-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group [[ACC_GRP15:![0-9]+]] +// ARRAY-NEXT: [[CONV2_I:%.*]] = sext i32 [[TMP26]] to i64 +// ARRAY-NEXT: [[TMP27:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias !14, !llvm.access.group [[ACC_GRP15]] +// ARRAY-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV2_I]], [[TMP27]] // ARRAY-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]] // ARRAY: omp.inner.for.body.i: -// ARRAY-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group [[ACC_GRP15]] -// ARRAY-NEXT: store i32 [[TMP33]], i32* [[I_I]], align 4, !noalias !14, !llvm.access.group [[ACC_GRP15]] -// ARRAY-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group [[ACC_GRP15]] -// ARRAY-NEXT: [[ADD3_I:%.*]] = add nsw i32 [[TMP34]], 1 -// ARRAY-NEXT: store i32 [[ADD3_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group [[ACC_GRP15]] +// ARRAY-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group [[ACC_GRP15]] +// ARRAY-NEXT: store i32 [[TMP28]], ptr [[I_I]], align 4, !noalias !14, !llvm.access.group [[ACC_GRP15]] +// ARRAY-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group [[ACC_GRP15]] +// ARRAY-NEXT: [[ADD3_I:%.*]] = add nsw i32 [[TMP29]], 1 +// ARRAY-NEXT: store i32 [[ADD3_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group [[ACC_GRP15]] // ARRAY-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP16:![0-9]+]] // ARRAY: .omp_outlined..exit: // ARRAY-NEXT: ret i32 0 @@ -1585,107 +1518,104 @@ void array_func(int n, float a[n], St s[2]) { // SIMD-ONLY0-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 // SIMD-ONLY0-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // SIMD-ONLY0-NEXT: [[I:%.*]] = alloca i32, align 4 -// SIMD-ONLY0-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// SIMD-ONLY0-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[TTT]]) -// SIMD-ONLY0-NEXT: call void @_ZN1SIdEC1ERKS0_d(%struct.S* noundef nonnull align 8 dereferenceable(8) [[TEST]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[TTT]], double noundef 0.000000e+00) -// SIMD-ONLY0-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// SIMD-ONLY0-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// SIMD-ONLY0-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// SIMD-ONLY0-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* noundef nonnull align 8 dereferenceable(8) [[ARRAYINIT_BEGIN]], double noundef 1.000000e+00) -// SIMD-ONLY0-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// SIMD-ONLY0-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* noundef nonnull align 8 dereferenceable(8) [[ARRAYINIT_ELEMENT]], double noundef 2.000000e+00) -// SIMD-ONLY0-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* noundef nonnull align 8 dereferenceable(8) [[VAR]], double noundef 3.000000e+00) -// SIMD-ONLY0-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 -// SIMD-ONLY0-NEXT: store i64 9, i64* [[DOTOMP_UB]], align 8 -// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 -// SIMD-ONLY0-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 -// SIMD-ONLY0-NEXT: store i32 [[CONV]], i32* [[DOTOMP_IV]], align 4 +// SIMD-ONLY0-NEXT: store i32 0, ptr [[RETVAL]], align 4 +// SIMD-ONLY0-NEXT: call void @_ZN1SIdEC1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[TTT]]) +// SIMD-ONLY0-NEXT: call void @_ZN1SIdEC1ERKS0_d(ptr noundef nonnull align 8 dereferenceable(8) [[TEST]], ptr noundef nonnull align 8 dereferenceable(8) [[TTT]], double noundef 0.000000e+00) +// SIMD-ONLY0-NEXT: store i32 0, ptr [[T_VAR]], align 4 +// SIMD-ONLY0-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const.main.vec, i64 8, i1 false) +// SIMD-ONLY0-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 0 +// SIMD-ONLY0-NEXT: call void @_ZN1SIdEC1Ed(ptr noundef nonnull align 8 dereferenceable(8) [[ARRAYINIT_BEGIN]], double noundef 1.000000e+00) +// SIMD-ONLY0-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYINIT_BEGIN]], i64 1 +// SIMD-ONLY0-NEXT: call void @_ZN1SIdEC1Ed(ptr noundef nonnull align 8 dereferenceable(8) [[ARRAYINIT_ELEMENT]], double noundef 2.000000e+00) +// SIMD-ONLY0-NEXT: call void @_ZN1SIdEC1Ed(ptr noundef nonnull align 8 dereferenceable(8) [[VAR]], double noundef 3.000000e+00) +// SIMD-ONLY0-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 +// SIMD-ONLY0-NEXT: store i64 9, ptr [[DOTOMP_UB]], align 8 +// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 +// SIMD-ONLY0-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// SIMD-ONLY0-NEXT: store i32 [[CONV]], ptr [[DOTOMP_IV]], align 4 // SIMD-ONLY0-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // SIMD-ONLY0: omp.inner.for.cond: -// SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]] -// SIMD-ONLY0-NEXT: [[CONV1:%.*]] = sext i32 [[TMP2]] to i64 -// SIMD-ONLY0-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP2]] -// SIMD-ONLY0-NEXT: [[CMP:%.*]] = icmp ule i64 [[CONV1]], [[TMP3]] +// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]] +// SIMD-ONLY0-NEXT: [[CONV1:%.*]] = sext i32 [[TMP1]] to i64 +// SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP2]] +// SIMD-ONLY0-NEXT: [[CMP:%.*]] = icmp ule i64 [[CONV1]], [[TMP2]] // SIMD-ONLY0-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // SIMD-ONLY0: omp.inner.for.body: -// SIMD-ONLY0-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] -// SIMD-ONLY0-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 1 +// SIMD-ONLY0-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] +// SIMD-ONLY0-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 // SIMD-ONLY0-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// SIMD-ONLY0-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group [[ACC_GRP2]] -// SIMD-ONLY0-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP2]] -// SIMD-ONLY0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// SIMD-ONLY0-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]] -// SIMD-ONLY0-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// SIMD-ONLY0-NEXT: [[TMP6:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* -// SIMD-ONLY0-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// SIMD-ONLY0-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP6]], i8* align 8 [[TMP7]], i64 8, i1 false), !llvm.access.group [[ACC_GRP2]] -// SIMD-ONLY0-NEXT: store i32 33, i32* @_ZZ4mainE5sivar, align 4, !llvm.access.group [[ACC_GRP2]] +// SIMD-ONLY0-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] +// SIMD-ONLY0-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP2]] +// SIMD-ONLY0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 0 +// SIMD-ONLY0-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]] +// SIMD-ONLY0-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 0 +// SIMD-ONLY0-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 16 [[ARRAYIDX2]], ptr align 8 [[VAR]], i64 8, i1 false), !llvm.access.group [[ACC_GRP2]] +// SIMD-ONLY0-NEXT: store i32 33, ptr @_ZZ4mainE5sivar, align 4, !llvm.access.group [[ACC_GRP2]] // SIMD-ONLY0-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // SIMD-ONLY0: omp.body.continue: // SIMD-ONLY0-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // SIMD-ONLY0: omp.inner.for.inc: -// SIMD-ONLY0-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] -// SIMD-ONLY0-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 -// SIMD-ONLY0-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] +// SIMD-ONLY0-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] +// SIMD-ONLY0-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP5]], 1 +// SIMD-ONLY0-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] // SIMD-ONLY0-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // SIMD-ONLY0: omp.inner.for.end: -// SIMD-ONLY0-NEXT: store i32 10, i32* [[I]], align 4 +// SIMD-ONLY0-NEXT: store i32 10, ptr [[I]], align 4 // SIMD-ONLY0-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() -// SIMD-ONLY0-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// SIMD-ONLY0-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[VAR]]) #[[ATTR4:[0-9]+]] -// SIMD-ONLY0-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// SIMD-ONLY0-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// SIMD-ONLY0-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 +// SIMD-ONLY0-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[VAR]]) #[[ATTR4:[0-9]+]] +// SIMD-ONLY0-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// SIMD-ONLY0-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // SIMD-ONLY0-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // SIMD-ONLY0: arraydestroy.body: -// SIMD-ONLY0-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// SIMD-ONLY0-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// SIMD-ONLY0-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// SIMD-ONLY0-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// SIMD-ONLY0-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP6]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// SIMD-ONLY0-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// SIMD-ONLY0-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// SIMD-ONLY0-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // SIMD-ONLY0-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] // SIMD-ONLY0: arraydestroy.done4: -// SIMD-ONLY0-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[TEST]]) #[[ATTR4]] -// SIMD-ONLY0-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[TTT]]) #[[ATTR4]] -// SIMD-ONLY0-NEXT: [[TMP10:%.*]] = load i32, i32* [[RETVAL]], align 4 -// SIMD-ONLY0-NEXT: ret i32 [[TMP10]] +// SIMD-ONLY0-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[TEST]]) #[[ATTR4]] +// SIMD-ONLY0-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[TTT]]) #[[ATTR4]] +// SIMD-ONLY0-NEXT: [[TMP7:%.*]] = load i32, ptr [[RETVAL]], align 4 +// SIMD-ONLY0-NEXT: ret i32 [[TMP7]] // // // SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIdEC1Ev -// SIMD-ONLY0-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { +// SIMD-ONLY0-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { // SIMD-ONLY0-NEXT: entry: -// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// SIMD-ONLY0-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// SIMD-ONLY0-NEXT: call void @_ZN1SIdEC2Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS1]]) +// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY0-NEXT: call void @_ZN1SIdEC2Ev(ptr noundef nonnull align 8 dereferenceable(8) [[THIS1]]) // SIMD-ONLY0-NEXT: ret void // // // SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIdEC1ERKS0_d -// SIMD-ONLY0-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[S:%.*]], double noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY0-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[S:%.*]], double noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY0-NEXT: entry: -// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// SIMD-ONLY0-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 +// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// SIMD-ONLY0-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY0-NEXT: [[T_ADDR:%.*]] = alloca double, align 8 -// SIMD-ONLY0-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// SIMD-ONLY0-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 -// SIMD-ONLY0-NEXT: store double [[T]], double* [[T_ADDR]], align 8 -// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 -// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load double, double* [[T_ADDR]], align 8 -// SIMD-ONLY0-NEXT: call void @_ZN1SIdEC2ERKS0_d(%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS1]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[TMP0]], double noundef [[TMP1]]) +// SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY0-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 +// SIMD-ONLY0-NEXT: store double [[T]], ptr [[T_ADDR]], align 8 +// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 +// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load double, ptr [[T_ADDR]], align 8 +// SIMD-ONLY0-NEXT: call void @_ZN1SIdEC2ERKS0_d(ptr noundef nonnull align 8 dereferenceable(8) [[THIS1]], ptr noundef nonnull align 8 dereferenceable(8) [[TMP0]], double noundef [[TMP1]]) // SIMD-ONLY0-NEXT: ret void // // // SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIdEC1Ed -// SIMD-ONLY0-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], double noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY0-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], double noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY0-NEXT: entry: -// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY0-NEXT: [[A_ADDR:%.*]] = alloca double, align 8 -// SIMD-ONLY0-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// SIMD-ONLY0-NEXT: store double [[A]], double* [[A_ADDR]], align 8 -// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load double, double* [[A_ADDR]], align 8 -// SIMD-ONLY0-NEXT: call void @_ZN1SIdEC2Ed(%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS1]], double noundef [[TMP0]]) +// SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY0-NEXT: store double [[A]], ptr [[A_ADDR]], align 8 +// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load double, ptr [[A_ADDR]], align 8 +// SIMD-ONLY0-NEXT: call void @_ZN1SIdEC2Ed(ptr noundef nonnull align 8 dereferenceable(8) [[THIS1]], double noundef [[TMP0]]) // SIMD-ONLY0-NEXT: ret void // // @@ -1704,232 +1634,229 @@ void array_func(int n, float a[n], St s[2]) { // SIMD-ONLY0-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 // SIMD-ONLY0-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // SIMD-ONLY0-NEXT: [[I:%.*]] = alloca i32, align 4 -// SIMD-ONLY0-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TTT]]) -// SIMD-ONLY0-NEXT: call void @_ZN1SIiEC1ERKS0_i(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TTT]], i32 noundef 0) -// SIMD-ONLY0-NEXT: store i32 0, i32* [[T_VAR]], align 128 -// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// SIMD-ONLY0-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// SIMD-ONLY0-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// SIMD-ONLY0-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef 1) -// SIMD-ONLY0-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// SIMD-ONLY0-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) -// SIMD-ONLY0-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]], i32 noundef 3) -// SIMD-ONLY0-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 -// SIMD-ONLY0-NEXT: store i64 9, i64* [[DOTOMP_UB]], align 8 -// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 -// SIMD-ONLY0-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 -// SIMD-ONLY0-NEXT: store i32 [[CONV]], i32* [[DOTOMP_IV]], align 4 +// SIMD-ONLY0-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TTT]]) +// SIMD-ONLY0-NEXT: call void @_ZN1SIiEC1ERKS0_i(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]], ptr noundef nonnull align 4 dereferenceable(4) [[TTT]], i32 noundef 0) +// SIMD-ONLY0-NEXT: store i32 0, ptr [[T_VAR]], align 128 +// SIMD-ONLY0-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false) +// SIMD-ONLY0-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 0 +// SIMD-ONLY0-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef 1) +// SIMD-ONLY0-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYINIT_BEGIN]], i64 1 +// SIMD-ONLY0-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// SIMD-ONLY0-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]], i32 noundef 3) +// SIMD-ONLY0-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 +// SIMD-ONLY0-NEXT: store i64 9, ptr [[DOTOMP_UB]], align 8 +// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 +// SIMD-ONLY0-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// SIMD-ONLY0-NEXT: store i32 [[CONV]], ptr [[DOTOMP_IV]], align 4 // SIMD-ONLY0-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // SIMD-ONLY0: omp.inner.for.cond: -// SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]] -// SIMD-ONLY0-NEXT: [[CONV1:%.*]] = sext i32 [[TMP2]] to i64 -// SIMD-ONLY0-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP6]] -// SIMD-ONLY0-NEXT: [[CMP:%.*]] = icmp ule i64 [[CONV1]], [[TMP3]] +// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]] +// SIMD-ONLY0-NEXT: [[CONV1:%.*]] = sext i32 [[TMP1]] to i64 +// SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP6]] +// SIMD-ONLY0-NEXT: [[CMP:%.*]] = icmp ule i64 [[CONV1]], [[TMP2]] // SIMD-ONLY0-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // SIMD-ONLY0: omp.inner.for.body: -// SIMD-ONLY0-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] -// SIMD-ONLY0-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 1 +// SIMD-ONLY0-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] +// SIMD-ONLY0-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 // SIMD-ONLY0-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// SIMD-ONLY0-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group [[ACC_GRP6]] -// SIMD-ONLY0-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 128, !llvm.access.group [[ACC_GRP6]] -// SIMD-ONLY0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// SIMD-ONLY0-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]] -// SIMD-ONLY0-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// SIMD-ONLY0-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX2]] to i8* -// SIMD-ONLY0-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* -// SIMD-ONLY0-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i64 4, i1 false), !llvm.access.group [[ACC_GRP6]] +// SIMD-ONLY0-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] +// SIMD-ONLY0-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR]], align 128, !llvm.access.group [[ACC_GRP6]] +// SIMD-ONLY0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 0 +// SIMD-ONLY0-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]] +// SIMD-ONLY0-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 0 +// SIMD-ONLY0-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i64 4, i1 false), !llvm.access.group [[ACC_GRP6]] // SIMD-ONLY0-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // SIMD-ONLY0: omp.body.continue: // SIMD-ONLY0-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // SIMD-ONLY0: omp.inner.for.inc: -// SIMD-ONLY0-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] -// SIMD-ONLY0-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 -// SIMD-ONLY0-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] +// SIMD-ONLY0-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] +// SIMD-ONLY0-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP5]], 1 +// SIMD-ONLY0-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] // SIMD-ONLY0-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // SIMD-ONLY0: omp.inner.for.end: -// SIMD-ONLY0-NEXT: store i32 10, i32* [[I]], align 4 -// SIMD-ONLY0-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// SIMD-ONLY0-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// SIMD-ONLY0-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// SIMD-ONLY0-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// SIMD-ONLY0-NEXT: store i32 10, ptr [[I]], align 4 +// SIMD-ONLY0-NEXT: store i32 0, ptr [[RETVAL]], align 4 +// SIMD-ONLY0-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] +// SIMD-ONLY0-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// SIMD-ONLY0-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // SIMD-ONLY0-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // SIMD-ONLY0: arraydestroy.body: -// SIMD-ONLY0-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// SIMD-ONLY0-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// SIMD-ONLY0-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// SIMD-ONLY0-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// SIMD-ONLY0-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP6]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// SIMD-ONLY0-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// SIMD-ONLY0-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// SIMD-ONLY0-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // SIMD-ONLY0-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] // SIMD-ONLY0: arraydestroy.done4: -// SIMD-ONLY0-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// SIMD-ONLY0-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TTT]]) #[[ATTR4]] -// SIMD-ONLY0-NEXT: [[TMP10:%.*]] = load i32, i32* [[RETVAL]], align 4 -// SIMD-ONLY0-NEXT: ret i32 [[TMP10]] +// SIMD-ONLY0-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// SIMD-ONLY0-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TTT]]) #[[ATTR4]] +// SIMD-ONLY0-NEXT: [[TMP7:%.*]] = load i32, ptr [[RETVAL]], align 4 +// SIMD-ONLY0-NEXT: ret i32 [[TMP7]] // // // SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIdED1Ev -// SIMD-ONLY0-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY0-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY0-NEXT: entry: -// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// SIMD-ONLY0-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// SIMD-ONLY0-NEXT: call void @_ZN1SIdED2Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS1]]) #[[ATTR4]] +// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY0-NEXT: call void @_ZN1SIdED2Ev(ptr noundef nonnull align 8 dereferenceable(8) [[THIS1]]) #[[ATTR4]] // SIMD-ONLY0-NEXT: ret void // // // SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIdEC2Ev -// SIMD-ONLY0-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY0-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY0-NEXT: entry: -// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// SIMD-ONLY0-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// SIMD-ONLY0-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// SIMD-ONLY0-NEXT: store double 0.000000e+00, double* [[F]], align 8 +// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY0-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 +// SIMD-ONLY0-NEXT: store double 0.000000e+00, ptr [[F]], align 8 // SIMD-ONLY0-NEXT: ret void // // // SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIdED2Ev -// SIMD-ONLY0-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY0-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY0-NEXT: entry: -// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// SIMD-ONLY0-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // SIMD-ONLY0-NEXT: ret void // // // SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIdEC2ERKS0_d -// SIMD-ONLY0-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[S:%.*]], double noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY0-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[S:%.*]], double noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY0-NEXT: entry: -// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// SIMD-ONLY0-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 +// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// SIMD-ONLY0-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY0-NEXT: [[T_ADDR:%.*]] = alloca double, align 8 -// SIMD-ONLY0-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// SIMD-ONLY0-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 -// SIMD-ONLY0-NEXT: store double [[T]], double* [[T_ADDR]], align 8 -// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// SIMD-ONLY0-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 -// SIMD-ONLY0-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0 -// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load double, double* [[F2]], align 8 -// SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load double, double* [[T_ADDR]], align 8 +// SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY0-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 +// SIMD-ONLY0-NEXT: store double [[T]], ptr [[T_ADDR]], align 8 +// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY0-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 +// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 +// SIMD-ONLY0-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0 +// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load double, ptr [[F2]], align 8 +// SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load double, ptr [[T_ADDR]], align 8 // SIMD-ONLY0-NEXT: [[ADD:%.*]] = fadd double [[TMP1]], [[TMP2]] -// SIMD-ONLY0-NEXT: store double [[ADD]], double* [[F]], align 8 +// SIMD-ONLY0-NEXT: store double [[ADD]], ptr [[F]], align 8 // SIMD-ONLY0-NEXT: ret void // // // SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIdEC2Ed -// SIMD-ONLY0-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], double noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY0-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], double noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY0-NEXT: entry: -// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY0-NEXT: [[A_ADDR:%.*]] = alloca double, align 8 -// SIMD-ONLY0-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// SIMD-ONLY0-NEXT: store double [[A]], double* [[A_ADDR]], align 8 -// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// SIMD-ONLY0-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load double, double* [[A_ADDR]], align 8 -// SIMD-ONLY0-NEXT: store double [[TMP0]], double* [[F]], align 8 +// SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY0-NEXT: store double [[A]], ptr [[A_ADDR]], align 8 +// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY0-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 +// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load double, ptr [[A_ADDR]], align 8 +// SIMD-ONLY0-NEXT: store double [[TMP0]], ptr [[F]], align 8 // SIMD-ONLY0-NEXT: ret void // // // SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// SIMD-ONLY0-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY0-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY0-NEXT: entry: -// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// SIMD-ONLY0-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// SIMD-ONLY0-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) +// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY0-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // SIMD-ONLY0-NEXT: ret void // // // SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_i -// SIMD-ONLY0-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], i32 noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY0-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], i32 noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY0-NEXT: entry: -// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// SIMD-ONLY0-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// SIMD-ONLY0-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY0-NEXT: [[T_ADDR:%.*]] = alloca i32, align 4 -// SIMD-ONLY0-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// SIMD-ONLY0-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 -// SIMD-ONLY0-NEXT: store i32 [[T]], i32* [[T_ADDR]], align 4 -// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 -// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_ADDR]], align 4 -// SIMD-ONLY0-NEXT: call void @_ZN1SIiEC2ERKS0_i(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], i32 noundef [[TMP1]]) +// SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY0-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 +// SIMD-ONLY0-NEXT: store i32 [[T]], ptr [[T_ADDR]], align 4 +// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 +// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_ADDR]], align 4 +// SIMD-ONLY0-NEXT: call void @_ZN1SIiEC2ERKS0_i(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], i32 noundef [[TMP1]]) // SIMD-ONLY0-NEXT: ret void // // // SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// SIMD-ONLY0-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY0-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY0-NEXT: entry: -// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY0-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// SIMD-ONLY0-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// SIMD-ONLY0-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// SIMD-ONLY0-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]) +// SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY0-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 +// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 +// SIMD-ONLY0-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]) // SIMD-ONLY0-NEXT: ret void // // // SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// SIMD-ONLY0-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY0-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY0-NEXT: entry: -// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// SIMD-ONLY0-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// SIMD-ONLY0-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY0-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // SIMD-ONLY0-NEXT: ret void // // // SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// SIMD-ONLY0-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY0-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY0-NEXT: entry: -// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// SIMD-ONLY0-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// SIMD-ONLY0-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// SIMD-ONLY0-NEXT: store i32 0, i32* [[F]], align 4 +// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY0-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 +// SIMD-ONLY0-NEXT: store i32 0, ptr [[F]], align 4 // SIMD-ONLY0-NEXT: ret void // // // SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_i -// SIMD-ONLY0-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], i32 noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY0-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], i32 noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY0-NEXT: entry: -// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// SIMD-ONLY0-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// SIMD-ONLY0-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY0-NEXT: [[T_ADDR:%.*]] = alloca i32, align 4 -// SIMD-ONLY0-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// SIMD-ONLY0-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 -// SIMD-ONLY0-NEXT: store i32 [[T]], i32* [[T_ADDR]], align 4 -// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// SIMD-ONLY0-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 -// SIMD-ONLY0-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0 -// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4 -// SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_ADDR]], align 4 +// SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY0-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 +// SIMD-ONLY0-NEXT: store i32 [[T]], ptr [[T_ADDR]], align 4 +// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY0-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 +// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 +// SIMD-ONLY0-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0 +// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4 +// SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load i32, ptr [[T_ADDR]], align 4 // SIMD-ONLY0-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] -// SIMD-ONLY0-NEXT: store i32 [[ADD]], i32* [[F]], align 4 +// SIMD-ONLY0-NEXT: store i32 [[ADD]], ptr [[F]], align 4 // SIMD-ONLY0-NEXT: ret void // // // SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// SIMD-ONLY0-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY0-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY0-NEXT: entry: -// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY0-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// SIMD-ONLY0-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// SIMD-ONLY0-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// SIMD-ONLY0-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// SIMD-ONLY0-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 +// SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY0-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 +// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY0-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 +// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 +// SIMD-ONLY0-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // SIMD-ONLY0-NEXT: ret void // // // SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// SIMD-ONLY0-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY0-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY0-NEXT: entry: -// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// SIMD-ONLY0-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // SIMD-ONLY0-NEXT: ret void // // @@ -1948,107 +1875,104 @@ void array_func(int n, float a[n], St s[2]) { // SIMD-ONLY1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 // SIMD-ONLY1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // SIMD-ONLY1-NEXT: [[I:%.*]] = alloca i32, align 4 -// SIMD-ONLY1-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// SIMD-ONLY1-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[TTT]]) -// SIMD-ONLY1-NEXT: call void @_ZN1SIdEC1ERKS0_d(%struct.S* noundef nonnull align 8 dereferenceable(8) [[TEST]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[TTT]], double noundef 0.000000e+00) -// SIMD-ONLY1-NEXT: store i32 0, i32* [[T_VAR]], align 4 -// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// SIMD-ONLY1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) -// SIMD-ONLY1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// SIMD-ONLY1-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* noundef nonnull align 8 dereferenceable(8) [[ARRAYINIT_BEGIN]], double noundef 1.000000e+00) -// SIMD-ONLY1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 -// SIMD-ONLY1-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* noundef nonnull align 8 dereferenceable(8) [[ARRAYINIT_ELEMENT]], double noundef 2.000000e+00) -// SIMD-ONLY1-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* noundef nonnull align 8 dereferenceable(8) [[VAR]], double noundef 3.000000e+00) -// SIMD-ONLY1-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 -// SIMD-ONLY1-NEXT: store i64 9, i64* [[DOTOMP_UB]], align 8 -// SIMD-ONLY1-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 -// SIMD-ONLY1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 -// SIMD-ONLY1-NEXT: store i32 [[CONV]], i32* [[DOTOMP_IV]], align 4 +// SIMD-ONLY1-NEXT: store i32 0, ptr [[RETVAL]], align 4 +// SIMD-ONLY1-NEXT: call void @_ZN1SIdEC1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[TTT]]) +// SIMD-ONLY1-NEXT: call void @_ZN1SIdEC1ERKS0_d(ptr noundef nonnull align 8 dereferenceable(8) [[TEST]], ptr noundef nonnull align 8 dereferenceable(8) [[TTT]], double noundef 0.000000e+00) +// SIMD-ONLY1-NEXT: store i32 0, ptr [[T_VAR]], align 4 +// SIMD-ONLY1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const.main.vec, i64 8, i1 false) +// SIMD-ONLY1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 0 +// SIMD-ONLY1-NEXT: call void @_ZN1SIdEC1Ed(ptr noundef nonnull align 8 dereferenceable(8) [[ARRAYINIT_BEGIN]], double noundef 1.000000e+00) +// SIMD-ONLY1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYINIT_BEGIN]], i64 1 +// SIMD-ONLY1-NEXT: call void @_ZN1SIdEC1Ed(ptr noundef nonnull align 8 dereferenceable(8) [[ARRAYINIT_ELEMENT]], double noundef 2.000000e+00) +// SIMD-ONLY1-NEXT: call void @_ZN1SIdEC1Ed(ptr noundef nonnull align 8 dereferenceable(8) [[VAR]], double noundef 3.000000e+00) +// SIMD-ONLY1-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 +// SIMD-ONLY1-NEXT: store i64 9, ptr [[DOTOMP_UB]], align 8 +// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 +// SIMD-ONLY1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// SIMD-ONLY1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_IV]], align 4 // SIMD-ONLY1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // SIMD-ONLY1: omp.inner.for.cond: -// SIMD-ONLY1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]] -// SIMD-ONLY1-NEXT: [[CONV1:%.*]] = sext i32 [[TMP2]] to i64 -// SIMD-ONLY1-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP2]] -// SIMD-ONLY1-NEXT: [[CMP:%.*]] = icmp ule i64 [[CONV1]], [[TMP3]] +// SIMD-ONLY1-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]] +// SIMD-ONLY1-NEXT: [[CONV1:%.*]] = sext i32 [[TMP1]] to i64 +// SIMD-ONLY1-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP2]] +// SIMD-ONLY1-NEXT: [[CMP:%.*]] = icmp ule i64 [[CONV1]], [[TMP2]] // SIMD-ONLY1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // SIMD-ONLY1: omp.inner.for.body: -// SIMD-ONLY1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] -// SIMD-ONLY1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 1 +// SIMD-ONLY1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] +// SIMD-ONLY1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 // SIMD-ONLY1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// SIMD-ONLY1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group [[ACC_GRP2]] -// SIMD-ONLY1-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP2]] -// SIMD-ONLY1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// SIMD-ONLY1-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]] -// SIMD-ONLY1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 -// SIMD-ONLY1-NEXT: [[TMP6:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* -// SIMD-ONLY1-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[VAR]] to i8* -// SIMD-ONLY1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP6]], i8* align 8 [[TMP7]], i64 8, i1 false), !llvm.access.group [[ACC_GRP2]] -// SIMD-ONLY1-NEXT: store i32 33, i32* @_ZZ4mainE5sivar, align 4, !llvm.access.group [[ACC_GRP2]] +// SIMD-ONLY1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] +// SIMD-ONLY1-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP2]] +// SIMD-ONLY1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 0 +// SIMD-ONLY1-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]] +// SIMD-ONLY1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 0 +// SIMD-ONLY1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 16 [[ARRAYIDX2]], ptr align 8 [[VAR]], i64 8, i1 false), !llvm.access.group [[ACC_GRP2]] +// SIMD-ONLY1-NEXT: store i32 33, ptr @_ZZ4mainE5sivar, align 4, !llvm.access.group [[ACC_GRP2]] // SIMD-ONLY1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // SIMD-ONLY1: omp.body.continue: // SIMD-ONLY1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // SIMD-ONLY1: omp.inner.for.inc: -// SIMD-ONLY1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] -// SIMD-ONLY1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 -// SIMD-ONLY1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] +// SIMD-ONLY1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] +// SIMD-ONLY1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP5]], 1 +// SIMD-ONLY1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] // SIMD-ONLY1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // SIMD-ONLY1: omp.inner.for.end: -// SIMD-ONLY1-NEXT: store i32 10, i32* [[I]], align 4 +// SIMD-ONLY1-NEXT: store i32 10, ptr [[I]], align 4 // SIMD-ONLY1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() -// SIMD-ONLY1-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 -// SIMD-ONLY1-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[VAR]]) #[[ATTR4:[0-9]+]] -// SIMD-ONLY1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 -// SIMD-ONLY1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 +// SIMD-ONLY1-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 +// SIMD-ONLY1-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[VAR]]) #[[ATTR4:[0-9]+]] +// SIMD-ONLY1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// SIMD-ONLY1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // SIMD-ONLY1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // SIMD-ONLY1: arraydestroy.body: -// SIMD-ONLY1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// SIMD-ONLY1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// SIMD-ONLY1-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// SIMD-ONLY1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// SIMD-ONLY1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP6]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// SIMD-ONLY1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// SIMD-ONLY1-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// SIMD-ONLY1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // SIMD-ONLY1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] // SIMD-ONLY1: arraydestroy.done4: -// SIMD-ONLY1-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[TEST]]) #[[ATTR4]] -// SIMD-ONLY1-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[TTT]]) #[[ATTR4]] -// SIMD-ONLY1-NEXT: [[TMP10:%.*]] = load i32, i32* [[RETVAL]], align 4 -// SIMD-ONLY1-NEXT: ret i32 [[TMP10]] +// SIMD-ONLY1-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[TEST]]) #[[ATTR4]] +// SIMD-ONLY1-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[TTT]]) #[[ATTR4]] +// SIMD-ONLY1-NEXT: [[TMP7:%.*]] = load i32, ptr [[RETVAL]], align 4 +// SIMD-ONLY1-NEXT: ret i32 [[TMP7]] // // // SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIdEC1Ev -// SIMD-ONLY1-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { +// SIMD-ONLY1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { // SIMD-ONLY1-NEXT: entry: -// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// SIMD-ONLY1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// SIMD-ONLY1-NEXT: call void @_ZN1SIdEC2Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS1]]) +// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// SIMD-ONLY1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY1-NEXT: call void @_ZN1SIdEC2Ev(ptr noundef nonnull align 8 dereferenceable(8) [[THIS1]]) // SIMD-ONLY1-NEXT: ret void // // // SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIdEC1ERKS0_d -// SIMD-ONLY1-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[S:%.*]], double noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[S:%.*]], double noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY1-NEXT: entry: -// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// SIMD-ONLY1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 +// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// SIMD-ONLY1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY1-NEXT: [[T_ADDR:%.*]] = alloca double, align 8 -// SIMD-ONLY1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// SIMD-ONLY1-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 -// SIMD-ONLY1-NEXT: store double [[T]], double* [[T_ADDR]], align 8 -// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 -// SIMD-ONLY1-NEXT: [[TMP1:%.*]] = load double, double* [[T_ADDR]], align 8 -// SIMD-ONLY1-NEXT: call void @_ZN1SIdEC2ERKS0_d(%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS1]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[TMP0]], double noundef [[TMP1]]) +// SIMD-ONLY1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 +// SIMD-ONLY1-NEXT: store double [[T]], ptr [[T_ADDR]], align 8 +// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 +// SIMD-ONLY1-NEXT: [[TMP1:%.*]] = load double, ptr [[T_ADDR]], align 8 +// SIMD-ONLY1-NEXT: call void @_ZN1SIdEC2ERKS0_d(ptr noundef nonnull align 8 dereferenceable(8) [[THIS1]], ptr noundef nonnull align 8 dereferenceable(8) [[TMP0]], double noundef [[TMP1]]) // SIMD-ONLY1-NEXT: ret void // // // SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIdEC1Ed -// SIMD-ONLY1-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], double noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], double noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY1-NEXT: entry: -// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY1-NEXT: [[A_ADDR:%.*]] = alloca double, align 8 -// SIMD-ONLY1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// SIMD-ONLY1-NEXT: store double [[A]], double* [[A_ADDR]], align 8 -// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load double, double* [[A_ADDR]], align 8 -// SIMD-ONLY1-NEXT: call void @_ZN1SIdEC2Ed(%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS1]], double noundef [[TMP0]]) +// SIMD-ONLY1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY1-NEXT: store double [[A]], ptr [[A_ADDR]], align 8 +// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load double, ptr [[A_ADDR]], align 8 +// SIMD-ONLY1-NEXT: call void @_ZN1SIdEC2Ed(ptr noundef nonnull align 8 dereferenceable(8) [[THIS1]], double noundef [[TMP0]]) // SIMD-ONLY1-NEXT: ret void // // @@ -2067,232 +1991,229 @@ void array_func(int n, float a[n], St s[2]) { // SIMD-ONLY1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 // SIMD-ONLY1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // SIMD-ONLY1-NEXT: [[I:%.*]] = alloca i32, align 4 -// SIMD-ONLY1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TTT]]) -// SIMD-ONLY1-NEXT: call void @_ZN1SIiEC1ERKS0_i(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TTT]], i32 noundef 0) -// SIMD-ONLY1-NEXT: store i32 0, i32* [[T_VAR]], align 128 -// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* -// SIMD-ONLY1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) -// SIMD-ONLY1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// SIMD-ONLY1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef 1) -// SIMD-ONLY1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 -// SIMD-ONLY1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) -// SIMD-ONLY1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]], i32 noundef 3) -// SIMD-ONLY1-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 -// SIMD-ONLY1-NEXT: store i64 9, i64* [[DOTOMP_UB]], align 8 -// SIMD-ONLY1-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 -// SIMD-ONLY1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 -// SIMD-ONLY1-NEXT: store i32 [[CONV]], i32* [[DOTOMP_IV]], align 4 +// SIMD-ONLY1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TTT]]) +// SIMD-ONLY1-NEXT: call void @_ZN1SIiEC1ERKS0_i(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]], ptr noundef nonnull align 4 dereferenceable(4) [[TTT]], i32 noundef 0) +// SIMD-ONLY1-NEXT: store i32 0, ptr [[T_VAR]], align 128 +// SIMD-ONLY1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false) +// SIMD-ONLY1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 0 +// SIMD-ONLY1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef 1) +// SIMD-ONLY1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYINIT_BEGIN]], i64 1 +// SIMD-ONLY1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) +// SIMD-ONLY1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]], i32 noundef 3) +// SIMD-ONLY1-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 +// SIMD-ONLY1-NEXT: store i64 9, ptr [[DOTOMP_UB]], align 8 +// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 +// SIMD-ONLY1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 +// SIMD-ONLY1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_IV]], align 4 // SIMD-ONLY1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // SIMD-ONLY1: omp.inner.for.cond: -// SIMD-ONLY1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]] -// SIMD-ONLY1-NEXT: [[CONV1:%.*]] = sext i32 [[TMP2]] to i64 -// SIMD-ONLY1-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP6]] -// SIMD-ONLY1-NEXT: [[CMP:%.*]] = icmp ule i64 [[CONV1]], [[TMP3]] +// SIMD-ONLY1-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]] +// SIMD-ONLY1-NEXT: [[CONV1:%.*]] = sext i32 [[TMP1]] to i64 +// SIMD-ONLY1-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP6]] +// SIMD-ONLY1-NEXT: [[CMP:%.*]] = icmp ule i64 [[CONV1]], [[TMP2]] // SIMD-ONLY1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // SIMD-ONLY1: omp.inner.for.body: -// SIMD-ONLY1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] -// SIMD-ONLY1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 1 +// SIMD-ONLY1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] +// SIMD-ONLY1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 // SIMD-ONLY1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// SIMD-ONLY1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group [[ACC_GRP6]] -// SIMD-ONLY1-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 128, !llvm.access.group [[ACC_GRP6]] -// SIMD-ONLY1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 -// SIMD-ONLY1-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]] -// SIMD-ONLY1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 -// SIMD-ONLY1-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX2]] to i8* -// SIMD-ONLY1-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* -// SIMD-ONLY1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i64 4, i1 false), !llvm.access.group [[ACC_GRP6]] +// SIMD-ONLY1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] +// SIMD-ONLY1-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR]], align 128, !llvm.access.group [[ACC_GRP6]] +// SIMD-ONLY1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 0 +// SIMD-ONLY1-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]] +// SIMD-ONLY1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 0 +// SIMD-ONLY1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i64 4, i1 false), !llvm.access.group [[ACC_GRP6]] // SIMD-ONLY1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // SIMD-ONLY1: omp.body.continue: // SIMD-ONLY1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // SIMD-ONLY1: omp.inner.for.inc: -// SIMD-ONLY1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] -// SIMD-ONLY1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 -// SIMD-ONLY1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] +// SIMD-ONLY1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] +// SIMD-ONLY1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP5]], 1 +// SIMD-ONLY1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] // SIMD-ONLY1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // SIMD-ONLY1: omp.inner.for.end: -// SIMD-ONLY1-NEXT: store i32 10, i32* [[I]], align 4 -// SIMD-ONLY1-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// SIMD-ONLY1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// SIMD-ONLY1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 -// SIMD-ONLY1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 +// SIMD-ONLY1-NEXT: store i32 10, ptr [[I]], align 4 +// SIMD-ONLY1-NEXT: store i32 0, ptr [[RETVAL]], align 4 +// SIMD-ONLY1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] +// SIMD-ONLY1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// SIMD-ONLY1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // SIMD-ONLY1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // SIMD-ONLY1: arraydestroy.body: -// SIMD-ONLY1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// SIMD-ONLY1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// SIMD-ONLY1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] -// SIMD-ONLY1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] +// SIMD-ONLY1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP6]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// SIMD-ONLY1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// SIMD-ONLY1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// SIMD-ONLY1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // SIMD-ONLY1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] // SIMD-ONLY1: arraydestroy.done4: -// SIMD-ONLY1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// SIMD-ONLY1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TTT]]) #[[ATTR4]] -// SIMD-ONLY1-NEXT: [[TMP10:%.*]] = load i32, i32* [[RETVAL]], align 4 -// SIMD-ONLY1-NEXT: ret i32 [[TMP10]] +// SIMD-ONLY1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// SIMD-ONLY1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TTT]]) #[[ATTR4]] +// SIMD-ONLY1-NEXT: [[TMP7:%.*]] = load i32, ptr [[RETVAL]], align 4 +// SIMD-ONLY1-NEXT: ret i32 [[TMP7]] // // // SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIdED1Ev -// SIMD-ONLY1-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY1-NEXT: entry: -// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// SIMD-ONLY1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// SIMD-ONLY1-NEXT: call void @_ZN1SIdED2Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS1]]) #[[ATTR4]] +// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// SIMD-ONLY1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY1-NEXT: call void @_ZN1SIdED2Ev(ptr noundef nonnull align 8 dereferenceable(8) [[THIS1]]) #[[ATTR4]] // SIMD-ONLY1-NEXT: ret void // // // SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIdEC2Ev -// SIMD-ONLY1-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY1-NEXT: entry: -// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// SIMD-ONLY1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// SIMD-ONLY1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// SIMD-ONLY1-NEXT: store double 0.000000e+00, double* [[F]], align 8 +// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// SIMD-ONLY1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 +// SIMD-ONLY1-NEXT: store double 0.000000e+00, ptr [[F]], align 8 // SIMD-ONLY1-NEXT: ret void // // // SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIdED2Ev -// SIMD-ONLY1-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY1-NEXT: entry: -// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// SIMD-ONLY1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 +// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// SIMD-ONLY1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // SIMD-ONLY1-NEXT: ret void // // // SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIdEC2ERKS0_d -// SIMD-ONLY1-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[S:%.*]], double noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[S:%.*]], double noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY1-NEXT: entry: -// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 -// SIMD-ONLY1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 +// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// SIMD-ONLY1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY1-NEXT: [[T_ADDR:%.*]] = alloca double, align 8 -// SIMD-ONLY1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// SIMD-ONLY1-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 -// SIMD-ONLY1-NEXT: store double [[T]], double* [[T_ADDR]], align 8 -// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// SIMD-ONLY1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 -// SIMD-ONLY1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0 -// SIMD-ONLY1-NEXT: [[TMP1:%.*]] = load double, double* [[F2]], align 8 -// SIMD-ONLY1-NEXT: [[TMP2:%.*]] = load double, double* [[T_ADDR]], align 8 +// SIMD-ONLY1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 +// SIMD-ONLY1-NEXT: store double [[T]], ptr [[T_ADDR]], align 8 +// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 +// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 +// SIMD-ONLY1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0 +// SIMD-ONLY1-NEXT: [[TMP1:%.*]] = load double, ptr [[F2]], align 8 +// SIMD-ONLY1-NEXT: [[TMP2:%.*]] = load double, ptr [[T_ADDR]], align 8 // SIMD-ONLY1-NEXT: [[ADD:%.*]] = fadd double [[TMP1]], [[TMP2]] -// SIMD-ONLY1-NEXT: store double [[ADD]], double* [[F]], align 8 +// SIMD-ONLY1-NEXT: store double [[ADD]], ptr [[F]], align 8 // SIMD-ONLY1-NEXT: ret void // // // SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIdEC2Ed -// SIMD-ONLY1-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], double noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], double noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY1-NEXT: entry: -// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 +// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY1-NEXT: [[A_ADDR:%.*]] = alloca double, align 8 -// SIMD-ONLY1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 -// SIMD-ONLY1-NEXT: store double [[A]], double* [[A_ADDR]], align 8 -// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 -// SIMD-ONLY1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 -// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load double, double* [[A_ADDR]], align 8 -// SIMD-ONLY1-NEXT: store double [[TMP0]], double* [[F]], align 8 +// SIMD-ONLY1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY1-NEXT: store double [[A]], ptr [[A_ADDR]], align 8 +// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 +// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load double, ptr [[A_ADDR]], align 8 +// SIMD-ONLY1-NEXT: store double [[TMP0]], ptr [[F]], align 8 // SIMD-ONLY1-NEXT: ret void // // // SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// SIMD-ONLY1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY1-NEXT: entry: -// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// SIMD-ONLY1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// SIMD-ONLY1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) +// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// SIMD-ONLY1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY1-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) // SIMD-ONLY1-NEXT: ret void // // // SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_i -// SIMD-ONLY1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], i32 noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], i32 noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY1-NEXT: entry: -// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// SIMD-ONLY1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// SIMD-ONLY1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY1-NEXT: [[T_ADDR:%.*]] = alloca i32, align 4 -// SIMD-ONLY1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// SIMD-ONLY1-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 -// SIMD-ONLY1-NEXT: store i32 [[T]], i32* [[T_ADDR]], align 4 -// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 -// SIMD-ONLY1-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_ADDR]], align 4 -// SIMD-ONLY1-NEXT: call void @_ZN1SIiEC2ERKS0_i(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], i32 noundef [[TMP1]]) +// SIMD-ONLY1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 +// SIMD-ONLY1-NEXT: store i32 [[T]], ptr [[T_ADDR]], align 4 +// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 +// SIMD-ONLY1-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_ADDR]], align 4 +// SIMD-ONLY1-NEXT: call void @_ZN1SIiEC2ERKS0_i(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], i32 noundef [[TMP1]]) // SIMD-ONLY1-NEXT: ret void // // // SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// SIMD-ONLY1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY1-NEXT: entry: -// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// SIMD-ONLY1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// SIMD-ONLY1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// SIMD-ONLY1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]) +// SIMD-ONLY1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 +// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 +// SIMD-ONLY1-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]) // SIMD-ONLY1-NEXT: ret void // // // SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// SIMD-ONLY1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY1-NEXT: entry: -// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// SIMD-ONLY1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// SIMD-ONLY1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// SIMD-ONLY1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] // SIMD-ONLY1-NEXT: ret void // // // SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// SIMD-ONLY1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY1-NEXT: entry: -// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// SIMD-ONLY1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// SIMD-ONLY1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// SIMD-ONLY1-NEXT: store i32 0, i32* [[F]], align 4 +// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// SIMD-ONLY1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 +// SIMD-ONLY1-NEXT: store i32 0, ptr [[F]], align 4 // SIMD-ONLY1-NEXT: ret void // // // SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_i -// SIMD-ONLY1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], i32 noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], i32 noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY1-NEXT: entry: -// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// SIMD-ONLY1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// SIMD-ONLY1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY1-NEXT: [[T_ADDR:%.*]] = alloca i32, align 4 -// SIMD-ONLY1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// SIMD-ONLY1-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 -// SIMD-ONLY1-NEXT: store i32 [[T]], i32* [[T_ADDR]], align 4 -// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// SIMD-ONLY1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 -// SIMD-ONLY1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0 -// SIMD-ONLY1-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4 -// SIMD-ONLY1-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_ADDR]], align 4 +// SIMD-ONLY1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 +// SIMD-ONLY1-NEXT: store i32 [[T]], ptr [[T_ADDR]], align 4 +// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 +// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 +// SIMD-ONLY1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0 +// SIMD-ONLY1-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4 +// SIMD-ONLY1-NEXT: [[TMP2:%.*]] = load i32, ptr [[T_ADDR]], align 4 // SIMD-ONLY1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] -// SIMD-ONLY1-NEXT: store i32 [[ADD]], i32* [[F]], align 4 +// SIMD-ONLY1-NEXT: store i32 [[ADD]], ptr [[F]], align 4 // SIMD-ONLY1-NEXT: ret void // // // SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// SIMD-ONLY1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY1-NEXT: entry: -// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 +// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// SIMD-ONLY1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// SIMD-ONLY1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 -// SIMD-ONLY1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 -// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// SIMD-ONLY1-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 +// SIMD-ONLY1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 +// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 +// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 +// SIMD-ONLY1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 // SIMD-ONLY1-NEXT: ret void // // // SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// SIMD-ONLY1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY1-NEXT: entry: -// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 -// SIMD-ONLY1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 -// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 +// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// SIMD-ONLY1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // SIMD-ONLY1-NEXT: ret void // // @@ -2301,8 +2222,8 @@ void array_func(int n, float a[n], St s[2]) { // SIMD-ONLY2-NEXT: entry: // SIMD-ONLY2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // SIMD-ONLY2-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 -// SIMD-ONLY2-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// SIMD-ONLY2-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef nonnull align 1 dereferenceable(1) [[REF_TMP]]) +// SIMD-ONLY2-NEXT: store i32 0, ptr [[RETVAL]], align 4 +// SIMD-ONLY2-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]]) // SIMD-ONLY2-NEXT: ret i32 0 // // @@ -2310,139 +2231,132 @@ void array_func(int n, float a[n], St s[2]) { // SIMD-ONLY3-SAME: () #[[ATTR1:[0-9]+]] { // SIMD-ONLY3-NEXT: entry: // SIMD-ONLY3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// SIMD-ONLY3-NEXT: store i32 0, i32* [[RETVAL]], align 4 -// SIMD-ONLY3-NEXT: [[TMP0:%.*]] = load i8*, i8** getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to %struct.__block_literal_generic*), i32 0, i32 3), align 8 -// SIMD-ONLY3-NEXT: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to void (i8*)* -// SIMD-ONLY3-NEXT: call void [[TMP1]](i8* noundef bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to i8*)) +// SIMD-ONLY3-NEXT: store i32 0, ptr [[RETVAL]], align 4 +// SIMD-ONLY3-NEXT: [[TMP0:%.*]] = load ptr, ptr getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr @__block_literal_global, i32 0, i32 3), align 8 +// SIMD-ONLY3-NEXT: call void [[TMP0]](ptr noundef @__block_literal_global) // SIMD-ONLY3-NEXT: ret i32 0 // // // SIMD-ONLY3-LABEL: define {{[^@]+}}@__main_block_invoke -// SIMD-ONLY3-SAME: (i8* noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] { +// SIMD-ONLY3-SAME: (ptr noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] { // SIMD-ONLY3-NEXT: entry: -// SIMD-ONLY3-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// SIMD-ONLY3-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*, align 8 +// SIMD-ONLY3-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 8 +// SIMD-ONLY3-NEXT: [[BLOCK_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY3-NEXT: [[TMP:%.*]] = alloca i32, align 4 // SIMD-ONLY3-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 // SIMD-ONLY3-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 // SIMD-ONLY3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // SIMD-ONLY3-NEXT: [[I:%.*]] = alloca i32, align 4 -// SIMD-ONLY3-NEXT: [[BLOCK2:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, align 8 -// SIMD-ONLY3-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// SIMD-ONLY3-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* -// SIMD-ONLY3-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>** [[BLOCK_ADDR]], align 8 -// SIMD-ONLY3-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 -// SIMD-ONLY3-NEXT: store i64 9, i64* [[DOTOMP_UB]], align 8 -// SIMD-ONLY3-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// SIMD-ONLY3-NEXT: [[BLOCK:%.*]] = alloca <{ ptr, i32, i32, ptr, ptr, double, i32 }>, align 8 +// SIMD-ONLY3-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 +// SIMD-ONLY3-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 8 +// SIMD-ONLY3-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 +// SIMD-ONLY3-NEXT: store i64 9, ptr [[DOTOMP_UB]], align 8 +// SIMD-ONLY3-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 // SIMD-ONLY3-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// SIMD-ONLY3-NEXT: store i32 [[CONV]], i32* [[DOTOMP_IV]], align 4 +// SIMD-ONLY3-NEXT: store i32 [[CONV]], ptr [[DOTOMP_IV]], align 4 // SIMD-ONLY3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // SIMD-ONLY3: omp.inner.for.cond: -// SIMD-ONLY3-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]] +// SIMD-ONLY3-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]] // SIMD-ONLY3-NEXT: [[CONV1:%.*]] = sext i32 [[TMP1]] to i64 -// SIMD-ONLY3-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP2]] +// SIMD-ONLY3-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP2]] // SIMD-ONLY3-NEXT: [[CMP:%.*]] = icmp ule i64 [[CONV1]], [[TMP2]] // SIMD-ONLY3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // SIMD-ONLY3: omp.inner.for.body: -// SIMD-ONLY3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] +// SIMD-ONLY3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] // SIMD-ONLY3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 // SIMD-ONLY3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// SIMD-ONLY3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group [[ACC_GRP2]] -// SIMD-ONLY3-NEXT: store double 1.000000e+00, double* @g, align 8, !llvm.access.group [[ACC_GRP2]] -// SIMD-ONLY3-NEXT: store i32 11, i32* @_ZZ4mainE5sivar, align 4, !llvm.access.group [[ACC_GRP2]] -// SIMD-ONLY3-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK2]], i32 0, i32 0 -// SIMD-ONLY3-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8, !llvm.access.group [[ACC_GRP2]] -// SIMD-ONLY3-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK2]], i32 0, i32 1 -// SIMD-ONLY3-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8, !llvm.access.group [[ACC_GRP2]] -// SIMD-ONLY3-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK2]], i32 0, i32 2 -// SIMD-ONLY3-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4, !llvm.access.group [[ACC_GRP2]] -// SIMD-ONLY3-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK2]], i32 0, i32 3 -// SIMD-ONLY3-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke_2 to i8*), i8** [[BLOCK_INVOKE]], align 8, !llvm.access.group [[ACC_GRP2]] -// SIMD-ONLY3-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK2]], i32 0, i32 4 -// SIMD-ONLY3-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.1 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8, !llvm.access.group [[ACC_GRP2]] -// SIMD-ONLY3-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK2]], i32 0, i32 5 -// SIMD-ONLY3-NEXT: [[TMP4:%.*]] = load volatile double, double* @g, align 8, !llvm.access.group [[ACC_GRP2]] -// SIMD-ONLY3-NEXT: store volatile double [[TMP4]], double* [[BLOCK_CAPTURED]], align 8, !llvm.access.group [[ACC_GRP2]] -// SIMD-ONLY3-NEXT: [[BLOCK_CAPTURED3:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK2]], i32 0, i32 6 -// SIMD-ONLY3-NEXT: [[TMP5:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4, !llvm.access.group [[ACC_GRP2]] -// SIMD-ONLY3-NEXT: store i32 [[TMP5]], i32* [[BLOCK_CAPTURED3]], align 8, !llvm.access.group [[ACC_GRP2]] -// SIMD-ONLY3-NEXT: [[TMP6:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK2]] to void ()* -// SIMD-ONLY3-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP6]] to %struct.__block_literal_generic* -// SIMD-ONLY3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 -// SIMD-ONLY3-NEXT: [[TMP8:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* -// SIMD-ONLY3-NEXT: [[TMP9:%.*]] = load i8*, i8** [[TMP7]], align 8, !llvm.access.group [[ACC_GRP2]] -// SIMD-ONLY3-NEXT: [[TMP10:%.*]] = bitcast i8* [[TMP9]] to void (i8*)* -// SIMD-ONLY3-NEXT: call void [[TMP10]](i8* noundef [[TMP8]]), !llvm.access.group [[ACC_GRP2]] +// SIMD-ONLY3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] +// SIMD-ONLY3-NEXT: store double 1.000000e+00, ptr @g, align 8, !llvm.access.group [[ACC_GRP2]] +// SIMD-ONLY3-NEXT: store i32 11, ptr @_ZZ4mainE5sivar, align 4, !llvm.access.group [[ACC_GRP2]] +// SIMD-ONLY3-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK]], i32 0, i32 0 +// SIMD-ONLY3-NEXT: store ptr @_NSConcreteStackBlock, ptr [[BLOCK_ISA]], align 8, !llvm.access.group [[ACC_GRP2]] +// SIMD-ONLY3-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK]], i32 0, i32 1 +// SIMD-ONLY3-NEXT: store i32 1073741824, ptr [[BLOCK_FLAGS]], align 8, !llvm.access.group [[ACC_GRP2]] +// SIMD-ONLY3-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK]], i32 0, i32 2 +// SIMD-ONLY3-NEXT: store i32 0, ptr [[BLOCK_RESERVED]], align 4, !llvm.access.group [[ACC_GRP2]] +// SIMD-ONLY3-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK]], i32 0, i32 3 +// SIMD-ONLY3-NEXT: store ptr @__main_block_invoke_2, ptr [[BLOCK_INVOKE]], align 8, !llvm.access.group [[ACC_GRP2]] +// SIMD-ONLY3-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK]], i32 0, i32 4 +// SIMD-ONLY3-NEXT: store ptr @__block_descriptor_tmp.1, ptr [[BLOCK_DESCRIPTOR]], align 8, !llvm.access.group [[ACC_GRP2]] +// SIMD-ONLY3-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK]], i32 0, i32 5 +// SIMD-ONLY3-NEXT: [[TMP4:%.*]] = load volatile double, ptr @g, align 8, !llvm.access.group [[ACC_GRP2]] +// SIMD-ONLY3-NEXT: store volatile double [[TMP4]], ptr [[BLOCK_CAPTURED]], align 8, !llvm.access.group [[ACC_GRP2]] +// SIMD-ONLY3-NEXT: [[BLOCK_CAPTURED2:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK]], i32 0, i32 6 +// SIMD-ONLY3-NEXT: [[TMP5:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4, !llvm.access.group [[ACC_GRP2]] +// SIMD-ONLY3-NEXT: store i32 [[TMP5]], ptr [[BLOCK_CAPTURED2]], align 8, !llvm.access.group [[ACC_GRP2]] +// SIMD-ONLY3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr [[BLOCK]], i32 0, i32 3 +// SIMD-ONLY3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8, !llvm.access.group [[ACC_GRP2]] +// SIMD-ONLY3-NEXT: call void [[TMP7]](ptr noundef [[BLOCK]]), !llvm.access.group [[ACC_GRP2]] // SIMD-ONLY3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // SIMD-ONLY3: omp.body.continue: // SIMD-ONLY3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // SIMD-ONLY3: omp.inner.for.inc: -// SIMD-ONLY3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] -// SIMD-ONLY3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 -// SIMD-ONLY3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] +// SIMD-ONLY3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] +// SIMD-ONLY3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 +// SIMD-ONLY3-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] // SIMD-ONLY3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // SIMD-ONLY3: omp.inner.for.end: -// SIMD-ONLY3-NEXT: store i32 10, i32* [[I]], align 4 +// SIMD-ONLY3-NEXT: store i32 10, ptr [[I]], align 4 // SIMD-ONLY3-NEXT: ret void // // // SIMD-ONLY3-LABEL: define {{[^@]+}}@__main_block_invoke_2 -// SIMD-ONLY3-SAME: (i8* noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { +// SIMD-ONLY3-SAME: (ptr noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { // SIMD-ONLY3-NEXT: entry: -// SIMD-ONLY3-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 -// SIMD-ONLY3-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>*, align 8 -// SIMD-ONLY3-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 -// SIMD-ONLY3-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* -// SIMD-ONLY3-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>** [[BLOCK_ADDR]], align 8 -// SIMD-ONLY3-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK]], i32 0, i32 5 -// SIMD-ONLY3-NEXT: store double 2.000000e+00, double* [[BLOCK_CAPTURE_ADDR]], align 8 -// SIMD-ONLY3-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK]], i32 0, i32 6 -// SIMD-ONLY3-NEXT: store i32 22, i32* [[BLOCK_CAPTURE_ADDR1]], align 8 +// SIMD-ONLY3-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 8 +// SIMD-ONLY3-NEXT: [[BLOCK_ADDR:%.*]] = alloca ptr, align 8 +// SIMD-ONLY3-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 +// SIMD-ONLY3-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 8 +// SIMD-ONLY3-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 5 +// SIMD-ONLY3-NEXT: store double 2.000000e+00, ptr [[BLOCK_CAPTURE_ADDR]], align 8 +// SIMD-ONLY3-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 6 +// SIMD-ONLY3-NEXT: store i32 22, ptr [[BLOCK_CAPTURE_ADDR1]], align 8 // SIMD-ONLY3-NEXT: ret void // // // SIMD-ONLY4-LABEL: define {{[^@]+}}@_Z10array_funciPfP2St -// SIMD-ONLY4-SAME: (i32 noundef [[N:%.*]], float* noundef [[A:%.*]], %struct.St* noundef [[S:%.*]]) #[[ATTR0:[0-9]+]] { +// SIMD-ONLY4-SAME: (i32 noundef [[N:%.*]], ptr noundef [[A:%.*]], ptr noundef [[S:%.*]]) #[[ATTR0:[0-9]+]] { // SIMD-ONLY4-NEXT: entry: // SIMD-ONLY4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// SIMD-ONLY4-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 -// SIMD-ONLY4-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 +// SIMD-ONLY4-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 +// SIMD-ONLY4-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY4-NEXT: [[TMP:%.*]] = alloca i32, align 4 // SIMD-ONLY4-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 // SIMD-ONLY4-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 // SIMD-ONLY4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // SIMD-ONLY4-NEXT: [[I:%.*]] = alloca i32, align 4 -// SIMD-ONLY4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// SIMD-ONLY4-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 -// SIMD-ONLY4-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 -// SIMD-ONLY4-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// SIMD-ONLY4-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// SIMD-ONLY4-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 +// SIMD-ONLY4-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 +// SIMD-ONLY4-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY4-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// SIMD-ONLY4-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 -// SIMD-ONLY4-NEXT: store i64 9, i64* [[DOTOMP_UB]], align 8 -// SIMD-ONLY4-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 +// SIMD-ONLY4-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 +// SIMD-ONLY4-NEXT: store i64 9, ptr [[DOTOMP_UB]], align 8 +// SIMD-ONLY4-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 // SIMD-ONLY4-NEXT: [[CONV:%.*]] = trunc i64 [[TMP2]] to i32 -// SIMD-ONLY4-NEXT: store i32 [[CONV]], i32* [[DOTOMP_IV]], align 4 +// SIMD-ONLY4-NEXT: store i32 [[CONV]], ptr [[DOTOMP_IV]], align 4 // SIMD-ONLY4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // SIMD-ONLY4: omp.inner.for.cond: -// SIMD-ONLY4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]] +// SIMD-ONLY4-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]] // SIMD-ONLY4-NEXT: [[CONV1:%.*]] = sext i32 [[TMP3]] to i64 -// SIMD-ONLY4-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP2]] +// SIMD-ONLY4-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP2]] // SIMD-ONLY4-NEXT: [[CMP:%.*]] = icmp ule i64 [[CONV1]], [[TMP4]] // SIMD-ONLY4-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // SIMD-ONLY4: omp.inner.for.body: -// SIMD-ONLY4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] +// SIMD-ONLY4-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] // SIMD-ONLY4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP5]], 1 // SIMD-ONLY4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// SIMD-ONLY4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group [[ACC_GRP2]] +// SIMD-ONLY4-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // SIMD-ONLY4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // SIMD-ONLY4: omp.body.continue: // SIMD-ONLY4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // SIMD-ONLY4: omp.inner.for.inc: -// SIMD-ONLY4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] +// SIMD-ONLY4-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] // SIMD-ONLY4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], 1 -// SIMD-ONLY4-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] +// SIMD-ONLY4-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] // SIMD-ONLY4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // SIMD-ONLY4: omp.inner.for.end: -// SIMD-ONLY4-NEXT: store i32 10, i32* [[I]], align 4 +// SIMD-ONLY4-NEXT: store i32 10, ptr [[I]], align 4 // SIMD-ONLY4-NEXT: ret void // diff --git a/clang/test/OpenMP/target_firstprivate_codegen.cpp b/clang/test/OpenMP/target_firstprivate_codegen.cpp index 05a6e891204f2e..8c42e5740e15fe 100644 --- a/clang/test/OpenMP/target_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/target_firstprivate_codegen.cpp @@ -1,37 +1,37 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ // Test host codegen. -// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK0 -// RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK1 -// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK2 -// RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK3 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK0 +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK1 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK2 +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK3 -// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s -// RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY01 %s -// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY02 %s -// RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -// RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY03 %s +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY01 %s +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY02 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY03 %s // Test target codegen - host bc file has to be created first. -// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix TCHECK -// RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK1 -// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix TCHECK2 -// RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK3 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix TCHECK +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s +// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK1 +// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix TCHECK2 +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s +// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK3 -// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc -// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s -// RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s -// RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY11 %s -// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc -// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck --check-prefix SIMD-ONLY12 %s -// RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s -// RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY13 %s +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY11 %s +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc +// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck --check-prefix SIMD-ONLY12 %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY13 %s // expected-no-diagnostics #ifndef HEADER @@ -6079,592 +6079,533 @@ int bar(int n, double *ptr) { // TCHECK3-32-NEXT: store i32 [[ADD2]], i32* [[ARRAYIDX]], align 4 // TCHECK3-32-NEXT: ret void // CHECK0-LABEL: define {{[^@]+}}@_Z3fooiPd -// CHECK0-SAME: (i32 noundef signext [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK0-SAME: (i32 noundef signext [[N:%.*]], ptr noundef [[PTR:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK0-NEXT: entry: // CHECK0-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK0-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 8 +// CHECK0-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8 // CHECK0-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK0-NEXT: [[AA:%.*]] = alloca i16, align 2 // CHECK0-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK0-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK0-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 // CHECK0-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 // CHECK0-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 // CHECK0-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 // CHECK0-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 // CHECK0-NEXT: [[E:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 4 -// CHECK0-NEXT: [[P:%.*]] = alloca i32*, align 64 +// CHECK0-NEXT: [[P:%.*]] = alloca ptr, align 64 // CHECK0-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK0-NEXT: [[GA_CASTED:%.*]] = alloca i64, align 8 -// CHECK0-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK0-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK0-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK0-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8 +// CHECK0-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 8 +// CHECK0-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 8 // CHECK0-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK0-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK0-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [9 x i8*], align 8 -// CHECK0-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [9 x i8*], align 8 -// CHECK0-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [9 x i8*], align 8 +// CHECK0-NEXT: [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [9 x ptr], align 8 +// CHECK0-NEXT: [[DOTOFFLOAD_PTRS3:%.*]] = alloca [9 x ptr], align 8 +// CHECK0-NEXT: [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [9 x ptr], align 8 // CHECK0-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 8 -// CHECK0-NEXT: [[KERNEL_ARGS7:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 -// CHECK0-NEXT: [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [2 x i8*], align 8 -// CHECK0-NEXT: [[DOTOFFLOAD_PTRS11:%.*]] = alloca [2 x i8*], align 8 -// CHECK0-NEXT: [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [2 x i8*], align 8 -// CHECK0-NEXT: [[KERNEL_ARGS13:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 -// CHECK0-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK0-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 8 -// CHECK0-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK0-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK0-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK0-NEXT: [[KERNEL_ARGS5:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 +// CHECK0-NEXT: [[DOTOFFLOAD_BASEPTRS8:%.*]] = alloca [2 x ptr], align 8 +// CHECK0-NEXT: [[DOTOFFLOAD_PTRS9:%.*]] = alloca [2 x ptr], align 8 +// CHECK0-NEXT: [[DOTOFFLOAD_MAPPERS10:%.*]] = alloca [2 x ptr], align 8 +// CHECK0-NEXT: [[KERNEL_ARGS11:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 +// CHECK0-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// CHECK0-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 8 +// CHECK0-NEXT: store i32 0, ptr [[A]], align 4 +// CHECK0-NEXT: store i16 0, ptr [[AA]], align 2 +// CHECK0-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK0-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK0-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK0-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 +// CHECK0-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() +// CHECK0-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // CHECK0-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// CHECK0-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK0-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK0-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 +// CHECK0-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK0-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 // CHECK0-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] // CHECK0-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// CHECK0-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// CHECK0-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 0 -// CHECK0-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK0-NEXT: store i32 [[TMP6]], i32* [[X]], align 4 -// CHECK0-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 1 -// CHECK0-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK0-NEXT: store i32 [[TMP7]], i32* [[Y]], align 4 -// CHECK0-NEXT: store i32* [[A]], i32** [[P]], align 64 -// CHECK0-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK0-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK0-NEXT: store i32 [[TMP8]], i32* [[CONV]], align 4 -// CHECK0-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK0-NEXT: [[TMP10:%.*]] = load i32*, i32** [[P]], align 64 -// CHECK0-NEXT: [[TMP11:%.*]] = load i32, i32* @ga, align 4 -// CHECK0-NEXT: [[CONV2:%.*]] = bitcast i64* [[GA_CASTED]] to i32* -// CHECK0-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4 -// CHECK0-NEXT: [[TMP12:%.*]] = load i64, i64* [[GA_CASTED]], align 8 -// CHECK0-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK0-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i64* -// CHECK0-NEXT: store i64 [[TMP9]], i64* [[TMP14]], align 8 -// CHECK0-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK0-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* -// CHECK0-NEXT: store i64 [[TMP9]], i64* [[TMP16]], align 8 -// CHECK0-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK0-NEXT: store i8* null, i8** [[TMP17]], align 8 -// CHECK0-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK0-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** -// CHECK0-NEXT: store i32* [[TMP10]], i32** [[TMP19]], align 8 -// CHECK0-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK0-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** -// CHECK0-NEXT: store i32* [[TMP10]], i32** [[TMP21]], align 8 -// CHECK0-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK0-NEXT: store i8* null, i8** [[TMP22]], align 8 -// CHECK0-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK0-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64* -// CHECK0-NEXT: store i64 [[TMP12]], i64* [[TMP24]], align 8 -// CHECK0-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK0-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64* -// CHECK0-NEXT: store i64 [[TMP12]], i64* [[TMP26]], align 8 -// CHECK0-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK0-NEXT: store i8* null, i8** [[TMP27]], align 8 -// CHECK0-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK0-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK0-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 -// CHECK0-NEXT: store i32 2, i32* [[TMP30]], align 4 -// CHECK0-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 -// CHECK0-NEXT: store i32 3, i32* [[TMP31]], align 4 -// CHECK0-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 -// CHECK0-NEXT: store i8** [[TMP28]], i8*** [[TMP32]], align 8 -// CHECK0-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 -// CHECK0-NEXT: store i8** [[TMP29]], i8*** [[TMP33]], align 8 -// CHECK0-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 -// CHECK0-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64** [[TMP34]], align 8 -// CHECK0-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 -// CHECK0-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i64** [[TMP35]], align 8 -// CHECK0-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 -// CHECK0-NEXT: store i8** null, i8*** [[TMP36]], align 8 -// CHECK0-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 -// CHECK0-NEXT: store i8** null, i8*** [[TMP37]], align 8 -// CHECK0-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 -// CHECK0-NEXT: store i64 0, i64* [[TMP38]], align 8 -// CHECK0-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 9 -// CHECK0-NEXT: store i64 0, i64* [[TMP39]], align 8 -// CHECK0-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 10 -// CHECK0-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP40]], align 4 -// CHECK0-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 11 -// CHECK0-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP41]], align 4 -// CHECK0-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 12 -// CHECK0-NEXT: store i32 0, i32* [[TMP42]], align 4 -// CHECK0-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) -// CHECK0-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 -// CHECK0-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK0-NEXT: store i64 [[TMP4]], ptr [[__VLA_EXPR1]], align 8 +// CHECK0-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 0 +// CHECK0-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// CHECK0-NEXT: store i32 [[TMP6]], ptr [[X]], align 4 +// CHECK0-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 1 +// CHECK0-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// CHECK0-NEXT: store i32 [[TMP7]], ptr [[Y]], align 4 +// CHECK0-NEXT: store ptr [[A]], ptr [[P]], align 64 +// CHECK0-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 +// CHECK0-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4 +// CHECK0-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8 +// CHECK0-NEXT: [[TMP10:%.*]] = load ptr, ptr [[P]], align 64 +// CHECK0-NEXT: [[TMP11:%.*]] = load i32, ptr @ga, align 4 +// CHECK0-NEXT: store i32 [[TMP11]], ptr [[GA_CASTED]], align 4 +// CHECK0-NEXT: [[TMP12:%.*]] = load i64, ptr [[GA_CASTED]], align 8 +// CHECK0-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK0-NEXT: store i64 [[TMP9]], ptr [[TMP13]], align 8 +// CHECK0-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK0-NEXT: store i64 [[TMP9]], ptr [[TMP14]], align 8 +// CHECK0-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK0-NEXT: store ptr null, ptr [[TMP15]], align 8 +// CHECK0-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK0-NEXT: store ptr [[TMP10]], ptr [[TMP16]], align 8 +// CHECK0-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK0-NEXT: store ptr [[TMP10]], ptr [[TMP17]], align 8 +// CHECK0-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK0-NEXT: store ptr null, ptr [[TMP18]], align 8 +// CHECK0-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK0-NEXT: store i64 [[TMP12]], ptr [[TMP19]], align 8 +// CHECK0-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK0-NEXT: store i64 [[TMP12]], ptr [[TMP20]], align 8 +// CHECK0-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK0-NEXT: store ptr null, ptr [[TMP21]], align 8 +// CHECK0-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK0-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK0-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 +// CHECK0-NEXT: store i32 2, ptr [[TMP24]], align 4 +// CHECK0-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 +// CHECK0-NEXT: store i32 3, ptr [[TMP25]], align 4 +// CHECK0-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 +// CHECK0-NEXT: store ptr [[TMP22]], ptr [[TMP26]], align 8 +// CHECK0-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 +// CHECK0-NEXT: store ptr [[TMP23]], ptr [[TMP27]], align 8 +// CHECK0-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 +// CHECK0-NEXT: store ptr @.offload_sizes, ptr [[TMP28]], align 8 +// CHECK0-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 +// CHECK0-NEXT: store ptr @.offload_maptypes, ptr [[TMP29]], align 8 +// CHECK0-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 +// CHECK0-NEXT: store ptr null, ptr [[TMP30]], align 8 +// CHECK0-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 +// CHECK0-NEXT: store ptr null, ptr [[TMP31]], align 8 +// CHECK0-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 +// CHECK0-NEXT: store i64 0, ptr [[TMP32]], align 8 +// CHECK0-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 +// CHECK0-NEXT: store i64 0, ptr [[TMP33]], align 8 +// CHECK0-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 +// CHECK0-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP34]], align 4 +// CHECK0-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 +// CHECK0-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP35]], align 4 +// CHECK0-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 +// CHECK0-NEXT: store i32 0, ptr [[TMP36]], align 4 +// CHECK0-NEXT: [[TMP37:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1:[0-9]+]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63.region_id, ptr [[KERNEL_ARGS]]) +// CHECK0-NEXT: [[TMP38:%.*]] = icmp ne i32 [[TMP37]], 0 +// CHECK0-NEXT: br i1 [[TMP38]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK0: omp_offload.failed: -// CHECK0-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63(i64 [[TMP9]], i32* [[TMP10]], i64 [[TMP12]]) #[[ATTR3:[0-9]+]] +// CHECK0-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63(i64 [[TMP9]], ptr [[TMP10]], i64 [[TMP12]]) #[[ATTR3:[0-9]+]] // CHECK0-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK0: omp_offload.cont: -// CHECK0-NEXT: [[TMP45:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK0-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK0-NEXT: store i16 [[TMP45]], i16* [[CONV3]], align 2 -// CHECK0-NEXT: [[TMP46:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK0-NEXT: [[TMP47:%.*]] = mul nuw i64 [[TMP1]], 4 -// CHECK0-NEXT: [[TMP48:%.*]] = mul nuw i64 5, [[TMP4]] -// CHECK0-NEXT: [[TMP49:%.*]] = mul nuw i64 [[TMP48]], 8 -// CHECK0-NEXT: [[TMP50:%.*]] = bitcast [9 x i64]* [[DOTOFFLOAD_SIZES]] to i8* -// CHECK0-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP50]], i8* align 8 bitcast ([9 x i64]* @.offload_sizes.1 to i8*), i64 72, i1 false) -// CHECK0-NEXT: [[TMP51:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK0-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i64* -// CHECK0-NEXT: store i64 [[TMP46]], i64* [[TMP52]], align 8 -// CHECK0-NEXT: [[TMP53:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK0-NEXT: [[TMP54:%.*]] = bitcast i8** [[TMP53]] to i64* -// CHECK0-NEXT: store i64 [[TMP46]], i64* [[TMP54]], align 8 -// CHECK0-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 -// CHECK0-NEXT: store i8* null, i8** [[TMP55]], align 8 -// CHECK0-NEXT: [[TMP56:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1 -// CHECK0-NEXT: [[TMP57:%.*]] = bitcast i8** [[TMP56]] to [10 x float]** -// CHECK0-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP57]], align 8 -// CHECK0-NEXT: [[TMP58:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1 -// CHECK0-NEXT: [[TMP59:%.*]] = bitcast i8** [[TMP58]] to [10 x float]** -// CHECK0-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP59]], align 8 -// CHECK0-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 1 -// CHECK0-NEXT: store i8* null, i8** [[TMP60]], align 8 -// CHECK0-NEXT: [[TMP61:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 2 -// CHECK0-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i64* -// CHECK0-NEXT: store i64 [[TMP1]], i64* [[TMP62]], align 8 -// CHECK0-NEXT: [[TMP63:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 2 -// CHECK0-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i64* -// CHECK0-NEXT: store i64 [[TMP1]], i64* [[TMP64]], align 8 -// CHECK0-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 2 -// CHECK0-NEXT: store i8* null, i8** [[TMP65]], align 8 -// CHECK0-NEXT: [[TMP66:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 3 -// CHECK0-NEXT: [[TMP67:%.*]] = bitcast i8** [[TMP66]] to float** -// CHECK0-NEXT: store float* [[VLA]], float** [[TMP67]], align 8 -// CHECK0-NEXT: [[TMP68:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 3 -// CHECK0-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to float** -// CHECK0-NEXT: store float* [[VLA]], float** [[TMP69]], align 8 -// CHECK0-NEXT: [[TMP70:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 -// CHECK0-NEXT: store i64 [[TMP47]], i64* [[TMP70]], align 8 -// CHECK0-NEXT: [[TMP71:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 3 -// CHECK0-NEXT: store i8* null, i8** [[TMP71]], align 8 -// CHECK0-NEXT: [[TMP72:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 4 -// CHECK0-NEXT: [[TMP73:%.*]] = bitcast i8** [[TMP72]] to [5 x [10 x double]]** -// CHECK0-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP73]], align 8 -// CHECK0-NEXT: [[TMP74:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 4 -// CHECK0-NEXT: [[TMP75:%.*]] = bitcast i8** [[TMP74]] to [5 x [10 x double]]** -// CHECK0-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP75]], align 8 -// CHECK0-NEXT: [[TMP76:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 4 -// CHECK0-NEXT: store i8* null, i8** [[TMP76]], align 8 -// CHECK0-NEXT: [[TMP77:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 5 -// CHECK0-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i64* -// CHECK0-NEXT: store i64 5, i64* [[TMP78]], align 8 -// CHECK0-NEXT: [[TMP79:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 5 -// CHECK0-NEXT: [[TMP80:%.*]] = bitcast i8** [[TMP79]] to i64* -// CHECK0-NEXT: store i64 5, i64* [[TMP80]], align 8 -// CHECK0-NEXT: [[TMP81:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 5 -// CHECK0-NEXT: store i8* null, i8** [[TMP81]], align 8 -// CHECK0-NEXT: [[TMP82:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 6 -// CHECK0-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i64* -// CHECK0-NEXT: store i64 [[TMP4]], i64* [[TMP83]], align 8 -// CHECK0-NEXT: [[TMP84:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 6 -// CHECK0-NEXT: [[TMP85:%.*]] = bitcast i8** [[TMP84]] to i64* -// CHECK0-NEXT: store i64 [[TMP4]], i64* [[TMP85]], align 8 -// CHECK0-NEXT: [[TMP86:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 6 -// CHECK0-NEXT: store i8* null, i8** [[TMP86]], align 8 -// CHECK0-NEXT: [[TMP87:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 7 -// CHECK0-NEXT: [[TMP88:%.*]] = bitcast i8** [[TMP87]] to double** -// CHECK0-NEXT: store double* [[VLA1]], double** [[TMP88]], align 8 -// CHECK0-NEXT: [[TMP89:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 7 -// CHECK0-NEXT: [[TMP90:%.*]] = bitcast i8** [[TMP89]] to double** -// CHECK0-NEXT: store double* [[VLA1]], double** [[TMP90]], align 8 -// CHECK0-NEXT: [[TMP91:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 -// CHECK0-NEXT: store i64 [[TMP49]], i64* [[TMP91]], align 8 -// CHECK0-NEXT: [[TMP92:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 7 -// CHECK0-NEXT: store i8* null, i8** [[TMP92]], align 8 -// CHECK0-NEXT: [[TMP93:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 8 -// CHECK0-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to %struct.TT** -// CHECK0-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP94]], align 8 -// CHECK0-NEXT: [[TMP95:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 8 -// CHECK0-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to %struct.TT** -// CHECK0-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP96]], align 8 -// CHECK0-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 8 -// CHECK0-NEXT: store i8* null, i8** [[TMP97]], align 8 -// CHECK0-NEXT: [[TMP98:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK0-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK0-NEXT: [[TMP100:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK0-NEXT: [[TMP101:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 0 -// CHECK0-NEXT: store i32 2, i32* [[TMP101]], align 4 -// CHECK0-NEXT: [[TMP102:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 1 -// CHECK0-NEXT: store i32 9, i32* [[TMP102]], align 4 -// CHECK0-NEXT: [[TMP103:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 2 -// CHECK0-NEXT: store i8** [[TMP98]], i8*** [[TMP103]], align 8 -// CHECK0-NEXT: [[TMP104:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 3 -// CHECK0-NEXT: store i8** [[TMP99]], i8*** [[TMP104]], align 8 -// CHECK0-NEXT: [[TMP105:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 4 -// CHECK0-NEXT: store i64* [[TMP100]], i64** [[TMP105]], align 8 -// CHECK0-NEXT: [[TMP106:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 5 -// CHECK0-NEXT: store i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.2, i32 0, i32 0), i64** [[TMP106]], align 8 -// CHECK0-NEXT: [[TMP107:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 6 -// CHECK0-NEXT: store i8** null, i8*** [[TMP107]], align 8 -// CHECK0-NEXT: [[TMP108:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 7 -// CHECK0-NEXT: store i8** null, i8*** [[TMP108]], align 8 -// CHECK0-NEXT: [[TMP109:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 8 -// CHECK0-NEXT: store i64 0, i64* [[TMP109]], align 8 -// CHECK0-NEXT: [[TMP110:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 9 -// CHECK0-NEXT: store i64 0, i64* [[TMP110]], align 8 -// CHECK0-NEXT: [[TMP111:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 10 -// CHECK0-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP111]], align 4 -// CHECK0-NEXT: [[TMP112:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 11 -// CHECK0-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP112]], align 4 -// CHECK0-NEXT: [[TMP113:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 12 -// CHECK0-NEXT: store i32 0, i32* [[TMP113]], align 4 -// CHECK0-NEXT: [[TMP114:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]]) -// CHECK0-NEXT: [[TMP115:%.*]] = icmp ne i32 [[TMP114]], 0 -// CHECK0-NEXT: br i1 [[TMP115]], label [[OMP_OFFLOAD_FAILED8:%.*]], label [[OMP_OFFLOAD_CONT9:%.*]] -// CHECK0: omp_offload.failed8: -// CHECK0-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70(i64 [[TMP46]], [10 x float]* [[B]], i64 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP4]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] -// CHECK0-NEXT: br label [[OMP_OFFLOAD_CONT9]] -// CHECK0: omp_offload.cont9: -// CHECK0-NEXT: [[TMP116:%.*]] = load double*, double** [[PTR_ADDR]], align 8 -// CHECK0-NEXT: [[TMP117:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0 -// CHECK0-NEXT: [[TMP118:%.*]] = bitcast i8** [[TMP117]] to double** -// CHECK0-NEXT: store double* [[TMP116]], double** [[TMP118]], align 8 -// CHECK0-NEXT: [[TMP119:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0 -// CHECK0-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to double** -// CHECK0-NEXT: store double* [[TMP116]], double** [[TMP120]], align 8 -// CHECK0-NEXT: [[TMP121:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 0 -// CHECK0-NEXT: store i8* null, i8** [[TMP121]], align 8 -// CHECK0-NEXT: [[TMP122:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 1 -// CHECK0-NEXT: [[TMP123:%.*]] = bitcast i8** [[TMP122]] to %struct.TT.0** -// CHECK0-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[TMP123]], align 8 -// CHECK0-NEXT: [[TMP124:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 1 -// CHECK0-NEXT: [[TMP125:%.*]] = bitcast i8** [[TMP124]] to %struct.TT.0** -// CHECK0-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[TMP125]], align 8 -// CHECK0-NEXT: [[TMP126:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 1 -// CHECK0-NEXT: store i8* null, i8** [[TMP126]], align 8 -// CHECK0-NEXT: [[TMP127:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0 -// CHECK0-NEXT: [[TMP128:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0 -// CHECK0-NEXT: [[TMP129:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 0 -// CHECK0-NEXT: store i32 2, i32* [[TMP129]], align 4 -// CHECK0-NEXT: [[TMP130:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 1 -// CHECK0-NEXT: store i32 2, i32* [[TMP130]], align 4 -// CHECK0-NEXT: [[TMP131:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 2 -// CHECK0-NEXT: store i8** [[TMP127]], i8*** [[TMP131]], align 8 -// CHECK0-NEXT: [[TMP132:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 3 -// CHECK0-NEXT: store i8** [[TMP128]], i8*** [[TMP132]], align 8 -// CHECK0-NEXT: [[TMP133:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 4 -// CHECK0-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.3, i32 0, i32 0), i64** [[TMP133]], align 8 -// CHECK0-NEXT: [[TMP134:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 5 -// CHECK0-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.4, i32 0, i32 0), i64** [[TMP134]], align 8 -// CHECK0-NEXT: [[TMP135:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 6 -// CHECK0-NEXT: store i8** null, i8*** [[TMP135]], align 8 -// CHECK0-NEXT: [[TMP136:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 7 -// CHECK0-NEXT: store i8** null, i8*** [[TMP136]], align 8 -// CHECK0-NEXT: [[TMP137:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 8 -// CHECK0-NEXT: store i64 0, i64* [[TMP137]], align 8 -// CHECK0-NEXT: [[TMP138:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 9 -// CHECK0-NEXT: store i64 0, i64* [[TMP138]], align 8 -// CHECK0-NEXT: [[TMP139:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 10 -// CHECK0-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP139]], align 4 -// CHECK0-NEXT: [[TMP140:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 11 -// CHECK0-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP140]], align 4 -// CHECK0-NEXT: [[TMP141:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 12 -// CHECK0-NEXT: store i32 0, i32* [[TMP141]], align 4 -// CHECK0-NEXT: [[TMP142:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]]) -// CHECK0-NEXT: [[TMP143:%.*]] = icmp ne i32 [[TMP142]], 0 -// CHECK0-NEXT: br i1 [[TMP143]], label [[OMP_OFFLOAD_FAILED14:%.*]], label [[OMP_OFFLOAD_CONT15:%.*]] -// CHECK0: omp_offload.failed14: -// CHECK0-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111(double* [[TMP116]], %struct.TT.0* [[E]]) #[[ATTR3]] -// CHECK0-NEXT: br label [[OMP_OFFLOAD_CONT15]] -// CHECK0: omp_offload.cont15: -// CHECK0-NEXT: [[TMP144:%.*]] = load i32, i32* [[A]], align 4 -// CHECK0-NEXT: [[TMP145:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK0-NEXT: call void @llvm.stackrestore(i8* [[TMP145]]) -// CHECK0-NEXT: ret i32 [[TMP144]] +// CHECK0-NEXT: [[TMP39:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK0-NEXT: store i16 [[TMP39]], ptr [[AA_CASTED]], align 2 +// CHECK0-NEXT: [[TMP40:%.*]] = load i64, ptr [[AA_CASTED]], align 8 +// CHECK0-NEXT: [[TMP41:%.*]] = mul nuw i64 [[TMP1]], 4 +// CHECK0-NEXT: [[TMP42:%.*]] = mul nuw i64 5, [[TMP4]] +// CHECK0-NEXT: [[TMP43:%.*]] = mul nuw i64 [[TMP42]], 8 +// CHECK0-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes.1, i64 72, i1 false) +// CHECK0-NEXT: [[TMP44:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 +// CHECK0-NEXT: store i64 [[TMP40]], ptr [[TMP44]], align 8 +// CHECK0-NEXT: [[TMP45:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 +// CHECK0-NEXT: store i64 [[TMP40]], ptr [[TMP45]], align 8 +// CHECK0-NEXT: [[TMP46:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i64 0, i64 0 +// CHECK0-NEXT: store ptr null, ptr [[TMP46]], align 8 +// CHECK0-NEXT: [[TMP47:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 1 +// CHECK0-NEXT: store ptr [[B]], ptr [[TMP47]], align 8 +// CHECK0-NEXT: [[TMP48:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 1 +// CHECK0-NEXT: store ptr [[B]], ptr [[TMP48]], align 8 +// CHECK0-NEXT: [[TMP49:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i64 0, i64 1 +// CHECK0-NEXT: store ptr null, ptr [[TMP49]], align 8 +// CHECK0-NEXT: [[TMP50:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 2 +// CHECK0-NEXT: store i64 [[TMP1]], ptr [[TMP50]], align 8 +// CHECK0-NEXT: [[TMP51:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 2 +// CHECK0-NEXT: store i64 [[TMP1]], ptr [[TMP51]], align 8 +// CHECK0-NEXT: [[TMP52:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i64 0, i64 2 +// CHECK0-NEXT: store ptr null, ptr [[TMP52]], align 8 +// CHECK0-NEXT: [[TMP53:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 3 +// CHECK0-NEXT: store ptr [[VLA]], ptr [[TMP53]], align 8 +// CHECK0-NEXT: [[TMP54:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 3 +// CHECK0-NEXT: store ptr [[VLA]], ptr [[TMP54]], align 8 +// CHECK0-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK0-NEXT: store i64 [[TMP41]], ptr [[TMP55]], align 8 +// CHECK0-NEXT: [[TMP56:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i64 0, i64 3 +// CHECK0-NEXT: store ptr null, ptr [[TMP56]], align 8 +// CHECK0-NEXT: [[TMP57:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 4 +// CHECK0-NEXT: store ptr [[C]], ptr [[TMP57]], align 8 +// CHECK0-NEXT: [[TMP58:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 4 +// CHECK0-NEXT: store ptr [[C]], ptr [[TMP58]], align 8 +// CHECK0-NEXT: [[TMP59:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i64 0, i64 4 +// CHECK0-NEXT: store ptr null, ptr [[TMP59]], align 8 +// CHECK0-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 5 +// CHECK0-NEXT: store i64 5, ptr [[TMP60]], align 8 +// CHECK0-NEXT: [[TMP61:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 5 +// CHECK0-NEXT: store i64 5, ptr [[TMP61]], align 8 +// CHECK0-NEXT: [[TMP62:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i64 0, i64 5 +// CHECK0-NEXT: store ptr null, ptr [[TMP62]], align 8 +// CHECK0-NEXT: [[TMP63:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 6 +// CHECK0-NEXT: store i64 [[TMP4]], ptr [[TMP63]], align 8 +// CHECK0-NEXT: [[TMP64:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 6 +// CHECK0-NEXT: store i64 [[TMP4]], ptr [[TMP64]], align 8 +// CHECK0-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i64 0, i64 6 +// CHECK0-NEXT: store ptr null, ptr [[TMP65]], align 8 +// CHECK0-NEXT: [[TMP66:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 7 +// CHECK0-NEXT: store ptr [[VLA1]], ptr [[TMP66]], align 8 +// CHECK0-NEXT: [[TMP67:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 7 +// CHECK0-NEXT: store ptr [[VLA1]], ptr [[TMP67]], align 8 +// CHECK0-NEXT: [[TMP68:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 7 +// CHECK0-NEXT: store i64 [[TMP43]], ptr [[TMP68]], align 8 +// CHECK0-NEXT: [[TMP69:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i64 0, i64 7 +// CHECK0-NEXT: store ptr null, ptr [[TMP69]], align 8 +// CHECK0-NEXT: [[TMP70:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 8 +// CHECK0-NEXT: store ptr [[D]], ptr [[TMP70]], align 8 +// CHECK0-NEXT: [[TMP71:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 8 +// CHECK0-NEXT: store ptr [[D]], ptr [[TMP71]], align 8 +// CHECK0-NEXT: [[TMP72:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i64 0, i64 8 +// CHECK0-NEXT: store ptr null, ptr [[TMP72]], align 8 +// CHECK0-NEXT: [[TMP73:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 +// CHECK0-NEXT: [[TMP74:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 +// CHECK0-NEXT: [[TMP75:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK0-NEXT: [[TMP76:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 0 +// CHECK0-NEXT: store i32 2, ptr [[TMP76]], align 4 +// CHECK0-NEXT: [[TMP77:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 1 +// CHECK0-NEXT: store i32 9, ptr [[TMP77]], align 4 +// CHECK0-NEXT: [[TMP78:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 2 +// CHECK0-NEXT: store ptr [[TMP73]], ptr [[TMP78]], align 8 +// CHECK0-NEXT: [[TMP79:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 3 +// CHECK0-NEXT: store ptr [[TMP74]], ptr [[TMP79]], align 8 +// CHECK0-NEXT: [[TMP80:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 4 +// CHECK0-NEXT: store ptr [[TMP75]], ptr [[TMP80]], align 8 +// CHECK0-NEXT: [[TMP81:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 5 +// CHECK0-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP81]], align 8 +// CHECK0-NEXT: [[TMP82:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 6 +// CHECK0-NEXT: store ptr null, ptr [[TMP82]], align 8 +// CHECK0-NEXT: [[TMP83:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 7 +// CHECK0-NEXT: store ptr null, ptr [[TMP83]], align 8 +// CHECK0-NEXT: [[TMP84:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 8 +// CHECK0-NEXT: store i64 0, ptr [[TMP84]], align 8 +// CHECK0-NEXT: [[TMP85:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 9 +// CHECK0-NEXT: store i64 0, ptr [[TMP85]], align 8 +// CHECK0-NEXT: [[TMP86:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 10 +// CHECK0-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP86]], align 4 +// CHECK0-NEXT: [[TMP87:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 11 +// CHECK0-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP87]], align 4 +// CHECK0-NEXT: [[TMP88:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 12 +// CHECK0-NEXT: store i32 0, ptr [[TMP88]], align 4 +// CHECK0-NEXT: [[TMP89:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70.region_id, ptr [[KERNEL_ARGS5]]) +// CHECK0-NEXT: [[TMP90:%.*]] = icmp ne i32 [[TMP89]], 0 +// CHECK0-NEXT: br i1 [[TMP90]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] +// CHECK0: omp_offload.failed6: +// CHECK0-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70(i64 [[TMP40]], ptr [[B]], i64 [[TMP1]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP4]], ptr [[VLA1]], ptr [[D]]) #[[ATTR3]] +// CHECK0-NEXT: br label [[OMP_OFFLOAD_CONT7]] +// CHECK0: omp_offload.cont7: +// CHECK0-NEXT: [[TMP91:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8 +// CHECK0-NEXT: [[TMP92:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 0 +// CHECK0-NEXT: store ptr [[TMP91]], ptr [[TMP92]], align 8 +// CHECK0-NEXT: [[TMP93:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS9]], i32 0, i32 0 +// CHECK0-NEXT: store ptr [[TMP91]], ptr [[TMP93]], align 8 +// CHECK0-NEXT: [[TMP94:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS10]], i64 0, i64 0 +// CHECK0-NEXT: store ptr null, ptr [[TMP94]], align 8 +// CHECK0-NEXT: [[TMP95:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 1 +// CHECK0-NEXT: store ptr [[E]], ptr [[TMP95]], align 8 +// CHECK0-NEXT: [[TMP96:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS9]], i32 0, i32 1 +// CHECK0-NEXT: store ptr [[E]], ptr [[TMP96]], align 8 +// CHECK0-NEXT: [[TMP97:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS10]], i64 0, i64 1 +// CHECK0-NEXT: store ptr null, ptr [[TMP97]], align 8 +// CHECK0-NEXT: [[TMP98:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 0 +// CHECK0-NEXT: [[TMP99:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS9]], i32 0, i32 0 +// CHECK0-NEXT: [[TMP100:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 0 +// CHECK0-NEXT: store i32 2, ptr [[TMP100]], align 4 +// CHECK0-NEXT: [[TMP101:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 1 +// CHECK0-NEXT: store i32 2, ptr [[TMP101]], align 4 +// CHECK0-NEXT: [[TMP102:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 2 +// CHECK0-NEXT: store ptr [[TMP98]], ptr [[TMP102]], align 8 +// CHECK0-NEXT: [[TMP103:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 3 +// CHECK0-NEXT: store ptr [[TMP99]], ptr [[TMP103]], align 8 +// CHECK0-NEXT: [[TMP104:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 4 +// CHECK0-NEXT: store ptr @.offload_sizes.3, ptr [[TMP104]], align 8 +// CHECK0-NEXT: [[TMP105:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 5 +// CHECK0-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP105]], align 8 +// CHECK0-NEXT: [[TMP106:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 6 +// CHECK0-NEXT: store ptr null, ptr [[TMP106]], align 8 +// CHECK0-NEXT: [[TMP107:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 7 +// CHECK0-NEXT: store ptr null, ptr [[TMP107]], align 8 +// CHECK0-NEXT: [[TMP108:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 8 +// CHECK0-NEXT: store i64 0, ptr [[TMP108]], align 8 +// CHECK0-NEXT: [[TMP109:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 9 +// CHECK0-NEXT: store i64 0, ptr [[TMP109]], align 8 +// CHECK0-NEXT: [[TMP110:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 10 +// CHECK0-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP110]], align 4 +// CHECK0-NEXT: [[TMP111:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 11 +// CHECK0-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP111]], align 4 +// CHECK0-NEXT: [[TMP112:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 12 +// CHECK0-NEXT: store i32 0, ptr [[TMP112]], align 4 +// CHECK0-NEXT: [[TMP113:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111.region_id, ptr [[KERNEL_ARGS11]]) +// CHECK0-NEXT: [[TMP114:%.*]] = icmp ne i32 [[TMP113]], 0 +// CHECK0-NEXT: br i1 [[TMP114]], label [[OMP_OFFLOAD_FAILED12:%.*]], label [[OMP_OFFLOAD_CONT13:%.*]] +// CHECK0: omp_offload.failed12: +// CHECK0-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111(ptr [[TMP91]], ptr [[E]]) #[[ATTR3]] +// CHECK0-NEXT: br label [[OMP_OFFLOAD_CONT13]] +// CHECK0: omp_offload.cont13: +// CHECK0-NEXT: [[TMP115:%.*]] = load i32, ptr [[A]], align 4 +// CHECK0-NEXT: [[TMP116:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 +// CHECK0-NEXT: call void @llvm.stackrestore(ptr [[TMP116]]) +// CHECK0-NEXT: ret i32 [[TMP115]] // // // CHECK0-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63 -// CHECK0-SAME: (i64 noundef [[A:%.*]], i32* noundef [[P:%.*]], i64 noundef [[GA:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK0-SAME: (i64 noundef [[A:%.*]], ptr noundef [[P:%.*]], i64 noundef [[GA:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK0-NEXT: entry: // CHECK0-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK0-NEXT: [[P_ADDR:%.*]] = alloca i32*, align 8 +// CHECK0-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 8 // CHECK0-NEXT: [[GA_ADDR:%.*]] = alloca i64, align 8 -// CHECK0-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK0-NEXT: store i32* [[P]], i32** [[P_ADDR]], align 8 -// CHECK0-NEXT: store i64 [[GA]], i64* [[GA_ADDR]], align 8 -// CHECK0-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK0-NEXT: [[CONV1:%.*]] = bitcast i64* [[GA_ADDR]] to i32* +// CHECK0-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 +// CHECK0-NEXT: store ptr [[P]], ptr [[P_ADDR]], align 8 +// CHECK0-NEXT: store i64 [[GA]], ptr [[GA_ADDR]], align 8 // CHECK0-NEXT: ret void // // // CHECK0-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70 -// CHECK0-SAME: (i64 noundef [[AA:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { +// CHECK0-SAME: (i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { // CHECK0-NEXT: entry: // CHECK0-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK0-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK0-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 // CHECK0-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK0-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 -// CHECK0-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK0-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 8 +// CHECK0-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 // CHECK0-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 // CHECK0-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 -// CHECK0-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 -// CHECK0-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK0-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 8 +// CHECK0-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 // CHECK0-NEXT: [[B5:%.*]] = alloca [10 x float], align 4 -// CHECK0-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK0-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 // CHECK0-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 // CHECK0-NEXT: [[C7:%.*]] = alloca [5 x [10 x double]], align 8 // CHECK0-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 // CHECK0-NEXT: [[__VLA_EXPR2:%.*]] = alloca i64, align 8 // CHECK0-NEXT: [[D9:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 -// CHECK0-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK0-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 -// CHECK0-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK0-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 -// CHECK0-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 -// CHECK0-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK0-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 -// CHECK0-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 -// CHECK0-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 -// CHECK0-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK0-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 -// CHECK0-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK0-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 -// CHECK0-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 -// CHECK0-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK0-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 -// CHECK0-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 -// CHECK0-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 -// CHECK0-NEXT: [[TMP8:%.*]] = bitcast [10 x float]* [[B5]] to i8* -// CHECK0-NEXT: [[TMP9:%.*]] = bitcast [10 x float]* [[TMP0]] to i8* -// CHECK0-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i64 40, i1 false) -// CHECK0-NEXT: [[TMP10:%.*]] = call i8* @llvm.stacksave() -// CHECK0-NEXT: store i8* [[TMP10]], i8** [[SAVED_STACK]], align 8 +// CHECK0-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 +// CHECK0-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 +// CHECK0-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 +// CHECK0-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 8 +// CHECK0-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 +// CHECK0-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 +// CHECK0-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8 +// CHECK0-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8 +// CHECK0-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 +// CHECK0-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// CHECK0-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 +// CHECK0-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8 +// CHECK0-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 +// CHECK0-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 +// CHECK0-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8 +// CHECK0-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8 +// CHECK0-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8 +// CHECK0-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[B5]], ptr align 4 [[TMP0]], i64 40, i1 false) +// CHECK0-NEXT: [[TMP8:%.*]] = call ptr @llvm.stacksave() +// CHECK0-NEXT: store ptr [[TMP8]], ptr [[SAVED_STACK]], align 8 // CHECK0-NEXT: [[VLA6:%.*]] = alloca float, i64 [[TMP1]], align 4 -// CHECK0-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK0-NEXT: [[TMP11:%.*]] = mul nuw i64 [[TMP1]], 4 -// CHECK0-NEXT: [[TMP12:%.*]] = bitcast float* [[VLA6]] to i8* -// CHECK0-NEXT: [[TMP13:%.*]] = bitcast float* [[TMP2]] to i8* -// CHECK0-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 [[TMP11]], i1 false) -// CHECK0-NEXT: [[TMP14:%.*]] = bitcast [5 x [10 x double]]* [[C7]] to i8* -// CHECK0-NEXT: [[TMP15:%.*]] = bitcast [5 x [10 x double]]* [[TMP3]] to i8* -// CHECK0-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP14]], i8* align 8 [[TMP15]], i64 400, i1 false) -// CHECK0-NEXT: [[TMP16:%.*]] = mul nuw i64 [[TMP4]], [[TMP5]] -// CHECK0-NEXT: [[VLA8:%.*]] = alloca double, i64 [[TMP16]], align 8 -// CHECK0-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// CHECK0-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR2]], align 8 -// CHECK0-NEXT: [[TMP17:%.*]] = mul nuw i64 [[TMP4]], [[TMP5]] -// CHECK0-NEXT: [[TMP18:%.*]] = mul nuw i64 [[TMP17]], 8 -// CHECK0-NEXT: [[TMP19:%.*]] = bitcast double* [[VLA8]] to i8* -// CHECK0-NEXT: [[TMP20:%.*]] = bitcast double* [[TMP6]] to i8* -// CHECK0-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP19]], i8* align 8 [[TMP20]], i64 [[TMP18]], i1 false) -// CHECK0-NEXT: [[TMP21:%.*]] = bitcast %struct.TT* [[D9]] to i8* -// CHECK0-NEXT: [[TMP22:%.*]] = bitcast %struct.TT* [[TMP7]] to i8* -// CHECK0-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP21]], i8* align 8 [[TMP22]], i64 16, i1 false) -// CHECK0-NEXT: [[TMP23:%.*]] = load i16, i16* [[CONV]], align 2 -// CHECK0-NEXT: [[CONV10:%.*]] = sext i16 [[TMP23]] to i32 -// CHECK0-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV10]], 1 -// CHECK0-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD]] to i16 -// CHECK0-NEXT: store i16 [[CONV11]], i16* [[CONV]], align 2 -// CHECK0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B5]], i64 0, i64 2 -// CHECK0-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4 -// CHECK0-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA6]], i64 3 -// CHECK0-NEXT: store float 1.000000e+00, float* [[ARRAYIDX12]], align 4 -// CHECK0-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C7]], i64 0, i64 1 -// CHECK0-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], i64 0, i64 2 -// CHECK0-NEXT: store double 1.000000e+00, double* [[ARRAYIDX14]], align 8 -// CHECK0-NEXT: [[TMP24:%.*]] = mul nsw i64 1, [[TMP5]] -// CHECK0-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[VLA8]], i64 [[TMP24]] -// CHECK0-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 -// CHECK0-NEXT: store double 1.000000e+00, double* [[ARRAYIDX16]], align 8 -// CHECK0-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 0 -// CHECK0-NEXT: store i64 1, i64* [[X]], align 8 -// CHECK0-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 1 -// CHECK0-NEXT: store i8 1, i8* [[Y]], align 8 -// CHECK0-NEXT: [[TMP25:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK0-NEXT: call void @llvm.stackrestore(i8* [[TMP25]]) +// CHECK0-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 +// CHECK0-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP1]], 4 +// CHECK0-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VLA6]], ptr align 4 [[TMP2]], i64 [[TMP9]], i1 false) +// CHECK0-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[C7]], ptr align 8 [[TMP3]], i64 400, i1 false) +// CHECK0-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP4]], [[TMP5]] +// CHECK0-NEXT: [[VLA8:%.*]] = alloca double, i64 [[TMP10]], align 8 +// CHECK0-NEXT: store i64 [[TMP4]], ptr [[__VLA_EXPR1]], align 8 +// CHECK0-NEXT: store i64 [[TMP5]], ptr [[__VLA_EXPR2]], align 8 +// CHECK0-NEXT: [[TMP11:%.*]] = mul nuw i64 [[TMP4]], [[TMP5]] +// CHECK0-NEXT: [[TMP12:%.*]] = mul nuw i64 [[TMP11]], 8 +// CHECK0-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[VLA8]], ptr align 8 [[TMP6]], i64 [[TMP12]], i1 false) +// CHECK0-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[D9]], ptr align 8 [[TMP7]], i64 16, i1 false) +// CHECK0-NEXT: [[TMP13:%.*]] = load i16, ptr [[AA_ADDR]], align 2 +// CHECK0-NEXT: [[CONV:%.*]] = sext i16 [[TMP13]] to i32 +// CHECK0-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 +// CHECK0-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16 +// CHECK0-NEXT: store i16 [[CONV10]], ptr [[AA_ADDR]], align 2 +// CHECK0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B5]], i64 0, i64 2 +// CHECK0-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX]], align 4 +// CHECK0-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds float, ptr [[VLA6]], i64 3 +// CHECK0-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX11]], align 4 +// CHECK0-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C7]], i64 0, i64 1 +// CHECK0-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX12]], i64 0, i64 2 +// CHECK0-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX13]], align 8 +// CHECK0-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP5]] +// CHECK0-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, ptr [[VLA8]], i64 [[TMP14]] +// CHECK0-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX14]], i64 3 +// CHECK0-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX15]], align 8 +// CHECK0-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D9]], i32 0, i32 0 +// CHECK0-NEXT: store i64 1, ptr [[X]], align 8 +// CHECK0-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D9]], i32 0, i32 1 +// CHECK0-NEXT: store i8 1, ptr [[Y]], align 8 +// CHECK0-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 +// CHECK0-NEXT: call void @llvm.stackrestore(ptr [[TMP15]]) // CHECK0-NEXT: ret void // // // CHECK0-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111 -// CHECK0-SAME: (double* noundef [[PTR:%.*]], %struct.TT.0* noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR2]] { +// CHECK0-SAME: (ptr noundef [[PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR2]] { // CHECK0-NEXT: entry: -// CHECK0-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 8 -// CHECK0-NEXT: [[E_ADDR:%.*]] = alloca %struct.TT.0*, align 8 +// CHECK0-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8 +// CHECK0-NEXT: [[E_ADDR:%.*]] = alloca ptr, align 8 // CHECK0-NEXT: [[E1:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 4 -// CHECK0-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 8 -// CHECK0-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[E_ADDR]], align 8 -// CHECK0-NEXT: [[TMP0:%.*]] = load %struct.TT.0*, %struct.TT.0** [[E_ADDR]], align 8 -// CHECK0-NEXT: [[TMP1:%.*]] = bitcast %struct.TT.0* [[E1]] to i8* -// CHECK0-NEXT: [[TMP2:%.*]] = bitcast %struct.TT.0* [[TMP0]] to i8* -// CHECK0-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i64 8, i1 false) -// CHECK0-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E1]], i32 0, i32 0 -// CHECK0-NEXT: [[TMP3:%.*]] = load i32, i32* [[X]], align 4 -// CHECK0-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP3]] to double -// CHECK0-NEXT: [[TMP4:%.*]] = load double*, double** [[PTR_ADDR]], align 8 -// CHECK0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP4]], i64 0 -// CHECK0-NEXT: store double [[CONV]], double* [[ARRAYIDX]], align 8 -// CHECK0-NEXT: [[TMP5:%.*]] = load double*, double** [[PTR_ADDR]], align 8 -// CHECK0-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds double, double* [[TMP5]], i64 0 -// CHECK0-NEXT: [[TMP6:%.*]] = load double, double* [[ARRAYIDX2]], align 8 -// CHECK0-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// CHECK0-NEXT: store double [[INC]], double* [[ARRAYIDX2]], align 8 +// CHECK0-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 8 +// CHECK0-NEXT: store ptr [[E]], ptr [[E_ADDR]], align 8 +// CHECK0-NEXT: [[TMP0:%.*]] = load ptr, ptr [[E_ADDR]], align 8 +// CHECK0-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[E1]], ptr align 4 [[TMP0]], i64 8, i1 false) +// CHECK0-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], ptr [[E1]], i32 0, i32 0 +// CHECK0-NEXT: [[TMP1:%.*]] = load i32, ptr [[X]], align 4 +// CHECK0-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double +// CHECK0-NEXT: [[TMP2:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8 +// CHECK0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[TMP2]], i64 0 +// CHECK0-NEXT: store double [[CONV]], ptr [[ARRAYIDX]], align 8 +// CHECK0-NEXT: [[TMP3:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8 +// CHECK0-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds double, ptr [[TMP3]], i64 0 +// CHECK0-NEXT: [[TMP4:%.*]] = load double, ptr [[ARRAYIDX2]], align 8 +// CHECK0-NEXT: [[INC:%.*]] = fadd double [[TMP4]], 1.000000e+00 +// CHECK0-NEXT: store double [[INC]], ptr [[ARRAYIDX2]], align 8 // CHECK0-NEXT: ret void // // // CHECK0-LABEL: define {{[^@]+}}@_Z3bariPd -// CHECK0-SAME: (i32 noundef signext [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0]] { +// CHECK0-SAME: (i32 noundef signext [[N:%.*]], ptr noundef [[PTR:%.*]]) #[[ATTR0]] { // CHECK0-NEXT: entry: // CHECK0-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK0-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 8 +// CHECK0-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8 // CHECK0-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK0-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK0-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK0-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 8 -// CHECK0-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK0-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK0-NEXT: [[TMP1:%.*]] = load double*, double** [[PTR_ADDR]], align 8 -// CHECK0-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooiPd(i32 noundef signext [[TMP0]], double* noundef [[TMP1]]) -// CHECK0-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 +// CHECK0-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// CHECK0-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 8 +// CHECK0-NEXT: store i32 0, ptr [[A]], align 4 +// CHECK0-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// CHECK0-NEXT: [[TMP1:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8 +// CHECK0-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooiPd(i32 noundef signext [[TMP0]], ptr noundef [[TMP1]]) +// CHECK0-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 // CHECK0-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CALL]] -// CHECK0-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK0-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK0-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP3]]) -// CHECK0-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 +// CHECK0-NEXT: store i32 [[ADD]], ptr [[A]], align 4 +// CHECK0-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// CHECK0-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(ptr noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP3]]) +// CHECK0-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 4 // CHECK0-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], [[CALL1]] -// CHECK0-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK0-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK0-NEXT: store i32 [[ADD2]], ptr [[A]], align 4 +// CHECK0-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK0-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP5]]) -// CHECK0-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 +// CHECK0-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4 // CHECK0-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], [[CALL3]] -// CHECK0-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK0-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK0-NEXT: store i32 [[ADD4]], ptr [[A]], align 4 +// CHECK0-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK0-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP7]]) -// CHECK0-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK0-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 // CHECK0-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP8]], [[CALL5]] -// CHECK0-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK0-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 +// CHECK0-NEXT: store i32 [[ADD6]], ptr [[A]], align 4 +// CHECK0-NEXT: [[TMP9:%.*]] = load i32, ptr [[A]], align 4 // CHECK0-NEXT: ret i32 [[TMP9]] // // // CHECK0-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK0-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK0-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK0-NEXT: entry: -// CHECK0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK0-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK0-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK0-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK0-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 // CHECK0-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 // CHECK0-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK0-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK0-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK0-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 +// CHECK0-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 8 +// CHECK0-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 8 +// CHECK0-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 8 // CHECK0-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 // CHECK0-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 -// CHECK0-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK0-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK0-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK0-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// CHECK0-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// CHECK0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// CHECK0-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK0-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK0-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK0-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK0-NEXT: store i32 [[ADD]], ptr [[B]], align 4 +// CHECK0-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK0-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK0-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK0-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 +// CHECK0-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave() +// CHECK0-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8 // CHECK0-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] // CHECK0-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK0-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK0-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK0-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* -// CHECK0-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4 -// CHECK0-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK0-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK0-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 +// CHECK0-NEXT: [[TMP5:%.*]] = load i32, ptr [[B]], align 4 +// CHECK0-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 4 +// CHECK0-NEXT: [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 8 +// CHECK0-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK0-NEXT: [[TMP7:%.*]] = mul nuw i64 2, [[TMP2]] // CHECK0-NEXT: [[TMP8:%.*]] = mul nuw i64 [[TMP7]], 2 -// CHECK0-NEXT: [[TMP9:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* -// CHECK0-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP9]], i8* align 8 bitcast ([5 x i64]* @.offload_sizes.5 to i8*), i64 40, i1 false) -// CHECK0-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK0-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1** -// CHECK0-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 8 -// CHECK0-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK0-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double** -// CHECK0-NEXT: store double* [[A]], double** [[TMP13]], align 8 -// CHECK0-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK0-NEXT: store i8* null, i8** [[TMP14]], align 8 -// CHECK0-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK0-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* -// CHECK0-NEXT: store i64 [[TMP6]], i64* [[TMP16]], align 8 -// CHECK0-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK0-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* -// CHECK0-NEXT: store i64 [[TMP6]], i64* [[TMP18]], align 8 -// CHECK0-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK0-NEXT: store i8* null, i8** [[TMP19]], align 8 -// CHECK0-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK0-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* -// CHECK0-NEXT: store i64 2, i64* [[TMP21]], align 8 -// CHECK0-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK0-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* -// CHECK0-NEXT: store i64 2, i64* [[TMP23]], align 8 -// CHECK0-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK0-NEXT: store i8* null, i8** [[TMP24]], align 8 -// CHECK0-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK0-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64* -// CHECK0-NEXT: store i64 [[TMP2]], i64* [[TMP26]], align 8 -// CHECK0-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK0-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64* -// CHECK0-NEXT: store i64 [[TMP2]], i64* [[TMP28]], align 8 -// CHECK0-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 -// CHECK0-NEXT: store i8* null, i8** [[TMP29]], align 8 -// CHECK0-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK0-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i16** -// CHECK0-NEXT: store i16* [[VLA]], i16** [[TMP31]], align 8 -// CHECK0-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK0-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i16** -// CHECK0-NEXT: store i16* [[VLA]], i16** [[TMP33]], align 8 -// CHECK0-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 -// CHECK0-NEXT: store i64 [[TMP8]], i64* [[TMP34]], align 8 -// CHECK0-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 -// CHECK0-NEXT: store i8* null, i8** [[TMP35]], align 8 -// CHECK0-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK0-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK0-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK0-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 -// CHECK0-NEXT: store i32 2, i32* [[TMP39]], align 4 -// CHECK0-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 -// CHECK0-NEXT: store i32 5, i32* [[TMP40]], align 4 -// CHECK0-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 -// CHECK0-NEXT: store i8** [[TMP36]], i8*** [[TMP41]], align 8 -// CHECK0-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 -// CHECK0-NEXT: store i8** [[TMP37]], i8*** [[TMP42]], align 8 -// CHECK0-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 -// CHECK0-NEXT: store i64* [[TMP38]], i64** [[TMP43]], align 8 -// CHECK0-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 -// CHECK0-NEXT: store i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.6, i32 0, i32 0), i64** [[TMP44]], align 8 -// CHECK0-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 -// CHECK0-NEXT: store i8** null, i8*** [[TMP45]], align 8 -// CHECK0-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 -// CHECK0-NEXT: store i8** null, i8*** [[TMP46]], align 8 -// CHECK0-NEXT: [[TMP47:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 -// CHECK0-NEXT: store i64 0, i64* [[TMP47]], align 8 -// CHECK0-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 9 -// CHECK0-NEXT: store i64 0, i64* [[TMP48]], align 8 -// CHECK0-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 10 -// CHECK0-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP49]], align 4 -// CHECK0-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 11 -// CHECK0-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP50]], align 4 -// CHECK0-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 12 -// CHECK0-NEXT: store i32 0, i32* [[TMP51]], align 4 -// CHECK0-NEXT: [[TMP52:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) -// CHECK0-NEXT: [[TMP53:%.*]] = icmp ne i32 [[TMP52]], 0 -// CHECK0-NEXT: br i1 [[TMP53]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK0-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes.5, i64 40, i1 false) +// CHECK0-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK0-NEXT: store ptr [[THIS1]], ptr [[TMP9]], align 8 +// CHECK0-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK0-NEXT: store ptr [[A]], ptr [[TMP10]], align 8 +// CHECK0-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK0-NEXT: store ptr null, ptr [[TMP11]], align 8 +// CHECK0-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK0-NEXT: store i64 [[TMP6]], ptr [[TMP12]], align 8 +// CHECK0-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK0-NEXT: store i64 [[TMP6]], ptr [[TMP13]], align 8 +// CHECK0-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK0-NEXT: store ptr null, ptr [[TMP14]], align 8 +// CHECK0-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK0-NEXT: store i64 2, ptr [[TMP15]], align 8 +// CHECK0-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK0-NEXT: store i64 2, ptr [[TMP16]], align 8 +// CHECK0-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK0-NEXT: store ptr null, ptr [[TMP17]], align 8 +// CHECK0-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK0-NEXT: store i64 [[TMP2]], ptr [[TMP18]], align 8 +// CHECK0-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK0-NEXT: store i64 [[TMP2]], ptr [[TMP19]], align 8 +// CHECK0-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK0-NEXT: store ptr null, ptr [[TMP20]], align 8 +// CHECK0-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK0-NEXT: store ptr [[VLA]], ptr [[TMP21]], align 8 +// CHECK0-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK0-NEXT: store ptr [[VLA]], ptr [[TMP22]], align 8 +// CHECK0-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK0-NEXT: store i64 [[TMP8]], ptr [[TMP23]], align 8 +// CHECK0-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 +// CHECK0-NEXT: store ptr null, ptr [[TMP24]], align 8 +// CHECK0-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK0-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK0-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK0-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 +// CHECK0-NEXT: store i32 2, ptr [[TMP28]], align 4 +// CHECK0-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 +// CHECK0-NEXT: store i32 5, ptr [[TMP29]], align 4 +// CHECK0-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 +// CHECK0-NEXT: store ptr [[TMP25]], ptr [[TMP30]], align 8 +// CHECK0-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 +// CHECK0-NEXT: store ptr [[TMP26]], ptr [[TMP31]], align 8 +// CHECK0-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 +// CHECK0-NEXT: store ptr [[TMP27]], ptr [[TMP32]], align 8 +// CHECK0-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 +// CHECK0-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP33]], align 8 +// CHECK0-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 +// CHECK0-NEXT: store ptr null, ptr [[TMP34]], align 8 +// CHECK0-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 +// CHECK0-NEXT: store ptr null, ptr [[TMP35]], align 8 +// CHECK0-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 +// CHECK0-NEXT: store i64 0, ptr [[TMP36]], align 8 +// CHECK0-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 +// CHECK0-NEXT: store i64 0, ptr [[TMP37]], align 8 +// CHECK0-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 +// CHECK0-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP38]], align 4 +// CHECK0-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 +// CHECK0-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP39]], align 4 +// CHECK0-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 +// CHECK0-NEXT: store i32 0, ptr [[TMP40]], align 4 +// CHECK0-NEXT: [[TMP41:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167.region_id, ptr [[KERNEL_ARGS]]) +// CHECK0-NEXT: [[TMP42:%.*]] = icmp ne i32 [[TMP41]], 0 +// CHECK0-NEXT: br i1 [[TMP42]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK0: omp_offload.failed: -// CHECK0-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]] +// CHECK0-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167(ptr [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], ptr [[VLA]]) #[[ATTR3]] // CHECK0-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK0: omp_offload.cont: -// CHECK0-NEXT: [[TMP54:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP54]] -// CHECK0-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK0-NEXT: [[TMP55:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 -// CHECK0-NEXT: [[CONV3:%.*]] = sext i16 [[TMP55]] to i32 -// CHECK0-NEXT: [[TMP56:%.*]] = load i32, i32* [[B]], align 4 -// CHECK0-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP56]] -// CHECK0-NEXT: [[TMP57:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK0-NEXT: call void @llvm.stackrestore(i8* [[TMP57]]) -// CHECK0-NEXT: ret i32 [[ADD4]] +// CHECK0-NEXT: [[TMP43:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP43]] +// CHECK0-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1 +// CHECK0-NEXT: [[TMP44:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2 +// CHECK0-NEXT: [[CONV:%.*]] = sext i16 [[TMP44]] to i32 +// CHECK0-NEXT: [[TMP45:%.*]] = load i32, ptr [[B]], align 4 +// CHECK0-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP45]] +// CHECK0-NEXT: [[TMP46:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 +// CHECK0-NEXT: call void @llvm.stackrestore(ptr [[TMP46]]) +// CHECK0-NEXT: ret i32 [[ADD3]] // // // CHECK0-LABEL: define {{[^@]+}}@_ZL7fstatici @@ -6676,82 +6617,74 @@ int bar(int n, double *ptr) { // CHECK0-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 // CHECK0-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK0-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 -// CHECK0-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK0-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK0-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK0-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8 +// CHECK0-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 8 +// CHECK0-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 8 // CHECK0-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 -// CHECK0-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK0-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK0-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK0-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK0-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK0-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 -// CHECK0-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK0-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK0-NEXT: [[CONV1:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* -// CHECK0-NEXT: store i8 [[TMP2]], i8* [[CONV1]], align 1 -// CHECK0-NEXT: [[TMP3:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 -// CHECK0-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK0-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* -// CHECK0-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8 -// CHECK0-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK0-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* -// CHECK0-NEXT: store i64 [[TMP1]], i64* [[TMP7]], align 8 -// CHECK0-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK0-NEXT: store i8* null, i8** [[TMP8]], align 8 -// CHECK0-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK0-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* -// CHECK0-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 -// CHECK0-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK0-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* -// CHECK0-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8 -// CHECK0-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK0-NEXT: store i8* null, i8** [[TMP13]], align 8 -// CHECK0-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK0-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [10 x i32]** -// CHECK0-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP15]], align 8 -// CHECK0-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK0-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [10 x i32]** -// CHECK0-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP17]], align 8 -// CHECK0-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK0-NEXT: store i8* null, i8** [[TMP18]], align 8 -// CHECK0-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK0-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK0-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 -// CHECK0-NEXT: store i32 2, i32* [[TMP21]], align 4 -// CHECK0-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 -// CHECK0-NEXT: store i32 3, i32* [[TMP22]], align 4 -// CHECK0-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 -// CHECK0-NEXT: store i8** [[TMP19]], i8*** [[TMP23]], align 8 -// CHECK0-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 -// CHECK0-NEXT: store i8** [[TMP20]], i8*** [[TMP24]], align 8 -// CHECK0-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 -// CHECK0-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.7, i32 0, i32 0), i64** [[TMP25]], align 8 -// CHECK0-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 -// CHECK0-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.8, i32 0, i32 0), i64** [[TMP26]], align 8 -// CHECK0-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 -// CHECK0-NEXT: store i8** null, i8*** [[TMP27]], align 8 -// CHECK0-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 -// CHECK0-NEXT: store i8** null, i8*** [[TMP28]], align 8 -// CHECK0-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 -// CHECK0-NEXT: store i64 0, i64* [[TMP29]], align 8 -// CHECK0-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 9 -// CHECK0-NEXT: store i64 0, i64* [[TMP30]], align 8 -// CHECK0-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 10 -// CHECK0-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP31]], align 4 -// CHECK0-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 11 -// CHECK0-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP32]], align 4 -// CHECK0-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 12 -// CHECK0-NEXT: store i32 0, i32* [[TMP33]], align 4 -// CHECK0-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) -// CHECK0-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 -// CHECK0-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK0-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// CHECK0-NEXT: store i32 0, ptr [[A]], align 4 +// CHECK0-NEXT: store i8 0, ptr [[AAA]], align 1 +// CHECK0-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 +// CHECK0-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 +// CHECK0-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8 +// CHECK0-NEXT: [[TMP2:%.*]] = load i8, ptr [[AAA]], align 1 +// CHECK0-NEXT: store i8 [[TMP2]], ptr [[AAA_CASTED]], align 1 +// CHECK0-NEXT: [[TMP3:%.*]] = load i64, ptr [[AAA_CASTED]], align 8 +// CHECK0-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK0-NEXT: store i64 [[TMP1]], ptr [[TMP4]], align 8 +// CHECK0-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK0-NEXT: store i64 [[TMP1]], ptr [[TMP5]], align 8 +// CHECK0-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK0-NEXT: store ptr null, ptr [[TMP6]], align 8 +// CHECK0-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK0-NEXT: store i64 [[TMP3]], ptr [[TMP7]], align 8 +// CHECK0-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK0-NEXT: store i64 [[TMP3]], ptr [[TMP8]], align 8 +// CHECK0-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK0-NEXT: store ptr null, ptr [[TMP9]], align 8 +// CHECK0-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK0-NEXT: store ptr [[B]], ptr [[TMP10]], align 8 +// CHECK0-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK0-NEXT: store ptr [[B]], ptr [[TMP11]], align 8 +// CHECK0-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK0-NEXT: store ptr null, ptr [[TMP12]], align 8 +// CHECK0-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK0-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK0-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 +// CHECK0-NEXT: store i32 2, ptr [[TMP15]], align 4 +// CHECK0-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 +// CHECK0-NEXT: store i32 3, ptr [[TMP16]], align 4 +// CHECK0-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 +// CHECK0-NEXT: store ptr [[TMP13]], ptr [[TMP17]], align 8 +// CHECK0-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 +// CHECK0-NEXT: store ptr [[TMP14]], ptr [[TMP18]], align 8 +// CHECK0-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 +// CHECK0-NEXT: store ptr @.offload_sizes.7, ptr [[TMP19]], align 8 +// CHECK0-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 +// CHECK0-NEXT: store ptr @.offload_maptypes.8, ptr [[TMP20]], align 8 +// CHECK0-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 +// CHECK0-NEXT: store ptr null, ptr [[TMP21]], align 8 +// CHECK0-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 +// CHECK0-NEXT: store ptr null, ptr [[TMP22]], align 8 +// CHECK0-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 +// CHECK0-NEXT: store i64 0, ptr [[TMP23]], align 8 +// CHECK0-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 +// CHECK0-NEXT: store i64 0, ptr [[TMP24]], align 8 +// CHECK0-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 +// CHECK0-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP25]], align 4 +// CHECK0-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 +// CHECK0-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP26]], align 4 +// CHECK0-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 +// CHECK0-NEXT: store i32 0, ptr [[TMP27]], align 4 +// CHECK0-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142.region_id, ptr [[KERNEL_ARGS]]) +// CHECK0-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 +// CHECK0-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK0: omp_offload.failed: -// CHECK0-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK0-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR3]] // CHECK0-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK0: omp_offload.cont: -// CHECK0-NEXT: [[TMP36:%.*]] = load i32, i32* [[A]], align 4 -// CHECK0-NEXT: ret i32 [[TMP36]] +// CHECK0-NEXT: [[TMP30:%.*]] = load i32, ptr [[A]], align 4 +// CHECK0-NEXT: ret i32 [[TMP30]] // // // CHECK0-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i @@ -6761,173 +6694,158 @@ int bar(int n, double *ptr) { // CHECK0-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK0-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 // CHECK0-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK0-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x i8*], align 8 -// CHECK0-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x i8*], align 8 -// CHECK0-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x i8*], align 8 +// CHECK0-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x ptr], align 8 +// CHECK0-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x ptr], align 8 +// CHECK0-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x ptr], align 8 // CHECK0-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 -// CHECK0-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK0-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK0-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK0-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK0-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 -// CHECK0-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK0-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK0-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64* -// CHECK0-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 8 -// CHECK0-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK0-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* -// CHECK0-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8 -// CHECK0-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK0-NEXT: store i8* null, i8** [[TMP6]], align 8 -// CHECK0-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK0-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to [10 x i32]** -// CHECK0-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP8]], align 8 -// CHECK0-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK0-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]** -// CHECK0-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP10]], align 8 -// CHECK0-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK0-NEXT: store i8* null, i8** [[TMP11]], align 8 -// CHECK0-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK0-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK0-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 -// CHECK0-NEXT: store i32 2, i32* [[TMP14]], align 4 -// CHECK0-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 -// CHECK0-NEXT: store i32 2, i32* [[TMP15]], align 4 -// CHECK0-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 -// CHECK0-NEXT: store i8** [[TMP12]], i8*** [[TMP16]], align 8 -// CHECK0-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 -// CHECK0-NEXT: store i8** [[TMP13]], i8*** [[TMP17]], align 8 -// CHECK0-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 -// CHECK0-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.9, i32 0, i32 0), i64** [[TMP18]], align 8 -// CHECK0-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 -// CHECK0-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.10, i32 0, i32 0), i64** [[TMP19]], align 8 -// CHECK0-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 -// CHECK0-NEXT: store i8** null, i8*** [[TMP20]], align 8 -// CHECK0-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 -// CHECK0-NEXT: store i8** null, i8*** [[TMP21]], align 8 -// CHECK0-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 -// CHECK0-NEXT: store i64 0, i64* [[TMP22]], align 8 -// CHECK0-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 9 -// CHECK0-NEXT: store i64 0, i64* [[TMP23]], align 8 -// CHECK0-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 10 -// CHECK0-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP24]], align 4 -// CHECK0-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 11 -// CHECK0-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP25]], align 4 -// CHECK0-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 12 -// CHECK0-NEXT: store i32 0, i32* [[TMP26]], align 4 -// CHECK0-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) -// CHECK0-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 -// CHECK0-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK0-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// CHECK0-NEXT: store i32 0, ptr [[A]], align 4 +// CHECK0-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 +// CHECK0-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 +// CHECK0-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8 +// CHECK0-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK0-NEXT: store i64 [[TMP1]], ptr [[TMP2]], align 8 +// CHECK0-NEXT: [[TMP3:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK0-NEXT: store i64 [[TMP1]], ptr [[TMP3]], align 8 +// CHECK0-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK0-NEXT: store ptr null, ptr [[TMP4]], align 8 +// CHECK0-NEXT: [[TMP5:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK0-NEXT: store ptr [[B]], ptr [[TMP5]], align 8 +// CHECK0-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK0-NEXT: store ptr [[B]], ptr [[TMP6]], align 8 +// CHECK0-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK0-NEXT: store ptr null, ptr [[TMP7]], align 8 +// CHECK0-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK0-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK0-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 +// CHECK0-NEXT: store i32 2, ptr [[TMP10]], align 4 +// CHECK0-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 +// CHECK0-NEXT: store i32 2, ptr [[TMP11]], align 4 +// CHECK0-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 +// CHECK0-NEXT: store ptr [[TMP8]], ptr [[TMP12]], align 8 +// CHECK0-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 +// CHECK0-NEXT: store ptr [[TMP9]], ptr [[TMP13]], align 8 +// CHECK0-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 +// CHECK0-NEXT: store ptr @.offload_sizes.9, ptr [[TMP14]], align 8 +// CHECK0-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 +// CHECK0-NEXT: store ptr @.offload_maptypes.10, ptr [[TMP15]], align 8 +// CHECK0-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 +// CHECK0-NEXT: store ptr null, ptr [[TMP16]], align 8 +// CHECK0-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 +// CHECK0-NEXT: store ptr null, ptr [[TMP17]], align 8 +// CHECK0-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 +// CHECK0-NEXT: store i64 0, ptr [[TMP18]], align 8 +// CHECK0-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 +// CHECK0-NEXT: store i64 0, ptr [[TMP19]], align 8 +// CHECK0-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 +// CHECK0-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP20]], align 4 +// CHECK0-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 +// CHECK0-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP21]], align 4 +// CHECK0-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 +// CHECK0-NEXT: store i32 0, ptr [[TMP22]], align 4 +// CHECK0-NEXT: [[TMP23:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128.region_id, ptr [[KERNEL_ARGS]]) +// CHECK0-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 +// CHECK0-NEXT: br i1 [[TMP24]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK0: omp_offload.failed: -// CHECK0-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128(i64 [[TMP1]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK0-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128(i64 [[TMP1]], ptr [[B]]) #[[ATTR3]] // CHECK0-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK0: omp_offload.cont: -// CHECK0-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 4 -// CHECK0-NEXT: ret i32 [[TMP29]] +// CHECK0-NEXT: [[TMP25:%.*]] = load i32, ptr [[A]], align 4 +// CHECK0-NEXT: ret i32 [[TMP25]] // // // CHECK0-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167 -// CHECK0-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK0-SAME: (ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK0-NEXT: entry: -// CHECK0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK0-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK0-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 // CHECK0-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK0-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 -// CHECK0-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK0-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 +// CHECK0-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 // CHECK0-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 // CHECK0-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK0-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK0-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK0-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK0-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK0-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 -// CHECK0-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK0-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK0-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK0-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK0-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 -// CHECK0-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave() -// CHECK0-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8 +// CHECK0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// CHECK0-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 +// CHECK0-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 +// CHECK0-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 +// CHECK0-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 +// CHECK0-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// CHECK0-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 +// CHECK0-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 +// CHECK0-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 +// CHECK0-NEXT: [[TMP4:%.*]] = call ptr @llvm.stacksave() +// CHECK0-NEXT: store ptr [[TMP4]], ptr [[SAVED_STACK]], align 8 // CHECK0-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP2]] // CHECK0-NEXT: [[VLA3:%.*]] = alloca i16, i64 [[TMP5]], align 2 -// CHECK0-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK0-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR1]], align 8 +// CHECK0-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 +// CHECK0-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR1]], align 8 // CHECK0-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP1]], [[TMP2]] // CHECK0-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP6]], 2 -// CHECK0-NEXT: [[TMP8:%.*]] = bitcast i16* [[VLA3]] to i8* -// CHECK0-NEXT: [[TMP9:%.*]] = bitcast i16* [[TMP3]] to i8* -// CHECK0-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 2 [[TMP8]], i8* align 2 [[TMP9]], i64 [[TMP7]], i1 false) -// CHECK0-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4 -// CHECK0-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP10]] to double -// CHECK0-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00 -// CHECK0-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK0-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK0-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK0-NEXT: [[TMP11:%.*]] = load double, double* [[A5]], align 8 -// CHECK0-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+00 -// CHECK0-NEXT: store double [[INC]], double* [[A5]], align 8 -// CHECK0-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 -// CHECK0-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA3]], i64 [[TMP12]] -// CHECK0-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK0-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2 -// CHECK0-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK0-NEXT: call void @llvm.stackrestore(i8* [[TMP13]]) +// CHECK0-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 2 [[VLA3]], ptr align 2 [[TMP3]], i64 [[TMP7]], i1 false) +// CHECK0-NEXT: [[TMP8:%.*]] = load i32, ptr [[B_ADDR]], align 4 +// CHECK0-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP8]] to double +// CHECK0-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK0-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK0-NEXT: store double [[ADD]], ptr [[A]], align 8 +// CHECK0-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 +// CHECK0-NEXT: [[TMP9:%.*]] = load double, ptr [[A4]], align 8 +// CHECK0-NEXT: [[INC:%.*]] = fadd double [[TMP9]], 1.000000e+00 +// CHECK0-NEXT: store double [[INC]], ptr [[A4]], align 8 +// CHECK0-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 +// CHECK0-NEXT: [[TMP10:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA3]], i64 [[TMP10]] +// CHECK0-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1 +// CHECK0-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2 +// CHECK0-NEXT: [[TMP11:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 +// CHECK0-NEXT: call void @llvm.stackrestore(ptr [[TMP11]]) // CHECK0-NEXT: ret void // // // CHECK0-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142 -// CHECK0-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK0-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK0-NEXT: entry: // CHECK0-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK0-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 -// CHECK0-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK0-NEXT: [[B2:%.*]] = alloca [10 x i32], align 4 -// CHECK0-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK0-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 -// CHECK0-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK0-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK0-NEXT: [[CONV1:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* -// CHECK0-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK0-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B2]] to i8* -// CHECK0-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8* -// CHECK0-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i64 40, i1 false) -// CHECK0-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4 -// CHECK0-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK0-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 -// CHECK0-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 1 -// CHECK0-NEXT: [[CONV3:%.*]] = sext i8 [[TMP4]] to i32 -// CHECK0-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK0-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK0-NEXT: store i8 [[CONV5]], i8* [[CONV1]], align 1 -// CHECK0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B2]], i64 0, i64 2 -// CHECK0-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK0-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK0-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 +// CHECK0-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 +// CHECK0-NEXT: [[B1:%.*]] = alloca [10 x i32], align 4 +// CHECK0-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 +// CHECK0-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8 +// CHECK0-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 +// CHECK0-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// CHECK0-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[B1]], ptr align 4 [[TMP0]], i64 40, i1 false) +// CHECK0-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 +// CHECK0-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK0-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 +// CHECK0-NEXT: [[TMP2:%.*]] = load i8, ptr [[AAA_ADDR]], align 1 +// CHECK0-NEXT: [[CONV:%.*]] = sext i8 [[TMP2]] to i32 +// CHECK0-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 +// CHECK0-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i8 +// CHECK0-NEXT: store i8 [[CONV3]], ptr [[AAA_ADDR]], align 1 +// CHECK0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B1]], i64 0, i64 2 +// CHECK0-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// CHECK0-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 +// CHECK0-NEXT: store i32 [[ADD4]], ptr [[ARRAYIDX]], align 4 // CHECK0-NEXT: ret void // // // CHECK0-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128 -// CHECK0-SAME: (i64 noundef [[A:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK0-SAME: (i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK0-NEXT: entry: // CHECK0-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK0-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK0-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 // CHECK0-NEXT: [[B1:%.*]] = alloca [10 x i32], align 4 -// CHECK0-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK0-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK0-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK0-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK0-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B1]] to i8* -// CHECK0-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8* -// CHECK0-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i64 40, i1 false) -// CHECK0-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4 -// CHECK0-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK0-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 -// CHECK0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], i64 0, i64 2 -// CHECK0-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK0-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK0-NEXT: store i32 [[ADD2]], i32* [[ARRAYIDX]], align 4 +// CHECK0-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 +// CHECK0-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 +// CHECK0-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// CHECK0-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[B1]], ptr align 4 [[TMP0]], i64 40, i1 false) +// CHECK0-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 +// CHECK0-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK0-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 +// CHECK0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B1]], i64 0, i64 2 +// CHECK0-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// CHECK0-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 +// CHECK0-NEXT: store i32 [[ADD2]], ptr [[ARRAYIDX]], align 4 // CHECK0-NEXT: ret void // // @@ -6939,592 +6857,533 @@ int bar(int n, double *ptr) { // // // CHECK1-LABEL: define {{[^@]+}}@_Z3fooiPd -// CHECK1-SAME: (i32 noundef signext [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK1-SAME: (i32 noundef signext [[N:%.*]], ptr noundef [[PTR:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 8 +// CHECK1-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 // CHECK1-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 // CHECK1-NEXT: [[E:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 4 -// CHECK1-NEXT: [[P:%.*]] = alloca i32*, align 64 +// CHECK1-NEXT: [[P:%.*]] = alloca ptr, align 64 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[GA_CASTED:%.*]] = alloca i64, align 8 -// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8 +// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 8 +// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 8 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 -// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [9 x i8*], align 8 -// CHECK1-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [9 x i8*], align 8 -// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [9 x i8*], align 8 +// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [9 x ptr], align 8 +// CHECK1-NEXT: [[DOTOFFLOAD_PTRS3:%.*]] = alloca [9 x ptr], align 8 +// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [9 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 8 -// CHECK1-NEXT: [[KERNEL_ARGS7:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 -// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [2 x i8*], align 8 -// CHECK1-NEXT: [[DOTOFFLOAD_PTRS11:%.*]] = alloca [2 x i8*], align 8 -// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [2 x i8*], align 8 -// CHECK1-NEXT: [[KERNEL_ARGS13:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 -// CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK1-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 8 -// CHECK1-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK1-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK1-NEXT: [[KERNEL_ARGS5:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 +// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS8:%.*]] = alloca [2 x ptr], align 8 +// CHECK1-NEXT: [[DOTOFFLOAD_PTRS9:%.*]] = alloca [2 x ptr], align 8 +// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS10:%.*]] = alloca [2 x ptr], align 8 +// CHECK1-NEXT: [[KERNEL_ARGS11:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 +// CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// CHECK1-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 8 +// CHECK1-NEXT: store i32 0, ptr [[A]], align 4 +// CHECK1-NEXT: store i16 0, ptr [[AA]], align 2 +// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK1-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// CHECK1-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK1-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 +// CHECK1-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() +// CHECK1-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// CHECK1-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK1-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 +// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK1-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 // CHECK1-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] // CHECK1-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// CHECK1-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// CHECK1-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK1-NEXT: store i32 [[TMP6]], i32* [[X]], align 4 -// CHECK1-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 1 -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK1-NEXT: store i32 [[TMP7]], i32* [[Y]], align 4 -// CHECK1-NEXT: store i32* [[A]], i32** [[P]], align 64 -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 -// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK1-NEXT: store i32 [[TMP8]], i32* [[CONV]], align 4 -// CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK1-NEXT: [[TMP10:%.*]] = load i32*, i32** [[P]], align 64 -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* @ga, align 4 -// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[GA_CASTED]] to i32* -// CHECK1-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4 -// CHECK1-NEXT: [[TMP12:%.*]] = load i64, i64* [[GA_CASTED]], align 8 -// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i64* -// CHECK1-NEXT: store i64 [[TMP9]], i64* [[TMP14]], align 8 -// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* -// CHECK1-NEXT: store i64 [[TMP9]], i64* [[TMP16]], align 8 -// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK1-NEXT: store i8* null, i8** [[TMP17]], align 8 -// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK1-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** -// CHECK1-NEXT: store i32* [[TMP10]], i32** [[TMP19]], align 8 -// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK1-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32** -// CHECK1-NEXT: store i32* [[TMP10]], i32** [[TMP21]], align 8 -// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK1-NEXT: store i8* null, i8** [[TMP22]], align 8 -// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK1-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64* -// CHECK1-NEXT: store i64 [[TMP12]], i64* [[TMP24]], align 8 -// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK1-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64* -// CHECK1-NEXT: store i64 [[TMP12]], i64* [[TMP26]], align 8 -// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK1-NEXT: store i8* null, i8** [[TMP27]], align 8 -// CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 -// CHECK1-NEXT: store i32 2, i32* [[TMP30]], align 4 -// CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 -// CHECK1-NEXT: store i32 3, i32* [[TMP31]], align 4 -// CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 -// CHECK1-NEXT: store i8** [[TMP28]], i8*** [[TMP32]], align 8 -// CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 -// CHECK1-NEXT: store i8** [[TMP29]], i8*** [[TMP33]], align 8 -// CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 -// CHECK1-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64** [[TMP34]], align 8 -// CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 -// CHECK1-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i64** [[TMP35]], align 8 -// CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 -// CHECK1-NEXT: store i8** null, i8*** [[TMP36]], align 8 -// CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 -// CHECK1-NEXT: store i8** null, i8*** [[TMP37]], align 8 -// CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 -// CHECK1-NEXT: store i64 0, i64* [[TMP38]], align 8 -// CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 9 -// CHECK1-NEXT: store i64 0, i64* [[TMP39]], align 8 -// CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 10 -// CHECK1-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP40]], align 4 -// CHECK1-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 11 -// CHECK1-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP41]], align 4 -// CHECK1-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 12 -// CHECK1-NEXT: store i32 0, i32* [[TMP42]], align 4 -// CHECK1-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) -// CHECK1-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 -// CHECK1-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK1-NEXT: store i64 [[TMP4]], ptr [[__VLA_EXPR1]], align 8 +// CHECK1-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// CHECK1-NEXT: store i32 [[TMP6]], ptr [[X]], align 4 +// CHECK1-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 1 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// CHECK1-NEXT: store i32 [[TMP7]], ptr [[Y]], align 4 +// CHECK1-NEXT: store ptr [[A]], ptr [[P]], align 64 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 +// CHECK1-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4 +// CHECK1-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8 +// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[P]], align 64 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr @ga, align 4 +// CHECK1-NEXT: store i32 [[TMP11]], ptr [[GA_CASTED]], align 4 +// CHECK1-NEXT: [[TMP12:%.*]] = load i64, ptr [[GA_CASTED]], align 8 +// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK1-NEXT: store i64 [[TMP9]], ptr [[TMP13]], align 8 +// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK1-NEXT: store i64 [[TMP9]], ptr [[TMP14]], align 8 +// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK1-NEXT: store ptr null, ptr [[TMP15]], align 8 +// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK1-NEXT: store ptr [[TMP10]], ptr [[TMP16]], align 8 +// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK1-NEXT: store ptr [[TMP10]], ptr [[TMP17]], align 8 +// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK1-NEXT: store ptr null, ptr [[TMP18]], align 8 +// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK1-NEXT: store i64 [[TMP12]], ptr [[TMP19]], align 8 +// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK1-NEXT: store i64 [[TMP12]], ptr [[TMP20]], align 8 +// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK1-NEXT: store ptr null, ptr [[TMP21]], align 8 +// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 +// CHECK1-NEXT: store i32 2, ptr [[TMP24]], align 4 +// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 +// CHECK1-NEXT: store i32 3, ptr [[TMP25]], align 4 +// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 +// CHECK1-NEXT: store ptr [[TMP22]], ptr [[TMP26]], align 8 +// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 +// CHECK1-NEXT: store ptr [[TMP23]], ptr [[TMP27]], align 8 +// CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 +// CHECK1-NEXT: store ptr @.offload_sizes, ptr [[TMP28]], align 8 +// CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 +// CHECK1-NEXT: store ptr @.offload_maptypes, ptr [[TMP29]], align 8 +// CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 +// CHECK1-NEXT: store ptr null, ptr [[TMP30]], align 8 +// CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 +// CHECK1-NEXT: store ptr null, ptr [[TMP31]], align 8 +// CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 +// CHECK1-NEXT: store i64 0, ptr [[TMP32]], align 8 +// CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 +// CHECK1-NEXT: store i64 0, ptr [[TMP33]], align 8 +// CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 +// CHECK1-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP34]], align 4 +// CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 +// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP35]], align 4 +// CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 +// CHECK1-NEXT: store i32 0, ptr [[TMP36]], align 4 +// CHECK1-NEXT: [[TMP37:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1:[0-9]+]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63.region_id, ptr [[KERNEL_ARGS]]) +// CHECK1-NEXT: [[TMP38:%.*]] = icmp ne i32 [[TMP37]], 0 +// CHECK1-NEXT: br i1 [[TMP38]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK1: omp_offload.failed: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63(i64 [[TMP9]], i32* [[TMP10]], i64 [[TMP12]]) #[[ATTR3:[0-9]+]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63(i64 [[TMP9]], ptr [[TMP10]], i64 [[TMP12]]) #[[ATTR3:[0-9]+]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: -// CHECK1-NEXT: [[TMP45:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* -// CHECK1-NEXT: store i16 [[TMP45]], i16* [[CONV3]], align 2 -// CHECK1-NEXT: [[TMP46:%.*]] = load i64, i64* [[AA_CASTED]], align 8 -// CHECK1-NEXT: [[TMP47:%.*]] = mul nuw i64 [[TMP1]], 4 -// CHECK1-NEXT: [[TMP48:%.*]] = mul nuw i64 5, [[TMP4]] -// CHECK1-NEXT: [[TMP49:%.*]] = mul nuw i64 [[TMP48]], 8 -// CHECK1-NEXT: [[TMP50:%.*]] = bitcast [9 x i64]* [[DOTOFFLOAD_SIZES]] to i8* -// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP50]], i8* align 8 bitcast ([9 x i64]* @.offload_sizes.1 to i8*), i64 72, i1 false) -// CHECK1-NEXT: [[TMP51:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i64* -// CHECK1-NEXT: store i64 [[TMP46]], i64* [[TMP52]], align 8 -// CHECK1-NEXT: [[TMP53:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP54:%.*]] = bitcast i8** [[TMP53]] to i64* -// CHECK1-NEXT: store i64 [[TMP46]], i64* [[TMP54]], align 8 -// CHECK1-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 -// CHECK1-NEXT: store i8* null, i8** [[TMP55]], align 8 -// CHECK1-NEXT: [[TMP56:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1 -// CHECK1-NEXT: [[TMP57:%.*]] = bitcast i8** [[TMP56]] to [10 x float]** -// CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP57]], align 8 -// CHECK1-NEXT: [[TMP58:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1 -// CHECK1-NEXT: [[TMP59:%.*]] = bitcast i8** [[TMP58]] to [10 x float]** -// CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP59]], align 8 -// CHECK1-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 1 -// CHECK1-NEXT: store i8* null, i8** [[TMP60]], align 8 -// CHECK1-NEXT: [[TMP61:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 2 -// CHECK1-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i64* -// CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP62]], align 8 -// CHECK1-NEXT: [[TMP63:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 2 -// CHECK1-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i64* -// CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP64]], align 8 -// CHECK1-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 2 -// CHECK1-NEXT: store i8* null, i8** [[TMP65]], align 8 -// CHECK1-NEXT: [[TMP66:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 3 -// CHECK1-NEXT: [[TMP67:%.*]] = bitcast i8** [[TMP66]] to float** -// CHECK1-NEXT: store float* [[VLA]], float** [[TMP67]], align 8 -// CHECK1-NEXT: [[TMP68:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 3 -// CHECK1-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to float** -// CHECK1-NEXT: store float* [[VLA]], float** [[TMP69]], align 8 -// CHECK1-NEXT: [[TMP70:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 -// CHECK1-NEXT: store i64 [[TMP47]], i64* [[TMP70]], align 8 -// CHECK1-NEXT: [[TMP71:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 3 -// CHECK1-NEXT: store i8* null, i8** [[TMP71]], align 8 -// CHECK1-NEXT: [[TMP72:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 4 -// CHECK1-NEXT: [[TMP73:%.*]] = bitcast i8** [[TMP72]] to [5 x [10 x double]]** -// CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP73]], align 8 -// CHECK1-NEXT: [[TMP74:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 4 -// CHECK1-NEXT: [[TMP75:%.*]] = bitcast i8** [[TMP74]] to [5 x [10 x double]]** -// CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP75]], align 8 -// CHECK1-NEXT: [[TMP76:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 4 -// CHECK1-NEXT: store i8* null, i8** [[TMP76]], align 8 -// CHECK1-NEXT: [[TMP77:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 5 -// CHECK1-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i64* -// CHECK1-NEXT: store i64 5, i64* [[TMP78]], align 8 -// CHECK1-NEXT: [[TMP79:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 5 -// CHECK1-NEXT: [[TMP80:%.*]] = bitcast i8** [[TMP79]] to i64* -// CHECK1-NEXT: store i64 5, i64* [[TMP80]], align 8 -// CHECK1-NEXT: [[TMP81:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 5 -// CHECK1-NEXT: store i8* null, i8** [[TMP81]], align 8 -// CHECK1-NEXT: [[TMP82:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 6 -// CHECK1-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i64* -// CHECK1-NEXT: store i64 [[TMP4]], i64* [[TMP83]], align 8 -// CHECK1-NEXT: [[TMP84:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 6 -// CHECK1-NEXT: [[TMP85:%.*]] = bitcast i8** [[TMP84]] to i64* -// CHECK1-NEXT: store i64 [[TMP4]], i64* [[TMP85]], align 8 -// CHECK1-NEXT: [[TMP86:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 6 -// CHECK1-NEXT: store i8* null, i8** [[TMP86]], align 8 -// CHECK1-NEXT: [[TMP87:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 7 -// CHECK1-NEXT: [[TMP88:%.*]] = bitcast i8** [[TMP87]] to double** -// CHECK1-NEXT: store double* [[VLA1]], double** [[TMP88]], align 8 -// CHECK1-NEXT: [[TMP89:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 7 -// CHECK1-NEXT: [[TMP90:%.*]] = bitcast i8** [[TMP89]] to double** -// CHECK1-NEXT: store double* [[VLA1]], double** [[TMP90]], align 8 -// CHECK1-NEXT: [[TMP91:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 -// CHECK1-NEXT: store i64 [[TMP49]], i64* [[TMP91]], align 8 -// CHECK1-NEXT: [[TMP92:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 7 -// CHECK1-NEXT: store i8* null, i8** [[TMP92]], align 8 -// CHECK1-NEXT: [[TMP93:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 8 -// CHECK1-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to %struct.TT** -// CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP94]], align 8 -// CHECK1-NEXT: [[TMP95:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 8 -// CHECK1-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to %struct.TT** -// CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP96]], align 8 -// CHECK1-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 8 -// CHECK1-NEXT: store i8* null, i8** [[TMP97]], align 8 -// CHECK1-NEXT: [[TMP98:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP100:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP101:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 0 -// CHECK1-NEXT: store i32 2, i32* [[TMP101]], align 4 -// CHECK1-NEXT: [[TMP102:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 1 -// CHECK1-NEXT: store i32 9, i32* [[TMP102]], align 4 -// CHECK1-NEXT: [[TMP103:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 2 -// CHECK1-NEXT: store i8** [[TMP98]], i8*** [[TMP103]], align 8 -// CHECK1-NEXT: [[TMP104:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 3 -// CHECK1-NEXT: store i8** [[TMP99]], i8*** [[TMP104]], align 8 -// CHECK1-NEXT: [[TMP105:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 4 -// CHECK1-NEXT: store i64* [[TMP100]], i64** [[TMP105]], align 8 -// CHECK1-NEXT: [[TMP106:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 5 -// CHECK1-NEXT: store i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.2, i32 0, i32 0), i64** [[TMP106]], align 8 -// CHECK1-NEXT: [[TMP107:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 6 -// CHECK1-NEXT: store i8** null, i8*** [[TMP107]], align 8 -// CHECK1-NEXT: [[TMP108:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 7 -// CHECK1-NEXT: store i8** null, i8*** [[TMP108]], align 8 -// CHECK1-NEXT: [[TMP109:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 8 -// CHECK1-NEXT: store i64 0, i64* [[TMP109]], align 8 -// CHECK1-NEXT: [[TMP110:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 9 -// CHECK1-NEXT: store i64 0, i64* [[TMP110]], align 8 -// CHECK1-NEXT: [[TMP111:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 10 -// CHECK1-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP111]], align 4 -// CHECK1-NEXT: [[TMP112:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 11 -// CHECK1-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP112]], align 4 -// CHECK1-NEXT: [[TMP113:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 12 -// CHECK1-NEXT: store i32 0, i32* [[TMP113]], align 4 -// CHECK1-NEXT: [[TMP114:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]]) -// CHECK1-NEXT: [[TMP115:%.*]] = icmp ne i32 [[TMP114]], 0 -// CHECK1-NEXT: br i1 [[TMP115]], label [[OMP_OFFLOAD_FAILED8:%.*]], label [[OMP_OFFLOAD_CONT9:%.*]] -// CHECK1: omp_offload.failed8: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70(i64 [[TMP46]], [10 x float]* [[B]], i64 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP4]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] -// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT9]] -// CHECK1: omp_offload.cont9: -// CHECK1-NEXT: [[TMP116:%.*]] = load double*, double** [[PTR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP117:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP118:%.*]] = bitcast i8** [[TMP117]] to double** -// CHECK1-NEXT: store double* [[TMP116]], double** [[TMP118]], align 8 -// CHECK1-NEXT: [[TMP119:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to double** -// CHECK1-NEXT: store double* [[TMP116]], double** [[TMP120]], align 8 -// CHECK1-NEXT: [[TMP121:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 0 -// CHECK1-NEXT: store i8* null, i8** [[TMP121]], align 8 -// CHECK1-NEXT: [[TMP122:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 1 -// CHECK1-NEXT: [[TMP123:%.*]] = bitcast i8** [[TMP122]] to %struct.TT.0** -// CHECK1-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[TMP123]], align 8 -// CHECK1-NEXT: [[TMP124:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 1 -// CHECK1-NEXT: [[TMP125:%.*]] = bitcast i8** [[TMP124]] to %struct.TT.0** -// CHECK1-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[TMP125]], align 8 -// CHECK1-NEXT: [[TMP126:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 1 -// CHECK1-NEXT: store i8* null, i8** [[TMP126]], align 8 -// CHECK1-NEXT: [[TMP127:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP128:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP129:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 0 -// CHECK1-NEXT: store i32 2, i32* [[TMP129]], align 4 -// CHECK1-NEXT: [[TMP130:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 1 -// CHECK1-NEXT: store i32 2, i32* [[TMP130]], align 4 -// CHECK1-NEXT: [[TMP131:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 2 -// CHECK1-NEXT: store i8** [[TMP127]], i8*** [[TMP131]], align 8 -// CHECK1-NEXT: [[TMP132:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 3 -// CHECK1-NEXT: store i8** [[TMP128]], i8*** [[TMP132]], align 8 -// CHECK1-NEXT: [[TMP133:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 4 -// CHECK1-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.3, i32 0, i32 0), i64** [[TMP133]], align 8 -// CHECK1-NEXT: [[TMP134:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 5 -// CHECK1-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.4, i32 0, i32 0), i64** [[TMP134]], align 8 -// CHECK1-NEXT: [[TMP135:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 6 -// CHECK1-NEXT: store i8** null, i8*** [[TMP135]], align 8 -// CHECK1-NEXT: [[TMP136:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 7 -// CHECK1-NEXT: store i8** null, i8*** [[TMP136]], align 8 -// CHECK1-NEXT: [[TMP137:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 8 -// CHECK1-NEXT: store i64 0, i64* [[TMP137]], align 8 -// CHECK1-NEXT: [[TMP138:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 9 -// CHECK1-NEXT: store i64 0, i64* [[TMP138]], align 8 -// CHECK1-NEXT: [[TMP139:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 10 -// CHECK1-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP139]], align 4 -// CHECK1-NEXT: [[TMP140:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 11 -// CHECK1-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP140]], align 4 -// CHECK1-NEXT: [[TMP141:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 12 -// CHECK1-NEXT: store i32 0, i32* [[TMP141]], align 4 -// CHECK1-NEXT: [[TMP142:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]]) -// CHECK1-NEXT: [[TMP143:%.*]] = icmp ne i32 [[TMP142]], 0 -// CHECK1-NEXT: br i1 [[TMP143]], label [[OMP_OFFLOAD_FAILED14:%.*]], label [[OMP_OFFLOAD_CONT15:%.*]] -// CHECK1: omp_offload.failed14: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111(double* [[TMP116]], %struct.TT.0* [[E]]) #[[ATTR3]] -// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT15]] -// CHECK1: omp_offload.cont15: -// CHECK1-NEXT: [[TMP144:%.*]] = load i32, i32* [[A]], align 4 -// CHECK1-NEXT: [[TMP145:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK1-NEXT: call void @llvm.stackrestore(i8* [[TMP145]]) -// CHECK1-NEXT: ret i32 [[TMP144]] +// CHECK1-NEXT: [[TMP39:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK1-NEXT: store i16 [[TMP39]], ptr [[AA_CASTED]], align 2 +// CHECK1-NEXT: [[TMP40:%.*]] = load i64, ptr [[AA_CASTED]], align 8 +// CHECK1-NEXT: [[TMP41:%.*]] = mul nuw i64 [[TMP1]], 4 +// CHECK1-NEXT: [[TMP42:%.*]] = mul nuw i64 5, [[TMP4]] +// CHECK1-NEXT: [[TMP43:%.*]] = mul nuw i64 [[TMP42]], 8 +// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes.1, i64 72, i1 false) +// CHECK1-NEXT: [[TMP44:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 +// CHECK1-NEXT: store i64 [[TMP40]], ptr [[TMP44]], align 8 +// CHECK1-NEXT: [[TMP45:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 +// CHECK1-NEXT: store i64 [[TMP40]], ptr [[TMP45]], align 8 +// CHECK1-NEXT: [[TMP46:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i64 0, i64 0 +// CHECK1-NEXT: store ptr null, ptr [[TMP46]], align 8 +// CHECK1-NEXT: [[TMP47:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 1 +// CHECK1-NEXT: store ptr [[B]], ptr [[TMP47]], align 8 +// CHECK1-NEXT: [[TMP48:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 1 +// CHECK1-NEXT: store ptr [[B]], ptr [[TMP48]], align 8 +// CHECK1-NEXT: [[TMP49:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i64 0, i64 1 +// CHECK1-NEXT: store ptr null, ptr [[TMP49]], align 8 +// CHECK1-NEXT: [[TMP50:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 2 +// CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP50]], align 8 +// CHECK1-NEXT: [[TMP51:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 2 +// CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP51]], align 8 +// CHECK1-NEXT: [[TMP52:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i64 0, i64 2 +// CHECK1-NEXT: store ptr null, ptr [[TMP52]], align 8 +// CHECK1-NEXT: [[TMP53:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 3 +// CHECK1-NEXT: store ptr [[VLA]], ptr [[TMP53]], align 8 +// CHECK1-NEXT: [[TMP54:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 3 +// CHECK1-NEXT: store ptr [[VLA]], ptr [[TMP54]], align 8 +// CHECK1-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK1-NEXT: store i64 [[TMP41]], ptr [[TMP55]], align 8 +// CHECK1-NEXT: [[TMP56:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i64 0, i64 3 +// CHECK1-NEXT: store ptr null, ptr [[TMP56]], align 8 +// CHECK1-NEXT: [[TMP57:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 4 +// CHECK1-NEXT: store ptr [[C]], ptr [[TMP57]], align 8 +// CHECK1-NEXT: [[TMP58:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 4 +// CHECK1-NEXT: store ptr [[C]], ptr [[TMP58]], align 8 +// CHECK1-NEXT: [[TMP59:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i64 0, i64 4 +// CHECK1-NEXT: store ptr null, ptr [[TMP59]], align 8 +// CHECK1-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 5 +// CHECK1-NEXT: store i64 5, ptr [[TMP60]], align 8 +// CHECK1-NEXT: [[TMP61:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 5 +// CHECK1-NEXT: store i64 5, ptr [[TMP61]], align 8 +// CHECK1-NEXT: [[TMP62:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i64 0, i64 5 +// CHECK1-NEXT: store ptr null, ptr [[TMP62]], align 8 +// CHECK1-NEXT: [[TMP63:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 6 +// CHECK1-NEXT: store i64 [[TMP4]], ptr [[TMP63]], align 8 +// CHECK1-NEXT: [[TMP64:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 6 +// CHECK1-NEXT: store i64 [[TMP4]], ptr [[TMP64]], align 8 +// CHECK1-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i64 0, i64 6 +// CHECK1-NEXT: store ptr null, ptr [[TMP65]], align 8 +// CHECK1-NEXT: [[TMP66:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 7 +// CHECK1-NEXT: store ptr [[VLA1]], ptr [[TMP66]], align 8 +// CHECK1-NEXT: [[TMP67:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 7 +// CHECK1-NEXT: store ptr [[VLA1]], ptr [[TMP67]], align 8 +// CHECK1-NEXT: [[TMP68:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 7 +// CHECK1-NEXT: store i64 [[TMP43]], ptr [[TMP68]], align 8 +// CHECK1-NEXT: [[TMP69:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i64 0, i64 7 +// CHECK1-NEXT: store ptr null, ptr [[TMP69]], align 8 +// CHECK1-NEXT: [[TMP70:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 8 +// CHECK1-NEXT: store ptr [[D]], ptr [[TMP70]], align 8 +// CHECK1-NEXT: [[TMP71:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 8 +// CHECK1-NEXT: store ptr [[D]], ptr [[TMP71]], align 8 +// CHECK1-NEXT: [[TMP72:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i64 0, i64 8 +// CHECK1-NEXT: store ptr null, ptr [[TMP72]], align 8 +// CHECK1-NEXT: [[TMP73:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP74:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP75:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP76:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 0 +// CHECK1-NEXT: store i32 2, ptr [[TMP76]], align 4 +// CHECK1-NEXT: [[TMP77:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 1 +// CHECK1-NEXT: store i32 9, ptr [[TMP77]], align 4 +// CHECK1-NEXT: [[TMP78:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 2 +// CHECK1-NEXT: store ptr [[TMP73]], ptr [[TMP78]], align 8 +// CHECK1-NEXT: [[TMP79:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 3 +// CHECK1-NEXT: store ptr [[TMP74]], ptr [[TMP79]], align 8 +// CHECK1-NEXT: [[TMP80:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 4 +// CHECK1-NEXT: store ptr [[TMP75]], ptr [[TMP80]], align 8 +// CHECK1-NEXT: [[TMP81:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 5 +// CHECK1-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP81]], align 8 +// CHECK1-NEXT: [[TMP82:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 6 +// CHECK1-NEXT: store ptr null, ptr [[TMP82]], align 8 +// CHECK1-NEXT: [[TMP83:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 7 +// CHECK1-NEXT: store ptr null, ptr [[TMP83]], align 8 +// CHECK1-NEXT: [[TMP84:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 8 +// CHECK1-NEXT: store i64 0, ptr [[TMP84]], align 8 +// CHECK1-NEXT: [[TMP85:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 9 +// CHECK1-NEXT: store i64 0, ptr [[TMP85]], align 8 +// CHECK1-NEXT: [[TMP86:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 10 +// CHECK1-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP86]], align 4 +// CHECK1-NEXT: [[TMP87:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 11 +// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP87]], align 4 +// CHECK1-NEXT: [[TMP88:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 12 +// CHECK1-NEXT: store i32 0, ptr [[TMP88]], align 4 +// CHECK1-NEXT: [[TMP89:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70.region_id, ptr [[KERNEL_ARGS5]]) +// CHECK1-NEXT: [[TMP90:%.*]] = icmp ne i32 [[TMP89]], 0 +// CHECK1-NEXT: br i1 [[TMP90]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] +// CHECK1: omp_offload.failed6: +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70(i64 [[TMP40]], ptr [[B]], i64 [[TMP1]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP4]], ptr [[VLA1]], ptr [[D]]) #[[ATTR3]] +// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT7]] +// CHECK1: omp_offload.cont7: +// CHECK1-NEXT: [[TMP91:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8 +// CHECK1-NEXT: [[TMP92:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 0 +// CHECK1-NEXT: store ptr [[TMP91]], ptr [[TMP92]], align 8 +// CHECK1-NEXT: [[TMP93:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS9]], i32 0, i32 0 +// CHECK1-NEXT: store ptr [[TMP91]], ptr [[TMP93]], align 8 +// CHECK1-NEXT: [[TMP94:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS10]], i64 0, i64 0 +// CHECK1-NEXT: store ptr null, ptr [[TMP94]], align 8 +// CHECK1-NEXT: [[TMP95:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 1 +// CHECK1-NEXT: store ptr [[E]], ptr [[TMP95]], align 8 +// CHECK1-NEXT: [[TMP96:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS9]], i32 0, i32 1 +// CHECK1-NEXT: store ptr [[E]], ptr [[TMP96]], align 8 +// CHECK1-NEXT: [[TMP97:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS10]], i64 0, i64 1 +// CHECK1-NEXT: store ptr null, ptr [[TMP97]], align 8 +// CHECK1-NEXT: [[TMP98:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP99:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS9]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP100:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 0 +// CHECK1-NEXT: store i32 2, ptr [[TMP100]], align 4 +// CHECK1-NEXT: [[TMP101:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 1 +// CHECK1-NEXT: store i32 2, ptr [[TMP101]], align 4 +// CHECK1-NEXT: [[TMP102:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 2 +// CHECK1-NEXT: store ptr [[TMP98]], ptr [[TMP102]], align 8 +// CHECK1-NEXT: [[TMP103:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 3 +// CHECK1-NEXT: store ptr [[TMP99]], ptr [[TMP103]], align 8 +// CHECK1-NEXT: [[TMP104:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 4 +// CHECK1-NEXT: store ptr @.offload_sizes.3, ptr [[TMP104]], align 8 +// CHECK1-NEXT: [[TMP105:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 5 +// CHECK1-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP105]], align 8 +// CHECK1-NEXT: [[TMP106:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 6 +// CHECK1-NEXT: store ptr null, ptr [[TMP106]], align 8 +// CHECK1-NEXT: [[TMP107:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 7 +// CHECK1-NEXT: store ptr null, ptr [[TMP107]], align 8 +// CHECK1-NEXT: [[TMP108:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 8 +// CHECK1-NEXT: store i64 0, ptr [[TMP108]], align 8 +// CHECK1-NEXT: [[TMP109:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 9 +// CHECK1-NEXT: store i64 0, ptr [[TMP109]], align 8 +// CHECK1-NEXT: [[TMP110:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 10 +// CHECK1-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP110]], align 4 +// CHECK1-NEXT: [[TMP111:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 11 +// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP111]], align 4 +// CHECK1-NEXT: [[TMP112:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 12 +// CHECK1-NEXT: store i32 0, ptr [[TMP112]], align 4 +// CHECK1-NEXT: [[TMP113:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111.region_id, ptr [[KERNEL_ARGS11]]) +// CHECK1-NEXT: [[TMP114:%.*]] = icmp ne i32 [[TMP113]], 0 +// CHECK1-NEXT: br i1 [[TMP114]], label [[OMP_OFFLOAD_FAILED12:%.*]], label [[OMP_OFFLOAD_CONT13:%.*]] +// CHECK1: omp_offload.failed12: +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111(ptr [[TMP91]], ptr [[E]]) #[[ATTR3]] +// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT13]] +// CHECK1: omp_offload.cont13: +// CHECK1-NEXT: [[TMP115:%.*]] = load i32, ptr [[A]], align 4 +// CHECK1-NEXT: [[TMP116:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 +// CHECK1-NEXT: call void @llvm.stackrestore(ptr [[TMP116]]) +// CHECK1-NEXT: ret i32 [[TMP115]] // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63 -// CHECK1-SAME: (i64 noundef [[A:%.*]], i32* noundef [[P:%.*]], i64 noundef [[GA:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK1-SAME: (i64 noundef [[A:%.*]], ptr noundef [[P:%.*]], i64 noundef [[GA:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK1-NEXT: [[P_ADDR:%.*]] = alloca i32*, align 8 +// CHECK1-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[GA_ADDR:%.*]] = alloca i64, align 8 -// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK1-NEXT: store i32* [[P]], i32** [[P_ADDR]], align 8 -// CHECK1-NEXT: store i64 [[GA]], i64* [[GA_ADDR]], align 8 -// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[GA_ADDR]] to i32* +// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 +// CHECK1-NEXT: store ptr [[P]], ptr [[P_ADDR]], align 8 +// CHECK1-NEXT: store i64 [[GA]], ptr [[GA_ADDR]], align 8 // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70 -// CHECK1-SAME: (i64 noundef [[AA:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK1-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 -// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// CHECK1-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 -// CHECK1-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 -// CHECK1-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// CHECK1-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[B5:%.*]] = alloca [10 x float], align 4 -// CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[C7:%.*]] = alloca [5 x [10 x double]], align 8 // CHECK1-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[__VLA_EXPR2:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[D9:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 -// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 -// CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK1-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 -// CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 -// CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK1-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 -// CHECK1-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 -// CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 -// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 -// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 -// CHECK1-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 -// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 -// CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 -// CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 -// CHECK1-NEXT: [[TMP8:%.*]] = bitcast [10 x float]* [[B5]] to i8* -// CHECK1-NEXT: [[TMP9:%.*]] = bitcast [10 x float]* [[TMP0]] to i8* -// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i64 40, i1 false) -// CHECK1-NEXT: [[TMP10:%.*]] = call i8* @llvm.stacksave() -// CHECK1-NEXT: store i8* [[TMP10]], i8** [[SAVED_STACK]], align 8 +// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 +// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 +// CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 +// CHECK1-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 8 +// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 +// CHECK1-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 +// CHECK1-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8 +// CHECK1-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8 +// CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8 +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 +// CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 +// CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8 +// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8 +// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8 +// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[B5]], ptr align 4 [[TMP0]], i64 40, i1 false) +// CHECK1-NEXT: [[TMP8:%.*]] = call ptr @llvm.stacksave() +// CHECK1-NEXT: store ptr [[TMP8]], ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: [[VLA6:%.*]] = alloca float, i64 [[TMP1]], align 4 -// CHECK1-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK1-NEXT: [[TMP11:%.*]] = mul nuw i64 [[TMP1]], 4 -// CHECK1-NEXT: [[TMP12:%.*]] = bitcast float* [[VLA6]] to i8* -// CHECK1-NEXT: [[TMP13:%.*]] = bitcast float* [[TMP2]] to i8* -// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 [[TMP11]], i1 false) -// CHECK1-NEXT: [[TMP14:%.*]] = bitcast [5 x [10 x double]]* [[C7]] to i8* -// CHECK1-NEXT: [[TMP15:%.*]] = bitcast [5 x [10 x double]]* [[TMP3]] to i8* -// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP14]], i8* align 8 [[TMP15]], i64 400, i1 false) -// CHECK1-NEXT: [[TMP16:%.*]] = mul nuw i64 [[TMP4]], [[TMP5]] -// CHECK1-NEXT: [[VLA8:%.*]] = alloca double, i64 [[TMP16]], align 8 -// CHECK1-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// CHECK1-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR2]], align 8 -// CHECK1-NEXT: [[TMP17:%.*]] = mul nuw i64 [[TMP4]], [[TMP5]] -// CHECK1-NEXT: [[TMP18:%.*]] = mul nuw i64 [[TMP17]], 8 -// CHECK1-NEXT: [[TMP19:%.*]] = bitcast double* [[VLA8]] to i8* -// CHECK1-NEXT: [[TMP20:%.*]] = bitcast double* [[TMP6]] to i8* -// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP19]], i8* align 8 [[TMP20]], i64 [[TMP18]], i1 false) -// CHECK1-NEXT: [[TMP21:%.*]] = bitcast %struct.TT* [[D9]] to i8* -// CHECK1-NEXT: [[TMP22:%.*]] = bitcast %struct.TT* [[TMP7]] to i8* -// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP21]], i8* align 8 [[TMP22]], i64 16, i1 false) -// CHECK1-NEXT: [[TMP23:%.*]] = load i16, i16* [[CONV]], align 2 -// CHECK1-NEXT: [[CONV10:%.*]] = sext i16 [[TMP23]] to i32 -// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV10]], 1 -// CHECK1-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD]] to i16 -// CHECK1-NEXT: store i16 [[CONV11]], i16* [[CONV]], align 2 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B5]], i64 0, i64 2 -// CHECK1-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4 -// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA6]], i64 3 -// CHECK1-NEXT: store float 1.000000e+00, float* [[ARRAYIDX12]], align 4 -// CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C7]], i64 0, i64 1 -// CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], i64 0, i64 2 -// CHECK1-NEXT: store double 1.000000e+00, double* [[ARRAYIDX14]], align 8 -// CHECK1-NEXT: [[TMP24:%.*]] = mul nsw i64 1, [[TMP5]] -// CHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[VLA8]], i64 [[TMP24]] -// CHECK1-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 -// CHECK1-NEXT: store double 1.000000e+00, double* [[ARRAYIDX16]], align 8 -// CHECK1-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 0 -// CHECK1-NEXT: store i64 1, i64* [[X]], align 8 -// CHECK1-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 1 -// CHECK1-NEXT: store i8 1, i8* [[Y]], align 8 -// CHECK1-NEXT: [[TMP25:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK1-NEXT: call void @llvm.stackrestore(i8* [[TMP25]]) +// CHECK1-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 +// CHECK1-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP1]], 4 +// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VLA6]], ptr align 4 [[TMP2]], i64 [[TMP9]], i1 false) +// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[C7]], ptr align 8 [[TMP3]], i64 400, i1 false) +// CHECK1-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP4]], [[TMP5]] +// CHECK1-NEXT: [[VLA8:%.*]] = alloca double, i64 [[TMP10]], align 8 +// CHECK1-NEXT: store i64 [[TMP4]], ptr [[__VLA_EXPR1]], align 8 +// CHECK1-NEXT: store i64 [[TMP5]], ptr [[__VLA_EXPR2]], align 8 +// CHECK1-NEXT: [[TMP11:%.*]] = mul nuw i64 [[TMP4]], [[TMP5]] +// CHECK1-NEXT: [[TMP12:%.*]] = mul nuw i64 [[TMP11]], 8 +// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[VLA8]], ptr align 8 [[TMP6]], i64 [[TMP12]], i1 false) +// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[D9]], ptr align 8 [[TMP7]], i64 16, i1 false) +// CHECK1-NEXT: [[TMP13:%.*]] = load i16, ptr [[AA_ADDR]], align 2 +// CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP13]] to i32 +// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 +// CHECK1-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16 +// CHECK1-NEXT: store i16 [[CONV10]], ptr [[AA_ADDR]], align 2 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B5]], i64 0, i64 2 +// CHECK1-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX]], align 4 +// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds float, ptr [[VLA6]], i64 3 +// CHECK1-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX11]], align 4 +// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C7]], i64 0, i64 1 +// CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX12]], i64 0, i64 2 +// CHECK1-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX13]], align 8 +// CHECK1-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP5]] +// CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, ptr [[VLA8]], i64 [[TMP14]] +// CHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX14]], i64 3 +// CHECK1-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX15]], align 8 +// CHECK1-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D9]], i32 0, i32 0 +// CHECK1-NEXT: store i64 1, ptr [[X]], align 8 +// CHECK1-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D9]], i32 0, i32 1 +// CHECK1-NEXT: store i8 1, ptr [[Y]], align 8 +// CHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 +// CHECK1-NEXT: call void @llvm.stackrestore(ptr [[TMP15]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111 -// CHECK1-SAME: (double* noundef [[PTR:%.*]], %struct.TT.0* noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (ptr noundef [[PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: -// CHECK1-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 8 -// CHECK1-NEXT: [[E_ADDR:%.*]] = alloca %struct.TT.0*, align 8 +// CHECK1-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: [[E_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[E1:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 4 -// CHECK1-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 8 -// CHECK1-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[E_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load %struct.TT.0*, %struct.TT.0** [[E_ADDR]], align 8 -// CHECK1-NEXT: [[TMP1:%.*]] = bitcast %struct.TT.0* [[E1]] to i8* -// CHECK1-NEXT: [[TMP2:%.*]] = bitcast %struct.TT.0* [[TMP0]] to i8* -// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i64 8, i1 false) -// CHECK1-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E1]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[X]], align 4 -// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP3]] to double -// CHECK1-NEXT: [[TMP4:%.*]] = load double*, double** [[PTR_ADDR]], align 8 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP4]], i64 0 -// CHECK1-NEXT: store double [[CONV]], double* [[ARRAYIDX]], align 8 -// CHECK1-NEXT: [[TMP5:%.*]] = load double*, double** [[PTR_ADDR]], align 8 -// CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds double, double* [[TMP5]], i64 0 -// CHECK1-NEXT: [[TMP6:%.*]] = load double, double* [[ARRAYIDX2]], align 8 -// CHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// CHECK1-NEXT: store double [[INC]], double* [[ARRAYIDX2]], align 8 +// CHECK1-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 8 +// CHECK1-NEXT: store ptr [[E]], ptr [[E_ADDR]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[E_ADDR]], align 8 +// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[E1]], ptr align 4 [[TMP0]], i64 8, i1 false) +// CHECK1-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], ptr [[E1]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[X]], align 4 +// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[TMP2]], i64 0 +// CHECK1-NEXT: store double [[CONV]], ptr [[ARRAYIDX]], align 8 +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8 +// CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds double, ptr [[TMP3]], i64 0 +// CHECK1-NEXT: [[TMP4:%.*]] = load double, ptr [[ARRAYIDX2]], align 8 +// CHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP4]], 1.000000e+00 +// CHECK1-NEXT: store double [[INC]], ptr [[ARRAYIDX2]], align 8 // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_Z3bariPd -// CHECK1-SAME: (i32 noundef signext [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0]] { +// CHECK1-SAME: (i32 noundef signext [[N:%.*]], ptr noundef [[PTR:%.*]]) #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 8 +// CHECK1-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK1-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 8 -// CHECK1-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK1-NEXT: [[TMP1:%.*]] = load double*, double** [[PTR_ADDR]], align 8 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooiPd(i32 noundef signext [[TMP0]], double* noundef [[TMP1]]) -// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 +// CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// CHECK1-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 8 +// CHECK1-NEXT: store i32 0, ptr [[A]], align 4 +// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8 +// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooiPd(i32 noundef signext [[TMP0]], ptr noundef [[TMP1]]) +// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CALL]] -// CHECK1-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK1-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP3]]) -// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 +// CHECK1-NEXT: store i32 [[ADD]], ptr [[A]], align 4 +// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// CHECK1-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(ptr noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP3]]) +// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 4 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], [[CALL1]] -// CHECK1-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK1-NEXT: store i32 [[ADD2]], ptr [[A]], align 4 +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK1-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP5]]) -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], [[CALL3]] -// CHECK1-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK1-NEXT: store i32 [[ADD4]], ptr [[A]], align 4 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK1-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP7]]) -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP8]], [[CALL5]] -// CHECK1-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 +// CHECK1-NEXT: store i32 [[ADD6]], ptr [[A]], align 4 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[A]], align 4 // CHECK1-NEXT: ret i32 [[TMP9]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK1-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK1-NEXT: entry: -// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 -// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 -// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 +// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 8 +// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 8 +// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 -// CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK1-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK1-NEXT: store i32 [[ADD]], ptr [[B]], align 4 +// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// CHECK1-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// CHECK1-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 +// CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave() +// CHECK1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] // CHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// CHECK1-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 -// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* -// CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4 -// CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 -// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[B]], align 4 +// CHECK1-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 4 +// CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 8 +// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[TMP7:%.*]] = mul nuw i64 2, [[TMP2]] // CHECK1-NEXT: [[TMP8:%.*]] = mul nuw i64 [[TMP7]], 2 -// CHECK1-NEXT: [[TMP9:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* -// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP9]], i8* align 8 bitcast ([5 x i64]* @.offload_sizes.5 to i8*), i64 40, i1 false) -// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1** -// CHECK1-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 8 -// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double** -// CHECK1-NEXT: store double* [[A]], double** [[TMP13]], align 8 -// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK1-NEXT: store i8* null, i8** [[TMP14]], align 8 -// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK1-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* -// CHECK1-NEXT: store i64 [[TMP6]], i64* [[TMP16]], align 8 -// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK1-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* -// CHECK1-NEXT: store i64 [[TMP6]], i64* [[TMP18]], align 8 -// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK1-NEXT: store i8* null, i8** [[TMP19]], align 8 -// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK1-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* -// CHECK1-NEXT: store i64 2, i64* [[TMP21]], align 8 -// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK1-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* -// CHECK1-NEXT: store i64 2, i64* [[TMP23]], align 8 -// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK1-NEXT: store i8* null, i8** [[TMP24]], align 8 -// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK1-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64* -// CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP26]], align 8 -// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK1-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64* -// CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP28]], align 8 -// CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 -// CHECK1-NEXT: store i8* null, i8** [[TMP29]], align 8 -// CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK1-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i16** -// CHECK1-NEXT: store i16* [[VLA]], i16** [[TMP31]], align 8 -// CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK1-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i16** -// CHECK1-NEXT: store i16* [[VLA]], i16** [[TMP33]], align 8 -// CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 -// CHECK1-NEXT: store i64 [[TMP8]], i64* [[TMP34]], align 8 -// CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 -// CHECK1-NEXT: store i8* null, i8** [[TMP35]], align 8 -// CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 -// CHECK1-NEXT: store i32 2, i32* [[TMP39]], align 4 -// CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 -// CHECK1-NEXT: store i32 5, i32* [[TMP40]], align 4 -// CHECK1-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 -// CHECK1-NEXT: store i8** [[TMP36]], i8*** [[TMP41]], align 8 -// CHECK1-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 -// CHECK1-NEXT: store i8** [[TMP37]], i8*** [[TMP42]], align 8 -// CHECK1-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 -// CHECK1-NEXT: store i64* [[TMP38]], i64** [[TMP43]], align 8 -// CHECK1-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 -// CHECK1-NEXT: store i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.6, i32 0, i32 0), i64** [[TMP44]], align 8 -// CHECK1-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 -// CHECK1-NEXT: store i8** null, i8*** [[TMP45]], align 8 -// CHECK1-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 -// CHECK1-NEXT: store i8** null, i8*** [[TMP46]], align 8 -// CHECK1-NEXT: [[TMP47:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 -// CHECK1-NEXT: store i64 0, i64* [[TMP47]], align 8 -// CHECK1-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 9 -// CHECK1-NEXT: store i64 0, i64* [[TMP48]], align 8 -// CHECK1-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 10 -// CHECK1-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP49]], align 4 -// CHECK1-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 11 -// CHECK1-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP50]], align 4 -// CHECK1-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 12 -// CHECK1-NEXT: store i32 0, i32* [[TMP51]], align 4 -// CHECK1-NEXT: [[TMP52:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) -// CHECK1-NEXT: [[TMP53:%.*]] = icmp ne i32 [[TMP52]], 0 -// CHECK1-NEXT: br i1 [[TMP53]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes.5, i64 40, i1 false) +// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK1-NEXT: store ptr [[THIS1]], ptr [[TMP9]], align 8 +// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK1-NEXT: store ptr [[A]], ptr [[TMP10]], align 8 +// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK1-NEXT: store ptr null, ptr [[TMP11]], align 8 +// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK1-NEXT: store i64 [[TMP6]], ptr [[TMP12]], align 8 +// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK1-NEXT: store i64 [[TMP6]], ptr [[TMP13]], align 8 +// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK1-NEXT: store ptr null, ptr [[TMP14]], align 8 +// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK1-NEXT: store i64 2, ptr [[TMP15]], align 8 +// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK1-NEXT: store i64 2, ptr [[TMP16]], align 8 +// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK1-NEXT: store ptr null, ptr [[TMP17]], align 8 +// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK1-NEXT: store i64 [[TMP2]], ptr [[TMP18]], align 8 +// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK1-NEXT: store i64 [[TMP2]], ptr [[TMP19]], align 8 +// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 +// CHECK1-NEXT: store ptr null, ptr [[TMP20]], align 8 +// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK1-NEXT: store ptr [[VLA]], ptr [[TMP21]], align 8 +// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK1-NEXT: store ptr [[VLA]], ptr [[TMP22]], align 8 +// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK1-NEXT: store i64 [[TMP8]], ptr [[TMP23]], align 8 +// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 +// CHECK1-NEXT: store ptr null, ptr [[TMP24]], align 8 +// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 +// CHECK1-NEXT: store i32 2, ptr [[TMP28]], align 4 +// CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 +// CHECK1-NEXT: store i32 5, ptr [[TMP29]], align 4 +// CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 +// CHECK1-NEXT: store ptr [[TMP25]], ptr [[TMP30]], align 8 +// CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 +// CHECK1-NEXT: store ptr [[TMP26]], ptr [[TMP31]], align 8 +// CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 +// CHECK1-NEXT: store ptr [[TMP27]], ptr [[TMP32]], align 8 +// CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 +// CHECK1-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP33]], align 8 +// CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 +// CHECK1-NEXT: store ptr null, ptr [[TMP34]], align 8 +// CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 +// CHECK1-NEXT: store ptr null, ptr [[TMP35]], align 8 +// CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 +// CHECK1-NEXT: store i64 0, ptr [[TMP36]], align 8 +// CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 +// CHECK1-NEXT: store i64 0, ptr [[TMP37]], align 8 +// CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 +// CHECK1-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP38]], align 4 +// CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 +// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP39]], align 4 +// CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 +// CHECK1-NEXT: store i32 0, ptr [[TMP40]], align 4 +// CHECK1-NEXT: [[TMP41:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167.region_id, ptr [[KERNEL_ARGS]]) +// CHECK1-NEXT: [[TMP42:%.*]] = icmp ne i32 [[TMP41]], 0 +// CHECK1-NEXT: br i1 [[TMP42]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK1: omp_offload.failed: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167(ptr [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], ptr [[VLA]]) #[[ATTR3]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: -// CHECK1-NEXT: [[TMP54:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP54]] -// CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK1-NEXT: [[TMP55:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 -// CHECK1-NEXT: [[CONV3:%.*]] = sext i16 [[TMP55]] to i32 -// CHECK1-NEXT: [[TMP56:%.*]] = load i32, i32* [[B]], align 4 -// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP56]] -// CHECK1-NEXT: [[TMP57:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK1-NEXT: call void @llvm.stackrestore(i8* [[TMP57]]) -// CHECK1-NEXT: ret i32 [[ADD4]] +// CHECK1-NEXT: [[TMP43:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP43]] +// CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1 +// CHECK1-NEXT: [[TMP44:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2 +// CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP44]] to i32 +// CHECK1-NEXT: [[TMP45:%.*]] = load i32, ptr [[B]], align 4 +// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP45]] +// CHECK1-NEXT: [[TMP46:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 +// CHECK1-NEXT: call void @llvm.stackrestore(ptr [[TMP46]]) +// CHECK1-NEXT: ret i32 [[ADD3]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici @@ -7536,82 +7395,74 @@ int bar(int n, double *ptr) { // CHECK1-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 -// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 -// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 +// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8 +// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 8 +// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 8 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 -// CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK1-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK1-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 -// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* -// CHECK1-NEXT: store i8 [[TMP2]], i8* [[CONV1]], align 1 -// CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 -// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* -// CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8 -// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* -// CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP7]], align 8 -// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK1-NEXT: store i8* null, i8** [[TMP8]], align 8 -// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK1-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* -// CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 -// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK1-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* -// CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8 -// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK1-NEXT: store i8* null, i8** [[TMP13]], align 8 -// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK1-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [10 x i32]** -// CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP15]], align 8 -// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK1-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [10 x i32]** -// CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP17]], align 8 -// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 -// CHECK1-NEXT: store i8* null, i8** [[TMP18]], align 8 -// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 -// CHECK1-NEXT: store i32 2, i32* [[TMP21]], align 4 -// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 -// CHECK1-NEXT: store i32 3, i32* [[TMP22]], align 4 -// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 -// CHECK1-NEXT: store i8** [[TMP19]], i8*** [[TMP23]], align 8 -// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 -// CHECK1-NEXT: store i8** [[TMP20]], i8*** [[TMP24]], align 8 -// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 -// CHECK1-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.7, i32 0, i32 0), i64** [[TMP25]], align 8 -// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 -// CHECK1-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.8, i32 0, i32 0), i64** [[TMP26]], align 8 -// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 -// CHECK1-NEXT: store i8** null, i8*** [[TMP27]], align 8 -// CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 -// CHECK1-NEXT: store i8** null, i8*** [[TMP28]], align 8 -// CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 -// CHECK1-NEXT: store i64 0, i64* [[TMP29]], align 8 -// CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 9 -// CHECK1-NEXT: store i64 0, i64* [[TMP30]], align 8 -// CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 10 -// CHECK1-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP31]], align 4 -// CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 11 -// CHECK1-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP32]], align 4 -// CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 12 -// CHECK1-NEXT: store i32 0, i32* [[TMP33]], align 4 -// CHECK1-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) -// CHECK1-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 -// CHECK1-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// CHECK1-NEXT: store i32 0, ptr [[A]], align 4 +// CHECK1-NEXT: store i8 0, ptr [[AAA]], align 1 +// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 +// CHECK1-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 +// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8 +// CHECK1-NEXT: [[TMP2:%.*]] = load i8, ptr [[AAA]], align 1 +// CHECK1-NEXT: store i8 [[TMP2]], ptr [[AAA_CASTED]], align 1 +// CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[AAA_CASTED]], align 8 +// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP4]], align 8 +// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP5]], align 8 +// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK1-NEXT: store ptr null, ptr [[TMP6]], align 8 +// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK1-NEXT: store i64 [[TMP3]], ptr [[TMP7]], align 8 +// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK1-NEXT: store i64 [[TMP3]], ptr [[TMP8]], align 8 +// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK1-NEXT: store ptr null, ptr [[TMP9]], align 8 +// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK1-NEXT: store ptr [[B]], ptr [[TMP10]], align 8 +// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK1-NEXT: store ptr [[B]], ptr [[TMP11]], align 8 +// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 +// CHECK1-NEXT: store ptr null, ptr [[TMP12]], align 8 +// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 +// CHECK1-NEXT: store i32 2, ptr [[TMP15]], align 4 +// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 +// CHECK1-NEXT: store i32 3, ptr [[TMP16]], align 4 +// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 +// CHECK1-NEXT: store ptr [[TMP13]], ptr [[TMP17]], align 8 +// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 +// CHECK1-NEXT: store ptr [[TMP14]], ptr [[TMP18]], align 8 +// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 +// CHECK1-NEXT: store ptr @.offload_sizes.7, ptr [[TMP19]], align 8 +// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 +// CHECK1-NEXT: store ptr @.offload_maptypes.8, ptr [[TMP20]], align 8 +// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 +// CHECK1-NEXT: store ptr null, ptr [[TMP21]], align 8 +// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 +// CHECK1-NEXT: store ptr null, ptr [[TMP22]], align 8 +// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 +// CHECK1-NEXT: store i64 0, ptr [[TMP23]], align 8 +// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 +// CHECK1-NEXT: store i64 0, ptr [[TMP24]], align 8 +// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 +// CHECK1-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP25]], align 4 +// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 +// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP26]], align 4 +// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 +// CHECK1-NEXT: store i32 0, ptr [[TMP27]], align 4 +// CHECK1-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142.region_id, ptr [[KERNEL_ARGS]]) +// CHECK1-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 +// CHECK1-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK1: omp_offload.failed: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR3]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: -// CHECK1-NEXT: [[TMP36:%.*]] = load i32, i32* [[A]], align 4 -// CHECK1-NEXT: ret i32 [[TMP36]] +// CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr [[A]], align 4 +// CHECK1-NEXT: ret i32 [[TMP30]] // // // CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i @@ -7621,173 +7472,158 @@ int bar(int n, double *ptr) { // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 -// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x i8*], align 8 -// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x i8*], align 8 -// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x i8*], align 8 +// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x ptr], align 8 +// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x ptr], align 8 +// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x ptr], align 8 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 -// CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK1-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* -// CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 -// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64* -// CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 8 -// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* -// CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8 -// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 -// CHECK1-NEXT: store i8* null, i8** [[TMP6]], align 8 -// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to [10 x i32]** -// CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP8]], align 8 -// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK1-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]** -// CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP10]], align 8 -// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 -// CHECK1-NEXT: store i8* null, i8** [[TMP11]], align 8 -// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 -// CHECK1-NEXT: store i32 2, i32* [[TMP14]], align 4 -// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 -// CHECK1-NEXT: store i32 2, i32* [[TMP15]], align 4 -// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 -// CHECK1-NEXT: store i8** [[TMP12]], i8*** [[TMP16]], align 8 -// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 -// CHECK1-NEXT: store i8** [[TMP13]], i8*** [[TMP17]], align 8 -// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 -// CHECK1-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.9, i32 0, i32 0), i64** [[TMP18]], align 8 -// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 -// CHECK1-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.10, i32 0, i32 0), i64** [[TMP19]], align 8 -// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 -// CHECK1-NEXT: store i8** null, i8*** [[TMP20]], align 8 -// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 -// CHECK1-NEXT: store i8** null, i8*** [[TMP21]], align 8 -// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 -// CHECK1-NEXT: store i64 0, i64* [[TMP22]], align 8 -// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 9 -// CHECK1-NEXT: store i64 0, i64* [[TMP23]], align 8 -// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 10 -// CHECK1-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP24]], align 4 -// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 11 -// CHECK1-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP25]], align 4 -// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 12 -// CHECK1-NEXT: store i32 0, i32* [[TMP26]], align 4 -// CHECK1-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) -// CHECK1-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 -// CHECK1-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// CHECK1-NEXT: store i32 0, ptr [[A]], align 4 +// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 +// CHECK1-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 +// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8 +// CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP2]], align 8 +// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP3]], align 8 +// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 +// CHECK1-NEXT: store ptr null, ptr [[TMP4]], align 8 +// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK1-NEXT: store ptr [[B]], ptr [[TMP5]], align 8 +// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK1-NEXT: store ptr [[B]], ptr [[TMP6]], align 8 +// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 +// CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8 +// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 +// CHECK1-NEXT: store i32 2, ptr [[TMP10]], align 4 +// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 +// CHECK1-NEXT: store i32 2, ptr [[TMP11]], align 4 +// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 +// CHECK1-NEXT: store ptr [[TMP8]], ptr [[TMP12]], align 8 +// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 +// CHECK1-NEXT: store ptr [[TMP9]], ptr [[TMP13]], align 8 +// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 +// CHECK1-NEXT: store ptr @.offload_sizes.9, ptr [[TMP14]], align 8 +// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 +// CHECK1-NEXT: store ptr @.offload_maptypes.10, ptr [[TMP15]], align 8 +// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 +// CHECK1-NEXT: store ptr null, ptr [[TMP16]], align 8 +// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 +// CHECK1-NEXT: store ptr null, ptr [[TMP17]], align 8 +// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 +// CHECK1-NEXT: store i64 0, ptr [[TMP18]], align 8 +// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 +// CHECK1-NEXT: store i64 0, ptr [[TMP19]], align 8 +// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 +// CHECK1-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP20]], align 4 +// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 +// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP21]], align 4 +// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 +// CHECK1-NEXT: store i32 0, ptr [[TMP22]], align 4 +// CHECK1-NEXT: [[TMP23:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128.region_id, ptr [[KERNEL_ARGS]]) +// CHECK1-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 +// CHECK1-NEXT: br i1 [[TMP24]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK1: omp_offload.failed: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128(i64 [[TMP1]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128(i64 [[TMP1]], ptr [[B]]) #[[ATTR3]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: -// CHECK1-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 4 -// CHECK1-NEXT: ret i32 [[TMP29]] +// CHECK1-NEXT: [[TMP25:%.*]] = load i32, ptr [[A]], align 4 +// CHECK1-NEXT: ret i32 [[TMP25]] // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167 -// CHECK1-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: -// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 -// CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// CHECK1-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 -// CHECK1-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave() -// CHECK1-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8 +// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// CHECK1-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 +// CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 +// CHECK1-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 +// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 +// CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 +// CHECK1-NEXT: [[TMP4:%.*]] = call ptr @llvm.stacksave() +// CHECK1-NEXT: store ptr [[TMP4]], ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP2]] // CHECK1-NEXT: [[VLA3:%.*]] = alloca i16, i64 [[TMP5]], align 2 -// CHECK1-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// CHECK1-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR1]], align 8 +// CHECK1-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 +// CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR1]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP1]], [[TMP2]] // CHECK1-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP6]], 2 -// CHECK1-NEXT: [[TMP8:%.*]] = bitcast i16* [[VLA3]] to i8* -// CHECK1-NEXT: [[TMP9:%.*]] = bitcast i16* [[TMP3]] to i8* -// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 2 [[TMP8]], i8* align 2 [[TMP9]], i64 [[TMP7]], i1 false) -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4 -// CHECK1-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP10]] to double -// CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00 -// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK1-NEXT: store double [[ADD]], double* [[A]], align 8 -// CHECK1-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP11:%.*]] = load double, double* [[A5]], align 8 -// CHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+00 -// CHECK1-NEXT: store double [[INC]], double* [[A5]], align 8 -// CHECK1-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 -// CHECK1-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP2]] -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA3]], i64 [[TMP12]] -// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// CHECK1-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2 -// CHECK1-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// CHECK1-NEXT: call void @llvm.stackrestore(i8* [[TMP13]]) +// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 2 [[VLA3]], ptr align 2 [[TMP3]], i64 [[TMP7]], i1 false) +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[B_ADDR]], align 4 +// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP8]] to double +// CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 +// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK1-NEXT: store double [[ADD]], ptr [[A]], align 8 +// CHECK1-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP9:%.*]] = load double, ptr [[A4]], align 8 +// CHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP9]], 1.000000e+00 +// CHECK1-NEXT: store double [[INC]], ptr [[A4]], align 8 +// CHECK1-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 +// CHECK1-NEXT: [[TMP10:%.*]] = mul nsw i64 1, [[TMP2]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA3]], i64 [[TMP10]] +// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1 +// CHECK1-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2 +// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 +// CHECK1-NEXT: call void @llvm.stackrestore(ptr [[TMP11]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142 -// CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 -// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// CHECK1-NEXT: [[B2:%.*]] = alloca [10 x i32], align 4 -// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK1-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 -// CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* -// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK1-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B2]] to i8* -// CHECK1-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8* -// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i64 40, i1 false) -// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4 -// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 -// CHECK1-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 1 -// CHECK1-NEXT: [[CONV3:%.*]] = sext i8 [[TMP4]] to i32 -// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// CHECK1-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// CHECK1-NEXT: store i8 [[CONV5]], i8* [[CONV1]], align 1 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B2]], i64 0, i64 2 -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK1-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 +// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: [[B1:%.*]] = alloca [10 x i32], align 4 +// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 +// CHECK1-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8 +// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[B1]], ptr align 4 [[TMP0]], i64 40, i1 false) +// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 +// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK1-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 +// CHECK1-NEXT: [[TMP2:%.*]] = load i8, ptr [[AAA_ADDR]], align 1 +// CHECK1-NEXT: [[CONV:%.*]] = sext i8 [[TMP2]] to i32 +// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 +// CHECK1-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i8 +// CHECK1-NEXT: store i8 [[CONV3]], ptr [[AAA_ADDR]], align 1 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B1]], i64 0, i64 2 +// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 +// CHECK1-NEXT: store i32 [[ADD4]], ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128 -// CHECK1-SAME: (i64 noundef [[A:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK1-SAME: (i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[B1:%.*]] = alloca [10 x i32], align 4 -// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// CHECK1-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B1]] to i8* -// CHECK1-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8* -// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i64 40, i1 false) -// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4 -// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], i64 0, i64 2 -// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK1-NEXT: store i32 [[ADD2]], i32* [[ARRAYIDX]], align 4 +// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 +// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[B1]], ptr align 4 [[TMP0]], i64 40, i1 false) +// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 +// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK1-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B1]], i64 0, i64 2 +// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 +// CHECK1-NEXT: store i32 [[ADD2]], ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: ret void // // @@ -7799,586 +7635,532 @@ int bar(int n, double *ptr) { // // // CHECK2-LABEL: define {{[^@]+}}@_Z3fooiPd -// CHECK2-SAME: (i32 noundef [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK2-SAME: (i32 noundef [[N:%.*]], ptr noundef [[PTR:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 4 +// CHECK2-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 4 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[AA:%.*]] = alloca i16, align 2 // CHECK2-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK2-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK2-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4 // CHECK2-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 // CHECK2-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 // CHECK2-NEXT: [[E:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 4 -// CHECK2-NEXT: [[P:%.*]] = alloca i32*, align 64 +// CHECK2-NEXT: [[P:%.*]] = alloca ptr, align 64 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[GA_CASTED:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 4 +// CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 4 +// CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 4 // CHECK2-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [9 x i8*], align 4 -// CHECK2-NEXT: [[DOTOFFLOAD_PTRS3:%.*]] = alloca [9 x i8*], align 4 -// CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [9 x i8*], align 4 +// CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [9 x ptr], align 4 +// CHECK2-NEXT: [[DOTOFFLOAD_PTRS3:%.*]] = alloca [9 x ptr], align 4 +// CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [9 x ptr], align 4 // CHECK2-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 4 // CHECK2-NEXT: [[KERNEL_ARGS5:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 -// CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS8:%.*]] = alloca [2 x i8*], align 4 -// CHECK2-NEXT: [[DOTOFFLOAD_PTRS9:%.*]] = alloca [2 x i8*], align 4 -// CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS10:%.*]] = alloca [2 x i8*], align 4 +// CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS8:%.*]] = alloca [2 x ptr], align 4 +// CHECK2-NEXT: [[DOTOFFLOAD_PTRS9:%.*]] = alloca [2 x ptr], align 4 +// CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS10:%.*]] = alloca [2 x ptr], align 4 // CHECK2-NEXT: [[KERNEL_ARGS11:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 -// CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK2-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 4 -// CHECK2-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK2-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK2-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK2-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 +// CHECK2-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// CHECK2-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 4 +// CHECK2-NEXT: store i32 0, ptr [[A]], align 4 +// CHECK2-NEXT: store i16 0, ptr [[AA]], align 2 +// CHECK2-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// CHECK2-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave() +// CHECK2-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4 // CHECK2-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// CHECK2-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK2-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 +// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK2-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] // CHECK2-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// CHECK2-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK2-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 0 -// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK2-NEXT: store i32 [[TMP4]], i32* [[X]], align 4 -// CHECK2-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 1 -// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK2-NEXT: store i32 [[TMP5]], i32* [[Y]], align 4 -// CHECK2-NEXT: store i32* [[A]], i32** [[P]], align 64 -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK2-NEXT: store i32 [[TMP6]], i32* [[A_CASTED]], align 4 -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK2-NEXT: [[TMP8:%.*]] = load i32*, i32** [[P]], align 64 -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* @ga, align 4 -// CHECK2-NEXT: store i32 [[TMP9]], i32* [[GA_CASTED]], align 4 -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[GA_CASTED]], align 4 -// CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK2-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* -// CHECK2-NEXT: store i32 [[TMP7]], i32* [[TMP12]], align 4 -// CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK2-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* -// CHECK2-NEXT: store i32 [[TMP7]], i32* [[TMP14]], align 4 -// CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK2-NEXT: store i8* null, i8** [[TMP15]], align 4 -// CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK2-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32** -// CHECK2-NEXT: store i32* [[TMP8]], i32** [[TMP17]], align 4 -// CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK2-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** -// CHECK2-NEXT: store i32* [[TMP8]], i32** [[TMP19]], align 4 -// CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK2-NEXT: store i8* null, i8** [[TMP20]], align 4 -// CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK2-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* -// CHECK2-NEXT: store i32 [[TMP10]], i32* [[TMP22]], align 4 -// CHECK2-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK2-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* -// CHECK2-NEXT: store i32 [[TMP10]], i32* [[TMP24]], align 4 -// CHECK2-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK2-NEXT: store i8* null, i8** [[TMP25]], align 4 -// CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK2-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 -// CHECK2-NEXT: store i32 2, i32* [[TMP28]], align 4 -// CHECK2-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 -// CHECK2-NEXT: store i32 3, i32* [[TMP29]], align 4 -// CHECK2-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 -// CHECK2-NEXT: store i8** [[TMP26]], i8*** [[TMP30]], align 4 -// CHECK2-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 -// CHECK2-NEXT: store i8** [[TMP27]], i8*** [[TMP31]], align 4 -// CHECK2-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 -// CHECK2-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64** [[TMP32]], align 4 -// CHECK2-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 -// CHECK2-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i64** [[TMP33]], align 4 -// CHECK2-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 -// CHECK2-NEXT: store i8** null, i8*** [[TMP34]], align 4 -// CHECK2-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 -// CHECK2-NEXT: store i8** null, i8*** [[TMP35]], align 4 -// CHECK2-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 -// CHECK2-NEXT: store i64 0, i64* [[TMP36]], align 8 -// CHECK2-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 9 -// CHECK2-NEXT: store i64 0, i64* [[TMP37]], align 8 -// CHECK2-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 10 -// CHECK2-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP38]], align 4 -// CHECK2-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 11 -// CHECK2-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP39]], align 4 -// CHECK2-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 12 -// CHECK2-NEXT: store i32 0, i32* [[TMP40]], align 4 -// CHECK2-NEXT: [[TMP41:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) -// CHECK2-NEXT: [[TMP42:%.*]] = icmp ne i32 [[TMP41]], 0 -// CHECK2-NEXT: br i1 [[TMP42]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK2-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 4 +// CHECK2-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 0 +// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// CHECK2-NEXT: store i32 [[TMP4]], ptr [[X]], align 4 +// CHECK2-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 1 +// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// CHECK2-NEXT: store i32 [[TMP5]], ptr [[Y]], align 4 +// CHECK2-NEXT: store ptr [[A]], ptr [[P]], align 64 +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4 +// CHECK2-NEXT: store i32 [[TMP6]], ptr [[A_CASTED]], align 4 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[A_CASTED]], align 4 +// CHECK2-NEXT: [[TMP8:%.*]] = load ptr, ptr [[P]], align 64 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr @ga, align 4 +// CHECK2-NEXT: store i32 [[TMP9]], ptr [[GA_CASTED]], align 4 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[GA_CASTED]], align 4 +// CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK2-NEXT: store i32 [[TMP7]], ptr [[TMP11]], align 4 +// CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK2-NEXT: store i32 [[TMP7]], ptr [[TMP12]], align 4 +// CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK2-NEXT: store ptr null, ptr [[TMP13]], align 4 +// CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK2-NEXT: store ptr [[TMP8]], ptr [[TMP14]], align 4 +// CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK2-NEXT: store ptr [[TMP8]], ptr [[TMP15]], align 4 +// CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK2-NEXT: store ptr null, ptr [[TMP16]], align 4 +// CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK2-NEXT: store i32 [[TMP10]], ptr [[TMP17]], align 4 +// CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK2-NEXT: store i32 [[TMP10]], ptr [[TMP18]], align 4 +// CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK2-NEXT: store ptr null, ptr [[TMP19]], align 4 +// CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 +// CHECK2-NEXT: store i32 2, ptr [[TMP22]], align 4 +// CHECK2-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 +// CHECK2-NEXT: store i32 3, ptr [[TMP23]], align 4 +// CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 +// CHECK2-NEXT: store ptr [[TMP20]], ptr [[TMP24]], align 4 +// CHECK2-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 +// CHECK2-NEXT: store ptr [[TMP21]], ptr [[TMP25]], align 4 +// CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 +// CHECK2-NEXT: store ptr @.offload_sizes, ptr [[TMP26]], align 4 +// CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 +// CHECK2-NEXT: store ptr @.offload_maptypes, ptr [[TMP27]], align 4 +// CHECK2-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 +// CHECK2-NEXT: store ptr null, ptr [[TMP28]], align 4 +// CHECK2-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 +// CHECK2-NEXT: store ptr null, ptr [[TMP29]], align 4 +// CHECK2-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 +// CHECK2-NEXT: store i64 0, ptr [[TMP30]], align 8 +// CHECK2-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 +// CHECK2-NEXT: store i64 0, ptr [[TMP31]], align 8 +// CHECK2-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 +// CHECK2-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP32]], align 4 +// CHECK2-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 +// CHECK2-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP33]], align 4 +// CHECK2-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 +// CHECK2-NEXT: store i32 0, ptr [[TMP34]], align 4 +// CHECK2-NEXT: [[TMP35:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1:[0-9]+]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63.region_id, ptr [[KERNEL_ARGS]]) +// CHECK2-NEXT: [[TMP36:%.*]] = icmp ne i32 [[TMP35]], 0 +// CHECK2-NEXT: br i1 [[TMP36]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK2: omp_offload.failed: -// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63(i32 [[TMP7]], i32* [[TMP8]], i32 [[TMP10]]) #[[ATTR3:[0-9]+]] +// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63(i32 [[TMP7]], ptr [[TMP8]], i32 [[TMP10]]) #[[ATTR3:[0-9]+]] // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK2: omp_offload.cont: -// CHECK2-NEXT: [[TMP43:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK2-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK2-NEXT: store i16 [[TMP43]], i16* [[CONV]], align 2 -// CHECK2-NEXT: [[TMP44:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK2-NEXT: [[TMP45:%.*]] = mul nuw i32 [[TMP0]], 4 -// CHECK2-NEXT: [[TMP46:%.*]] = sext i32 [[TMP45]] to i64 -// CHECK2-NEXT: [[TMP47:%.*]] = mul nuw i32 5, [[TMP2]] -// CHECK2-NEXT: [[TMP48:%.*]] = mul nuw i32 [[TMP47]], 8 -// CHECK2-NEXT: [[TMP49:%.*]] = sext i32 [[TMP48]] to i64 -// CHECK2-NEXT: [[TMP50:%.*]] = bitcast [9 x i64]* [[DOTOFFLOAD_SIZES]] to i8* -// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP50]], i8* align 4 bitcast ([9 x i64]* @.offload_sizes.1 to i8*), i32 72, i1 false) -// CHECK2-NEXT: [[TMP51:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 -// CHECK2-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i32* -// CHECK2-NEXT: store i32 [[TMP44]], i32* [[TMP52]], align 4 -// CHECK2-NEXT: [[TMP53:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 -// CHECK2-NEXT: [[TMP54:%.*]] = bitcast i8** [[TMP53]] to i32* -// CHECK2-NEXT: store i32 [[TMP44]], i32* [[TMP54]], align 4 -// CHECK2-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 0 -// CHECK2-NEXT: store i8* null, i8** [[TMP55]], align 4 -// CHECK2-NEXT: [[TMP56:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 1 -// CHECK2-NEXT: [[TMP57:%.*]] = bitcast i8** [[TMP56]] to [10 x float]** -// CHECK2-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP57]], align 4 -// CHECK2-NEXT: [[TMP58:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 1 -// CHECK2-NEXT: [[TMP59:%.*]] = bitcast i8** [[TMP58]] to [10 x float]** -// CHECK2-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP59]], align 4 -// CHECK2-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 1 -// CHECK2-NEXT: store i8* null, i8** [[TMP60]], align 4 -// CHECK2-NEXT: [[TMP61:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 2 -// CHECK2-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32* -// CHECK2-NEXT: store i32 [[TMP0]], i32* [[TMP62]], align 4 -// CHECK2-NEXT: [[TMP63:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 2 -// CHECK2-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i32* -// CHECK2-NEXT: store i32 [[TMP0]], i32* [[TMP64]], align 4 -// CHECK2-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 2 -// CHECK2-NEXT: store i8* null, i8** [[TMP65]], align 4 -// CHECK2-NEXT: [[TMP66:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 3 -// CHECK2-NEXT: [[TMP67:%.*]] = bitcast i8** [[TMP66]] to float** -// CHECK2-NEXT: store float* [[VLA]], float** [[TMP67]], align 4 -// CHECK2-NEXT: [[TMP68:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 3 -// CHECK2-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to float** -// CHECK2-NEXT: store float* [[VLA]], float** [[TMP69]], align 4 -// CHECK2-NEXT: [[TMP70:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 -// CHECK2-NEXT: store i64 [[TMP46]], i64* [[TMP70]], align 4 -// CHECK2-NEXT: [[TMP71:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 3 -// CHECK2-NEXT: store i8* null, i8** [[TMP71]], align 4 -// CHECK2-NEXT: [[TMP72:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 4 -// CHECK2-NEXT: [[TMP73:%.*]] = bitcast i8** [[TMP72]] to [5 x [10 x double]]** -// CHECK2-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP73]], align 4 -// CHECK2-NEXT: [[TMP74:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 4 -// CHECK2-NEXT: [[TMP75:%.*]] = bitcast i8** [[TMP74]] to [5 x [10 x double]]** -// CHECK2-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP75]], align 4 -// CHECK2-NEXT: [[TMP76:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 4 -// CHECK2-NEXT: store i8* null, i8** [[TMP76]], align 4 -// CHECK2-NEXT: [[TMP77:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 5 -// CHECK2-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i32* -// CHECK2-NEXT: store i32 5, i32* [[TMP78]], align 4 -// CHECK2-NEXT: [[TMP79:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 5 -// CHECK2-NEXT: [[TMP80:%.*]] = bitcast i8** [[TMP79]] to i32* -// CHECK2-NEXT: store i32 5, i32* [[TMP80]], align 4 -// CHECK2-NEXT: [[TMP81:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 5 -// CHECK2-NEXT: store i8* null, i8** [[TMP81]], align 4 -// CHECK2-NEXT: [[TMP82:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 6 -// CHECK2-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i32* -// CHECK2-NEXT: store i32 [[TMP2]], i32* [[TMP83]], align 4 -// CHECK2-NEXT: [[TMP84:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 6 -// CHECK2-NEXT: [[TMP85:%.*]] = bitcast i8** [[TMP84]] to i32* -// CHECK2-NEXT: store i32 [[TMP2]], i32* [[TMP85]], align 4 -// CHECK2-NEXT: [[TMP86:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 6 -// CHECK2-NEXT: store i8* null, i8** [[TMP86]], align 4 -// CHECK2-NEXT: [[TMP87:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 7 -// CHECK2-NEXT: [[TMP88:%.*]] = bitcast i8** [[TMP87]] to double** -// CHECK2-NEXT: store double* [[VLA1]], double** [[TMP88]], align 4 -// CHECK2-NEXT: [[TMP89:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 7 -// CHECK2-NEXT: [[TMP90:%.*]] = bitcast i8** [[TMP89]] to double** -// CHECK2-NEXT: store double* [[VLA1]], double** [[TMP90]], align 4 -// CHECK2-NEXT: [[TMP91:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 -// CHECK2-NEXT: store i64 [[TMP49]], i64* [[TMP91]], align 4 -// CHECK2-NEXT: [[TMP92:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 7 -// CHECK2-NEXT: store i8* null, i8** [[TMP92]], align 4 -// CHECK2-NEXT: [[TMP93:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 8 -// CHECK2-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to %struct.TT** -// CHECK2-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP94]], align 4 -// CHECK2-NEXT: [[TMP95:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 8 -// CHECK2-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to %struct.TT** -// CHECK2-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP96]], align 4 -// CHECK2-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 8 -// CHECK2-NEXT: store i8* null, i8** [[TMP97]], align 4 -// CHECK2-NEXT: [[TMP98:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 -// CHECK2-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 -// CHECK2-NEXT: [[TMP100:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK2-NEXT: [[TMP101:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 0 -// CHECK2-NEXT: store i32 2, i32* [[TMP101]], align 4 -// CHECK2-NEXT: [[TMP102:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 1 -// CHECK2-NEXT: store i32 9, i32* [[TMP102]], align 4 -// CHECK2-NEXT: [[TMP103:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 2 -// CHECK2-NEXT: store i8** [[TMP98]], i8*** [[TMP103]], align 4 -// CHECK2-NEXT: [[TMP104:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 3 -// CHECK2-NEXT: store i8** [[TMP99]], i8*** [[TMP104]], align 4 -// CHECK2-NEXT: [[TMP105:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 4 -// CHECK2-NEXT: store i64* [[TMP100]], i64** [[TMP105]], align 4 -// CHECK2-NEXT: [[TMP106:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 5 -// CHECK2-NEXT: store i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.2, i32 0, i32 0), i64** [[TMP106]], align 4 -// CHECK2-NEXT: [[TMP107:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 6 -// CHECK2-NEXT: store i8** null, i8*** [[TMP107]], align 4 -// CHECK2-NEXT: [[TMP108:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 7 -// CHECK2-NEXT: store i8** null, i8*** [[TMP108]], align 4 -// CHECK2-NEXT: [[TMP109:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 8 -// CHECK2-NEXT: store i64 0, i64* [[TMP109]], align 8 -// CHECK2-NEXT: [[TMP110:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 9 -// CHECK2-NEXT: store i64 0, i64* [[TMP110]], align 8 -// CHECK2-NEXT: [[TMP111:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 10 -// CHECK2-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP111]], align 4 -// CHECK2-NEXT: [[TMP112:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 11 -// CHECK2-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP112]], align 4 -// CHECK2-NEXT: [[TMP113:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 12 -// CHECK2-NEXT: store i32 0, i32* [[TMP113]], align 4 -// CHECK2-NEXT: [[TMP114:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]]) -// CHECK2-NEXT: [[TMP115:%.*]] = icmp ne i32 [[TMP114]], 0 -// CHECK2-NEXT: br i1 [[TMP115]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] +// CHECK2-NEXT: [[TMP37:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK2-NEXT: store i16 [[TMP37]], ptr [[AA_CASTED]], align 2 +// CHECK2-NEXT: [[TMP38:%.*]] = load i32, ptr [[AA_CASTED]], align 4 +// CHECK2-NEXT: [[TMP39:%.*]] = mul nuw i32 [[TMP0]], 4 +// CHECK2-NEXT: [[TMP40:%.*]] = sext i32 [[TMP39]] to i64 +// CHECK2-NEXT: [[TMP41:%.*]] = mul nuw i32 5, [[TMP2]] +// CHECK2-NEXT: [[TMP42:%.*]] = mul nuw i32 [[TMP41]], 8 +// CHECK2-NEXT: [[TMP43:%.*]] = sext i32 [[TMP42]] to i64 +// CHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes.1, i32 72, i1 false) +// CHECK2-NEXT: [[TMP44:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 +// CHECK2-NEXT: store i32 [[TMP38]], ptr [[TMP44]], align 4 +// CHECK2-NEXT: [[TMP45:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 +// CHECK2-NEXT: store i32 [[TMP38]], ptr [[TMP45]], align 4 +// CHECK2-NEXT: [[TMP46:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 0 +// CHECK2-NEXT: store ptr null, ptr [[TMP46]], align 4 +// CHECK2-NEXT: [[TMP47:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 1 +// CHECK2-NEXT: store ptr [[B]], ptr [[TMP47]], align 4 +// CHECK2-NEXT: [[TMP48:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 1 +// CHECK2-NEXT: store ptr [[B]], ptr [[TMP48]], align 4 +// CHECK2-NEXT: [[TMP49:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 1 +// CHECK2-NEXT: store ptr null, ptr [[TMP49]], align 4 +// CHECK2-NEXT: [[TMP50:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 2 +// CHECK2-NEXT: store i32 [[TMP0]], ptr [[TMP50]], align 4 +// CHECK2-NEXT: [[TMP51:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 2 +// CHECK2-NEXT: store i32 [[TMP0]], ptr [[TMP51]], align 4 +// CHECK2-NEXT: [[TMP52:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 2 +// CHECK2-NEXT: store ptr null, ptr [[TMP52]], align 4 +// CHECK2-NEXT: [[TMP53:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 3 +// CHECK2-NEXT: store ptr [[VLA]], ptr [[TMP53]], align 4 +// CHECK2-NEXT: [[TMP54:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 3 +// CHECK2-NEXT: store ptr [[VLA]], ptr [[TMP54]], align 4 +// CHECK2-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK2-NEXT: store i64 [[TMP40]], ptr [[TMP55]], align 4 +// CHECK2-NEXT: [[TMP56:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 3 +// CHECK2-NEXT: store ptr null, ptr [[TMP56]], align 4 +// CHECK2-NEXT: [[TMP57:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 4 +// CHECK2-NEXT: store ptr [[C]], ptr [[TMP57]], align 4 +// CHECK2-NEXT: [[TMP58:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 4 +// CHECK2-NEXT: store ptr [[C]], ptr [[TMP58]], align 4 +// CHECK2-NEXT: [[TMP59:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 4 +// CHECK2-NEXT: store ptr null, ptr [[TMP59]], align 4 +// CHECK2-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 5 +// CHECK2-NEXT: store i32 5, ptr [[TMP60]], align 4 +// CHECK2-NEXT: [[TMP61:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 5 +// CHECK2-NEXT: store i32 5, ptr [[TMP61]], align 4 +// CHECK2-NEXT: [[TMP62:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 5 +// CHECK2-NEXT: store ptr null, ptr [[TMP62]], align 4 +// CHECK2-NEXT: [[TMP63:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 6 +// CHECK2-NEXT: store i32 [[TMP2]], ptr [[TMP63]], align 4 +// CHECK2-NEXT: [[TMP64:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 6 +// CHECK2-NEXT: store i32 [[TMP2]], ptr [[TMP64]], align 4 +// CHECK2-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 6 +// CHECK2-NEXT: store ptr null, ptr [[TMP65]], align 4 +// CHECK2-NEXT: [[TMP66:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 7 +// CHECK2-NEXT: store ptr [[VLA1]], ptr [[TMP66]], align 4 +// CHECK2-NEXT: [[TMP67:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 7 +// CHECK2-NEXT: store ptr [[VLA1]], ptr [[TMP67]], align 4 +// CHECK2-NEXT: [[TMP68:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 7 +// CHECK2-NEXT: store i64 [[TMP43]], ptr [[TMP68]], align 4 +// CHECK2-NEXT: [[TMP69:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 7 +// CHECK2-NEXT: store ptr null, ptr [[TMP69]], align 4 +// CHECK2-NEXT: [[TMP70:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 8 +// CHECK2-NEXT: store ptr [[D]], ptr [[TMP70]], align 4 +// CHECK2-NEXT: [[TMP71:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 8 +// CHECK2-NEXT: store ptr [[D]], ptr [[TMP71]], align 4 +// CHECK2-NEXT: [[TMP72:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 8 +// CHECK2-NEXT: store ptr null, ptr [[TMP72]], align 4 +// CHECK2-NEXT: [[TMP73:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 +// CHECK2-NEXT: [[TMP74:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 +// CHECK2-NEXT: [[TMP75:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK2-NEXT: [[TMP76:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 0 +// CHECK2-NEXT: store i32 2, ptr [[TMP76]], align 4 +// CHECK2-NEXT: [[TMP77:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 1 +// CHECK2-NEXT: store i32 9, ptr [[TMP77]], align 4 +// CHECK2-NEXT: [[TMP78:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 2 +// CHECK2-NEXT: store ptr [[TMP73]], ptr [[TMP78]], align 4 +// CHECK2-NEXT: [[TMP79:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 3 +// CHECK2-NEXT: store ptr [[TMP74]], ptr [[TMP79]], align 4 +// CHECK2-NEXT: [[TMP80:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 4 +// CHECK2-NEXT: store ptr [[TMP75]], ptr [[TMP80]], align 4 +// CHECK2-NEXT: [[TMP81:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 5 +// CHECK2-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP81]], align 4 +// CHECK2-NEXT: [[TMP82:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 6 +// CHECK2-NEXT: store ptr null, ptr [[TMP82]], align 4 +// CHECK2-NEXT: [[TMP83:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 7 +// CHECK2-NEXT: store ptr null, ptr [[TMP83]], align 4 +// CHECK2-NEXT: [[TMP84:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 8 +// CHECK2-NEXT: store i64 0, ptr [[TMP84]], align 8 +// CHECK2-NEXT: [[TMP85:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 9 +// CHECK2-NEXT: store i64 0, ptr [[TMP85]], align 8 +// CHECK2-NEXT: [[TMP86:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 10 +// CHECK2-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP86]], align 4 +// CHECK2-NEXT: [[TMP87:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 11 +// CHECK2-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP87]], align 4 +// CHECK2-NEXT: [[TMP88:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 12 +// CHECK2-NEXT: store i32 0, ptr [[TMP88]], align 4 +// CHECK2-NEXT: [[TMP89:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70.region_id, ptr [[KERNEL_ARGS5]]) +// CHECK2-NEXT: [[TMP90:%.*]] = icmp ne i32 [[TMP89]], 0 +// CHECK2-NEXT: br i1 [[TMP90]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] // CHECK2: omp_offload.failed6: -// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70(i32 [[TMP44]], [10 x float]* [[B]], i32 [[TMP0]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP2]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] +// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70(i32 [[TMP38]], ptr [[B]], i32 [[TMP0]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP2]], ptr [[VLA1]], ptr [[D]]) #[[ATTR3]] // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT7]] // CHECK2: omp_offload.cont7: -// CHECK2-NEXT: [[TMP116:%.*]] = load double*, double** [[PTR_ADDR]], align 4 -// CHECK2-NEXT: [[TMP117:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 0 -// CHECK2-NEXT: [[TMP118:%.*]] = bitcast i8** [[TMP117]] to double** -// CHECK2-NEXT: store double* [[TMP116]], double** [[TMP118]], align 4 -// CHECK2-NEXT: [[TMP119:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS9]], i32 0, i32 0 -// CHECK2-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to double** -// CHECK2-NEXT: store double* [[TMP116]], double** [[TMP120]], align 4 -// CHECK2-NEXT: [[TMP121:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS10]], i32 0, i32 0 -// CHECK2-NEXT: store i8* null, i8** [[TMP121]], align 4 -// CHECK2-NEXT: [[TMP122:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 1 -// CHECK2-NEXT: [[TMP123:%.*]] = bitcast i8** [[TMP122]] to %struct.TT.0** -// CHECK2-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[TMP123]], align 4 -// CHECK2-NEXT: [[TMP124:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS9]], i32 0, i32 1 -// CHECK2-NEXT: [[TMP125:%.*]] = bitcast i8** [[TMP124]] to %struct.TT.0** -// CHECK2-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[TMP125]], align 4 -// CHECK2-NEXT: [[TMP126:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS10]], i32 0, i32 1 -// CHECK2-NEXT: store i8* null, i8** [[TMP126]], align 4 -// CHECK2-NEXT: [[TMP127:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 0 -// CHECK2-NEXT: [[TMP128:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS9]], i32 0, i32 0 -// CHECK2-NEXT: [[TMP129:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 0 -// CHECK2-NEXT: store i32 2, i32* [[TMP129]], align 4 -// CHECK2-NEXT: [[TMP130:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 1 -// CHECK2-NEXT: store i32 2, i32* [[TMP130]], align 4 -// CHECK2-NEXT: [[TMP131:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 2 -// CHECK2-NEXT: store i8** [[TMP127]], i8*** [[TMP131]], align 4 -// CHECK2-NEXT: [[TMP132:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 3 -// CHECK2-NEXT: store i8** [[TMP128]], i8*** [[TMP132]], align 4 -// CHECK2-NEXT: [[TMP133:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 4 -// CHECK2-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.3, i32 0, i32 0), i64** [[TMP133]], align 4 -// CHECK2-NEXT: [[TMP134:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 5 -// CHECK2-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.4, i32 0, i32 0), i64** [[TMP134]], align 4 -// CHECK2-NEXT: [[TMP135:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 6 -// CHECK2-NEXT: store i8** null, i8*** [[TMP135]], align 4 -// CHECK2-NEXT: [[TMP136:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 7 -// CHECK2-NEXT: store i8** null, i8*** [[TMP136]], align 4 -// CHECK2-NEXT: [[TMP137:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 8 -// CHECK2-NEXT: store i64 0, i64* [[TMP137]], align 8 -// CHECK2-NEXT: [[TMP138:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 9 -// CHECK2-NEXT: store i64 0, i64* [[TMP138]], align 8 -// CHECK2-NEXT: [[TMP139:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 10 -// CHECK2-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP139]], align 4 -// CHECK2-NEXT: [[TMP140:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 11 -// CHECK2-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP140]], align 4 -// CHECK2-NEXT: [[TMP141:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 12 -// CHECK2-NEXT: store i32 0, i32* [[TMP141]], align 4 -// CHECK2-NEXT: [[TMP142:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]]) -// CHECK2-NEXT: [[TMP143:%.*]] = icmp ne i32 [[TMP142]], 0 -// CHECK2-NEXT: br i1 [[TMP143]], label [[OMP_OFFLOAD_FAILED12:%.*]], label [[OMP_OFFLOAD_CONT13:%.*]] +// CHECK2-NEXT: [[TMP91:%.*]] = load ptr, ptr [[PTR_ADDR]], align 4 +// CHECK2-NEXT: [[TMP92:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 0 +// CHECK2-NEXT: store ptr [[TMP91]], ptr [[TMP92]], align 4 +// CHECK2-NEXT: [[TMP93:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS9]], i32 0, i32 0 +// CHECK2-NEXT: store ptr [[TMP91]], ptr [[TMP93]], align 4 +// CHECK2-NEXT: [[TMP94:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS10]], i32 0, i32 0 +// CHECK2-NEXT: store ptr null, ptr [[TMP94]], align 4 +// CHECK2-NEXT: [[TMP95:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 1 +// CHECK2-NEXT: store ptr [[E]], ptr [[TMP95]], align 4 +// CHECK2-NEXT: [[TMP96:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS9]], i32 0, i32 1 +// CHECK2-NEXT: store ptr [[E]], ptr [[TMP96]], align 4 +// CHECK2-NEXT: [[TMP97:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS10]], i32 0, i32 1 +// CHECK2-NEXT: store ptr null, ptr [[TMP97]], align 4 +// CHECK2-NEXT: [[TMP98:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 0 +// CHECK2-NEXT: [[TMP99:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS9]], i32 0, i32 0 +// CHECK2-NEXT: [[TMP100:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 0 +// CHECK2-NEXT: store i32 2, ptr [[TMP100]], align 4 +// CHECK2-NEXT: [[TMP101:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 1 +// CHECK2-NEXT: store i32 2, ptr [[TMP101]], align 4 +// CHECK2-NEXT: [[TMP102:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 2 +// CHECK2-NEXT: store ptr [[TMP98]], ptr [[TMP102]], align 4 +// CHECK2-NEXT: [[TMP103:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 3 +// CHECK2-NEXT: store ptr [[TMP99]], ptr [[TMP103]], align 4 +// CHECK2-NEXT: [[TMP104:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 4 +// CHECK2-NEXT: store ptr @.offload_sizes.3, ptr [[TMP104]], align 4 +// CHECK2-NEXT: [[TMP105:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 5 +// CHECK2-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP105]], align 4 +// CHECK2-NEXT: [[TMP106:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 6 +// CHECK2-NEXT: store ptr null, ptr [[TMP106]], align 4 +// CHECK2-NEXT: [[TMP107:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 7 +// CHECK2-NEXT: store ptr null, ptr [[TMP107]], align 4 +// CHECK2-NEXT: [[TMP108:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 8 +// CHECK2-NEXT: store i64 0, ptr [[TMP108]], align 8 +// CHECK2-NEXT: [[TMP109:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 9 +// CHECK2-NEXT: store i64 0, ptr [[TMP109]], align 8 +// CHECK2-NEXT: [[TMP110:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 10 +// CHECK2-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP110]], align 4 +// CHECK2-NEXT: [[TMP111:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 11 +// CHECK2-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP111]], align 4 +// CHECK2-NEXT: [[TMP112:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 12 +// CHECK2-NEXT: store i32 0, ptr [[TMP112]], align 4 +// CHECK2-NEXT: [[TMP113:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111.region_id, ptr [[KERNEL_ARGS11]]) +// CHECK2-NEXT: [[TMP114:%.*]] = icmp ne i32 [[TMP113]], 0 +// CHECK2-NEXT: br i1 [[TMP114]], label [[OMP_OFFLOAD_FAILED12:%.*]], label [[OMP_OFFLOAD_CONT13:%.*]] // CHECK2: omp_offload.failed12: -// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111(double* [[TMP116]], %struct.TT.0* [[E]]) #[[ATTR3]] +// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111(ptr [[TMP91]], ptr [[E]]) #[[ATTR3]] // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT13]] // CHECK2: omp_offload.cont13: -// CHECK2-NEXT: [[TMP144:%.*]] = load i32, i32* [[A]], align 4 -// CHECK2-NEXT: [[TMP145:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK2-NEXT: call void @llvm.stackrestore(i8* [[TMP145]]) -// CHECK2-NEXT: ret i32 [[TMP144]] +// CHECK2-NEXT: [[TMP115:%.*]] = load i32, ptr [[A]], align 4 +// CHECK2-NEXT: [[TMP116:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 +// CHECK2-NEXT: call void @llvm.stackrestore(ptr [[TMP116]]) +// CHECK2-NEXT: ret i32 [[TMP115]] // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63 -// CHECK2-SAME: (i32 noundef [[A:%.*]], i32* noundef [[P:%.*]], i32 noundef [[GA:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK2-SAME: (i32 noundef [[A:%.*]], ptr noundef [[P:%.*]], i32 noundef [[GA:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[P_ADDR:%.*]] = alloca i32*, align 4 +// CHECK2-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 4 // CHECK2-NEXT: [[GA_ADDR:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK2-NEXT: store i32* [[P]], i32** [[P_ADDR]], align 4 -// CHECK2-NEXT: store i32 [[GA]], i32* [[GA_ADDR]], align 4 +// CHECK2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 +// CHECK2-NEXT: store ptr [[P]], ptr [[P_ADDR]], align 4 +// CHECK2-NEXT: store i32 [[GA]], ptr [[GA_ADDR]], align 4 // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70 -// CHECK2-SAME: (i32 noundef [[AA:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 // CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 -// CHECK2-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK2-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 4 +// CHECK2-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 // CHECK2-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 -// CHECK2-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK2-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 4 +// CHECK2-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 // CHECK2-NEXT: [[B5:%.*]] = alloca [10 x float], align 4 -// CHECK2-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK2-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4 // CHECK2-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[C7:%.*]] = alloca [5 x [10 x double]], align 8 // CHECK2-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[__VLA_EXPR2:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[D9:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 -// CHECK2-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK2-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 -// CHECK2-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK2-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 -// CHECK2-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 -// CHECK2-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK2-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 -// CHECK2-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 -// CHECK2-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 -// CHECK2-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK2-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 -// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK2-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 -// CHECK2-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 -// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 -// CHECK2-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 -// CHECK2-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 -// CHECK2-NEXT: [[TMP8:%.*]] = bitcast [10 x float]* [[B5]] to i8* -// CHECK2-NEXT: [[TMP9:%.*]] = bitcast [10 x float]* [[TMP0]] to i8* -// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i32 40, i1 false) -// CHECK2-NEXT: [[TMP10:%.*]] = call i8* @llvm.stacksave() -// CHECK2-NEXT: store i8* [[TMP10]], i8** [[SAVED_STACK]], align 4 +// CHECK2-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 +// CHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 +// CHECK2-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 +// CHECK2-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 4 +// CHECK2-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 +// CHECK2-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 +// CHECK2-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4 +// CHECK2-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4 +// CHECK2-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 +// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 +// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 +// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4 +// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 +// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 +// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4 +// CHECK2-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4 +// CHECK2-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4 +// CHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[B5]], ptr align 4 [[TMP0]], i32 40, i1 false) +// CHECK2-NEXT: [[TMP8:%.*]] = call ptr @llvm.stacksave() +// CHECK2-NEXT: store ptr [[TMP8]], ptr [[SAVED_STACK]], align 4 // CHECK2-NEXT: [[VLA6:%.*]] = alloca float, i32 [[TMP1]], align 4 -// CHECK2-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK2-NEXT: [[TMP11:%.*]] = mul nuw i32 [[TMP1]], 4 -// CHECK2-NEXT: [[TMP12:%.*]] = bitcast float* [[VLA6]] to i8* -// CHECK2-NEXT: [[TMP13:%.*]] = bitcast float* [[TMP2]] to i8* -// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 [[TMP11]], i1 false) -// CHECK2-NEXT: [[TMP14:%.*]] = bitcast [5 x [10 x double]]* [[C7]] to i8* -// CHECK2-NEXT: [[TMP15:%.*]] = bitcast [5 x [10 x double]]* [[TMP3]] to i8* -// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 [[TMP14]], i8* align 8 [[TMP15]], i32 400, i1 false) -// CHECK2-NEXT: [[TMP16:%.*]] = mul nuw i32 [[TMP4]], [[TMP5]] -// CHECK2-NEXT: [[VLA8:%.*]] = alloca double, i32 [[TMP16]], align 8 -// CHECK2-NEXT: store i32 [[TMP4]], i32* [[__VLA_EXPR1]], align 4 -// CHECK2-NEXT: store i32 [[TMP5]], i32* [[__VLA_EXPR2]], align 4 -// CHECK2-NEXT: [[TMP17:%.*]] = mul nuw i32 [[TMP4]], [[TMP5]] -// CHECK2-NEXT: [[TMP18:%.*]] = mul nuw i32 [[TMP17]], 8 -// CHECK2-NEXT: [[TMP19:%.*]] = bitcast double* [[VLA8]] to i8* -// CHECK2-NEXT: [[TMP20:%.*]] = bitcast double* [[TMP6]] to i8* -// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 [[TMP19]], i8* align 8 [[TMP20]], i32 [[TMP18]], i1 false) -// CHECK2-NEXT: [[TMP21:%.*]] = bitcast %struct.TT* [[D9]] to i8* -// CHECK2-NEXT: [[TMP22:%.*]] = bitcast %struct.TT* [[TMP7]] to i8* -// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP21]], i8* align 4 [[TMP22]], i32 12, i1 false) -// CHECK2-NEXT: [[TMP23:%.*]] = load i16, i16* [[CONV]], align 2 -// CHECK2-NEXT: [[CONV10:%.*]] = sext i16 [[TMP23]] to i32 -// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV10]], 1 -// CHECK2-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD]] to i16 -// CHECK2-NEXT: store i16 [[CONV11]], i16* [[CONV]], align 2 -// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B5]], i32 0, i32 2 -// CHECK2-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4 -// CHECK2-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA6]], i32 3 -// CHECK2-NEXT: store float 1.000000e+00, float* [[ARRAYIDX12]], align 4 -// CHECK2-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C7]], i32 0, i32 1 -// CHECK2-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], i32 0, i32 2 -// CHECK2-NEXT: store double 1.000000e+00, double* [[ARRAYIDX14]], align 8 -// CHECK2-NEXT: [[TMP24:%.*]] = mul nsw i32 1, [[TMP5]] -// CHECK2-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[VLA8]], i32 [[TMP24]] -// CHECK2-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i32 3 -// CHECK2-NEXT: store double 1.000000e+00, double* [[ARRAYIDX16]], align 8 -// CHECK2-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 0 -// CHECK2-NEXT: store i64 1, i64* [[X]], align 4 -// CHECK2-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 1 -// CHECK2-NEXT: store i8 1, i8* [[Y]], align 4 -// CHECK2-NEXT: [[TMP25:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK2-NEXT: call void @llvm.stackrestore(i8* [[TMP25]]) +// CHECK2-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 +// CHECK2-NEXT: [[TMP9:%.*]] = mul nuw i32 [[TMP1]], 4 +// CHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VLA6]], ptr align 4 [[TMP2]], i32 [[TMP9]], i1 false) +// CHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[C7]], ptr align 8 [[TMP3]], i32 400, i1 false) +// CHECK2-NEXT: [[TMP10:%.*]] = mul nuw i32 [[TMP4]], [[TMP5]] +// CHECK2-NEXT: [[VLA8:%.*]] = alloca double, i32 [[TMP10]], align 8 +// CHECK2-NEXT: store i32 [[TMP4]], ptr [[__VLA_EXPR1]], align 4 +// CHECK2-NEXT: store i32 [[TMP5]], ptr [[__VLA_EXPR2]], align 4 +// CHECK2-NEXT: [[TMP11:%.*]] = mul nuw i32 [[TMP4]], [[TMP5]] +// CHECK2-NEXT: [[TMP12:%.*]] = mul nuw i32 [[TMP11]], 8 +// CHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[VLA8]], ptr align 8 [[TMP6]], i32 [[TMP12]], i1 false) +// CHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[D9]], ptr align 4 [[TMP7]], i32 12, i1 false) +// CHECK2-NEXT: [[TMP13:%.*]] = load i16, ptr [[AA_ADDR]], align 2 +// CHECK2-NEXT: [[CONV:%.*]] = sext i16 [[TMP13]] to i32 +// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 +// CHECK2-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16 +// CHECK2-NEXT: store i16 [[CONV10]], ptr [[AA_ADDR]], align 2 +// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B5]], i32 0, i32 2 +// CHECK2-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX]], align 4 +// CHECK2-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds float, ptr [[VLA6]], i32 3 +// CHECK2-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX11]], align 4 +// CHECK2-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C7]], i32 0, i32 1 +// CHECK2-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX12]], i32 0, i32 2 +// CHECK2-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX13]], align 8 +// CHECK2-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP5]] +// CHECK2-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, ptr [[VLA8]], i32 [[TMP14]] +// CHECK2-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX14]], i32 3 +// CHECK2-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX15]], align 8 +// CHECK2-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D9]], i32 0, i32 0 +// CHECK2-NEXT: store i64 1, ptr [[X]], align 4 +// CHECK2-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D9]], i32 0, i32 1 +// CHECK2-NEXT: store i8 1, ptr [[Y]], align 4 +// CHECK2-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 +// CHECK2-NEXT: call void @llvm.stackrestore(ptr [[TMP15]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111 -// CHECK2-SAME: (double* noundef [[PTR:%.*]], %struct.TT.0* noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (ptr noundef [[PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: -// CHECK2-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 4 -// CHECK2-NEXT: [[E_ADDR:%.*]] = alloca %struct.TT.0*, align 4 +// CHECK2-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 4 +// CHECK2-NEXT: [[E_ADDR:%.*]] = alloca ptr, align 4 // CHECK2-NEXT: [[E1:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 4 -// CHECK2-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 4 -// CHECK2-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[E_ADDR]], align 4 -// CHECK2-NEXT: [[TMP0:%.*]] = load %struct.TT.0*, %struct.TT.0** [[E_ADDR]], align 4 -// CHECK2-NEXT: [[TMP1:%.*]] = bitcast %struct.TT.0* [[E1]] to i8* -// CHECK2-NEXT: [[TMP2:%.*]] = bitcast %struct.TT.0* [[TMP0]] to i8* -// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i32 8, i1 false) -// CHECK2-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E1]], i32 0, i32 0 -// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[X]], align 4 -// CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP3]] to double -// CHECK2-NEXT: [[TMP4:%.*]] = load double*, double** [[PTR_ADDR]], align 4 -// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP4]], i32 0 -// CHECK2-NEXT: store double [[CONV]], double* [[ARRAYIDX]], align 4 -// CHECK2-NEXT: [[TMP5:%.*]] = load double*, double** [[PTR_ADDR]], align 4 -// CHECK2-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds double, double* [[TMP5]], i32 0 -// CHECK2-NEXT: [[TMP6:%.*]] = load double, double* [[ARRAYIDX2]], align 4 -// CHECK2-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// CHECK2-NEXT: store double [[INC]], double* [[ARRAYIDX2]], align 4 +// CHECK2-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 4 +// CHECK2-NEXT: store ptr [[E]], ptr [[E_ADDR]], align 4 +// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[E_ADDR]], align 4 +// CHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[E1]], ptr align 4 [[TMP0]], i32 8, i1 false) +// CHECK2-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], ptr [[E1]], i32 0, i32 0 +// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[X]], align 4 +// CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double +// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[PTR_ADDR]], align 4 +// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[TMP2]], i32 0 +// CHECK2-NEXT: store double [[CONV]], ptr [[ARRAYIDX]], align 4 +// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[PTR_ADDR]], align 4 +// CHECK2-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds double, ptr [[TMP3]], i32 0 +// CHECK2-NEXT: [[TMP4:%.*]] = load double, ptr [[ARRAYIDX2]], align 4 +// CHECK2-NEXT: [[INC:%.*]] = fadd double [[TMP4]], 1.000000e+00 +// CHECK2-NEXT: store double [[INC]], ptr [[ARRAYIDX2]], align 4 // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_Z3bariPd -// CHECK2-SAME: (i32 noundef [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0]] { +// CHECK2-SAME: (i32 noundef [[N:%.*]], ptr noundef [[PTR:%.*]]) #[[ATTR0]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 4 +// CHECK2-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 4 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK2-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 4 -// CHECK2-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK2-NEXT: [[TMP1:%.*]] = load double*, double** [[PTR_ADDR]], align 4 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooiPd(i32 noundef [[TMP0]], double* noundef [[TMP1]]) -// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 +// CHECK2-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// CHECK2-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 4 +// CHECK2-NEXT: store i32 0, ptr [[A]], align 4 +// CHECK2-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[PTR_ADDR]], align 4 +// CHECK2-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooiPd(i32 noundef [[TMP0]], ptr noundef [[TMP1]]) +// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CALL]] -// CHECK2-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK2-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP3]]) -// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 +// CHECK2-NEXT: store i32 [[ADD]], ptr [[A]], align 4 +// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// CHECK2-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP3]]) +// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 4 // CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], [[CALL1]] -// CHECK2-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK2-NEXT: store i32 [[ADD2]], ptr [[A]], align 4 +// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK2-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP5]]) -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], [[CALL3]] -// CHECK2-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK2-NEXT: store i32 [[ADD4]], ptr [[A]], align 4 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK2-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP7]]) -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 // CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP8]], [[CALL5]] -// CHECK2-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 +// CHECK2-NEXT: store i32 [[ADD6]], ptr [[A]], align 4 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[A]], align 4 // CHECK2-NEXT: ret i32 [[TMP9]] // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK2-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK2-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK2-NEXT: entry: -// CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK2-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4 // CHECK2-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 +// CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 4 +// CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 4 +// CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 4 // CHECK2-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 // CHECK2-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 -// CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 +// CHECK2-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// CHECK2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 +// CHECK2-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK2-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK2-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK2-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 +// CHECK2-NEXT: store i32 [[ADD]], ptr [[B]], align 4 +// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// CHECK2-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() +// CHECK2-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 // CHECK2-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] // CHECK2-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK2-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 -// CHECK2-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 -// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK2-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 +// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[B]], align 4 +// CHECK2-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4 +// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4 +// CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK2-NEXT: [[TMP6:%.*]] = mul nuw i32 2, [[TMP1]] // CHECK2-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP6]], 2 // CHECK2-NEXT: [[TMP8:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK2-NEXT: [[TMP9:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* -// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP9]], i8* align 4 bitcast ([5 x i64]* @.offload_sizes.5 to i8*), i32 40, i1 false) -// CHECK2-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK2-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1** -// CHECK2-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 4 -// CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK2-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double** -// CHECK2-NEXT: store double* [[A]], double** [[TMP13]], align 4 -// CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK2-NEXT: store i8* null, i8** [[TMP14]], align 4 -// CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK2-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* -// CHECK2-NEXT: store i32 [[TMP5]], i32* [[TMP16]], align 4 -// CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK2-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* -// CHECK2-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4 -// CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK2-NEXT: store i8* null, i8** [[TMP19]], align 4 -// CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK2-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32* -// CHECK2-NEXT: store i32 2, i32* [[TMP21]], align 4 -// CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK2-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* -// CHECK2-NEXT: store i32 2, i32* [[TMP23]], align 4 -// CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK2-NEXT: store i8* null, i8** [[TMP24]], align 4 -// CHECK2-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK2-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* -// CHECK2-NEXT: store i32 [[TMP1]], i32* [[TMP26]], align 4 -// CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK2-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* -// CHECK2-NEXT: store i32 [[TMP1]], i32* [[TMP28]], align 4 -// CHECK2-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 -// CHECK2-NEXT: store i8* null, i8** [[TMP29]], align 4 -// CHECK2-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK2-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i16** -// CHECK2-NEXT: store i16* [[VLA]], i16** [[TMP31]], align 4 -// CHECK2-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK2-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i16** -// CHECK2-NEXT: store i16* [[VLA]], i16** [[TMP33]], align 4 -// CHECK2-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 -// CHECK2-NEXT: store i64 [[TMP8]], i64* [[TMP34]], align 4 -// CHECK2-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 -// CHECK2-NEXT: store i8* null, i8** [[TMP35]], align 4 -// CHECK2-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK2-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK2-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK2-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 -// CHECK2-NEXT: store i32 2, i32* [[TMP39]], align 4 -// CHECK2-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 -// CHECK2-NEXT: store i32 5, i32* [[TMP40]], align 4 -// CHECK2-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 -// CHECK2-NEXT: store i8** [[TMP36]], i8*** [[TMP41]], align 4 -// CHECK2-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 -// CHECK2-NEXT: store i8** [[TMP37]], i8*** [[TMP42]], align 4 -// CHECK2-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 -// CHECK2-NEXT: store i64* [[TMP38]], i64** [[TMP43]], align 4 -// CHECK2-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 -// CHECK2-NEXT: store i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.6, i32 0, i32 0), i64** [[TMP44]], align 4 -// CHECK2-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 -// CHECK2-NEXT: store i8** null, i8*** [[TMP45]], align 4 -// CHECK2-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 -// CHECK2-NEXT: store i8** null, i8*** [[TMP46]], align 4 -// CHECK2-NEXT: [[TMP47:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 -// CHECK2-NEXT: store i64 0, i64* [[TMP47]], align 8 -// CHECK2-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 9 -// CHECK2-NEXT: store i64 0, i64* [[TMP48]], align 8 -// CHECK2-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 10 -// CHECK2-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP49]], align 4 -// CHECK2-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 11 -// CHECK2-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP50]], align 4 -// CHECK2-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 12 -// CHECK2-NEXT: store i32 0, i32* [[TMP51]], align 4 -// CHECK2-NEXT: [[TMP52:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) -// CHECK2-NEXT: [[TMP53:%.*]] = icmp ne i32 [[TMP52]], 0 -// CHECK2-NEXT: br i1 [[TMP53]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes.5, i32 40, i1 false) +// CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK2-NEXT: store ptr [[THIS1]], ptr [[TMP9]], align 4 +// CHECK2-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK2-NEXT: store ptr [[A]], ptr [[TMP10]], align 4 +// CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK2-NEXT: store ptr null, ptr [[TMP11]], align 4 +// CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK2-NEXT: store i32 [[TMP5]], ptr [[TMP12]], align 4 +// CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK2-NEXT: store i32 [[TMP5]], ptr [[TMP13]], align 4 +// CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK2-NEXT: store ptr null, ptr [[TMP14]], align 4 +// CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK2-NEXT: store i32 2, ptr [[TMP15]], align 4 +// CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK2-NEXT: store i32 2, ptr [[TMP16]], align 4 +// CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK2-NEXT: store ptr null, ptr [[TMP17]], align 4 +// CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK2-NEXT: store i32 [[TMP1]], ptr [[TMP18]], align 4 +// CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK2-NEXT: store i32 [[TMP1]], ptr [[TMP19]], align 4 +// CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK2-NEXT: store ptr null, ptr [[TMP20]], align 4 +// CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK2-NEXT: store ptr [[VLA]], ptr [[TMP21]], align 4 +// CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK2-NEXT: store ptr [[VLA]], ptr [[TMP22]], align 4 +// CHECK2-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK2-NEXT: store i64 [[TMP8]], ptr [[TMP23]], align 4 +// CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 +// CHECK2-NEXT: store ptr null, ptr [[TMP24]], align 4 +// CHECK2-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK2-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 +// CHECK2-NEXT: store i32 2, ptr [[TMP28]], align 4 +// CHECK2-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 +// CHECK2-NEXT: store i32 5, ptr [[TMP29]], align 4 +// CHECK2-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 +// CHECK2-NEXT: store ptr [[TMP25]], ptr [[TMP30]], align 4 +// CHECK2-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 +// CHECK2-NEXT: store ptr [[TMP26]], ptr [[TMP31]], align 4 +// CHECK2-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 +// CHECK2-NEXT: store ptr [[TMP27]], ptr [[TMP32]], align 4 +// CHECK2-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 +// CHECK2-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP33]], align 4 +// CHECK2-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 +// CHECK2-NEXT: store ptr null, ptr [[TMP34]], align 4 +// CHECK2-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 +// CHECK2-NEXT: store ptr null, ptr [[TMP35]], align 4 +// CHECK2-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 +// CHECK2-NEXT: store i64 0, ptr [[TMP36]], align 8 +// CHECK2-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 +// CHECK2-NEXT: store i64 0, ptr [[TMP37]], align 8 +// CHECK2-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 +// CHECK2-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP38]], align 4 +// CHECK2-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 +// CHECK2-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP39]], align 4 +// CHECK2-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 +// CHECK2-NEXT: store i32 0, ptr [[TMP40]], align 4 +// CHECK2-NEXT: [[TMP41:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167.region_id, ptr [[KERNEL_ARGS]]) +// CHECK2-NEXT: [[TMP42:%.*]] = icmp ne i32 [[TMP41]], 0 +// CHECK2-NEXT: br i1 [[TMP42]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK2: omp_offload.failed: -// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]] +// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167(ptr [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3]] // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK2: omp_offload.cont: -// CHECK2-NEXT: [[TMP54:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP54]] -// CHECK2-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK2-NEXT: [[TMP55:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 -// CHECK2-NEXT: [[CONV:%.*]] = sext i16 [[TMP55]] to i32 -// CHECK2-NEXT: [[TMP56:%.*]] = load i32, i32* [[B]], align 4 -// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP56]] -// CHECK2-NEXT: [[TMP57:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK2-NEXT: call void @llvm.stackrestore(i8* [[TMP57]]) +// CHECK2-NEXT: [[TMP43:%.*]] = mul nsw i32 1, [[TMP1]] +// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP43]] +// CHECK2-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1 +// CHECK2-NEXT: [[TMP44:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2 +// CHECK2-NEXT: [[CONV:%.*]] = sext i16 [[TMP44]] to i32 +// CHECK2-NEXT: [[TMP45:%.*]] = load i32, ptr [[B]], align 4 +// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP45]] +// CHECK2-NEXT: [[TMP46:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 +// CHECK2-NEXT: call void @llvm.stackrestore(ptr [[TMP46]]) // CHECK2-NEXT: ret i32 [[ADD3]] // // @@ -8391,81 +8173,74 @@ int bar(int n, double *ptr) { // CHECK2-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 4 +// CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 4 +// CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 4 // CHECK2-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 -// CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK2-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK2-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK2-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 -// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK2-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK2-NEXT: [[CONV:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* -// CHECK2-NEXT: store i8 [[TMP2]], i8* [[CONV]], align 1 -// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 -// CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK2-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32* -// CHECK2-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4 -// CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK2-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* -// CHECK2-NEXT: store i32 [[TMP1]], i32* [[TMP7]], align 4 -// CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK2-NEXT: store i8* null, i8** [[TMP8]], align 4 -// CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK2-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* -// CHECK2-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 -// CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK2-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* -// CHECK2-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4 -// CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK2-NEXT: store i8* null, i8** [[TMP13]], align 4 -// CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK2-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [10 x i32]** -// CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP15]], align 4 -// CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK2-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [10 x i32]** -// CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP17]], align 4 -// CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK2-NEXT: store i8* null, i8** [[TMP18]], align 4 -// CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 -// CHECK2-NEXT: store i32 2, i32* [[TMP21]], align 4 -// CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 -// CHECK2-NEXT: store i32 3, i32* [[TMP22]], align 4 -// CHECK2-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 -// CHECK2-NEXT: store i8** [[TMP19]], i8*** [[TMP23]], align 4 -// CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 -// CHECK2-NEXT: store i8** [[TMP20]], i8*** [[TMP24]], align 4 -// CHECK2-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 -// CHECK2-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.7, i32 0, i32 0), i64** [[TMP25]], align 4 -// CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 -// CHECK2-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.8, i32 0, i32 0), i64** [[TMP26]], align 4 -// CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 -// CHECK2-NEXT: store i8** null, i8*** [[TMP27]], align 4 -// CHECK2-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 -// CHECK2-NEXT: store i8** null, i8*** [[TMP28]], align 4 -// CHECK2-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 -// CHECK2-NEXT: store i64 0, i64* [[TMP29]], align 8 -// CHECK2-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 9 -// CHECK2-NEXT: store i64 0, i64* [[TMP30]], align 8 -// CHECK2-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 10 -// CHECK2-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP31]], align 4 -// CHECK2-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 11 -// CHECK2-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP32]], align 4 -// CHECK2-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 12 -// CHECK2-NEXT: store i32 0, i32* [[TMP33]], align 4 -// CHECK2-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) -// CHECK2-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 -// CHECK2-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK2-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// CHECK2-NEXT: store i32 0, ptr [[A]], align 4 +// CHECK2-NEXT: store i8 0, ptr [[AAA]], align 1 +// CHECK2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 +// CHECK2-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 +// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4 +// CHECK2-NEXT: [[TMP2:%.*]] = load i8, ptr [[AAA]], align 1 +// CHECK2-NEXT: store i8 [[TMP2]], ptr [[AAA_CASTED]], align 1 +// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[AAA_CASTED]], align 4 +// CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK2-NEXT: store i32 [[TMP1]], ptr [[TMP4]], align 4 +// CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK2-NEXT: store i32 [[TMP1]], ptr [[TMP5]], align 4 +// CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK2-NEXT: store ptr null, ptr [[TMP6]], align 4 +// CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK2-NEXT: store i32 [[TMP3]], ptr [[TMP7]], align 4 +// CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK2-NEXT: store i32 [[TMP3]], ptr [[TMP8]], align 4 +// CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK2-NEXT: store ptr null, ptr [[TMP9]], align 4 +// CHECK2-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK2-NEXT: store ptr [[B]], ptr [[TMP10]], align 4 +// CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK2-NEXT: store ptr [[B]], ptr [[TMP11]], align 4 +// CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK2-NEXT: store ptr null, ptr [[TMP12]], align 4 +// CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 +// CHECK2-NEXT: store i32 2, ptr [[TMP15]], align 4 +// CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 +// CHECK2-NEXT: store i32 3, ptr [[TMP16]], align 4 +// CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 +// CHECK2-NEXT: store ptr [[TMP13]], ptr [[TMP17]], align 4 +// CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 +// CHECK2-NEXT: store ptr [[TMP14]], ptr [[TMP18]], align 4 +// CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 +// CHECK2-NEXT: store ptr @.offload_sizes.7, ptr [[TMP19]], align 4 +// CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 +// CHECK2-NEXT: store ptr @.offload_maptypes.8, ptr [[TMP20]], align 4 +// CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 +// CHECK2-NEXT: store ptr null, ptr [[TMP21]], align 4 +// CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 +// CHECK2-NEXT: store ptr null, ptr [[TMP22]], align 4 +// CHECK2-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 +// CHECK2-NEXT: store i64 0, ptr [[TMP23]], align 8 +// CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 +// CHECK2-NEXT: store i64 0, ptr [[TMP24]], align 8 +// CHECK2-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 +// CHECK2-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP25]], align 4 +// CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 +// CHECK2-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP26]], align 4 +// CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 +// CHECK2-NEXT: store i32 0, ptr [[TMP27]], align 4 +// CHECK2-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142.region_id, ptr [[KERNEL_ARGS]]) +// CHECK2-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 +// CHECK2-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK2: omp_offload.failed: -// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR3]] // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK2: omp_offload.cont: -// CHECK2-NEXT: [[TMP36:%.*]] = load i32, i32* [[A]], align 4 -// CHECK2-NEXT: ret i32 [[TMP36]] +// CHECK2-NEXT: [[TMP30:%.*]] = load i32, ptr [[A]], align 4 +// CHECK2-NEXT: ret i32 [[TMP30]] // // // CHECK2-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i @@ -8475,169 +8250,158 @@ int bar(int n, double *ptr) { // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x i8*], align 4 -// CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x i8*], align 4 -// CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x i8*], align 4 +// CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x ptr], align 4 +// CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x ptr], align 4 +// CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x ptr], align 4 // CHECK2-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 -// CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK2-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK2-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 -// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK2-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK2-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i32* -// CHECK2-NEXT: store i32 [[TMP1]], i32* [[TMP3]], align 4 -// CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK2-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32* -// CHECK2-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4 -// CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK2-NEXT: store i8* null, i8** [[TMP6]], align 4 -// CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK2-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to [10 x i32]** -// CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP8]], align 4 -// CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK2-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]** -// CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP10]], align 4 -// CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK2-NEXT: store i8* null, i8** [[TMP11]], align 4 -// CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 -// CHECK2-NEXT: store i32 2, i32* [[TMP14]], align 4 -// CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 -// CHECK2-NEXT: store i32 2, i32* [[TMP15]], align 4 -// CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 -// CHECK2-NEXT: store i8** [[TMP12]], i8*** [[TMP16]], align 4 -// CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 -// CHECK2-NEXT: store i8** [[TMP13]], i8*** [[TMP17]], align 4 -// CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 -// CHECK2-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.9, i32 0, i32 0), i64** [[TMP18]], align 4 -// CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 -// CHECK2-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.10, i32 0, i32 0), i64** [[TMP19]], align 4 -// CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 -// CHECK2-NEXT: store i8** null, i8*** [[TMP20]], align 4 -// CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 -// CHECK2-NEXT: store i8** null, i8*** [[TMP21]], align 4 -// CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 -// CHECK2-NEXT: store i64 0, i64* [[TMP22]], align 8 -// CHECK2-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 9 -// CHECK2-NEXT: store i64 0, i64* [[TMP23]], align 8 -// CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 10 -// CHECK2-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP24]], align 4 -// CHECK2-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 11 -// CHECK2-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP25]], align 4 -// CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 12 -// CHECK2-NEXT: store i32 0, i32* [[TMP26]], align 4 -// CHECK2-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) -// CHECK2-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 -// CHECK2-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK2-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// CHECK2-NEXT: store i32 0, ptr [[A]], align 4 +// CHECK2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 +// CHECK2-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 +// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4 +// CHECK2-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK2-NEXT: store i32 [[TMP1]], ptr [[TMP2]], align 4 +// CHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK2-NEXT: store i32 [[TMP1]], ptr [[TMP3]], align 4 +// CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK2-NEXT: store ptr null, ptr [[TMP4]], align 4 +// CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK2-NEXT: store ptr [[B]], ptr [[TMP5]], align 4 +// CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK2-NEXT: store ptr [[B]], ptr [[TMP6]], align 4 +// CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK2-NEXT: store ptr null, ptr [[TMP7]], align 4 +// CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK2-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 +// CHECK2-NEXT: store i32 2, ptr [[TMP10]], align 4 +// CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 +// CHECK2-NEXT: store i32 2, ptr [[TMP11]], align 4 +// CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 +// CHECK2-NEXT: store ptr [[TMP8]], ptr [[TMP12]], align 4 +// CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 +// CHECK2-NEXT: store ptr [[TMP9]], ptr [[TMP13]], align 4 +// CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 +// CHECK2-NEXT: store ptr @.offload_sizes.9, ptr [[TMP14]], align 4 +// CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 +// CHECK2-NEXT: store ptr @.offload_maptypes.10, ptr [[TMP15]], align 4 +// CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 +// CHECK2-NEXT: store ptr null, ptr [[TMP16]], align 4 +// CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 +// CHECK2-NEXT: store ptr null, ptr [[TMP17]], align 4 +// CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 +// CHECK2-NEXT: store i64 0, ptr [[TMP18]], align 8 +// CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 +// CHECK2-NEXT: store i64 0, ptr [[TMP19]], align 8 +// CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 +// CHECK2-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP20]], align 4 +// CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 +// CHECK2-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP21]], align 4 +// CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 +// CHECK2-NEXT: store i32 0, ptr [[TMP22]], align 4 +// CHECK2-NEXT: [[TMP23:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128.region_id, ptr [[KERNEL_ARGS]]) +// CHECK2-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 +// CHECK2-NEXT: br i1 [[TMP24]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK2: omp_offload.failed: -// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128(i32 [[TMP1]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128(i32 [[TMP1]], ptr [[B]]) #[[ATTR3]] // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK2: omp_offload.cont: -// CHECK2-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 4 -// CHECK2-NEXT: ret i32 [[TMP29]] +// CHECK2-NEXT: [[TMP25:%.*]] = load i32, ptr [[A]], align 4 +// CHECK2-NEXT: ret i32 [[TMP25]] // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167 -// CHECK2-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: -// CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 -// CHECK2-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK2-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 +// CHECK2-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4 // CHECK2-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK2-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK2-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK2-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK2-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 -// CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK2-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 -// CHECK2-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave() -// CHECK2-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 4 +// CHECK2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 +// CHECK2-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 +// CHECK2-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 +// CHECK2-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 +// CHECK2-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 +// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 +// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 +// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 +// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 +// CHECK2-NEXT: [[TMP4:%.*]] = call ptr @llvm.stacksave() +// CHECK2-NEXT: store ptr [[TMP4]], ptr [[SAVED_STACK]], align 4 // CHECK2-NEXT: [[TMP5:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] // CHECK2-NEXT: [[VLA3:%.*]] = alloca i16, i32 [[TMP5]], align 2 -// CHECK2-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK2-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 +// CHECK2-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 +// CHECK2-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 4 // CHECK2-NEXT: [[TMP6:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] // CHECK2-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP6]], 2 -// CHECK2-NEXT: [[TMP8:%.*]] = bitcast i16* [[VLA3]] to i8* -// CHECK2-NEXT: [[TMP9:%.*]] = bitcast i16* [[TMP3]] to i8* -// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 2 [[TMP8]], i8* align 2 [[TMP9]], i32 [[TMP7]], i1 false) -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP10]] to double +// CHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 2 [[VLA3]], ptr align 2 [[TMP3]], i32 [[TMP7]], i1 false) +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[B_ADDR]], align 4 +// CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP8]] to double // CHECK2-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK2-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK2-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK2-NEXT: [[TMP11:%.*]] = load double, double* [[A4]], align 4 -// CHECK2-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+00 -// CHECK2-NEXT: store double [[INC]], double* [[A4]], align 4 +// CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK2-NEXT: store double [[ADD]], ptr [[A]], align 4 +// CHECK2-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 +// CHECK2-NEXT: [[TMP9:%.*]] = load double, ptr [[A4]], align 4 +// CHECK2-NEXT: [[INC:%.*]] = fadd double [[TMP9]], 1.000000e+00 +// CHECK2-NEXT: store double [[INC]], ptr [[A4]], align 4 // CHECK2-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 -// CHECK2-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA3]], i32 [[TMP12]] -// CHECK2-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK2-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 -// CHECK2-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK2-NEXT: call void @llvm.stackrestore(i8* [[TMP13]]) +// CHECK2-NEXT: [[TMP10:%.*]] = mul nsw i32 1, [[TMP2]] +// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA3]], i32 [[TMP10]] +// CHECK2-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1 +// CHECK2-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2 +// CHECK2-NEXT: [[TMP11:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 +// CHECK2-NEXT: call void @llvm.stackrestore(ptr [[TMP11]]) // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142 -// CHECK2-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 // CHECK2-NEXT: [[B1:%.*]] = alloca [10 x i32], align 4 -// CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK2-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 -// CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK2-NEXT: [[CONV:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* -// CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK2-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B1]] to i8* -// CHECK2-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8* -// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i32 40, i1 false) -// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK2-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK2-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 1 -// CHECK2-NEXT: [[CONV2:%.*]] = sext i8 [[TMP4]] to i32 -// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 -// CHECK2-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i8 -// CHECK2-NEXT: store i8 [[CONV4]], i8* [[CONV]], align 1 -// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], i32 0, i32 2 -// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK2-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 +// CHECK2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 +// CHECK2-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4 +// CHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 +// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 +// CHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[B1]], ptr align 4 [[TMP0]], i32 40, i1 false) +// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 +// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK2-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 +// CHECK2-NEXT: [[TMP2:%.*]] = load i8, ptr [[AAA_ADDR]], align 1 +// CHECK2-NEXT: [[CONV:%.*]] = sext i8 [[TMP2]] to i32 +// CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 +// CHECK2-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i8 +// CHECK2-NEXT: store i8 [[CONV3]], ptr [[AAA_ADDR]], align 1 +// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B1]], i32 0, i32 2 +// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 +// CHECK2-NEXT: store i32 [[ADD4]], ptr [[ARRAYIDX]], align 4 // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128 -// CHECK2-SAME: (i32 noundef [[A:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK2-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 // CHECK2-NEXT: [[B1:%.*]] = alloca [10 x i32], align 4 -// CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK2-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B1]] to i8* -// CHECK2-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8* -// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i32 40, i1 false) -// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK2-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], i32 0, i32 2 -// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK2-NEXT: store i32 [[ADD2]], i32* [[ARRAYIDX]], align 4 +// CHECK2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 +// CHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 +// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 +// CHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[B1]], ptr align 4 [[TMP0]], i32 40, i1 false) +// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 +// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK2-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 +// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B1]], i32 0, i32 2 +// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 +// CHECK2-NEXT: store i32 [[ADD2]], ptr [[ARRAYIDX]], align 4 // CHECK2-NEXT: ret void // // @@ -8649,586 +8413,532 @@ int bar(int n, double *ptr) { // // // CHECK3-LABEL: define {{[^@]+}}@_Z3fooiPd -// CHECK3-SAME: (i32 noundef [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK3-SAME: (i32 noundef [[N:%.*]], ptr noundef [[PTR:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 4 +// CHECK3-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 // CHECK3-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 // CHECK3-NEXT: [[E:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 4 -// CHECK3-NEXT: [[P:%.*]] = alloca i32*, align 64 +// CHECK3-NEXT: [[P:%.*]] = alloca ptr, align 64 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[GA_CASTED:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 4 +// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 4 +// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 4 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [9 x i8*], align 4 -// CHECK3-NEXT: [[DOTOFFLOAD_PTRS3:%.*]] = alloca [9 x i8*], align 4 -// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [9 x i8*], align 4 +// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [9 x ptr], align 4 +// CHECK3-NEXT: [[DOTOFFLOAD_PTRS3:%.*]] = alloca [9 x ptr], align 4 +// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [9 x ptr], align 4 // CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 4 // CHECK3-NEXT: [[KERNEL_ARGS5:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 -// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS8:%.*]] = alloca [2 x i8*], align 4 -// CHECK3-NEXT: [[DOTOFFLOAD_PTRS9:%.*]] = alloca [2 x i8*], align 4 -// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS10:%.*]] = alloca [2 x i8*], align 4 +// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS8:%.*]] = alloca [2 x ptr], align 4 +// CHECK3-NEXT: [[DOTOFFLOAD_PTRS9:%.*]] = alloca [2 x ptr], align 4 +// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS10:%.*]] = alloca [2 x ptr], align 4 // CHECK3-NEXT: [[KERNEL_ARGS11:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 -// CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK3-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 4 -// CHECK3-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK3-NEXT: store i16 0, i16* [[AA]], align 2 -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK3-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// CHECK3-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 +// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// CHECK3-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 4 +// CHECK3-NEXT: store i32 0, ptr [[A]], align 4 +// CHECK3-NEXT: store i16 0, ptr [[AA]], align 2 +// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// CHECK3-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave() +// CHECK3-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4 // CHECK3-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// CHECK3-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK3-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] // CHECK3-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// CHECK3-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// CHECK3-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK3-NEXT: store i32 [[TMP4]], i32* [[X]], align 4 -// CHECK3-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 1 -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK3-NEXT: store i32 [[TMP5]], i32* [[Y]], align 4 -// CHECK3-NEXT: store i32* [[A]], i32** [[P]], align 64 -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 -// CHECK3-NEXT: store i32 [[TMP6]], i32* [[A_CASTED]], align 4 -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK3-NEXT: [[TMP8:%.*]] = load i32*, i32** [[P]], align 64 -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* @ga, align 4 -// CHECK3-NEXT: store i32 [[TMP9]], i32* [[GA_CASTED]], align 4 -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[GA_CASTED]], align 4 -// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* -// CHECK3-NEXT: store i32 [[TMP7]], i32* [[TMP12]], align 4 -// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* -// CHECK3-NEXT: store i32 [[TMP7]], i32* [[TMP14]], align 4 -// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK3-NEXT: store i8* null, i8** [[TMP15]], align 4 -// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK3-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32** -// CHECK3-NEXT: store i32* [[TMP8]], i32** [[TMP17]], align 4 -// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK3-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32** -// CHECK3-NEXT: store i32* [[TMP8]], i32** [[TMP19]], align 4 -// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK3-NEXT: store i8* null, i8** [[TMP20]], align 4 -// CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK3-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* -// CHECK3-NEXT: store i32 [[TMP10]], i32* [[TMP22]], align 4 -// CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK3-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* -// CHECK3-NEXT: store i32 [[TMP10]], i32* [[TMP24]], align 4 -// CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK3-NEXT: store i8* null, i8** [[TMP25]], align 4 -// CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 -// CHECK3-NEXT: store i32 2, i32* [[TMP28]], align 4 -// CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 -// CHECK3-NEXT: store i32 3, i32* [[TMP29]], align 4 -// CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 -// CHECK3-NEXT: store i8** [[TMP26]], i8*** [[TMP30]], align 4 -// CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 -// CHECK3-NEXT: store i8** [[TMP27]], i8*** [[TMP31]], align 4 -// CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 -// CHECK3-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64** [[TMP32]], align 4 -// CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 -// CHECK3-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i64** [[TMP33]], align 4 -// CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 -// CHECK3-NEXT: store i8** null, i8*** [[TMP34]], align 4 -// CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 -// CHECK3-NEXT: store i8** null, i8*** [[TMP35]], align 4 -// CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 -// CHECK3-NEXT: store i64 0, i64* [[TMP36]], align 8 -// CHECK3-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 9 -// CHECK3-NEXT: store i64 0, i64* [[TMP37]], align 8 -// CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 10 -// CHECK3-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP38]], align 4 -// CHECK3-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 11 -// CHECK3-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP39]], align 4 -// CHECK3-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 12 -// CHECK3-NEXT: store i32 0, i32* [[TMP40]], align 4 -// CHECK3-NEXT: [[TMP41:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) -// CHECK3-NEXT: [[TMP42:%.*]] = icmp ne i32 [[TMP41]], 0 -// CHECK3-NEXT: br i1 [[TMP42]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK3-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 4 +// CHECK3-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// CHECK3-NEXT: store i32 [[TMP4]], ptr [[X]], align 4 +// CHECK3-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 1 +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// CHECK3-NEXT: store i32 [[TMP5]], ptr [[Y]], align 4 +// CHECK3-NEXT: store ptr [[A]], ptr [[P]], align 64 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4 +// CHECK3-NEXT: store i32 [[TMP6]], ptr [[A_CASTED]], align 4 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[A_CASTED]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load ptr, ptr [[P]], align 64 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr @ga, align 4 +// CHECK3-NEXT: store i32 [[TMP9]], ptr [[GA_CASTED]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[GA_CASTED]], align 4 +// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK3-NEXT: store i32 [[TMP7]], ptr [[TMP11]], align 4 +// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK3-NEXT: store i32 [[TMP7]], ptr [[TMP12]], align 4 +// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK3-NEXT: store ptr null, ptr [[TMP13]], align 4 +// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK3-NEXT: store ptr [[TMP8]], ptr [[TMP14]], align 4 +// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK3-NEXT: store ptr [[TMP8]], ptr [[TMP15]], align 4 +// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK3-NEXT: store ptr null, ptr [[TMP16]], align 4 +// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK3-NEXT: store i32 [[TMP10]], ptr [[TMP17]], align 4 +// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK3-NEXT: store i32 [[TMP10]], ptr [[TMP18]], align 4 +// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK3-NEXT: store ptr null, ptr [[TMP19]], align 4 +// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 +// CHECK3-NEXT: store i32 2, ptr [[TMP22]], align 4 +// CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 +// CHECK3-NEXT: store i32 3, ptr [[TMP23]], align 4 +// CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 +// CHECK3-NEXT: store ptr [[TMP20]], ptr [[TMP24]], align 4 +// CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 +// CHECK3-NEXT: store ptr [[TMP21]], ptr [[TMP25]], align 4 +// CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 +// CHECK3-NEXT: store ptr @.offload_sizes, ptr [[TMP26]], align 4 +// CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 +// CHECK3-NEXT: store ptr @.offload_maptypes, ptr [[TMP27]], align 4 +// CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 +// CHECK3-NEXT: store ptr null, ptr [[TMP28]], align 4 +// CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 +// CHECK3-NEXT: store ptr null, ptr [[TMP29]], align 4 +// CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 +// CHECK3-NEXT: store i64 0, ptr [[TMP30]], align 8 +// CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 +// CHECK3-NEXT: store i64 0, ptr [[TMP31]], align 8 +// CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 +// CHECK3-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP32]], align 4 +// CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 +// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP33]], align 4 +// CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 +// CHECK3-NEXT: store i32 0, ptr [[TMP34]], align 4 +// CHECK3-NEXT: [[TMP35:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1:[0-9]+]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63.region_id, ptr [[KERNEL_ARGS]]) +// CHECK3-NEXT: [[TMP36:%.*]] = icmp ne i32 [[TMP35]], 0 +// CHECK3-NEXT: br i1 [[TMP36]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK3: omp_offload.failed: -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63(i32 [[TMP7]], i32* [[TMP8]], i32 [[TMP10]]) #[[ATTR3:[0-9]+]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63(i32 [[TMP7]], ptr [[TMP8]], i32 [[TMP10]]) #[[ATTR3:[0-9]+]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: -// CHECK3-NEXT: [[TMP43:%.*]] = load i16, i16* [[AA]], align 2 -// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* -// CHECK3-NEXT: store i16 [[TMP43]], i16* [[CONV]], align 2 -// CHECK3-NEXT: [[TMP44:%.*]] = load i32, i32* [[AA_CASTED]], align 4 -// CHECK3-NEXT: [[TMP45:%.*]] = mul nuw i32 [[TMP0]], 4 -// CHECK3-NEXT: [[TMP46:%.*]] = sext i32 [[TMP45]] to i64 -// CHECK3-NEXT: [[TMP47:%.*]] = mul nuw i32 5, [[TMP2]] -// CHECK3-NEXT: [[TMP48:%.*]] = mul nuw i32 [[TMP47]], 8 -// CHECK3-NEXT: [[TMP49:%.*]] = sext i32 [[TMP48]] to i64 -// CHECK3-NEXT: [[TMP50:%.*]] = bitcast [9 x i64]* [[DOTOFFLOAD_SIZES]] to i8* -// CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP50]], i8* align 4 bitcast ([9 x i64]* @.offload_sizes.1 to i8*), i32 72, i1 false) -// CHECK3-NEXT: [[TMP51:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i32* -// CHECK3-NEXT: store i32 [[TMP44]], i32* [[TMP52]], align 4 -// CHECK3-NEXT: [[TMP53:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP54:%.*]] = bitcast i8** [[TMP53]] to i32* -// CHECK3-NEXT: store i32 [[TMP44]], i32* [[TMP54]], align 4 -// CHECK3-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 0 -// CHECK3-NEXT: store i8* null, i8** [[TMP55]], align 4 -// CHECK3-NEXT: [[TMP56:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 1 -// CHECK3-NEXT: [[TMP57:%.*]] = bitcast i8** [[TMP56]] to [10 x float]** -// CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP57]], align 4 -// CHECK3-NEXT: [[TMP58:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 1 -// CHECK3-NEXT: [[TMP59:%.*]] = bitcast i8** [[TMP58]] to [10 x float]** -// CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP59]], align 4 -// CHECK3-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 1 -// CHECK3-NEXT: store i8* null, i8** [[TMP60]], align 4 -// CHECK3-NEXT: [[TMP61:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 2 -// CHECK3-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32* -// CHECK3-NEXT: store i32 [[TMP0]], i32* [[TMP62]], align 4 -// CHECK3-NEXT: [[TMP63:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 2 -// CHECK3-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i32* -// CHECK3-NEXT: store i32 [[TMP0]], i32* [[TMP64]], align 4 -// CHECK3-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 2 -// CHECK3-NEXT: store i8* null, i8** [[TMP65]], align 4 -// CHECK3-NEXT: [[TMP66:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 3 -// CHECK3-NEXT: [[TMP67:%.*]] = bitcast i8** [[TMP66]] to float** -// CHECK3-NEXT: store float* [[VLA]], float** [[TMP67]], align 4 -// CHECK3-NEXT: [[TMP68:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 3 -// CHECK3-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to float** -// CHECK3-NEXT: store float* [[VLA]], float** [[TMP69]], align 4 -// CHECK3-NEXT: [[TMP70:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 -// CHECK3-NEXT: store i64 [[TMP46]], i64* [[TMP70]], align 4 -// CHECK3-NEXT: [[TMP71:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 3 -// CHECK3-NEXT: store i8* null, i8** [[TMP71]], align 4 -// CHECK3-NEXT: [[TMP72:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 4 -// CHECK3-NEXT: [[TMP73:%.*]] = bitcast i8** [[TMP72]] to [5 x [10 x double]]** -// CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP73]], align 4 -// CHECK3-NEXT: [[TMP74:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 4 -// CHECK3-NEXT: [[TMP75:%.*]] = bitcast i8** [[TMP74]] to [5 x [10 x double]]** -// CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP75]], align 4 -// CHECK3-NEXT: [[TMP76:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 4 -// CHECK3-NEXT: store i8* null, i8** [[TMP76]], align 4 -// CHECK3-NEXT: [[TMP77:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 5 -// CHECK3-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i32* -// CHECK3-NEXT: store i32 5, i32* [[TMP78]], align 4 -// CHECK3-NEXT: [[TMP79:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 5 -// CHECK3-NEXT: [[TMP80:%.*]] = bitcast i8** [[TMP79]] to i32* -// CHECK3-NEXT: store i32 5, i32* [[TMP80]], align 4 -// CHECK3-NEXT: [[TMP81:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 5 -// CHECK3-NEXT: store i8* null, i8** [[TMP81]], align 4 -// CHECK3-NEXT: [[TMP82:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 6 -// CHECK3-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i32* -// CHECK3-NEXT: store i32 [[TMP2]], i32* [[TMP83]], align 4 -// CHECK3-NEXT: [[TMP84:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 6 -// CHECK3-NEXT: [[TMP85:%.*]] = bitcast i8** [[TMP84]] to i32* -// CHECK3-NEXT: store i32 [[TMP2]], i32* [[TMP85]], align 4 -// CHECK3-NEXT: [[TMP86:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 6 -// CHECK3-NEXT: store i8* null, i8** [[TMP86]], align 4 -// CHECK3-NEXT: [[TMP87:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 7 -// CHECK3-NEXT: [[TMP88:%.*]] = bitcast i8** [[TMP87]] to double** -// CHECK3-NEXT: store double* [[VLA1]], double** [[TMP88]], align 4 -// CHECK3-NEXT: [[TMP89:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 7 -// CHECK3-NEXT: [[TMP90:%.*]] = bitcast i8** [[TMP89]] to double** -// CHECK3-NEXT: store double* [[VLA1]], double** [[TMP90]], align 4 -// CHECK3-NEXT: [[TMP91:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 -// CHECK3-NEXT: store i64 [[TMP49]], i64* [[TMP91]], align 4 -// CHECK3-NEXT: [[TMP92:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 7 -// CHECK3-NEXT: store i8* null, i8** [[TMP92]], align 4 -// CHECK3-NEXT: [[TMP93:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 8 -// CHECK3-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to %struct.TT** -// CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP94]], align 4 -// CHECK3-NEXT: [[TMP95:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 8 -// CHECK3-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to %struct.TT** -// CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP96]], align 4 -// CHECK3-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 8 -// CHECK3-NEXT: store i8* null, i8** [[TMP97]], align 4 -// CHECK3-NEXT: [[TMP98:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP100:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP101:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 0 -// CHECK3-NEXT: store i32 2, i32* [[TMP101]], align 4 -// CHECK3-NEXT: [[TMP102:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 1 -// CHECK3-NEXT: store i32 9, i32* [[TMP102]], align 4 -// CHECK3-NEXT: [[TMP103:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 2 -// CHECK3-NEXT: store i8** [[TMP98]], i8*** [[TMP103]], align 4 -// CHECK3-NEXT: [[TMP104:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 3 -// CHECK3-NEXT: store i8** [[TMP99]], i8*** [[TMP104]], align 4 -// CHECK3-NEXT: [[TMP105:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 4 -// CHECK3-NEXT: store i64* [[TMP100]], i64** [[TMP105]], align 4 -// CHECK3-NEXT: [[TMP106:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 5 -// CHECK3-NEXT: store i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.2, i32 0, i32 0), i64** [[TMP106]], align 4 -// CHECK3-NEXT: [[TMP107:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 6 -// CHECK3-NEXT: store i8** null, i8*** [[TMP107]], align 4 -// CHECK3-NEXT: [[TMP108:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 7 -// CHECK3-NEXT: store i8** null, i8*** [[TMP108]], align 4 -// CHECK3-NEXT: [[TMP109:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 8 -// CHECK3-NEXT: store i64 0, i64* [[TMP109]], align 8 -// CHECK3-NEXT: [[TMP110:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 9 -// CHECK3-NEXT: store i64 0, i64* [[TMP110]], align 8 -// CHECK3-NEXT: [[TMP111:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 10 -// CHECK3-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP111]], align 4 -// CHECK3-NEXT: [[TMP112:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 11 -// CHECK3-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP112]], align 4 -// CHECK3-NEXT: [[TMP113:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 12 -// CHECK3-NEXT: store i32 0, i32* [[TMP113]], align 4 -// CHECK3-NEXT: [[TMP114:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]]) -// CHECK3-NEXT: [[TMP115:%.*]] = icmp ne i32 [[TMP114]], 0 -// CHECK3-NEXT: br i1 [[TMP115]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] +// CHECK3-NEXT: [[TMP37:%.*]] = load i16, ptr [[AA]], align 2 +// CHECK3-NEXT: store i16 [[TMP37]], ptr [[AA_CASTED]], align 2 +// CHECK3-NEXT: [[TMP38:%.*]] = load i32, ptr [[AA_CASTED]], align 4 +// CHECK3-NEXT: [[TMP39:%.*]] = mul nuw i32 [[TMP0]], 4 +// CHECK3-NEXT: [[TMP40:%.*]] = sext i32 [[TMP39]] to i64 +// CHECK3-NEXT: [[TMP41:%.*]] = mul nuw i32 5, [[TMP2]] +// CHECK3-NEXT: [[TMP42:%.*]] = mul nuw i32 [[TMP41]], 8 +// CHECK3-NEXT: [[TMP43:%.*]] = sext i32 [[TMP42]] to i64 +// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes.1, i32 72, i1 false) +// CHECK3-NEXT: [[TMP44:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 +// CHECK3-NEXT: store i32 [[TMP38]], ptr [[TMP44]], align 4 +// CHECK3-NEXT: [[TMP45:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 +// CHECK3-NEXT: store i32 [[TMP38]], ptr [[TMP45]], align 4 +// CHECK3-NEXT: [[TMP46:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 0 +// CHECK3-NEXT: store ptr null, ptr [[TMP46]], align 4 +// CHECK3-NEXT: [[TMP47:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 1 +// CHECK3-NEXT: store ptr [[B]], ptr [[TMP47]], align 4 +// CHECK3-NEXT: [[TMP48:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 1 +// CHECK3-NEXT: store ptr [[B]], ptr [[TMP48]], align 4 +// CHECK3-NEXT: [[TMP49:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 1 +// CHECK3-NEXT: store ptr null, ptr [[TMP49]], align 4 +// CHECK3-NEXT: [[TMP50:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 2 +// CHECK3-NEXT: store i32 [[TMP0]], ptr [[TMP50]], align 4 +// CHECK3-NEXT: [[TMP51:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 2 +// CHECK3-NEXT: store i32 [[TMP0]], ptr [[TMP51]], align 4 +// CHECK3-NEXT: [[TMP52:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 2 +// CHECK3-NEXT: store ptr null, ptr [[TMP52]], align 4 +// CHECK3-NEXT: [[TMP53:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 3 +// CHECK3-NEXT: store ptr [[VLA]], ptr [[TMP53]], align 4 +// CHECK3-NEXT: [[TMP54:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 3 +// CHECK3-NEXT: store ptr [[VLA]], ptr [[TMP54]], align 4 +// CHECK3-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 3 +// CHECK3-NEXT: store i64 [[TMP40]], ptr [[TMP55]], align 4 +// CHECK3-NEXT: [[TMP56:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 3 +// CHECK3-NEXT: store ptr null, ptr [[TMP56]], align 4 +// CHECK3-NEXT: [[TMP57:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 4 +// CHECK3-NEXT: store ptr [[C]], ptr [[TMP57]], align 4 +// CHECK3-NEXT: [[TMP58:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 4 +// CHECK3-NEXT: store ptr [[C]], ptr [[TMP58]], align 4 +// CHECK3-NEXT: [[TMP59:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 4 +// CHECK3-NEXT: store ptr null, ptr [[TMP59]], align 4 +// CHECK3-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 5 +// CHECK3-NEXT: store i32 5, ptr [[TMP60]], align 4 +// CHECK3-NEXT: [[TMP61:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 5 +// CHECK3-NEXT: store i32 5, ptr [[TMP61]], align 4 +// CHECK3-NEXT: [[TMP62:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 5 +// CHECK3-NEXT: store ptr null, ptr [[TMP62]], align 4 +// CHECK3-NEXT: [[TMP63:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 6 +// CHECK3-NEXT: store i32 [[TMP2]], ptr [[TMP63]], align 4 +// CHECK3-NEXT: [[TMP64:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 6 +// CHECK3-NEXT: store i32 [[TMP2]], ptr [[TMP64]], align 4 +// CHECK3-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 6 +// CHECK3-NEXT: store ptr null, ptr [[TMP65]], align 4 +// CHECK3-NEXT: [[TMP66:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 7 +// CHECK3-NEXT: store ptr [[VLA1]], ptr [[TMP66]], align 4 +// CHECK3-NEXT: [[TMP67:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 7 +// CHECK3-NEXT: store ptr [[VLA1]], ptr [[TMP67]], align 4 +// CHECK3-NEXT: [[TMP68:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 7 +// CHECK3-NEXT: store i64 [[TMP43]], ptr [[TMP68]], align 4 +// CHECK3-NEXT: [[TMP69:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 7 +// CHECK3-NEXT: store ptr null, ptr [[TMP69]], align 4 +// CHECK3-NEXT: [[TMP70:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 8 +// CHECK3-NEXT: store ptr [[D]], ptr [[TMP70]], align 4 +// CHECK3-NEXT: [[TMP71:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 8 +// CHECK3-NEXT: store ptr [[D]], ptr [[TMP71]], align 4 +// CHECK3-NEXT: [[TMP72:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 8 +// CHECK3-NEXT: store ptr null, ptr [[TMP72]], align 4 +// CHECK3-NEXT: [[TMP73:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP74:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP75:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP76:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 0 +// CHECK3-NEXT: store i32 2, ptr [[TMP76]], align 4 +// CHECK3-NEXT: [[TMP77:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 1 +// CHECK3-NEXT: store i32 9, ptr [[TMP77]], align 4 +// CHECK3-NEXT: [[TMP78:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 2 +// CHECK3-NEXT: store ptr [[TMP73]], ptr [[TMP78]], align 4 +// CHECK3-NEXT: [[TMP79:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 3 +// CHECK3-NEXT: store ptr [[TMP74]], ptr [[TMP79]], align 4 +// CHECK3-NEXT: [[TMP80:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 4 +// CHECK3-NEXT: store ptr [[TMP75]], ptr [[TMP80]], align 4 +// CHECK3-NEXT: [[TMP81:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 5 +// CHECK3-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP81]], align 4 +// CHECK3-NEXT: [[TMP82:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 6 +// CHECK3-NEXT: store ptr null, ptr [[TMP82]], align 4 +// CHECK3-NEXT: [[TMP83:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 7 +// CHECK3-NEXT: store ptr null, ptr [[TMP83]], align 4 +// CHECK3-NEXT: [[TMP84:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 8 +// CHECK3-NEXT: store i64 0, ptr [[TMP84]], align 8 +// CHECK3-NEXT: [[TMP85:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 9 +// CHECK3-NEXT: store i64 0, ptr [[TMP85]], align 8 +// CHECK3-NEXT: [[TMP86:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 10 +// CHECK3-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP86]], align 4 +// CHECK3-NEXT: [[TMP87:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 11 +// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP87]], align 4 +// CHECK3-NEXT: [[TMP88:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 12 +// CHECK3-NEXT: store i32 0, ptr [[TMP88]], align 4 +// CHECK3-NEXT: [[TMP89:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70.region_id, ptr [[KERNEL_ARGS5]]) +// CHECK3-NEXT: [[TMP90:%.*]] = icmp ne i32 [[TMP89]], 0 +// CHECK3-NEXT: br i1 [[TMP90]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] // CHECK3: omp_offload.failed6: -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70(i32 [[TMP44]], [10 x float]* [[B]], i32 [[TMP0]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP2]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70(i32 [[TMP38]], ptr [[B]], i32 [[TMP0]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP2]], ptr [[VLA1]], ptr [[D]]) #[[ATTR3]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT7]] // CHECK3: omp_offload.cont7: -// CHECK3-NEXT: [[TMP116:%.*]] = load double*, double** [[PTR_ADDR]], align 4 -// CHECK3-NEXT: [[TMP117:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP118:%.*]] = bitcast i8** [[TMP117]] to double** -// CHECK3-NEXT: store double* [[TMP116]], double** [[TMP118]], align 4 -// CHECK3-NEXT: [[TMP119:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS9]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to double** -// CHECK3-NEXT: store double* [[TMP116]], double** [[TMP120]], align 4 -// CHECK3-NEXT: [[TMP121:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS10]], i32 0, i32 0 -// CHECK3-NEXT: store i8* null, i8** [[TMP121]], align 4 -// CHECK3-NEXT: [[TMP122:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 1 -// CHECK3-NEXT: [[TMP123:%.*]] = bitcast i8** [[TMP122]] to %struct.TT.0** -// CHECK3-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[TMP123]], align 4 -// CHECK3-NEXT: [[TMP124:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS9]], i32 0, i32 1 -// CHECK3-NEXT: [[TMP125:%.*]] = bitcast i8** [[TMP124]] to %struct.TT.0** -// CHECK3-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[TMP125]], align 4 -// CHECK3-NEXT: [[TMP126:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS10]], i32 0, i32 1 -// CHECK3-NEXT: store i8* null, i8** [[TMP126]], align 4 -// CHECK3-NEXT: [[TMP127:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP128:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS9]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP129:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 0 -// CHECK3-NEXT: store i32 2, i32* [[TMP129]], align 4 -// CHECK3-NEXT: [[TMP130:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 1 -// CHECK3-NEXT: store i32 2, i32* [[TMP130]], align 4 -// CHECK3-NEXT: [[TMP131:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 2 -// CHECK3-NEXT: store i8** [[TMP127]], i8*** [[TMP131]], align 4 -// CHECK3-NEXT: [[TMP132:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 3 -// CHECK3-NEXT: store i8** [[TMP128]], i8*** [[TMP132]], align 4 -// CHECK3-NEXT: [[TMP133:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 4 -// CHECK3-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.3, i32 0, i32 0), i64** [[TMP133]], align 4 -// CHECK3-NEXT: [[TMP134:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 5 -// CHECK3-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.4, i32 0, i32 0), i64** [[TMP134]], align 4 -// CHECK3-NEXT: [[TMP135:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 6 -// CHECK3-NEXT: store i8** null, i8*** [[TMP135]], align 4 -// CHECK3-NEXT: [[TMP136:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 7 -// CHECK3-NEXT: store i8** null, i8*** [[TMP136]], align 4 -// CHECK3-NEXT: [[TMP137:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 8 -// CHECK3-NEXT: store i64 0, i64* [[TMP137]], align 8 -// CHECK3-NEXT: [[TMP138:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 9 -// CHECK3-NEXT: store i64 0, i64* [[TMP138]], align 8 -// CHECK3-NEXT: [[TMP139:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 10 -// CHECK3-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP139]], align 4 -// CHECK3-NEXT: [[TMP140:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 11 -// CHECK3-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP140]], align 4 -// CHECK3-NEXT: [[TMP141:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 12 -// CHECK3-NEXT: store i32 0, i32* [[TMP141]], align 4 -// CHECK3-NEXT: [[TMP142:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]]) -// CHECK3-NEXT: [[TMP143:%.*]] = icmp ne i32 [[TMP142]], 0 -// CHECK3-NEXT: br i1 [[TMP143]], label [[OMP_OFFLOAD_FAILED12:%.*]], label [[OMP_OFFLOAD_CONT13:%.*]] +// CHECK3-NEXT: [[TMP91:%.*]] = load ptr, ptr [[PTR_ADDR]], align 4 +// CHECK3-NEXT: [[TMP92:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 0 +// CHECK3-NEXT: store ptr [[TMP91]], ptr [[TMP92]], align 4 +// CHECK3-NEXT: [[TMP93:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS9]], i32 0, i32 0 +// CHECK3-NEXT: store ptr [[TMP91]], ptr [[TMP93]], align 4 +// CHECK3-NEXT: [[TMP94:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS10]], i32 0, i32 0 +// CHECK3-NEXT: store ptr null, ptr [[TMP94]], align 4 +// CHECK3-NEXT: [[TMP95:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 1 +// CHECK3-NEXT: store ptr [[E]], ptr [[TMP95]], align 4 +// CHECK3-NEXT: [[TMP96:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS9]], i32 0, i32 1 +// CHECK3-NEXT: store ptr [[E]], ptr [[TMP96]], align 4 +// CHECK3-NEXT: [[TMP97:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS10]], i32 0, i32 1 +// CHECK3-NEXT: store ptr null, ptr [[TMP97]], align 4 +// CHECK3-NEXT: [[TMP98:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP99:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS9]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP100:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 0 +// CHECK3-NEXT: store i32 2, ptr [[TMP100]], align 4 +// CHECK3-NEXT: [[TMP101:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 1 +// CHECK3-NEXT: store i32 2, ptr [[TMP101]], align 4 +// CHECK3-NEXT: [[TMP102:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 2 +// CHECK3-NEXT: store ptr [[TMP98]], ptr [[TMP102]], align 4 +// CHECK3-NEXT: [[TMP103:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 3 +// CHECK3-NEXT: store ptr [[TMP99]], ptr [[TMP103]], align 4 +// CHECK3-NEXT: [[TMP104:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 4 +// CHECK3-NEXT: store ptr @.offload_sizes.3, ptr [[TMP104]], align 4 +// CHECK3-NEXT: [[TMP105:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 5 +// CHECK3-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP105]], align 4 +// CHECK3-NEXT: [[TMP106:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 6 +// CHECK3-NEXT: store ptr null, ptr [[TMP106]], align 4 +// CHECK3-NEXT: [[TMP107:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 7 +// CHECK3-NEXT: store ptr null, ptr [[TMP107]], align 4 +// CHECK3-NEXT: [[TMP108:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 8 +// CHECK3-NEXT: store i64 0, ptr [[TMP108]], align 8 +// CHECK3-NEXT: [[TMP109:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 9 +// CHECK3-NEXT: store i64 0, ptr [[TMP109]], align 8 +// CHECK3-NEXT: [[TMP110:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 10 +// CHECK3-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP110]], align 4 +// CHECK3-NEXT: [[TMP111:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 11 +// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP111]], align 4 +// CHECK3-NEXT: [[TMP112:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS11]], i32 0, i32 12 +// CHECK3-NEXT: store i32 0, ptr [[TMP112]], align 4 +// CHECK3-NEXT: [[TMP113:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111.region_id, ptr [[KERNEL_ARGS11]]) +// CHECK3-NEXT: [[TMP114:%.*]] = icmp ne i32 [[TMP113]], 0 +// CHECK3-NEXT: br i1 [[TMP114]], label [[OMP_OFFLOAD_FAILED12:%.*]], label [[OMP_OFFLOAD_CONT13:%.*]] // CHECK3: omp_offload.failed12: -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111(double* [[TMP116]], %struct.TT.0* [[E]]) #[[ATTR3]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111(ptr [[TMP91]], ptr [[E]]) #[[ATTR3]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT13]] // CHECK3: omp_offload.cont13: -// CHECK3-NEXT: [[TMP144:%.*]] = load i32, i32* [[A]], align 4 -// CHECK3-NEXT: [[TMP145:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK3-NEXT: call void @llvm.stackrestore(i8* [[TMP145]]) -// CHECK3-NEXT: ret i32 [[TMP144]] +// CHECK3-NEXT: [[TMP115:%.*]] = load i32, ptr [[A]], align 4 +// CHECK3-NEXT: [[TMP116:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 +// CHECK3-NEXT: call void @llvm.stackrestore(ptr [[TMP116]]) +// CHECK3-NEXT: ret i32 [[TMP115]] // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63 -// CHECK3-SAME: (i32 noundef [[A:%.*]], i32* noundef [[P:%.*]], i32 noundef [[GA:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK3-SAME: (i32 noundef [[A:%.*]], ptr noundef [[P:%.*]], i32 noundef [[GA:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[P_ADDR:%.*]] = alloca i32*, align 4 +// CHECK3-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[GA_ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK3-NEXT: store i32* [[P]], i32** [[P_ADDR]], align 4 -// CHECK3-NEXT: store i32 [[GA]], i32* [[GA_ADDR]], align 4 +// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 +// CHECK3-NEXT: store ptr [[P]], ptr [[P_ADDR]], align 4 +// CHECK3-NEXT: store i32 [[GA]], ptr [[GA_ADDR]], align 4 // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70 -// CHECK3-SAME: (i32 noundef [[AA:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 -// CHECK3-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// CHECK3-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 4 +// CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 -// CHECK3-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// CHECK3-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 4 +// CHECK3-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[B5:%.*]] = alloca [10 x float], align 4 -// CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[C7:%.*]] = alloca [5 x [10 x double]], align 8 // CHECK3-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[__VLA_EXPR2:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[D9:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 -// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 -// CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK3-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 -// CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 -// CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK3-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 -// CHECK3-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 -// CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 -// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// CHECK3-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 -// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 -// CHECK3-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 -// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 -// CHECK3-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 -// CHECK3-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 -// CHECK3-NEXT: [[TMP8:%.*]] = bitcast [10 x float]* [[B5]] to i8* -// CHECK3-NEXT: [[TMP9:%.*]] = bitcast [10 x float]* [[TMP0]] to i8* -// CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i32 40, i1 false) -// CHECK3-NEXT: [[TMP10:%.*]] = call i8* @llvm.stacksave() -// CHECK3-NEXT: store i8* [[TMP10]], i8** [[SAVED_STACK]], align 4 +// CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 +// CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 +// CHECK3-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 +// CHECK3-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 4 +// CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 +// CHECK3-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 +// CHECK3-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4 +// CHECK3-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4 +// CHECK3-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 +// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4 +// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4 +// CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4 +// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[B5]], ptr align 4 [[TMP0]], i32 40, i1 false) +// CHECK3-NEXT: [[TMP8:%.*]] = call ptr @llvm.stacksave() +// CHECK3-NEXT: store ptr [[TMP8]], ptr [[SAVED_STACK]], align 4 // CHECK3-NEXT: [[VLA6:%.*]] = alloca float, i32 [[TMP1]], align 4 -// CHECK3-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK3-NEXT: [[TMP11:%.*]] = mul nuw i32 [[TMP1]], 4 -// CHECK3-NEXT: [[TMP12:%.*]] = bitcast float* [[VLA6]] to i8* -// CHECK3-NEXT: [[TMP13:%.*]] = bitcast float* [[TMP2]] to i8* -// CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 [[TMP11]], i1 false) -// CHECK3-NEXT: [[TMP14:%.*]] = bitcast [5 x [10 x double]]* [[C7]] to i8* -// CHECK3-NEXT: [[TMP15:%.*]] = bitcast [5 x [10 x double]]* [[TMP3]] to i8* -// CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 [[TMP14]], i8* align 8 [[TMP15]], i32 400, i1 false) -// CHECK3-NEXT: [[TMP16:%.*]] = mul nuw i32 [[TMP4]], [[TMP5]] -// CHECK3-NEXT: [[VLA8:%.*]] = alloca double, i32 [[TMP16]], align 8 -// CHECK3-NEXT: store i32 [[TMP4]], i32* [[__VLA_EXPR1]], align 4 -// CHECK3-NEXT: store i32 [[TMP5]], i32* [[__VLA_EXPR2]], align 4 -// CHECK3-NEXT: [[TMP17:%.*]] = mul nuw i32 [[TMP4]], [[TMP5]] -// CHECK3-NEXT: [[TMP18:%.*]] = mul nuw i32 [[TMP17]], 8 -// CHECK3-NEXT: [[TMP19:%.*]] = bitcast double* [[VLA8]] to i8* -// CHECK3-NEXT: [[TMP20:%.*]] = bitcast double* [[TMP6]] to i8* -// CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 [[TMP19]], i8* align 8 [[TMP20]], i32 [[TMP18]], i1 false) -// CHECK3-NEXT: [[TMP21:%.*]] = bitcast %struct.TT* [[D9]] to i8* -// CHECK3-NEXT: [[TMP22:%.*]] = bitcast %struct.TT* [[TMP7]] to i8* -// CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP21]], i8* align 4 [[TMP22]], i32 12, i1 false) -// CHECK3-NEXT: [[TMP23:%.*]] = load i16, i16* [[CONV]], align 2 -// CHECK3-NEXT: [[CONV10:%.*]] = sext i16 [[TMP23]] to i32 -// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV10]], 1 -// CHECK3-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD]] to i16 -// CHECK3-NEXT: store i16 [[CONV11]], i16* [[CONV]], align 2 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B5]], i32 0, i32 2 -// CHECK3-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4 -// CHECK3-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA6]], i32 3 -// CHECK3-NEXT: store float 1.000000e+00, float* [[ARRAYIDX12]], align 4 -// CHECK3-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C7]], i32 0, i32 1 -// CHECK3-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], i32 0, i32 2 -// CHECK3-NEXT: store double 1.000000e+00, double* [[ARRAYIDX14]], align 8 -// CHECK3-NEXT: [[TMP24:%.*]] = mul nsw i32 1, [[TMP5]] -// CHECK3-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[VLA8]], i32 [[TMP24]] -// CHECK3-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i32 3 -// CHECK3-NEXT: store double 1.000000e+00, double* [[ARRAYIDX16]], align 8 -// CHECK3-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 0 -// CHECK3-NEXT: store i64 1, i64* [[X]], align 4 -// CHECK3-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 1 -// CHECK3-NEXT: store i8 1, i8* [[Y]], align 4 -// CHECK3-NEXT: [[TMP25:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK3-NEXT: call void @llvm.stackrestore(i8* [[TMP25]]) +// CHECK3-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 +// CHECK3-NEXT: [[TMP9:%.*]] = mul nuw i32 [[TMP1]], 4 +// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VLA6]], ptr align 4 [[TMP2]], i32 [[TMP9]], i1 false) +// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[C7]], ptr align 8 [[TMP3]], i32 400, i1 false) +// CHECK3-NEXT: [[TMP10:%.*]] = mul nuw i32 [[TMP4]], [[TMP5]] +// CHECK3-NEXT: [[VLA8:%.*]] = alloca double, i32 [[TMP10]], align 8 +// CHECK3-NEXT: store i32 [[TMP4]], ptr [[__VLA_EXPR1]], align 4 +// CHECK3-NEXT: store i32 [[TMP5]], ptr [[__VLA_EXPR2]], align 4 +// CHECK3-NEXT: [[TMP11:%.*]] = mul nuw i32 [[TMP4]], [[TMP5]] +// CHECK3-NEXT: [[TMP12:%.*]] = mul nuw i32 [[TMP11]], 8 +// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[VLA8]], ptr align 8 [[TMP6]], i32 [[TMP12]], i1 false) +// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[D9]], ptr align 4 [[TMP7]], i32 12, i1 false) +// CHECK3-NEXT: [[TMP13:%.*]] = load i16, ptr [[AA_ADDR]], align 2 +// CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP13]] to i32 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 +// CHECK3-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16 +// CHECK3-NEXT: store i16 [[CONV10]], ptr [[AA_ADDR]], align 2 +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B5]], i32 0, i32 2 +// CHECK3-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX]], align 4 +// CHECK3-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds float, ptr [[VLA6]], i32 3 +// CHECK3-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX11]], align 4 +// CHECK3-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C7]], i32 0, i32 1 +// CHECK3-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX12]], i32 0, i32 2 +// CHECK3-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX13]], align 8 +// CHECK3-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP5]] +// CHECK3-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, ptr [[VLA8]], i32 [[TMP14]] +// CHECK3-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX14]], i32 3 +// CHECK3-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX15]], align 8 +// CHECK3-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D9]], i32 0, i32 0 +// CHECK3-NEXT: store i64 1, ptr [[X]], align 4 +// CHECK3-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D9]], i32 0, i32 1 +// CHECK3-NEXT: store i8 1, ptr [[Y]], align 4 +// CHECK3-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 +// CHECK3-NEXT: call void @llvm.stackrestore(ptr [[TMP15]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111 -// CHECK3-SAME: (double* noundef [[PTR:%.*]], %struct.TT.0* noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (ptr noundef [[PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: -// CHECK3-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 4 -// CHECK3-NEXT: [[E_ADDR:%.*]] = alloca %struct.TT.0*, align 4 +// CHECK3-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 4 +// CHECK3-NEXT: [[E_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[E1:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 4 -// CHECK3-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 4 -// CHECK3-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[E_ADDR]], align 4 -// CHECK3-NEXT: [[TMP0:%.*]] = load %struct.TT.0*, %struct.TT.0** [[E_ADDR]], align 4 -// CHECK3-NEXT: [[TMP1:%.*]] = bitcast %struct.TT.0* [[E1]] to i8* -// CHECK3-NEXT: [[TMP2:%.*]] = bitcast %struct.TT.0* [[TMP0]] to i8* -// CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i32 8, i1 false) -// CHECK3-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E1]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[X]], align 4 -// CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP3]] to double -// CHECK3-NEXT: [[TMP4:%.*]] = load double*, double** [[PTR_ADDR]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP4]], i32 0 -// CHECK3-NEXT: store double [[CONV]], double* [[ARRAYIDX]], align 4 -// CHECK3-NEXT: [[TMP5:%.*]] = load double*, double** [[PTR_ADDR]], align 4 -// CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds double, double* [[TMP5]], i32 0 -// CHECK3-NEXT: [[TMP6:%.*]] = load double, double* [[ARRAYIDX2]], align 4 -// CHECK3-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// CHECK3-NEXT: store double [[INC]], double* [[ARRAYIDX2]], align 4 +// CHECK3-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 4 +// CHECK3-NEXT: store ptr [[E]], ptr [[E_ADDR]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[E_ADDR]], align 4 +// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[E1]], ptr align 4 [[TMP0]], i32 8, i1 false) +// CHECK3-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], ptr [[E1]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[X]], align 4 +// CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double +// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[PTR_ADDR]], align 4 +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[TMP2]], i32 0 +// CHECK3-NEXT: store double [[CONV]], ptr [[ARRAYIDX]], align 4 +// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[PTR_ADDR]], align 4 +// CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds double, ptr [[TMP3]], i32 0 +// CHECK3-NEXT: [[TMP4:%.*]] = load double, ptr [[ARRAYIDX2]], align 4 +// CHECK3-NEXT: [[INC:%.*]] = fadd double [[TMP4]], 1.000000e+00 +// CHECK3-NEXT: store double [[INC]], ptr [[ARRAYIDX2]], align 4 // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@_Z3bariPd -// CHECK3-SAME: (i32 noundef [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0]] { +// CHECK3-SAME: (i32 noundef [[N:%.*]], ptr noundef [[PTR:%.*]]) #[[ATTR0]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 4 +// CHECK3-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK3-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 4 -// CHECK3-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK3-NEXT: [[TMP1:%.*]] = load double*, double** [[PTR_ADDR]], align 4 -// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooiPd(i32 noundef [[TMP0]], double* noundef [[TMP1]]) -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 +// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// CHECK3-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 4 +// CHECK3-NEXT: store i32 0, ptr [[A]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[PTR_ADDR]], align 4 +// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooiPd(i32 noundef [[TMP0]], ptr noundef [[TMP1]]) +// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CALL]] -// CHECK3-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK3-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP3]]) -// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 +// CHECK3-NEXT: store i32 [[ADD]], ptr [[A]], align 4 +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// CHECK3-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP3]]) +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 4 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], [[CALL1]] -// CHECK3-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK3-NEXT: store i32 [[ADD2]], ptr [[A]], align 4 +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK3-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP5]]) -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], [[CALL3]] -// CHECK3-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK3-NEXT: store i32 [[ADD4]], ptr [[A]], align 4 +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK3-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP7]]) -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP8]], [[CALL5]] -// CHECK3-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 +// CHECK3-NEXT: store i32 [[ADD6]], ptr [[A]], align 4 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[A]], align 4 // CHECK3-NEXT: ret i32 [[TMP9]] // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// CHECK3-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK3-NEXT: entry: -// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[B:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 -// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 +// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 4 +// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 4 +// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 4 // CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 -// CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 +// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// CHECK3-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// CHECK3-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// CHECK3-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 +// CHECK3-NEXT: store i32 [[ADD]], ptr [[B]], align 4 +// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() +// CHECK3-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] // CHECK3-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// CHECK3-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 -// CHECK3-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 -// CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 +// CHECK3-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[B]], align 4 +// CHECK3-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4 +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4 +// CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK3-NEXT: [[TMP6:%.*]] = mul nuw i32 2, [[TMP1]] // CHECK3-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP6]], 2 // CHECK3-NEXT: [[TMP8:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK3-NEXT: [[TMP9:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* -// CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP9]], i8* align 4 bitcast ([5 x i64]* @.offload_sizes.5 to i8*), i32 40, i1 false) -// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1** -// CHECK3-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 4 -// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double** -// CHECK3-NEXT: store double* [[A]], double** [[TMP13]], align 4 -// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK3-NEXT: store i8* null, i8** [[TMP14]], align 4 -// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK3-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* -// CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP16]], align 4 -// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK3-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* -// CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4 -// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK3-NEXT: store i8* null, i8** [[TMP19]], align 4 -// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK3-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32* -// CHECK3-NEXT: store i32 2, i32* [[TMP21]], align 4 -// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK3-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* -// CHECK3-NEXT: store i32 2, i32* [[TMP23]], align 4 -// CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK3-NEXT: store i8* null, i8** [[TMP24]], align 4 -// CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 -// CHECK3-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* -// CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP26]], align 4 -// CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 -// CHECK3-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* -// CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP28]], align 4 -// CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 -// CHECK3-NEXT: store i8* null, i8** [[TMP29]], align 4 -// CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 -// CHECK3-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i16** -// CHECK3-NEXT: store i16* [[VLA]], i16** [[TMP31]], align 4 -// CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 -// CHECK3-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i16** -// CHECK3-NEXT: store i16* [[VLA]], i16** [[TMP33]], align 4 -// CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 -// CHECK3-NEXT: store i64 [[TMP8]], i64* [[TMP34]], align 4 -// CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 -// CHECK3-NEXT: store i8* null, i8** [[TMP35]], align 4 -// CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 -// CHECK3-NEXT: store i32 2, i32* [[TMP39]], align 4 -// CHECK3-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 -// CHECK3-NEXT: store i32 5, i32* [[TMP40]], align 4 -// CHECK3-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 -// CHECK3-NEXT: store i8** [[TMP36]], i8*** [[TMP41]], align 4 -// CHECK3-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 -// CHECK3-NEXT: store i8** [[TMP37]], i8*** [[TMP42]], align 4 -// CHECK3-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 -// CHECK3-NEXT: store i64* [[TMP38]], i64** [[TMP43]], align 4 -// CHECK3-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 -// CHECK3-NEXT: store i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.6, i32 0, i32 0), i64** [[TMP44]], align 4 -// CHECK3-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 -// CHECK3-NEXT: store i8** null, i8*** [[TMP45]], align 4 -// CHECK3-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 -// CHECK3-NEXT: store i8** null, i8*** [[TMP46]], align 4 -// CHECK3-NEXT: [[TMP47:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 -// CHECK3-NEXT: store i64 0, i64* [[TMP47]], align 8 -// CHECK3-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 9 -// CHECK3-NEXT: store i64 0, i64* [[TMP48]], align 8 -// CHECK3-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 10 -// CHECK3-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP49]], align 4 -// CHECK3-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 11 -// CHECK3-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP50]], align 4 -// CHECK3-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 12 -// CHECK3-NEXT: store i32 0, i32* [[TMP51]], align 4 -// CHECK3-NEXT: [[TMP52:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) -// CHECK3-NEXT: [[TMP53:%.*]] = icmp ne i32 [[TMP52]], 0 -// CHECK3-NEXT: br i1 [[TMP53]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes.5, i32 40, i1 false) +// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK3-NEXT: store ptr [[THIS1]], ptr [[TMP9]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK3-NEXT: store ptr [[A]], ptr [[TMP10]], align 4 +// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK3-NEXT: store ptr null, ptr [[TMP11]], align 4 +// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK3-NEXT: store i32 [[TMP5]], ptr [[TMP12]], align 4 +// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK3-NEXT: store i32 [[TMP5]], ptr [[TMP13]], align 4 +// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK3-NEXT: store ptr null, ptr [[TMP14]], align 4 +// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK3-NEXT: store i32 2, ptr [[TMP15]], align 4 +// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK3-NEXT: store i32 2, ptr [[TMP16]], align 4 +// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK3-NEXT: store ptr null, ptr [[TMP17]], align 4 +// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 +// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP18]], align 4 +// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 +// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP19]], align 4 +// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 +// CHECK3-NEXT: store ptr null, ptr [[TMP20]], align 4 +// CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 +// CHECK3-NEXT: store ptr [[VLA]], ptr [[TMP21]], align 4 +// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4 +// CHECK3-NEXT: store ptr [[VLA]], ptr [[TMP22]], align 4 +// CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 4 +// CHECK3-NEXT: store i64 [[TMP8]], ptr [[TMP23]], align 4 +// CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 +// CHECK3-NEXT: store ptr null, ptr [[TMP24]], align 4 +// CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 +// CHECK3-NEXT: store i32 2, ptr [[TMP28]], align 4 +// CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 +// CHECK3-NEXT: store i32 5, ptr [[TMP29]], align 4 +// CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 +// CHECK3-NEXT: store ptr [[TMP25]], ptr [[TMP30]], align 4 +// CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 +// CHECK3-NEXT: store ptr [[TMP26]], ptr [[TMP31]], align 4 +// CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 +// CHECK3-NEXT: store ptr [[TMP27]], ptr [[TMP32]], align 4 +// CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 +// CHECK3-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP33]], align 4 +// CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 +// CHECK3-NEXT: store ptr null, ptr [[TMP34]], align 4 +// CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 +// CHECK3-NEXT: store ptr null, ptr [[TMP35]], align 4 +// CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 +// CHECK3-NEXT: store i64 0, ptr [[TMP36]], align 8 +// CHECK3-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 +// CHECK3-NEXT: store i64 0, ptr [[TMP37]], align 8 +// CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 +// CHECK3-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP38]], align 4 +// CHECK3-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 +// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP39]], align 4 +// CHECK3-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 +// CHECK3-NEXT: store i32 0, ptr [[TMP40]], align 4 +// CHECK3-NEXT: [[TMP41:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167.region_id, ptr [[KERNEL_ARGS]]) +// CHECK3-NEXT: [[TMP42:%.*]] = icmp ne i32 [[TMP41]], 0 +// CHECK3-NEXT: br i1 [[TMP42]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK3: omp_offload.failed: -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167(ptr [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: -// CHECK3-NEXT: [[TMP54:%.*]] = mul nsw i32 1, [[TMP1]] -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP54]] -// CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK3-NEXT: [[TMP55:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 -// CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP55]] to i32 -// CHECK3-NEXT: [[TMP56:%.*]] = load i32, i32* [[B]], align 4 -// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP56]] -// CHECK3-NEXT: [[TMP57:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK3-NEXT: call void @llvm.stackrestore(i8* [[TMP57]]) +// CHECK3-NEXT: [[TMP43:%.*]] = mul nsw i32 1, [[TMP1]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP43]] +// CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1 +// CHECK3-NEXT: [[TMP44:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2 +// CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP44]] to i32 +// CHECK3-NEXT: [[TMP45:%.*]] = load i32, ptr [[B]], align 4 +// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP45]] +// CHECK3-NEXT: [[TMP46:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 +// CHECK3-NEXT: call void @llvm.stackrestore(ptr [[TMP46]]) // CHECK3-NEXT: ret i32 [[ADD3]] // // @@ -9241,81 +8951,74 @@ int bar(int n, double *ptr) { // CHECK3-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 -// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 +// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 4 +// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 4 +// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 4 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 -// CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK3-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK3-NEXT: store i8 0, i8* [[AAA]], align 1 -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 -// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK3-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1 -// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* -// CHECK3-NEXT: store i8 [[TMP2]], i8* [[CONV]], align 1 -// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 -// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32* -// CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4 -// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* -// CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP7]], align 4 -// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK3-NEXT: store i8* null, i8** [[TMP8]], align 4 -// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* -// CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 -// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK3-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* -// CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4 -// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK3-NEXT: store i8* null, i8** [[TMP13]], align 4 -// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 -// CHECK3-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [10 x i32]** -// CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP15]], align 4 -// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 -// CHECK3-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [10 x i32]** -// CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP17]], align 4 -// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 -// CHECK3-NEXT: store i8* null, i8** [[TMP18]], align 4 -// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 -// CHECK3-NEXT: store i32 2, i32* [[TMP21]], align 4 -// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 -// CHECK3-NEXT: store i32 3, i32* [[TMP22]], align 4 -// CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 -// CHECK3-NEXT: store i8** [[TMP19]], i8*** [[TMP23]], align 4 -// CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 -// CHECK3-NEXT: store i8** [[TMP20]], i8*** [[TMP24]], align 4 -// CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 -// CHECK3-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.7, i32 0, i32 0), i64** [[TMP25]], align 4 -// CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 -// CHECK3-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.8, i32 0, i32 0), i64** [[TMP26]], align 4 -// CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 -// CHECK3-NEXT: store i8** null, i8*** [[TMP27]], align 4 -// CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 -// CHECK3-NEXT: store i8** null, i8*** [[TMP28]], align 4 -// CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 -// CHECK3-NEXT: store i64 0, i64* [[TMP29]], align 8 -// CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 9 -// CHECK3-NEXT: store i64 0, i64* [[TMP30]], align 8 -// CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 10 -// CHECK3-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP31]], align 4 -// CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 11 -// CHECK3-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP32]], align 4 -// CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 12 -// CHECK3-NEXT: store i32 0, i32* [[TMP33]], align 4 -// CHECK3-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) -// CHECK3-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 -// CHECK3-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// CHECK3-NEXT: store i32 0, ptr [[A]], align 4 +// CHECK3-NEXT: store i8 0, ptr [[AAA]], align 1 +// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 +// CHECK3-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 +// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load i8, ptr [[AAA]], align 1 +// CHECK3-NEXT: store i8 [[TMP2]], ptr [[AAA_CASTED]], align 1 +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[AAA_CASTED]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP4]], align 4 +// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP5]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK3-NEXT: store ptr null, ptr [[TMP6]], align 4 +// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP7]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP8]], align 4 +// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK3-NEXT: store ptr null, ptr [[TMP9]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 +// CHECK3-NEXT: store ptr [[B]], ptr [[TMP10]], align 4 +// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 +// CHECK3-NEXT: store ptr [[B]], ptr [[TMP11]], align 4 +// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 +// CHECK3-NEXT: store ptr null, ptr [[TMP12]], align 4 +// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 +// CHECK3-NEXT: store i32 2, ptr [[TMP15]], align 4 +// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 +// CHECK3-NEXT: store i32 3, ptr [[TMP16]], align 4 +// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 +// CHECK3-NEXT: store ptr [[TMP13]], ptr [[TMP17]], align 4 +// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 +// CHECK3-NEXT: store ptr [[TMP14]], ptr [[TMP18]], align 4 +// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 +// CHECK3-NEXT: store ptr @.offload_sizes.7, ptr [[TMP19]], align 4 +// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 +// CHECK3-NEXT: store ptr @.offload_maptypes.8, ptr [[TMP20]], align 4 +// CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 +// CHECK3-NEXT: store ptr null, ptr [[TMP21]], align 4 +// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 +// CHECK3-NEXT: store ptr null, ptr [[TMP22]], align 4 +// CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 +// CHECK3-NEXT: store i64 0, ptr [[TMP23]], align 8 +// CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 +// CHECK3-NEXT: store i64 0, ptr [[TMP24]], align 8 +// CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 +// CHECK3-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP25]], align 4 +// CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 +// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP26]], align 4 +// CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 +// CHECK3-NEXT: store i32 0, ptr [[TMP27]], align 4 +// CHECK3-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142.region_id, ptr [[KERNEL_ARGS]]) +// CHECK3-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 +// CHECK3-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK3: omp_offload.failed: -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR3]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: -// CHECK3-NEXT: [[TMP36:%.*]] = load i32, i32* [[A]], align 4 -// CHECK3-NEXT: ret i32 [[TMP36]] +// CHECK3-NEXT: [[TMP30:%.*]] = load i32, ptr [[A]], align 4 +// CHECK3-NEXT: ret i32 [[TMP30]] // // // CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i @@ -9325,169 +9028,158 @@ int bar(int n, double *ptr) { // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x i8*], align 4 -// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x i8*], align 4 -// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x i8*], align 4 +// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x ptr], align 4 +// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x ptr], align 4 +// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x ptr], align 4 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 -// CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// CHECK3-NEXT: store i32 0, i32* [[A]], align 4 -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 -// CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 -// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 -// CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i32* -// CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP3]], align 4 -// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32* -// CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4 -// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 -// CHECK3-NEXT: store i8* null, i8** [[TMP6]], align 4 -// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 -// CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to [10 x i32]** -// CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP8]], align 4 -// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 -// CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]** -// CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP10]], align 4 -// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 -// CHECK3-NEXT: store i8* null, i8** [[TMP11]], align 4 -// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 -// CHECK3-NEXT: store i32 2, i32* [[TMP14]], align 4 -// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 -// CHECK3-NEXT: store i32 2, i32* [[TMP15]], align 4 -// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 -// CHECK3-NEXT: store i8** [[TMP12]], i8*** [[TMP16]], align 4 -// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 -// CHECK3-NEXT: store i8** [[TMP13]], i8*** [[TMP17]], align 4 -// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 -// CHECK3-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.9, i32 0, i32 0), i64** [[TMP18]], align 4 -// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 -// CHECK3-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.10, i32 0, i32 0), i64** [[TMP19]], align 4 -// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 -// CHECK3-NEXT: store i8** null, i8*** [[TMP20]], align 4 -// CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 -// CHECK3-NEXT: store i8** null, i8*** [[TMP21]], align 4 -// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 -// CHECK3-NEXT: store i64 0, i64* [[TMP22]], align 8 -// CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 9 -// CHECK3-NEXT: store i64 0, i64* [[TMP23]], align 8 -// CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 10 -// CHECK3-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP24]], align 4 -// CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 11 -// CHECK3-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP25]], align 4 -// CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 12 -// CHECK3-NEXT: store i32 0, i32* [[TMP26]], align 4 -// CHECK3-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) -// CHECK3-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 -// CHECK3-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] +// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// CHECK3-NEXT: store i32 0, ptr [[A]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 +// CHECK3-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 +// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP2]], align 4 +// CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP3]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 +// CHECK3-NEXT: store ptr null, ptr [[TMP4]], align 4 +// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 +// CHECK3-NEXT: store ptr [[B]], ptr [[TMP5]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 +// CHECK3-NEXT: store ptr [[B]], ptr [[TMP6]], align 4 +// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 +// CHECK3-NEXT: store ptr null, ptr [[TMP7]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 +// CHECK3-NEXT: store i32 2, ptr [[TMP10]], align 4 +// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 +// CHECK3-NEXT: store i32 2, ptr [[TMP11]], align 4 +// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 +// CHECK3-NEXT: store ptr [[TMP8]], ptr [[TMP12]], align 4 +// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 +// CHECK3-NEXT: store ptr [[TMP9]], ptr [[TMP13]], align 4 +// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 +// CHECK3-NEXT: store ptr @.offload_sizes.9, ptr [[TMP14]], align 4 +// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 +// CHECK3-NEXT: store ptr @.offload_maptypes.10, ptr [[TMP15]], align 4 +// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 +// CHECK3-NEXT: store ptr null, ptr [[TMP16]], align 4 +// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 +// CHECK3-NEXT: store ptr null, ptr [[TMP17]], align 4 +// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 +// CHECK3-NEXT: store i64 0, ptr [[TMP18]], align 8 +// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 +// CHECK3-NEXT: store i64 0, ptr [[TMP19]], align 8 +// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 +// CHECK3-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP20]], align 4 +// CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 +// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP21]], align 4 +// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 +// CHECK3-NEXT: store i32 0, ptr [[TMP22]], align 4 +// CHECK3-NEXT: [[TMP23:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128.region_id, ptr [[KERNEL_ARGS]]) +// CHECK3-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 +// CHECK3-NEXT: br i1 [[TMP24]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK3: omp_offload.failed: -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128(i32 [[TMP1]], [10 x i32]* [[B]]) #[[ATTR3]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128(i32 [[TMP1]], ptr [[B]]) #[[ATTR3]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: -// CHECK3-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 4 -// CHECK3-NEXT: ret i32 [[TMP29]] +// CHECK3-NEXT: [[TMP25:%.*]] = load i32, ptr [[A]], align 4 +// CHECK3-NEXT: ret i32 [[TMP25]] // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167 -// CHECK3-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: -// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 -// CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 +// CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// CHECK3-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 -// CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// CHECK3-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 -// CHECK3-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave() -// CHECK3-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 4 +// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 +// CHECK3-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 +// CHECK3-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 +// CHECK3-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 +// CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 +// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 +// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = call ptr @llvm.stacksave() +// CHECK3-NEXT: store ptr [[TMP4]], ptr [[SAVED_STACK]], align 4 // CHECK3-NEXT: [[TMP5:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] // CHECK3-NEXT: [[VLA3:%.*]] = alloca i16, i32 [[TMP5]], align 2 -// CHECK3-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// CHECK3-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 +// CHECK3-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 +// CHECK3-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 4 // CHECK3-NEXT: [[TMP6:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] // CHECK3-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP6]], 2 -// CHECK3-NEXT: [[TMP8:%.*]] = bitcast i16* [[VLA3]] to i8* -// CHECK3-NEXT: [[TMP9:%.*]] = bitcast i16* [[TMP3]] to i8* -// CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 2 [[TMP8]], i8* align 2 [[TMP9]], i32 [[TMP7]], i1 false) -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP10]] to double +// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 2 [[VLA3]], ptr align 2 [[TMP3]], i32 [[TMP7]], i1 false) +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[B_ADDR]], align 4 +// CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP8]] to double // CHECK3-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK3-NEXT: store double [[ADD]], double* [[A]], align 4 -// CHECK3-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP11:%.*]] = load double, double* [[A4]], align 4 -// CHECK3-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+00 -// CHECK3-NEXT: store double [[INC]], double* [[A4]], align 4 +// CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK3-NEXT: store double [[ADD]], ptr [[A]], align 4 +// CHECK3-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP9:%.*]] = load double, ptr [[A4]], align 4 +// CHECK3-NEXT: [[INC:%.*]] = fadd double [[TMP9]], 1.000000e+00 +// CHECK3-NEXT: store double [[INC]], ptr [[A4]], align 4 // CHECK3-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 -// CHECK3-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP2]] -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA3]], i32 [[TMP12]] -// CHECK3-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// CHECK3-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 -// CHECK3-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// CHECK3-NEXT: call void @llvm.stackrestore(i8* [[TMP13]]) +// CHECK3-NEXT: [[TMP10:%.*]] = mul nsw i32 1, [[TMP2]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA3]], i32 [[TMP10]] +// CHECK3-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1 +// CHECK3-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2 +// CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 +// CHECK3-NEXT: call void @llvm.stackrestore(ptr [[TMP11]]) // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142 -// CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[B1:%.*]] = alloca [10 x i32], align 4 -// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK3-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 -// CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* -// CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK3-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B1]] to i8* -// CHECK3-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8* -// CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i32 40, i1 false) -// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK3-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 1 -// CHECK3-NEXT: [[CONV2:%.*]] = sext i8 [[TMP4]] to i32 -// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 -// CHECK3-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i8 -// CHECK3-NEXT: store i8 [[CONV4]], i8* [[CONV]], align 1 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], i32 0, i32 2 -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP5]], 1 -// CHECK3-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 +// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 +// CHECK3-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4 +// CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 +// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[B1]], ptr align 4 [[TMP0]], i32 40, i1 false) +// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK3-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load i8, ptr [[AAA_ADDR]], align 1 +// CHECK3-NEXT: [[CONV:%.*]] = sext i8 [[TMP2]] to i32 +// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 +// CHECK3-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i8 +// CHECK3-NEXT: store i8 [[CONV3]], ptr [[AAA_ADDR]], align 1 +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B1]], i32 0, i32 2 +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 +// CHECK3-NEXT: store i32 [[ADD4]], ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: ret void // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128 -// CHECK3-SAME: (i32 noundef [[A:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { +// CHECK3-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[B1:%.*]] = alloca [10 x i32], align 4 -// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// CHECK3-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B1]] to i8* -// CHECK3-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8* -// CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i32 40, i1 false) -// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 -// CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], i32 0, i32 2 -// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], 1 -// CHECK3-NEXT: store i32 [[ADD2]], i32* [[ARRAYIDX]], align 4 +// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 +// CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 +// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[B1]], ptr align 4 [[TMP0]], i32 40, i1 false) +// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// CHECK3-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B1]], i32 0, i32 2 +// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 +// CHECK3-NEXT: store i32 [[ADD2]], ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: ret void // // @@ -9499,158 +9191,158 @@ int bar(int n, double *ptr) { // // // SIMD-ONLY0-LABEL: define {{[^@]+}}@_Z3fooiPd -// SIMD-ONLY0-SAME: (i32 noundef signext [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0:[0-9]+]] { +// SIMD-ONLY0-SAME: (i32 noundef signext [[N:%.*]], ptr noundef [[PTR:%.*]]) #[[ATTR0:[0-9]+]] { // SIMD-ONLY0-NEXT: entry: // SIMD-ONLY0-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// SIMD-ONLY0-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 8 +// SIMD-ONLY0-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY0-NEXT: [[A:%.*]] = alloca i32, align 4 // SIMD-ONLY0-NEXT: [[AA:%.*]] = alloca i16, align 2 // SIMD-ONLY0-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// SIMD-ONLY0-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// SIMD-ONLY0-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 // SIMD-ONLY0-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 // SIMD-ONLY0-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 // SIMD-ONLY0-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 // SIMD-ONLY0-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 // SIMD-ONLY0-NEXT: [[E:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 4 -// SIMD-ONLY0-NEXT: [[P:%.*]] = alloca i32*, align 64 -// SIMD-ONLY0-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// SIMD-ONLY0-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 8 -// SIMD-ONLY0-NEXT: store i32 0, i32* [[A]], align 4 -// SIMD-ONLY0-NEXT: store i16 0, i16* [[AA]], align 2 -// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// SIMD-ONLY0-NEXT: [[P:%.*]] = alloca ptr, align 64 +// SIMD-ONLY0-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// SIMD-ONLY0-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 8 +// SIMD-ONLY0-NEXT: store i32 0, ptr [[A]], align 4 +// SIMD-ONLY0-NEXT: store i16 0, ptr [[AA]], align 2 +// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY0-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// SIMD-ONLY0-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// SIMD-ONLY0-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 +// SIMD-ONLY0-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() +// SIMD-ONLY0-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // SIMD-ONLY0-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// SIMD-ONLY0-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// SIMD-ONLY0-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// SIMD-ONLY0-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 +// SIMD-ONLY0-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY0-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 // SIMD-ONLY0-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] // SIMD-ONLY0-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// SIMD-ONLY0-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// SIMD-ONLY0-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 0 -// SIMD-ONLY0-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// SIMD-ONLY0-NEXT: store i32 [[TMP6]], i32* [[X]], align 4 -// SIMD-ONLY0-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 1 -// SIMD-ONLY0-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// SIMD-ONLY0-NEXT: store i32 [[TMP7]], i32* [[Y]], align 4 -// SIMD-ONLY0-NEXT: store i32* [[A]], i32** [[P]], align 64 -// SIMD-ONLY0-NEXT: [[TMP8:%.*]] = load i16, i16* [[AA]], align 2 +// SIMD-ONLY0-NEXT: store i64 [[TMP4]], ptr [[__VLA_EXPR1]], align 8 +// SIMD-ONLY0-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 0 +// SIMD-ONLY0-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// SIMD-ONLY0-NEXT: store i32 [[TMP6]], ptr [[X]], align 4 +// SIMD-ONLY0-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 1 +// SIMD-ONLY0-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// SIMD-ONLY0-NEXT: store i32 [[TMP7]], ptr [[Y]], align 4 +// SIMD-ONLY0-NEXT: store ptr [[A]], ptr [[P]], align 64 +// SIMD-ONLY0-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA]], align 2 // SIMD-ONLY0-NEXT: [[CONV:%.*]] = sext i16 [[TMP8]] to i32 // SIMD-ONLY0-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 // SIMD-ONLY0-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 -// SIMD-ONLY0-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// SIMD-ONLY0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 -// SIMD-ONLY0-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4 -// SIMD-ONLY0-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 -// SIMD-ONLY0-NEXT: store float 1.000000e+00, float* [[ARRAYIDX3]], align 4 -// SIMD-ONLY0-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// SIMD-ONLY0-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX4]], i64 0, i64 2 -// SIMD-ONLY0-NEXT: store double 1.000000e+00, double* [[ARRAYIDX5]], align 8 +// SIMD-ONLY0-NEXT: store i16 [[CONV2]], ptr [[AA]], align 2 +// SIMD-ONLY0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], i64 0, i64 2 +// SIMD-ONLY0-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX]], align 4 +// SIMD-ONLY0-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[VLA]], i64 3 +// SIMD-ONLY0-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX3]], align 4 +// SIMD-ONLY0-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C]], i64 0, i64 1 +// SIMD-ONLY0-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX4]], i64 0, i64 2 +// SIMD-ONLY0-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX5]], align 8 // SIMD-ONLY0-NEXT: [[TMP9:%.*]] = mul nsw i64 1, [[TMP4]] -// SIMD-ONLY0-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP9]] -// SIMD-ONLY0-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX6]], i64 3 -// SIMD-ONLY0-NEXT: store double 1.000000e+00, double* [[ARRAYIDX7]], align 8 -// SIMD-ONLY0-NEXT: [[X8:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// SIMD-ONLY0-NEXT: store i64 1, i64* [[X8]], align 8 -// SIMD-ONLY0-NEXT: [[Y9:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// SIMD-ONLY0-NEXT: store i8 1, i8* [[Y9]], align 8 -// SIMD-ONLY0-NEXT: [[X10:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 0 -// SIMD-ONLY0-NEXT: [[TMP10:%.*]] = load i32, i32* [[X10]], align 4 +// SIMD-ONLY0-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds double, ptr [[VLA1]], i64 [[TMP9]] +// SIMD-ONLY0-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX6]], i64 3 +// SIMD-ONLY0-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX7]], align 8 +// SIMD-ONLY0-NEXT: [[X8:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D]], i32 0, i32 0 +// SIMD-ONLY0-NEXT: store i64 1, ptr [[X8]], align 8 +// SIMD-ONLY0-NEXT: [[Y9:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D]], i32 0, i32 1 +// SIMD-ONLY0-NEXT: store i8 1, ptr [[Y9]], align 8 +// SIMD-ONLY0-NEXT: [[X10:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 0 +// SIMD-ONLY0-NEXT: [[TMP10:%.*]] = load i32, ptr [[X10]], align 4 // SIMD-ONLY0-NEXT: [[CONV11:%.*]] = sitofp i32 [[TMP10]] to double -// SIMD-ONLY0-NEXT: [[TMP11:%.*]] = load double*, double** [[PTR_ADDR]], align 8 -// SIMD-ONLY0-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds double, double* [[TMP11]], i64 0 -// SIMD-ONLY0-NEXT: store double [[CONV11]], double* [[ARRAYIDX12]], align 8 -// SIMD-ONLY0-NEXT: [[TMP12:%.*]] = load double*, double** [[PTR_ADDR]], align 8 -// SIMD-ONLY0-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds double, double* [[TMP12]], i64 0 -// SIMD-ONLY0-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX13]], align 8 +// SIMD-ONLY0-NEXT: [[TMP11:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8 +// SIMD-ONLY0-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds double, ptr [[TMP11]], i64 0 +// SIMD-ONLY0-NEXT: store double [[CONV11]], ptr [[ARRAYIDX12]], align 8 +// SIMD-ONLY0-NEXT: [[TMP12:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8 +// SIMD-ONLY0-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds double, ptr [[TMP12]], i64 0 +// SIMD-ONLY0-NEXT: [[TMP13:%.*]] = load double, ptr [[ARRAYIDX13]], align 8 // SIMD-ONLY0-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// SIMD-ONLY0-NEXT: store double [[INC]], double* [[ARRAYIDX13]], align 8 -// SIMD-ONLY0-NEXT: [[TMP14:%.*]] = load i32, i32* [[A]], align 4 -// SIMD-ONLY0-NEXT: [[TMP15:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// SIMD-ONLY0-NEXT: call void @llvm.stackrestore(i8* [[TMP15]]) +// SIMD-ONLY0-NEXT: store double [[INC]], ptr [[ARRAYIDX13]], align 8 +// SIMD-ONLY0-NEXT: [[TMP14:%.*]] = load i32, ptr [[A]], align 4 +// SIMD-ONLY0-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 +// SIMD-ONLY0-NEXT: call void @llvm.stackrestore(ptr [[TMP15]]) // SIMD-ONLY0-NEXT: ret i32 [[TMP14]] // // // SIMD-ONLY0-LABEL: define {{[^@]+}}@_Z3bariPd -// SIMD-ONLY0-SAME: (i32 noundef signext [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0]] { +// SIMD-ONLY0-SAME: (i32 noundef signext [[N:%.*]], ptr noundef [[PTR:%.*]]) #[[ATTR0]] { // SIMD-ONLY0-NEXT: entry: // SIMD-ONLY0-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// SIMD-ONLY0-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 8 +// SIMD-ONLY0-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY0-NEXT: [[A:%.*]] = alloca i32, align 4 // SIMD-ONLY0-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// SIMD-ONLY0-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// SIMD-ONLY0-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 8 -// SIMD-ONLY0-NEXT: store i32 0, i32* [[A]], align 4 -// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load double*, double** [[PTR_ADDR]], align 8 -// SIMD-ONLY0-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooiPd(i32 noundef signext [[TMP0]], double* noundef [[TMP1]]) -// SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY0-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// SIMD-ONLY0-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 8 +// SIMD-ONLY0-NEXT: store i32 0, ptr [[A]], align 4 +// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8 +// SIMD-ONLY0-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooiPd(i32 noundef signext [[TMP0]], ptr noundef [[TMP1]]) +// SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY0-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CALL]] -// SIMD-ONLY0-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// SIMD-ONLY0-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// SIMD-ONLY0-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP3]]) -// SIMD-ONLY0-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY0-NEXT: store i32 [[ADD]], ptr [[A]], align 4 +// SIMD-ONLY0-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// SIMD-ONLY0-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(ptr noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP3]]) +// SIMD-ONLY0-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY0-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], [[CALL1]] -// SIMD-ONLY0-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// SIMD-ONLY0-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// SIMD-ONLY0-NEXT: store i32 [[ADD2]], ptr [[A]], align 4 +// SIMD-ONLY0-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY0-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP5]]) -// SIMD-ONLY0-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY0-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY0-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], [[CALL3]] -// SIMD-ONLY0-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// SIMD-ONLY0-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// SIMD-ONLY0-NEXT: store i32 [[ADD4]], ptr [[A]], align 4 +// SIMD-ONLY0-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY0-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP7]]) -// SIMD-ONLY0-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY0-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY0-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP8]], [[CALL5]] -// SIMD-ONLY0-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// SIMD-ONLY0-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY0-NEXT: store i32 [[ADD6]], ptr [[A]], align 4 +// SIMD-ONLY0-NEXT: [[TMP9:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY0-NEXT: ret i32 [[TMP9]] // // // SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// SIMD-ONLY0-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// SIMD-ONLY0-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // SIMD-ONLY0-NEXT: entry: -// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY0-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // SIMD-ONLY0-NEXT: [[B:%.*]] = alloca i32, align 4 -// SIMD-ONLY0-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// SIMD-ONLY0-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 // SIMD-ONLY0-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// SIMD-ONLY0-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// SIMD-ONLY0-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY0-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY0-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// SIMD-ONLY0-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// SIMD-ONLY0-NEXT: store i32 [[ADD]], ptr [[B]], align 4 +// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY0-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// SIMD-ONLY0-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// SIMD-ONLY0-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 +// SIMD-ONLY0-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave() +// SIMD-ONLY0-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8 // SIMD-ONLY0-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] // SIMD-ONLY0-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// SIMD-ONLY0-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// SIMD-ONLY0-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 +// SIMD-ONLY0-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 +// SIMD-ONLY0-NEXT: [[TMP5:%.*]] = load i32, ptr [[B]], align 4 // SIMD-ONLY0-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double // SIMD-ONLY0-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// SIMD-ONLY0-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// SIMD-ONLY0-NEXT: store double [[ADD2]], double* [[A]], align 8 -// SIMD-ONLY0-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// SIMD-ONLY0-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 8 +// SIMD-ONLY0-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0 +// SIMD-ONLY0-NEXT: store double [[ADD2]], ptr [[A]], align 8 +// SIMD-ONLY0-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[THIS1]], i32 0, i32 0 +// SIMD-ONLY0-NEXT: [[TMP6:%.*]] = load double, ptr [[A3]], align 8 // SIMD-ONLY0-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// SIMD-ONLY0-NEXT: store double [[INC]], double* [[A3]], align 8 +// SIMD-ONLY0-NEXT: store double [[INC]], ptr [[A3]], align 8 // SIMD-ONLY0-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 // SIMD-ONLY0-NEXT: [[TMP7:%.*]] = mul nsw i64 1, [[TMP2]] -// SIMD-ONLY0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP7]] -// SIMD-ONLY0-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// SIMD-ONLY0-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 +// SIMD-ONLY0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP7]] +// SIMD-ONLY0-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1 +// SIMD-ONLY0-NEXT: store i16 [[CONV4]], ptr [[ARRAYIDX5]], align 2 // SIMD-ONLY0-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] -// SIMD-ONLY0-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] -// SIMD-ONLY0-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1 -// SIMD-ONLY0-NEXT: [[TMP9:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 +// SIMD-ONLY0-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP8]] +// SIMD-ONLY0-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX6]], i64 1 +// SIMD-ONLY0-NEXT: [[TMP9:%.*]] = load i16, ptr [[ARRAYIDX7]], align 2 // SIMD-ONLY0-NEXT: [[CONV8:%.*]] = sext i16 [[TMP9]] to i32 -// SIMD-ONLY0-NEXT: [[TMP10:%.*]] = load i32, i32* [[B]], align 4 +// SIMD-ONLY0-NEXT: [[TMP10:%.*]] = load i32, ptr [[B]], align 4 // SIMD-ONLY0-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP10]] -// SIMD-ONLY0-NEXT: [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// SIMD-ONLY0-NEXT: call void @llvm.stackrestore(i8* [[TMP11]]) +// SIMD-ONLY0-NEXT: [[TMP11:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 +// SIMD-ONLY0-NEXT: call void @llvm.stackrestore(ptr [[TMP11]]) // SIMD-ONLY0-NEXT: ret i32 [[ADD9]] // // @@ -9661,22 +9353,22 @@ int bar(int n, double *ptr) { // SIMD-ONLY0-NEXT: [[A:%.*]] = alloca i32, align 4 // SIMD-ONLY0-NEXT: [[AAA:%.*]] = alloca i8, align 1 // SIMD-ONLY0-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// SIMD-ONLY0-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// SIMD-ONLY0-NEXT: store i32 0, i32* [[A]], align 4 -// SIMD-ONLY0-NEXT: store i8 0, i8* [[AAA]], align 1 -// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY0-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// SIMD-ONLY0-NEXT: store i32 0, ptr [[A]], align 4 +// SIMD-ONLY0-NEXT: store i8 0, ptr [[AAA]], align 1 +// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY0-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// SIMD-ONLY0-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load i8, i8* [[AAA]], align 1 +// SIMD-ONLY0-NEXT: store i32 [[ADD]], ptr [[A]], align 4 +// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load i8, ptr [[AAA]], align 1 // SIMD-ONLY0-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32 // SIMD-ONLY0-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 // SIMD-ONLY0-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i8 -// SIMD-ONLY0-NEXT: store i8 [[CONV2]], i8* [[AAA]], align 1 -// SIMD-ONLY0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// SIMD-ONLY0-NEXT: store i8 [[CONV2]], ptr [[AAA]], align 1 +// SIMD-ONLY0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i64 0, i64 2 +// SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // SIMD-ONLY0-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// SIMD-ONLY0-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// SIMD-ONLY0-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY0-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4 +// SIMD-ONLY0-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY0-NEXT: ret i32 [[TMP3]] // // @@ -9686,172 +9378,172 @@ int bar(int n, double *ptr) { // SIMD-ONLY0-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // SIMD-ONLY0-NEXT: [[A:%.*]] = alloca i32, align 4 // SIMD-ONLY0-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// SIMD-ONLY0-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// SIMD-ONLY0-NEXT: store i32 0, i32* [[A]], align 4 -// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY0-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// SIMD-ONLY0-NEXT: store i32 0, ptr [[A]], align 4 +// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY0-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// SIMD-ONLY0-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// SIMD-ONLY0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// SIMD-ONLY0-NEXT: store i32 [[ADD]], ptr [[A]], align 4 +// SIMD-ONLY0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i64 0, i64 2 +// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // SIMD-ONLY0-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP1]], 1 -// SIMD-ONLY0-NEXT: store i32 [[ADD1]], i32* [[ARRAYIDX]], align 4 -// SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY0-NEXT: store i32 [[ADD1]], ptr [[ARRAYIDX]], align 4 +// SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY0-NEXT: ret i32 [[TMP2]] // // // SIMD-ONLY01-LABEL: define {{[^@]+}}@_Z3fooiPd -// SIMD-ONLY01-SAME: (i32 noundef signext [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0:[0-9]+]] { +// SIMD-ONLY01-SAME: (i32 noundef signext [[N:%.*]], ptr noundef [[PTR:%.*]]) #[[ATTR0:[0-9]+]] { // SIMD-ONLY01-NEXT: entry: // SIMD-ONLY01-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// SIMD-ONLY01-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 8 +// SIMD-ONLY01-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY01-NEXT: [[A:%.*]] = alloca i32, align 4 // SIMD-ONLY01-NEXT: [[AA:%.*]] = alloca i16, align 2 // SIMD-ONLY01-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// SIMD-ONLY01-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// SIMD-ONLY01-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 // SIMD-ONLY01-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 // SIMD-ONLY01-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 // SIMD-ONLY01-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 // SIMD-ONLY01-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 // SIMD-ONLY01-NEXT: [[E:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 4 -// SIMD-ONLY01-NEXT: [[P:%.*]] = alloca i32*, align 64 -// SIMD-ONLY01-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// SIMD-ONLY01-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 8 -// SIMD-ONLY01-NEXT: store i32 0, i32* [[A]], align 4 -// SIMD-ONLY01-NEXT: store i16 0, i16* [[AA]], align 2 -// SIMD-ONLY01-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// SIMD-ONLY01-NEXT: [[P:%.*]] = alloca ptr, align 64 +// SIMD-ONLY01-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// SIMD-ONLY01-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 8 +// SIMD-ONLY01-NEXT: store i32 0, ptr [[A]], align 4 +// SIMD-ONLY01-NEXT: store i16 0, ptr [[AA]], align 2 +// SIMD-ONLY01-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY01-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// SIMD-ONLY01-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// SIMD-ONLY01-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 +// SIMD-ONLY01-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() +// SIMD-ONLY01-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // SIMD-ONLY01-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// SIMD-ONLY01-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// SIMD-ONLY01-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// SIMD-ONLY01-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 +// SIMD-ONLY01-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY01-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 // SIMD-ONLY01-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] // SIMD-ONLY01-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// SIMD-ONLY01-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// SIMD-ONLY01-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 0 -// SIMD-ONLY01-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// SIMD-ONLY01-NEXT: store i32 [[TMP6]], i32* [[X]], align 4 -// SIMD-ONLY01-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 1 -// SIMD-ONLY01-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// SIMD-ONLY01-NEXT: store i32 [[TMP7]], i32* [[Y]], align 4 -// SIMD-ONLY01-NEXT: store i32* [[A]], i32** [[P]], align 64 -// SIMD-ONLY01-NEXT: [[TMP8:%.*]] = load i16, i16* [[AA]], align 2 +// SIMD-ONLY01-NEXT: store i64 [[TMP4]], ptr [[__VLA_EXPR1]], align 8 +// SIMD-ONLY01-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 0 +// SIMD-ONLY01-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// SIMD-ONLY01-NEXT: store i32 [[TMP6]], ptr [[X]], align 4 +// SIMD-ONLY01-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 1 +// SIMD-ONLY01-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// SIMD-ONLY01-NEXT: store i32 [[TMP7]], ptr [[Y]], align 4 +// SIMD-ONLY01-NEXT: store ptr [[A]], ptr [[P]], align 64 +// SIMD-ONLY01-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA]], align 2 // SIMD-ONLY01-NEXT: [[CONV:%.*]] = sext i16 [[TMP8]] to i32 // SIMD-ONLY01-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 // SIMD-ONLY01-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 -// SIMD-ONLY01-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// SIMD-ONLY01-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 -// SIMD-ONLY01-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4 -// SIMD-ONLY01-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 -// SIMD-ONLY01-NEXT: store float 1.000000e+00, float* [[ARRAYIDX3]], align 4 -// SIMD-ONLY01-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// SIMD-ONLY01-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX4]], i64 0, i64 2 -// SIMD-ONLY01-NEXT: store double 1.000000e+00, double* [[ARRAYIDX5]], align 8 +// SIMD-ONLY01-NEXT: store i16 [[CONV2]], ptr [[AA]], align 2 +// SIMD-ONLY01-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], i64 0, i64 2 +// SIMD-ONLY01-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX]], align 4 +// SIMD-ONLY01-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[VLA]], i64 3 +// SIMD-ONLY01-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX3]], align 4 +// SIMD-ONLY01-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C]], i64 0, i64 1 +// SIMD-ONLY01-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX4]], i64 0, i64 2 +// SIMD-ONLY01-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX5]], align 8 // SIMD-ONLY01-NEXT: [[TMP9:%.*]] = mul nsw i64 1, [[TMP4]] -// SIMD-ONLY01-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP9]] -// SIMD-ONLY01-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX6]], i64 3 -// SIMD-ONLY01-NEXT: store double 1.000000e+00, double* [[ARRAYIDX7]], align 8 -// SIMD-ONLY01-NEXT: [[X8:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// SIMD-ONLY01-NEXT: store i64 1, i64* [[X8]], align 8 -// SIMD-ONLY01-NEXT: [[Y9:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// SIMD-ONLY01-NEXT: store i8 1, i8* [[Y9]], align 8 -// SIMD-ONLY01-NEXT: [[X10:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 0 -// SIMD-ONLY01-NEXT: [[TMP10:%.*]] = load i32, i32* [[X10]], align 4 +// SIMD-ONLY01-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds double, ptr [[VLA1]], i64 [[TMP9]] +// SIMD-ONLY01-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX6]], i64 3 +// SIMD-ONLY01-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX7]], align 8 +// SIMD-ONLY01-NEXT: [[X8:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D]], i32 0, i32 0 +// SIMD-ONLY01-NEXT: store i64 1, ptr [[X8]], align 8 +// SIMD-ONLY01-NEXT: [[Y9:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D]], i32 0, i32 1 +// SIMD-ONLY01-NEXT: store i8 1, ptr [[Y9]], align 8 +// SIMD-ONLY01-NEXT: [[X10:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 0 +// SIMD-ONLY01-NEXT: [[TMP10:%.*]] = load i32, ptr [[X10]], align 4 // SIMD-ONLY01-NEXT: [[CONV11:%.*]] = sitofp i32 [[TMP10]] to double -// SIMD-ONLY01-NEXT: [[TMP11:%.*]] = load double*, double** [[PTR_ADDR]], align 8 -// SIMD-ONLY01-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds double, double* [[TMP11]], i64 0 -// SIMD-ONLY01-NEXT: store double [[CONV11]], double* [[ARRAYIDX12]], align 8 -// SIMD-ONLY01-NEXT: [[TMP12:%.*]] = load double*, double** [[PTR_ADDR]], align 8 -// SIMD-ONLY01-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds double, double* [[TMP12]], i64 0 -// SIMD-ONLY01-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX13]], align 8 +// SIMD-ONLY01-NEXT: [[TMP11:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8 +// SIMD-ONLY01-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds double, ptr [[TMP11]], i64 0 +// SIMD-ONLY01-NEXT: store double [[CONV11]], ptr [[ARRAYIDX12]], align 8 +// SIMD-ONLY01-NEXT: [[TMP12:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8 +// SIMD-ONLY01-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds double, ptr [[TMP12]], i64 0 +// SIMD-ONLY01-NEXT: [[TMP13:%.*]] = load double, ptr [[ARRAYIDX13]], align 8 // SIMD-ONLY01-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// SIMD-ONLY01-NEXT: store double [[INC]], double* [[ARRAYIDX13]], align 8 -// SIMD-ONLY01-NEXT: [[TMP14:%.*]] = load i32, i32* [[A]], align 4 -// SIMD-ONLY01-NEXT: [[TMP15:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// SIMD-ONLY01-NEXT: call void @llvm.stackrestore(i8* [[TMP15]]) +// SIMD-ONLY01-NEXT: store double [[INC]], ptr [[ARRAYIDX13]], align 8 +// SIMD-ONLY01-NEXT: [[TMP14:%.*]] = load i32, ptr [[A]], align 4 +// SIMD-ONLY01-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 +// SIMD-ONLY01-NEXT: call void @llvm.stackrestore(ptr [[TMP15]]) // SIMD-ONLY01-NEXT: ret i32 [[TMP14]] // // // SIMD-ONLY01-LABEL: define {{[^@]+}}@_Z3bariPd -// SIMD-ONLY01-SAME: (i32 noundef signext [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0]] { +// SIMD-ONLY01-SAME: (i32 noundef signext [[N:%.*]], ptr noundef [[PTR:%.*]]) #[[ATTR0]] { // SIMD-ONLY01-NEXT: entry: // SIMD-ONLY01-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// SIMD-ONLY01-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 8 +// SIMD-ONLY01-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY01-NEXT: [[A:%.*]] = alloca i32, align 4 // SIMD-ONLY01-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// SIMD-ONLY01-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// SIMD-ONLY01-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 8 -// SIMD-ONLY01-NEXT: store i32 0, i32* [[A]], align 4 -// SIMD-ONLY01-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// SIMD-ONLY01-NEXT: [[TMP1:%.*]] = load double*, double** [[PTR_ADDR]], align 8 -// SIMD-ONLY01-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooiPd(i32 noundef signext [[TMP0]], double* noundef [[TMP1]]) -// SIMD-ONLY01-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY01-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// SIMD-ONLY01-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 8 +// SIMD-ONLY01-NEXT: store i32 0, ptr [[A]], align 4 +// SIMD-ONLY01-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// SIMD-ONLY01-NEXT: [[TMP1:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8 +// SIMD-ONLY01-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooiPd(i32 noundef signext [[TMP0]], ptr noundef [[TMP1]]) +// SIMD-ONLY01-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY01-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CALL]] -// SIMD-ONLY01-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// SIMD-ONLY01-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// SIMD-ONLY01-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP3]]) -// SIMD-ONLY01-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY01-NEXT: store i32 [[ADD]], ptr [[A]], align 4 +// SIMD-ONLY01-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// SIMD-ONLY01-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(ptr noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP3]]) +// SIMD-ONLY01-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY01-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], [[CALL1]] -// SIMD-ONLY01-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// SIMD-ONLY01-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// SIMD-ONLY01-NEXT: store i32 [[ADD2]], ptr [[A]], align 4 +// SIMD-ONLY01-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY01-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP5]]) -// SIMD-ONLY01-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY01-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY01-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], [[CALL3]] -// SIMD-ONLY01-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// SIMD-ONLY01-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// SIMD-ONLY01-NEXT: store i32 [[ADD4]], ptr [[A]], align 4 +// SIMD-ONLY01-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY01-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP7]]) -// SIMD-ONLY01-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY01-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY01-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP8]], [[CALL5]] -// SIMD-ONLY01-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// SIMD-ONLY01-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY01-NEXT: store i32 [[ADD6]], ptr [[A]], align 4 +// SIMD-ONLY01-NEXT: [[TMP9:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY01-NEXT: ret i32 [[TMP9]] // // // SIMD-ONLY01-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// SIMD-ONLY01-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// SIMD-ONLY01-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // SIMD-ONLY01-NEXT: entry: -// SIMD-ONLY01-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// SIMD-ONLY01-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY01-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // SIMD-ONLY01-NEXT: [[B:%.*]] = alloca i32, align 4 -// SIMD-ONLY01-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// SIMD-ONLY01-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 // SIMD-ONLY01-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// SIMD-ONLY01-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// SIMD-ONLY01-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// SIMD-ONLY01-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// SIMD-ONLY01-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// SIMD-ONLY01-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY01-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// SIMD-ONLY01-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY01-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY01-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// SIMD-ONLY01-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// SIMD-ONLY01-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// SIMD-ONLY01-NEXT: store i32 [[ADD]], ptr [[B]], align 4 +// SIMD-ONLY01-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY01-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// SIMD-ONLY01-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// SIMD-ONLY01-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 +// SIMD-ONLY01-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave() +// SIMD-ONLY01-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8 // SIMD-ONLY01-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] // SIMD-ONLY01-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// SIMD-ONLY01-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// SIMD-ONLY01-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 +// SIMD-ONLY01-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 +// SIMD-ONLY01-NEXT: [[TMP5:%.*]] = load i32, ptr [[B]], align 4 // SIMD-ONLY01-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double // SIMD-ONLY01-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// SIMD-ONLY01-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// SIMD-ONLY01-NEXT: store double [[ADD2]], double* [[A]], align 8 -// SIMD-ONLY01-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// SIMD-ONLY01-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 8 +// SIMD-ONLY01-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0 +// SIMD-ONLY01-NEXT: store double [[ADD2]], ptr [[A]], align 8 +// SIMD-ONLY01-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[THIS1]], i32 0, i32 0 +// SIMD-ONLY01-NEXT: [[TMP6:%.*]] = load double, ptr [[A3]], align 8 // SIMD-ONLY01-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// SIMD-ONLY01-NEXT: store double [[INC]], double* [[A3]], align 8 +// SIMD-ONLY01-NEXT: store double [[INC]], ptr [[A3]], align 8 // SIMD-ONLY01-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 // SIMD-ONLY01-NEXT: [[TMP7:%.*]] = mul nsw i64 1, [[TMP2]] -// SIMD-ONLY01-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP7]] -// SIMD-ONLY01-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// SIMD-ONLY01-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 +// SIMD-ONLY01-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP7]] +// SIMD-ONLY01-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1 +// SIMD-ONLY01-NEXT: store i16 [[CONV4]], ptr [[ARRAYIDX5]], align 2 // SIMD-ONLY01-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] -// SIMD-ONLY01-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] -// SIMD-ONLY01-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1 -// SIMD-ONLY01-NEXT: [[TMP9:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 +// SIMD-ONLY01-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP8]] +// SIMD-ONLY01-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX6]], i64 1 +// SIMD-ONLY01-NEXT: [[TMP9:%.*]] = load i16, ptr [[ARRAYIDX7]], align 2 // SIMD-ONLY01-NEXT: [[CONV8:%.*]] = sext i16 [[TMP9]] to i32 -// SIMD-ONLY01-NEXT: [[TMP10:%.*]] = load i32, i32* [[B]], align 4 +// SIMD-ONLY01-NEXT: [[TMP10:%.*]] = load i32, ptr [[B]], align 4 // SIMD-ONLY01-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP10]] -// SIMD-ONLY01-NEXT: [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// SIMD-ONLY01-NEXT: call void @llvm.stackrestore(i8* [[TMP11]]) +// SIMD-ONLY01-NEXT: [[TMP11:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 +// SIMD-ONLY01-NEXT: call void @llvm.stackrestore(ptr [[TMP11]]) // SIMD-ONLY01-NEXT: ret i32 [[ADD9]] // // @@ -9862,22 +9554,22 @@ int bar(int n, double *ptr) { // SIMD-ONLY01-NEXT: [[A:%.*]] = alloca i32, align 4 // SIMD-ONLY01-NEXT: [[AAA:%.*]] = alloca i8, align 1 // SIMD-ONLY01-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// SIMD-ONLY01-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// SIMD-ONLY01-NEXT: store i32 0, i32* [[A]], align 4 -// SIMD-ONLY01-NEXT: store i8 0, i8* [[AAA]], align 1 -// SIMD-ONLY01-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY01-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// SIMD-ONLY01-NEXT: store i32 0, ptr [[A]], align 4 +// SIMD-ONLY01-NEXT: store i8 0, ptr [[AAA]], align 1 +// SIMD-ONLY01-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY01-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// SIMD-ONLY01-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// SIMD-ONLY01-NEXT: [[TMP1:%.*]] = load i8, i8* [[AAA]], align 1 +// SIMD-ONLY01-NEXT: store i32 [[ADD]], ptr [[A]], align 4 +// SIMD-ONLY01-NEXT: [[TMP1:%.*]] = load i8, ptr [[AAA]], align 1 // SIMD-ONLY01-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32 // SIMD-ONLY01-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 // SIMD-ONLY01-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i8 -// SIMD-ONLY01-NEXT: store i8 [[CONV2]], i8* [[AAA]], align 1 -// SIMD-ONLY01-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// SIMD-ONLY01-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// SIMD-ONLY01-NEXT: store i8 [[CONV2]], ptr [[AAA]], align 1 +// SIMD-ONLY01-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i64 0, i64 2 +// SIMD-ONLY01-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // SIMD-ONLY01-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// SIMD-ONLY01-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// SIMD-ONLY01-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY01-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4 +// SIMD-ONLY01-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY01-NEXT: ret i32 [[TMP3]] // // @@ -9887,169 +9579,169 @@ int bar(int n, double *ptr) { // SIMD-ONLY01-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // SIMD-ONLY01-NEXT: [[A:%.*]] = alloca i32, align 4 // SIMD-ONLY01-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// SIMD-ONLY01-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// SIMD-ONLY01-NEXT: store i32 0, i32* [[A]], align 4 -// SIMD-ONLY01-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY01-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// SIMD-ONLY01-NEXT: store i32 0, ptr [[A]], align 4 +// SIMD-ONLY01-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY01-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// SIMD-ONLY01-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// SIMD-ONLY01-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// SIMD-ONLY01-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// SIMD-ONLY01-NEXT: store i32 [[ADD]], ptr [[A]], align 4 +// SIMD-ONLY01-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i64 0, i64 2 +// SIMD-ONLY01-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // SIMD-ONLY01-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP1]], 1 -// SIMD-ONLY01-NEXT: store i32 [[ADD1]], i32* [[ARRAYIDX]], align 4 -// SIMD-ONLY01-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY01-NEXT: store i32 [[ADD1]], ptr [[ARRAYIDX]], align 4 +// SIMD-ONLY01-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY01-NEXT: ret i32 [[TMP2]] // // // SIMD-ONLY02-LABEL: define {{[^@]+}}@_Z3fooiPd -// SIMD-ONLY02-SAME: (i32 noundef [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0:[0-9]+]] { +// SIMD-ONLY02-SAME: (i32 noundef [[N:%.*]], ptr noundef [[PTR:%.*]]) #[[ATTR0:[0-9]+]] { // SIMD-ONLY02-NEXT: entry: // SIMD-ONLY02-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// SIMD-ONLY02-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 4 +// SIMD-ONLY02-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 4 // SIMD-ONLY02-NEXT: [[A:%.*]] = alloca i32, align 4 // SIMD-ONLY02-NEXT: [[AA:%.*]] = alloca i16, align 2 // SIMD-ONLY02-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// SIMD-ONLY02-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// SIMD-ONLY02-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4 // SIMD-ONLY02-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 // SIMD-ONLY02-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 // SIMD-ONLY02-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 // SIMD-ONLY02-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 // SIMD-ONLY02-NEXT: [[E:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 4 -// SIMD-ONLY02-NEXT: [[P:%.*]] = alloca i32*, align 64 -// SIMD-ONLY02-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// SIMD-ONLY02-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 4 -// SIMD-ONLY02-NEXT: store i32 0, i32* [[A]], align 4 -// SIMD-ONLY02-NEXT: store i16 0, i16* [[AA]], align 2 -// SIMD-ONLY02-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// SIMD-ONLY02-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// SIMD-ONLY02-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 +// SIMD-ONLY02-NEXT: [[P:%.*]] = alloca ptr, align 64 +// SIMD-ONLY02-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// SIMD-ONLY02-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 4 +// SIMD-ONLY02-NEXT: store i32 0, ptr [[A]], align 4 +// SIMD-ONLY02-NEXT: store i16 0, ptr [[AA]], align 2 +// SIMD-ONLY02-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// SIMD-ONLY02-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave() +// SIMD-ONLY02-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4 // SIMD-ONLY02-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// SIMD-ONLY02-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// SIMD-ONLY02-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// SIMD-ONLY02-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 +// SIMD-ONLY02-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY02-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] // SIMD-ONLY02-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// SIMD-ONLY02-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// SIMD-ONLY02-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 0 -// SIMD-ONLY02-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// SIMD-ONLY02-NEXT: store i32 [[TMP4]], i32* [[X]], align 4 -// SIMD-ONLY02-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 1 -// SIMD-ONLY02-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// SIMD-ONLY02-NEXT: store i32 [[TMP5]], i32* [[Y]], align 4 -// SIMD-ONLY02-NEXT: store i32* [[A]], i32** [[P]], align 64 -// SIMD-ONLY02-NEXT: [[TMP6:%.*]] = load i16, i16* [[AA]], align 2 +// SIMD-ONLY02-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 4 +// SIMD-ONLY02-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 0 +// SIMD-ONLY02-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// SIMD-ONLY02-NEXT: store i32 [[TMP4]], ptr [[X]], align 4 +// SIMD-ONLY02-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 1 +// SIMD-ONLY02-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// SIMD-ONLY02-NEXT: store i32 [[TMP5]], ptr [[Y]], align 4 +// SIMD-ONLY02-NEXT: store ptr [[A]], ptr [[P]], align 64 +// SIMD-ONLY02-NEXT: [[TMP6:%.*]] = load i16, ptr [[AA]], align 2 // SIMD-ONLY02-NEXT: [[CONV:%.*]] = sext i16 [[TMP6]] to i32 // SIMD-ONLY02-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 // SIMD-ONLY02-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 -// SIMD-ONLY02-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// SIMD-ONLY02-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 -// SIMD-ONLY02-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4 -// SIMD-ONLY02-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 -// SIMD-ONLY02-NEXT: store float 1.000000e+00, float* [[ARRAYIDX3]], align 4 -// SIMD-ONLY02-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// SIMD-ONLY02-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX4]], i32 0, i32 2 -// SIMD-ONLY02-NEXT: store double 1.000000e+00, double* [[ARRAYIDX5]], align 8 +// SIMD-ONLY02-NEXT: store i16 [[CONV2]], ptr [[AA]], align 2 +// SIMD-ONLY02-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], i32 0, i32 2 +// SIMD-ONLY02-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX]], align 4 +// SIMD-ONLY02-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[VLA]], i32 3 +// SIMD-ONLY02-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX3]], align 4 +// SIMD-ONLY02-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C]], i32 0, i32 1 +// SIMD-ONLY02-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX4]], i32 0, i32 2 +// SIMD-ONLY02-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX5]], align 8 // SIMD-ONLY02-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP2]] -// SIMD-ONLY02-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP7]] -// SIMD-ONLY02-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX6]], i32 3 -// SIMD-ONLY02-NEXT: store double 1.000000e+00, double* [[ARRAYIDX7]], align 8 -// SIMD-ONLY02-NEXT: [[X8:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// SIMD-ONLY02-NEXT: store i64 1, i64* [[X8]], align 4 -// SIMD-ONLY02-NEXT: [[Y9:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// SIMD-ONLY02-NEXT: store i8 1, i8* [[Y9]], align 4 -// SIMD-ONLY02-NEXT: [[X10:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 0 -// SIMD-ONLY02-NEXT: [[TMP8:%.*]] = load i32, i32* [[X10]], align 4 +// SIMD-ONLY02-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds double, ptr [[VLA1]], i32 [[TMP7]] +// SIMD-ONLY02-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX6]], i32 3 +// SIMD-ONLY02-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX7]], align 8 +// SIMD-ONLY02-NEXT: [[X8:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D]], i32 0, i32 0 +// SIMD-ONLY02-NEXT: store i64 1, ptr [[X8]], align 4 +// SIMD-ONLY02-NEXT: [[Y9:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D]], i32 0, i32 1 +// SIMD-ONLY02-NEXT: store i8 1, ptr [[Y9]], align 4 +// SIMD-ONLY02-NEXT: [[X10:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 0 +// SIMD-ONLY02-NEXT: [[TMP8:%.*]] = load i32, ptr [[X10]], align 4 // SIMD-ONLY02-NEXT: [[CONV11:%.*]] = sitofp i32 [[TMP8]] to double -// SIMD-ONLY02-NEXT: [[TMP9:%.*]] = load double*, double** [[PTR_ADDR]], align 4 -// SIMD-ONLY02-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds double, double* [[TMP9]], i32 0 -// SIMD-ONLY02-NEXT: store double [[CONV11]], double* [[ARRAYIDX12]], align 4 -// SIMD-ONLY02-NEXT: [[TMP10:%.*]] = load double*, double** [[PTR_ADDR]], align 4 -// SIMD-ONLY02-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds double, double* [[TMP10]], i32 0 -// SIMD-ONLY02-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 4 +// SIMD-ONLY02-NEXT: [[TMP9:%.*]] = load ptr, ptr [[PTR_ADDR]], align 4 +// SIMD-ONLY02-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds double, ptr [[TMP9]], i32 0 +// SIMD-ONLY02-NEXT: store double [[CONV11]], ptr [[ARRAYIDX12]], align 4 +// SIMD-ONLY02-NEXT: [[TMP10:%.*]] = load ptr, ptr [[PTR_ADDR]], align 4 +// SIMD-ONLY02-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds double, ptr [[TMP10]], i32 0 +// SIMD-ONLY02-NEXT: [[TMP11:%.*]] = load double, ptr [[ARRAYIDX13]], align 4 // SIMD-ONLY02-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+00 -// SIMD-ONLY02-NEXT: store double [[INC]], double* [[ARRAYIDX13]], align 4 -// SIMD-ONLY02-NEXT: [[TMP12:%.*]] = load i32, i32* [[A]], align 4 -// SIMD-ONLY02-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// SIMD-ONLY02-NEXT: call void @llvm.stackrestore(i8* [[TMP13]]) +// SIMD-ONLY02-NEXT: store double [[INC]], ptr [[ARRAYIDX13]], align 4 +// SIMD-ONLY02-NEXT: [[TMP12:%.*]] = load i32, ptr [[A]], align 4 +// SIMD-ONLY02-NEXT: [[TMP13:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 +// SIMD-ONLY02-NEXT: call void @llvm.stackrestore(ptr [[TMP13]]) // SIMD-ONLY02-NEXT: ret i32 [[TMP12]] // // // SIMD-ONLY02-LABEL: define {{[^@]+}}@_Z3bariPd -// SIMD-ONLY02-SAME: (i32 noundef [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0]] { +// SIMD-ONLY02-SAME: (i32 noundef [[N:%.*]], ptr noundef [[PTR:%.*]]) #[[ATTR0]] { // SIMD-ONLY02-NEXT: entry: // SIMD-ONLY02-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// SIMD-ONLY02-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 4 +// SIMD-ONLY02-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 4 // SIMD-ONLY02-NEXT: [[A:%.*]] = alloca i32, align 4 // SIMD-ONLY02-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// SIMD-ONLY02-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// SIMD-ONLY02-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 4 -// SIMD-ONLY02-NEXT: store i32 0, i32* [[A]], align 4 -// SIMD-ONLY02-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// SIMD-ONLY02-NEXT: [[TMP1:%.*]] = load double*, double** [[PTR_ADDR]], align 4 -// SIMD-ONLY02-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooiPd(i32 noundef [[TMP0]], double* noundef [[TMP1]]) -// SIMD-ONLY02-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY02-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// SIMD-ONLY02-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 4 +// SIMD-ONLY02-NEXT: store i32 0, ptr [[A]], align 4 +// SIMD-ONLY02-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// SIMD-ONLY02-NEXT: [[TMP1:%.*]] = load ptr, ptr [[PTR_ADDR]], align 4 +// SIMD-ONLY02-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooiPd(i32 noundef [[TMP0]], ptr noundef [[TMP1]]) +// SIMD-ONLY02-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY02-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CALL]] -// SIMD-ONLY02-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// SIMD-ONLY02-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// SIMD-ONLY02-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP3]]) -// SIMD-ONLY02-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY02-NEXT: store i32 [[ADD]], ptr [[A]], align 4 +// SIMD-ONLY02-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// SIMD-ONLY02-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP3]]) +// SIMD-ONLY02-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY02-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], [[CALL1]] -// SIMD-ONLY02-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// SIMD-ONLY02-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// SIMD-ONLY02-NEXT: store i32 [[ADD2]], ptr [[A]], align 4 +// SIMD-ONLY02-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY02-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP5]]) -// SIMD-ONLY02-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY02-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY02-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], [[CALL3]] -// SIMD-ONLY02-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// SIMD-ONLY02-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// SIMD-ONLY02-NEXT: store i32 [[ADD4]], ptr [[A]], align 4 +// SIMD-ONLY02-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY02-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP7]]) -// SIMD-ONLY02-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY02-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY02-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP8]], [[CALL5]] -// SIMD-ONLY02-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// SIMD-ONLY02-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY02-NEXT: store i32 [[ADD6]], ptr [[A]], align 4 +// SIMD-ONLY02-NEXT: [[TMP9:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY02-NEXT: ret i32 [[TMP9]] // // // SIMD-ONLY02-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// SIMD-ONLY02-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// SIMD-ONLY02-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { // SIMD-ONLY02-NEXT: entry: -// SIMD-ONLY02-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// SIMD-ONLY02-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // SIMD-ONLY02-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // SIMD-ONLY02-NEXT: [[B:%.*]] = alloca i32, align 4 -// SIMD-ONLY02-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// SIMD-ONLY02-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4 // SIMD-ONLY02-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// SIMD-ONLY02-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// SIMD-ONLY02-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// SIMD-ONLY02-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// SIMD-ONLY02-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// SIMD-ONLY02-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 +// SIMD-ONLY02-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// SIMD-ONLY02-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 +// SIMD-ONLY02-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY02-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// SIMD-ONLY02-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// SIMD-ONLY02-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// SIMD-ONLY02-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// SIMD-ONLY02-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 +// SIMD-ONLY02-NEXT: store i32 [[ADD]], ptr [[B]], align 4 +// SIMD-ONLY02-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// SIMD-ONLY02-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() +// SIMD-ONLY02-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 // SIMD-ONLY02-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] // SIMD-ONLY02-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// SIMD-ONLY02-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// SIMD-ONLY02-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 +// SIMD-ONLY02-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 +// SIMD-ONLY02-NEXT: [[TMP4:%.*]] = load i32, ptr [[B]], align 4 // SIMD-ONLY02-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double // SIMD-ONLY02-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// SIMD-ONLY02-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// SIMD-ONLY02-NEXT: store double [[ADD2]], double* [[A]], align 4 -// SIMD-ONLY02-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// SIMD-ONLY02-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 +// SIMD-ONLY02-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0 +// SIMD-ONLY02-NEXT: store double [[ADD2]], ptr [[A]], align 4 +// SIMD-ONLY02-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[THIS1]], i32 0, i32 0 +// SIMD-ONLY02-NEXT: [[TMP5:%.*]] = load double, ptr [[A3]], align 4 // SIMD-ONLY02-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 -// SIMD-ONLY02-NEXT: store double [[INC]], double* [[A3]], align 4 +// SIMD-ONLY02-NEXT: store double [[INC]], ptr [[A3]], align 4 // SIMD-ONLY02-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 // SIMD-ONLY02-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP1]] -// SIMD-ONLY02-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP6]] -// SIMD-ONLY02-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// SIMD-ONLY02-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 +// SIMD-ONLY02-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP6]] +// SIMD-ONLY02-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1 +// SIMD-ONLY02-NEXT: store i16 [[CONV4]], ptr [[ARRAYIDX5]], align 2 // SIMD-ONLY02-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] -// SIMD-ONLY02-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] -// SIMD-ONLY02-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1 -// SIMD-ONLY02-NEXT: [[TMP8:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 +// SIMD-ONLY02-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP7]] +// SIMD-ONLY02-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX6]], i32 1 +// SIMD-ONLY02-NEXT: [[TMP8:%.*]] = load i16, ptr [[ARRAYIDX7]], align 2 // SIMD-ONLY02-NEXT: [[CONV8:%.*]] = sext i16 [[TMP8]] to i32 -// SIMD-ONLY02-NEXT: [[TMP9:%.*]] = load i32, i32* [[B]], align 4 +// SIMD-ONLY02-NEXT: [[TMP9:%.*]] = load i32, ptr [[B]], align 4 // SIMD-ONLY02-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP9]] -// SIMD-ONLY02-NEXT: [[TMP10:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// SIMD-ONLY02-NEXT: call void @llvm.stackrestore(i8* [[TMP10]]) +// SIMD-ONLY02-NEXT: [[TMP10:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 +// SIMD-ONLY02-NEXT: call void @llvm.stackrestore(ptr [[TMP10]]) // SIMD-ONLY02-NEXT: ret i32 [[ADD9]] // // @@ -10060,22 +9752,22 @@ int bar(int n, double *ptr) { // SIMD-ONLY02-NEXT: [[A:%.*]] = alloca i32, align 4 // SIMD-ONLY02-NEXT: [[AAA:%.*]] = alloca i8, align 1 // SIMD-ONLY02-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// SIMD-ONLY02-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// SIMD-ONLY02-NEXT: store i32 0, i32* [[A]], align 4 -// SIMD-ONLY02-NEXT: store i8 0, i8* [[AAA]], align 1 -// SIMD-ONLY02-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY02-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// SIMD-ONLY02-NEXT: store i32 0, ptr [[A]], align 4 +// SIMD-ONLY02-NEXT: store i8 0, ptr [[AAA]], align 1 +// SIMD-ONLY02-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY02-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// SIMD-ONLY02-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// SIMD-ONLY02-NEXT: [[TMP1:%.*]] = load i8, i8* [[AAA]], align 1 +// SIMD-ONLY02-NEXT: store i32 [[ADD]], ptr [[A]], align 4 +// SIMD-ONLY02-NEXT: [[TMP1:%.*]] = load i8, ptr [[AAA]], align 1 // SIMD-ONLY02-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32 // SIMD-ONLY02-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 // SIMD-ONLY02-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i8 -// SIMD-ONLY02-NEXT: store i8 [[CONV2]], i8* [[AAA]], align 1 -// SIMD-ONLY02-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// SIMD-ONLY02-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// SIMD-ONLY02-NEXT: store i8 [[CONV2]], ptr [[AAA]], align 1 +// SIMD-ONLY02-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i32 0, i32 2 +// SIMD-ONLY02-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // SIMD-ONLY02-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// SIMD-ONLY02-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// SIMD-ONLY02-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY02-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4 +// SIMD-ONLY02-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY02-NEXT: ret i32 [[TMP3]] // // @@ -10085,169 +9777,169 @@ int bar(int n, double *ptr) { // SIMD-ONLY02-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // SIMD-ONLY02-NEXT: [[A:%.*]] = alloca i32, align 4 // SIMD-ONLY02-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// SIMD-ONLY02-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// SIMD-ONLY02-NEXT: store i32 0, i32* [[A]], align 4 -// SIMD-ONLY02-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY02-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// SIMD-ONLY02-NEXT: store i32 0, ptr [[A]], align 4 +// SIMD-ONLY02-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY02-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// SIMD-ONLY02-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// SIMD-ONLY02-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// SIMD-ONLY02-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// SIMD-ONLY02-NEXT: store i32 [[ADD]], ptr [[A]], align 4 +// SIMD-ONLY02-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i32 0, i32 2 +// SIMD-ONLY02-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // SIMD-ONLY02-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP1]], 1 -// SIMD-ONLY02-NEXT: store i32 [[ADD1]], i32* [[ARRAYIDX]], align 4 -// SIMD-ONLY02-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY02-NEXT: store i32 [[ADD1]], ptr [[ARRAYIDX]], align 4 +// SIMD-ONLY02-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY02-NEXT: ret i32 [[TMP2]] // // // SIMD-ONLY03-LABEL: define {{[^@]+}}@_Z3fooiPd -// SIMD-ONLY03-SAME: (i32 noundef [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0:[0-9]+]] { +// SIMD-ONLY03-SAME: (i32 noundef [[N:%.*]], ptr noundef [[PTR:%.*]]) #[[ATTR0:[0-9]+]] { // SIMD-ONLY03-NEXT: entry: // SIMD-ONLY03-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// SIMD-ONLY03-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 4 +// SIMD-ONLY03-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 4 // SIMD-ONLY03-NEXT: [[A:%.*]] = alloca i32, align 4 // SIMD-ONLY03-NEXT: [[AA:%.*]] = alloca i16, align 2 // SIMD-ONLY03-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// SIMD-ONLY03-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// SIMD-ONLY03-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4 // SIMD-ONLY03-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 // SIMD-ONLY03-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 // SIMD-ONLY03-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 // SIMD-ONLY03-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 // SIMD-ONLY03-NEXT: [[E:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 4 -// SIMD-ONLY03-NEXT: [[P:%.*]] = alloca i32*, align 64 -// SIMD-ONLY03-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// SIMD-ONLY03-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 4 -// SIMD-ONLY03-NEXT: store i32 0, i32* [[A]], align 4 -// SIMD-ONLY03-NEXT: store i16 0, i16* [[AA]], align 2 -// SIMD-ONLY03-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// SIMD-ONLY03-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// SIMD-ONLY03-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 +// SIMD-ONLY03-NEXT: [[P:%.*]] = alloca ptr, align 64 +// SIMD-ONLY03-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// SIMD-ONLY03-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 4 +// SIMD-ONLY03-NEXT: store i32 0, ptr [[A]], align 4 +// SIMD-ONLY03-NEXT: store i16 0, ptr [[AA]], align 2 +// SIMD-ONLY03-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// SIMD-ONLY03-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave() +// SIMD-ONLY03-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4 // SIMD-ONLY03-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// SIMD-ONLY03-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// SIMD-ONLY03-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// SIMD-ONLY03-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 +// SIMD-ONLY03-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY03-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] // SIMD-ONLY03-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// SIMD-ONLY03-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// SIMD-ONLY03-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 0 -// SIMD-ONLY03-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// SIMD-ONLY03-NEXT: store i32 [[TMP4]], i32* [[X]], align 4 -// SIMD-ONLY03-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 1 -// SIMD-ONLY03-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// SIMD-ONLY03-NEXT: store i32 [[TMP5]], i32* [[Y]], align 4 -// SIMD-ONLY03-NEXT: store i32* [[A]], i32** [[P]], align 64 -// SIMD-ONLY03-NEXT: [[TMP6:%.*]] = load i16, i16* [[AA]], align 2 +// SIMD-ONLY03-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 4 +// SIMD-ONLY03-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 0 +// SIMD-ONLY03-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// SIMD-ONLY03-NEXT: store i32 [[TMP4]], ptr [[X]], align 4 +// SIMD-ONLY03-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 1 +// SIMD-ONLY03-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// SIMD-ONLY03-NEXT: store i32 [[TMP5]], ptr [[Y]], align 4 +// SIMD-ONLY03-NEXT: store ptr [[A]], ptr [[P]], align 64 +// SIMD-ONLY03-NEXT: [[TMP6:%.*]] = load i16, ptr [[AA]], align 2 // SIMD-ONLY03-NEXT: [[CONV:%.*]] = sext i16 [[TMP6]] to i32 // SIMD-ONLY03-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 // SIMD-ONLY03-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 -// SIMD-ONLY03-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// SIMD-ONLY03-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 -// SIMD-ONLY03-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4 -// SIMD-ONLY03-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 -// SIMD-ONLY03-NEXT: store float 1.000000e+00, float* [[ARRAYIDX3]], align 4 -// SIMD-ONLY03-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// SIMD-ONLY03-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX4]], i32 0, i32 2 -// SIMD-ONLY03-NEXT: store double 1.000000e+00, double* [[ARRAYIDX5]], align 8 +// SIMD-ONLY03-NEXT: store i16 [[CONV2]], ptr [[AA]], align 2 +// SIMD-ONLY03-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], i32 0, i32 2 +// SIMD-ONLY03-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX]], align 4 +// SIMD-ONLY03-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[VLA]], i32 3 +// SIMD-ONLY03-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX3]], align 4 +// SIMD-ONLY03-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C]], i32 0, i32 1 +// SIMD-ONLY03-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX4]], i32 0, i32 2 +// SIMD-ONLY03-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX5]], align 8 // SIMD-ONLY03-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP2]] -// SIMD-ONLY03-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP7]] -// SIMD-ONLY03-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX6]], i32 3 -// SIMD-ONLY03-NEXT: store double 1.000000e+00, double* [[ARRAYIDX7]], align 8 -// SIMD-ONLY03-NEXT: [[X8:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// SIMD-ONLY03-NEXT: store i64 1, i64* [[X8]], align 4 -// SIMD-ONLY03-NEXT: [[Y9:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// SIMD-ONLY03-NEXT: store i8 1, i8* [[Y9]], align 4 -// SIMD-ONLY03-NEXT: [[X10:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 0 -// SIMD-ONLY03-NEXT: [[TMP8:%.*]] = load i32, i32* [[X10]], align 4 +// SIMD-ONLY03-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds double, ptr [[VLA1]], i32 [[TMP7]] +// SIMD-ONLY03-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX6]], i32 3 +// SIMD-ONLY03-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX7]], align 8 +// SIMD-ONLY03-NEXT: [[X8:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D]], i32 0, i32 0 +// SIMD-ONLY03-NEXT: store i64 1, ptr [[X8]], align 4 +// SIMD-ONLY03-NEXT: [[Y9:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D]], i32 0, i32 1 +// SIMD-ONLY03-NEXT: store i8 1, ptr [[Y9]], align 4 +// SIMD-ONLY03-NEXT: [[X10:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 0 +// SIMD-ONLY03-NEXT: [[TMP8:%.*]] = load i32, ptr [[X10]], align 4 // SIMD-ONLY03-NEXT: [[CONV11:%.*]] = sitofp i32 [[TMP8]] to double -// SIMD-ONLY03-NEXT: [[TMP9:%.*]] = load double*, double** [[PTR_ADDR]], align 4 -// SIMD-ONLY03-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds double, double* [[TMP9]], i32 0 -// SIMD-ONLY03-NEXT: store double [[CONV11]], double* [[ARRAYIDX12]], align 4 -// SIMD-ONLY03-NEXT: [[TMP10:%.*]] = load double*, double** [[PTR_ADDR]], align 4 -// SIMD-ONLY03-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds double, double* [[TMP10]], i32 0 -// SIMD-ONLY03-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 4 +// SIMD-ONLY03-NEXT: [[TMP9:%.*]] = load ptr, ptr [[PTR_ADDR]], align 4 +// SIMD-ONLY03-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds double, ptr [[TMP9]], i32 0 +// SIMD-ONLY03-NEXT: store double [[CONV11]], ptr [[ARRAYIDX12]], align 4 +// SIMD-ONLY03-NEXT: [[TMP10:%.*]] = load ptr, ptr [[PTR_ADDR]], align 4 +// SIMD-ONLY03-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds double, ptr [[TMP10]], i32 0 +// SIMD-ONLY03-NEXT: [[TMP11:%.*]] = load double, ptr [[ARRAYIDX13]], align 4 // SIMD-ONLY03-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+00 -// SIMD-ONLY03-NEXT: store double [[INC]], double* [[ARRAYIDX13]], align 4 -// SIMD-ONLY03-NEXT: [[TMP12:%.*]] = load i32, i32* [[A]], align 4 -// SIMD-ONLY03-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// SIMD-ONLY03-NEXT: call void @llvm.stackrestore(i8* [[TMP13]]) +// SIMD-ONLY03-NEXT: store double [[INC]], ptr [[ARRAYIDX13]], align 4 +// SIMD-ONLY03-NEXT: [[TMP12:%.*]] = load i32, ptr [[A]], align 4 +// SIMD-ONLY03-NEXT: [[TMP13:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 +// SIMD-ONLY03-NEXT: call void @llvm.stackrestore(ptr [[TMP13]]) // SIMD-ONLY03-NEXT: ret i32 [[TMP12]] // // // SIMD-ONLY03-LABEL: define {{[^@]+}}@_Z3bariPd -// SIMD-ONLY03-SAME: (i32 noundef [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0]] { +// SIMD-ONLY03-SAME: (i32 noundef [[N:%.*]], ptr noundef [[PTR:%.*]]) #[[ATTR0]] { // SIMD-ONLY03-NEXT: entry: // SIMD-ONLY03-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// SIMD-ONLY03-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 4 +// SIMD-ONLY03-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 4 // SIMD-ONLY03-NEXT: [[A:%.*]] = alloca i32, align 4 // SIMD-ONLY03-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// SIMD-ONLY03-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// SIMD-ONLY03-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 4 -// SIMD-ONLY03-NEXT: store i32 0, i32* [[A]], align 4 -// SIMD-ONLY03-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// SIMD-ONLY03-NEXT: [[TMP1:%.*]] = load double*, double** [[PTR_ADDR]], align 4 -// SIMD-ONLY03-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooiPd(i32 noundef [[TMP0]], double* noundef [[TMP1]]) -// SIMD-ONLY03-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY03-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// SIMD-ONLY03-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 4 +// SIMD-ONLY03-NEXT: store i32 0, ptr [[A]], align 4 +// SIMD-ONLY03-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// SIMD-ONLY03-NEXT: [[TMP1:%.*]] = load ptr, ptr [[PTR_ADDR]], align 4 +// SIMD-ONLY03-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooiPd(i32 noundef [[TMP0]], ptr noundef [[TMP1]]) +// SIMD-ONLY03-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY03-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CALL]] -// SIMD-ONLY03-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// SIMD-ONLY03-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// SIMD-ONLY03-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP3]]) -// SIMD-ONLY03-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY03-NEXT: store i32 [[ADD]], ptr [[A]], align 4 +// SIMD-ONLY03-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// SIMD-ONLY03-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP3]]) +// SIMD-ONLY03-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY03-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], [[CALL1]] -// SIMD-ONLY03-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// SIMD-ONLY03-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// SIMD-ONLY03-NEXT: store i32 [[ADD2]], ptr [[A]], align 4 +// SIMD-ONLY03-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY03-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP5]]) -// SIMD-ONLY03-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY03-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY03-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], [[CALL3]] -// SIMD-ONLY03-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// SIMD-ONLY03-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// SIMD-ONLY03-NEXT: store i32 [[ADD4]], ptr [[A]], align 4 +// SIMD-ONLY03-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY03-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP7]]) -// SIMD-ONLY03-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY03-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY03-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP8]], [[CALL5]] -// SIMD-ONLY03-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// SIMD-ONLY03-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY03-NEXT: store i32 [[ADD6]], ptr [[A]], align 4 +// SIMD-ONLY03-NEXT: [[TMP9:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY03-NEXT: ret i32 [[TMP9]] // // // SIMD-ONLY03-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// SIMD-ONLY03-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// SIMD-ONLY03-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { // SIMD-ONLY03-NEXT: entry: -// SIMD-ONLY03-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// SIMD-ONLY03-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // SIMD-ONLY03-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // SIMD-ONLY03-NEXT: [[B:%.*]] = alloca i32, align 4 -// SIMD-ONLY03-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// SIMD-ONLY03-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4 // SIMD-ONLY03-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// SIMD-ONLY03-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// SIMD-ONLY03-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// SIMD-ONLY03-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// SIMD-ONLY03-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// SIMD-ONLY03-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 +// SIMD-ONLY03-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// SIMD-ONLY03-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 +// SIMD-ONLY03-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY03-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// SIMD-ONLY03-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// SIMD-ONLY03-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// SIMD-ONLY03-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// SIMD-ONLY03-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 +// SIMD-ONLY03-NEXT: store i32 [[ADD]], ptr [[B]], align 4 +// SIMD-ONLY03-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// SIMD-ONLY03-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() +// SIMD-ONLY03-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 // SIMD-ONLY03-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] // SIMD-ONLY03-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// SIMD-ONLY03-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// SIMD-ONLY03-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 +// SIMD-ONLY03-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 +// SIMD-ONLY03-NEXT: [[TMP4:%.*]] = load i32, ptr [[B]], align 4 // SIMD-ONLY03-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double // SIMD-ONLY03-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// SIMD-ONLY03-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// SIMD-ONLY03-NEXT: store double [[ADD2]], double* [[A]], align 4 -// SIMD-ONLY03-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// SIMD-ONLY03-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 +// SIMD-ONLY03-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0 +// SIMD-ONLY03-NEXT: store double [[ADD2]], ptr [[A]], align 4 +// SIMD-ONLY03-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[THIS1]], i32 0, i32 0 +// SIMD-ONLY03-NEXT: [[TMP5:%.*]] = load double, ptr [[A3]], align 4 // SIMD-ONLY03-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 -// SIMD-ONLY03-NEXT: store double [[INC]], double* [[A3]], align 4 +// SIMD-ONLY03-NEXT: store double [[INC]], ptr [[A3]], align 4 // SIMD-ONLY03-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 // SIMD-ONLY03-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP1]] -// SIMD-ONLY03-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP6]] -// SIMD-ONLY03-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// SIMD-ONLY03-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 +// SIMD-ONLY03-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP6]] +// SIMD-ONLY03-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1 +// SIMD-ONLY03-NEXT: store i16 [[CONV4]], ptr [[ARRAYIDX5]], align 2 // SIMD-ONLY03-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] -// SIMD-ONLY03-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] -// SIMD-ONLY03-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1 -// SIMD-ONLY03-NEXT: [[TMP8:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 +// SIMD-ONLY03-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP7]] +// SIMD-ONLY03-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX6]], i32 1 +// SIMD-ONLY03-NEXT: [[TMP8:%.*]] = load i16, ptr [[ARRAYIDX7]], align 2 // SIMD-ONLY03-NEXT: [[CONV8:%.*]] = sext i16 [[TMP8]] to i32 -// SIMD-ONLY03-NEXT: [[TMP9:%.*]] = load i32, i32* [[B]], align 4 +// SIMD-ONLY03-NEXT: [[TMP9:%.*]] = load i32, ptr [[B]], align 4 // SIMD-ONLY03-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP9]] -// SIMD-ONLY03-NEXT: [[TMP10:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// SIMD-ONLY03-NEXT: call void @llvm.stackrestore(i8* [[TMP10]]) +// SIMD-ONLY03-NEXT: [[TMP10:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 +// SIMD-ONLY03-NEXT: call void @llvm.stackrestore(ptr [[TMP10]]) // SIMD-ONLY03-NEXT: ret i32 [[ADD9]] // // @@ -10258,22 +9950,22 @@ int bar(int n, double *ptr) { // SIMD-ONLY03-NEXT: [[A:%.*]] = alloca i32, align 4 // SIMD-ONLY03-NEXT: [[AAA:%.*]] = alloca i8, align 1 // SIMD-ONLY03-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// SIMD-ONLY03-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// SIMD-ONLY03-NEXT: store i32 0, i32* [[A]], align 4 -// SIMD-ONLY03-NEXT: store i8 0, i8* [[AAA]], align 1 -// SIMD-ONLY03-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY03-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// SIMD-ONLY03-NEXT: store i32 0, ptr [[A]], align 4 +// SIMD-ONLY03-NEXT: store i8 0, ptr [[AAA]], align 1 +// SIMD-ONLY03-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY03-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// SIMD-ONLY03-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// SIMD-ONLY03-NEXT: [[TMP1:%.*]] = load i8, i8* [[AAA]], align 1 +// SIMD-ONLY03-NEXT: store i32 [[ADD]], ptr [[A]], align 4 +// SIMD-ONLY03-NEXT: [[TMP1:%.*]] = load i8, ptr [[AAA]], align 1 // SIMD-ONLY03-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32 // SIMD-ONLY03-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 // SIMD-ONLY03-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i8 -// SIMD-ONLY03-NEXT: store i8 [[CONV2]], i8* [[AAA]], align 1 -// SIMD-ONLY03-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// SIMD-ONLY03-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// SIMD-ONLY03-NEXT: store i8 [[CONV2]], ptr [[AAA]], align 1 +// SIMD-ONLY03-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i32 0, i32 2 +// SIMD-ONLY03-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // SIMD-ONLY03-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// SIMD-ONLY03-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// SIMD-ONLY03-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY03-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4 +// SIMD-ONLY03-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY03-NEXT: ret i32 [[TMP3]] // // @@ -10283,1078 +9975,996 @@ int bar(int n, double *ptr) { // SIMD-ONLY03-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // SIMD-ONLY03-NEXT: [[A:%.*]] = alloca i32, align 4 // SIMD-ONLY03-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// SIMD-ONLY03-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// SIMD-ONLY03-NEXT: store i32 0, i32* [[A]], align 4 -// SIMD-ONLY03-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY03-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// SIMD-ONLY03-NEXT: store i32 0, ptr [[A]], align 4 +// SIMD-ONLY03-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY03-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// SIMD-ONLY03-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// SIMD-ONLY03-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// SIMD-ONLY03-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// SIMD-ONLY03-NEXT: store i32 [[ADD]], ptr [[A]], align 4 +// SIMD-ONLY03-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i32 0, i32 2 +// SIMD-ONLY03-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // SIMD-ONLY03-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP1]], 1 -// SIMD-ONLY03-NEXT: store i32 [[ADD1]], i32* [[ARRAYIDX]], align 4 -// SIMD-ONLY03-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY03-NEXT: store i32 [[ADD1]], ptr [[ARRAYIDX]], align 4 +// SIMD-ONLY03-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY03-NEXT: ret i32 [[TMP2]] // // // TCHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63 -// TCHECK-SAME: (i64 noundef [[A:%.*]], i32* noundef [[P:%.*]], i64 noundef [[GA:%.*]]) #[[ATTR0:[0-9]+]] { +// TCHECK-SAME: (i64 noundef [[A:%.*]], ptr noundef [[P:%.*]], i64 noundef [[GA:%.*]]) #[[ATTR0:[0-9]+]] { // TCHECK-NEXT: entry: // TCHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// TCHECK-NEXT: [[P_ADDR:%.*]] = alloca i32*, align 8 +// TCHECK-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 8 // TCHECK-NEXT: [[GA_ADDR:%.*]] = alloca i64, align 8 -// TCHECK-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// TCHECK-NEXT: store i32* [[P]], i32** [[P_ADDR]], align 8 -// TCHECK-NEXT: store i64 [[GA]], i64* [[GA_ADDR]], align 8 -// TCHECK-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// TCHECK-NEXT: [[CONV1:%.*]] = bitcast i64* [[GA_ADDR]] to i32* +// TCHECK-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 +// TCHECK-NEXT: store ptr [[P]], ptr [[P_ADDR]], align 8 +// TCHECK-NEXT: store i64 [[GA]], ptr [[GA_ADDR]], align 8 // TCHECK-NEXT: ret void // // // TCHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70 -// TCHECK-SAME: (i64 noundef [[AA:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { +// TCHECK-SAME: (i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { // TCHECK-NEXT: entry: // TCHECK-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// TCHECK-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// TCHECK-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 // TCHECK-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// TCHECK-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 -// TCHECK-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// TCHECK-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 8 +// TCHECK-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 // TCHECK-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 // TCHECK-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 -// TCHECK-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 -// TCHECK-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// TCHECK-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 8 +// TCHECK-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 // TCHECK-NEXT: [[B5:%.*]] = alloca [10 x float], align 4 -// TCHECK-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// TCHECK-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 // TCHECK-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 // TCHECK-NEXT: [[C7:%.*]] = alloca [5 x [10 x double]], align 8 // TCHECK-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 // TCHECK-NEXT: [[__VLA_EXPR2:%.*]] = alloca i64, align 8 // TCHECK-NEXT: [[D9:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 -// TCHECK-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// TCHECK-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 -// TCHECK-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// TCHECK-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 -// TCHECK-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 -// TCHECK-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// TCHECK-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 -// TCHECK-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 -// TCHECK-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 -// TCHECK-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// TCHECK-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 -// TCHECK-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// TCHECK-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 -// TCHECK-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 -// TCHECK-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// TCHECK-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 -// TCHECK-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 -// TCHECK-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 -// TCHECK-NEXT: [[TMP8:%.*]] = bitcast [10 x float]* [[B5]] to i8* -// TCHECK-NEXT: [[TMP9:%.*]] = bitcast [10 x float]* [[TMP0]] to i8* -// TCHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i64 40, i1 false) -// TCHECK-NEXT: [[TMP10:%.*]] = call i8* @llvm.stacksave() -// TCHECK-NEXT: store i8* [[TMP10]], i8** [[SAVED_STACK]], align 8 +// TCHECK-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 +// TCHECK-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 +// TCHECK-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 +// TCHECK-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 8 +// TCHECK-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 +// TCHECK-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 +// TCHECK-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8 +// TCHECK-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8 +// TCHECK-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 +// TCHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// TCHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 +// TCHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8 +// TCHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 +// TCHECK-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 +// TCHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8 +// TCHECK-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8 +// TCHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8 +// TCHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[B5]], ptr align 4 [[TMP0]], i64 40, i1 false) +// TCHECK-NEXT: [[TMP8:%.*]] = call ptr @llvm.stacksave() +// TCHECK-NEXT: store ptr [[TMP8]], ptr [[SAVED_STACK]], align 8 // TCHECK-NEXT: [[VLA6:%.*]] = alloca float, i64 [[TMP1]], align 4 -// TCHECK-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// TCHECK-NEXT: [[TMP11:%.*]] = mul nuw i64 [[TMP1]], 4 -// TCHECK-NEXT: [[TMP12:%.*]] = bitcast float* [[VLA6]] to i8* -// TCHECK-NEXT: [[TMP13:%.*]] = bitcast float* [[TMP2]] to i8* -// TCHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 [[TMP11]], i1 false) -// TCHECK-NEXT: [[TMP14:%.*]] = bitcast [5 x [10 x double]]* [[C7]] to i8* -// TCHECK-NEXT: [[TMP15:%.*]] = bitcast [5 x [10 x double]]* [[TMP3]] to i8* -// TCHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP14]], i8* align 8 [[TMP15]], i64 400, i1 false) -// TCHECK-NEXT: [[TMP16:%.*]] = mul nuw i64 [[TMP4]], [[TMP5]] -// TCHECK-NEXT: [[VLA8:%.*]] = alloca double, i64 [[TMP16]], align 8 -// TCHECK-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// TCHECK-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR2]], align 8 -// TCHECK-NEXT: [[TMP17:%.*]] = mul nuw i64 [[TMP4]], [[TMP5]] -// TCHECK-NEXT: [[TMP18:%.*]] = mul nuw i64 [[TMP17]], 8 -// TCHECK-NEXT: [[TMP19:%.*]] = bitcast double* [[VLA8]] to i8* -// TCHECK-NEXT: [[TMP20:%.*]] = bitcast double* [[TMP6]] to i8* -// TCHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP19]], i8* align 8 [[TMP20]], i64 [[TMP18]], i1 false) -// TCHECK-NEXT: [[TMP21:%.*]] = bitcast %struct.TT* [[D9]] to i8* -// TCHECK-NEXT: [[TMP22:%.*]] = bitcast %struct.TT* [[TMP7]] to i8* -// TCHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP21]], i8* align 8 [[TMP22]], i64 16, i1 false) -// TCHECK-NEXT: [[TMP23:%.*]] = load i16, i16* [[CONV]], align 2 -// TCHECK-NEXT: [[CONV10:%.*]] = sext i16 [[TMP23]] to i32 -// TCHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV10]], 1 -// TCHECK-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD]] to i16 -// TCHECK-NEXT: store i16 [[CONV11]], i16* [[CONV]], align 2 -// TCHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B5]], i64 0, i64 2 -// TCHECK-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4 -// TCHECK-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA6]], i64 3 -// TCHECK-NEXT: store float 1.000000e+00, float* [[ARRAYIDX12]], align 4 -// TCHECK-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C7]], i64 0, i64 1 -// TCHECK-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], i64 0, i64 2 -// TCHECK-NEXT: store double 1.000000e+00, double* [[ARRAYIDX14]], align 8 -// TCHECK-NEXT: [[TMP24:%.*]] = mul nsw i64 1, [[TMP5]] -// TCHECK-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[VLA8]], i64 [[TMP24]] -// TCHECK-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 -// TCHECK-NEXT: store double 1.000000e+00, double* [[ARRAYIDX16]], align 8 -// TCHECK-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 0 -// TCHECK-NEXT: store i64 1, i64* [[X]], align 8 -// TCHECK-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 1 -// TCHECK-NEXT: store i8 1, i8* [[Y]], align 8 -// TCHECK-NEXT: [[TMP25:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// TCHECK-NEXT: call void @llvm.stackrestore(i8* [[TMP25]]) +// TCHECK-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 +// TCHECK-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP1]], 4 +// TCHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VLA6]], ptr align 4 [[TMP2]], i64 [[TMP9]], i1 false) +// TCHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[C7]], ptr align 8 [[TMP3]], i64 400, i1 false) +// TCHECK-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP4]], [[TMP5]] +// TCHECK-NEXT: [[VLA8:%.*]] = alloca double, i64 [[TMP10]], align 8 +// TCHECK-NEXT: store i64 [[TMP4]], ptr [[__VLA_EXPR1]], align 8 +// TCHECK-NEXT: store i64 [[TMP5]], ptr [[__VLA_EXPR2]], align 8 +// TCHECK-NEXT: [[TMP11:%.*]] = mul nuw i64 [[TMP4]], [[TMP5]] +// TCHECK-NEXT: [[TMP12:%.*]] = mul nuw i64 [[TMP11]], 8 +// TCHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[VLA8]], ptr align 8 [[TMP6]], i64 [[TMP12]], i1 false) +// TCHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[D9]], ptr align 8 [[TMP7]], i64 16, i1 false) +// TCHECK-NEXT: [[TMP13:%.*]] = load i16, ptr [[AA_ADDR]], align 2 +// TCHECK-NEXT: [[CONV:%.*]] = sext i16 [[TMP13]] to i32 +// TCHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 +// TCHECK-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16 +// TCHECK-NEXT: store i16 [[CONV10]], ptr [[AA_ADDR]], align 2 +// TCHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B5]], i64 0, i64 2 +// TCHECK-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX]], align 4 +// TCHECK-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds float, ptr [[VLA6]], i64 3 +// TCHECK-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX11]], align 4 +// TCHECK-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C7]], i64 0, i64 1 +// TCHECK-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX12]], i64 0, i64 2 +// TCHECK-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX13]], align 8 +// TCHECK-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP5]] +// TCHECK-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, ptr [[VLA8]], i64 [[TMP14]] +// TCHECK-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX14]], i64 3 +// TCHECK-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX15]], align 8 +// TCHECK-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D9]], i32 0, i32 0 +// TCHECK-NEXT: store i64 1, ptr [[X]], align 8 +// TCHECK-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D9]], i32 0, i32 1 +// TCHECK-NEXT: store i8 1, ptr [[Y]], align 8 +// TCHECK-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 +// TCHECK-NEXT: call void @llvm.stackrestore(ptr [[TMP15]]) // TCHECK-NEXT: ret void // // // TCHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111 -// TCHECK-SAME: (double* noundef [[PTR:%.*]], %struct.TT.0* noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR0]] { +// TCHECK-SAME: (ptr noundef [[PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR0]] { // TCHECK-NEXT: entry: -// TCHECK-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 8 -// TCHECK-NEXT: [[E_ADDR:%.*]] = alloca %struct.TT.0*, align 8 -// TCHECK-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 8 -// TCHECK-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[E_ADDR]], align 8 -// TCHECK-NEXT: [[TMP0:%.*]] = load %struct.TT.0*, %struct.TT.0** [[E_ADDR]], align 8 -// TCHECK-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0:%.*]], %struct.TT.0* [[TMP0]], i32 0, i32 0 -// TCHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[X]], align 4 +// TCHECK-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8 +// TCHECK-NEXT: [[E_ADDR:%.*]] = alloca ptr, align 8 +// TCHECK-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 8 +// TCHECK-NEXT: store ptr [[E]], ptr [[E_ADDR]], align 8 +// TCHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[E_ADDR]], align 8 +// TCHECK-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0:%.*]], ptr [[TMP0]], i32 0, i32 0 +// TCHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[X]], align 4 // TCHECK-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double -// TCHECK-NEXT: [[TMP2:%.*]] = load double*, double** [[PTR_ADDR]], align 8 -// TCHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP2]], i64 0 -// TCHECK-NEXT: store double [[CONV]], double* [[ARRAYIDX]], align 8 -// TCHECK-NEXT: [[TMP3:%.*]] = load double*, double** [[PTR_ADDR]], align 8 -// TCHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds double, double* [[TMP3]], i64 0 -// TCHECK-NEXT: [[TMP4:%.*]] = load double, double* [[ARRAYIDX1]], align 8 +// TCHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8 +// TCHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[TMP2]], i64 0 +// TCHECK-NEXT: store double [[CONV]], ptr [[ARRAYIDX]], align 8 +// TCHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8 +// TCHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds double, ptr [[TMP3]], i64 0 +// TCHECK-NEXT: [[TMP4:%.*]] = load double, ptr [[ARRAYIDX1]], align 8 // TCHECK-NEXT: [[INC:%.*]] = fadd double [[TMP4]], 1.000000e+00 -// TCHECK-NEXT: store double [[INC]], double* [[ARRAYIDX1]], align 8 +// TCHECK-NEXT: store double [[INC]], ptr [[ARRAYIDX1]], align 8 // TCHECK-NEXT: ret void // // // TCHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142 -// TCHECK-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// TCHECK-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // TCHECK-NEXT: entry: // TCHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // TCHECK-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 -// TCHECK-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// TCHECK-NEXT: [[B2:%.*]] = alloca [10 x i32], align 4 -// TCHECK-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// TCHECK-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 -// TCHECK-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// TCHECK-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// TCHECK-NEXT: [[CONV1:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* -// TCHECK-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// TCHECK-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B2]] to i8* -// TCHECK-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8* -// TCHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i64 40, i1 false) -// TCHECK-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4 -// TCHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 -// TCHECK-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 -// TCHECK-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 1 -// TCHECK-NEXT: [[CONV3:%.*]] = sext i8 [[TMP4]] to i32 -// TCHECK-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// TCHECK-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// TCHECK-NEXT: store i8 [[CONV5]], i8* [[CONV1]], align 1 -// TCHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B2]], i64 0, i64 2 -// TCHECK-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// TCHECK-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP5]], 1 -// TCHECK-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 +// TCHECK-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 +// TCHECK-NEXT: [[B1:%.*]] = alloca [10 x i32], align 4 +// TCHECK-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 +// TCHECK-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8 +// TCHECK-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 +// TCHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// TCHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[B1]], ptr align 4 [[TMP0]], i64 40, i1 false) +// TCHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 +// TCHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// TCHECK-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 +// TCHECK-NEXT: [[TMP2:%.*]] = load i8, ptr [[AAA_ADDR]], align 1 +// TCHECK-NEXT: [[CONV:%.*]] = sext i8 [[TMP2]] to i32 +// TCHECK-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 +// TCHECK-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i8 +// TCHECK-NEXT: store i8 [[CONV3]], ptr [[AAA_ADDR]], align 1 +// TCHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B1]], i64 0, i64 2 +// TCHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// TCHECK-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 +// TCHECK-NEXT: store i32 [[ADD4]], ptr [[ARRAYIDX]], align 4 // TCHECK-NEXT: ret void // // // TCHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167 -// TCHECK-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// TCHECK-SAME: (ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // TCHECK-NEXT: entry: -// TCHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// TCHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // TCHECK-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // TCHECK-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 // TCHECK-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// TCHECK-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 -// TCHECK-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// TCHECK-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 +// TCHECK-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 // TCHECK-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 // TCHECK-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// TCHECK-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// TCHECK-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// TCHECK-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// TCHECK-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// TCHECK-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 -// TCHECK-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// TCHECK-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// TCHECK-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// TCHECK-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// TCHECK-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 -// TCHECK-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave() -// TCHECK-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8 +// TCHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// TCHECK-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 +// TCHECK-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 +// TCHECK-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 +// TCHECK-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 +// TCHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// TCHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 +// TCHECK-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 +// TCHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 +// TCHECK-NEXT: [[TMP4:%.*]] = call ptr @llvm.stacksave() +// TCHECK-NEXT: store ptr [[TMP4]], ptr [[SAVED_STACK]], align 8 // TCHECK-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP2]] // TCHECK-NEXT: [[VLA3:%.*]] = alloca i16, i64 [[TMP5]], align 2 -// TCHECK-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// TCHECK-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR1]], align 8 +// TCHECK-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 +// TCHECK-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR1]], align 8 // TCHECK-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP1]], [[TMP2]] // TCHECK-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP6]], 2 -// TCHECK-NEXT: [[TMP8:%.*]] = bitcast i16* [[VLA3]] to i8* -// TCHECK-NEXT: [[TMP9:%.*]] = bitcast i16* [[TMP3]] to i8* -// TCHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 2 [[TMP8]], i8* align 2 [[TMP9]], i64 [[TMP7]], i1 false) -// TCHECK-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4 -// TCHECK-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP10]] to double -// TCHECK-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00 -// TCHECK-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// TCHECK-NEXT: store double [[ADD]], double* [[A]], align 8 -// TCHECK-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 -// TCHECK-NEXT: [[TMP11:%.*]] = load double, double* [[A5]], align 8 -// TCHECK-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+00 -// TCHECK-NEXT: store double [[INC]], double* [[A5]], align 8 -// TCHECK-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 -// TCHECK-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP2]] -// TCHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA3]], i64 [[TMP12]] -// TCHECK-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// TCHECK-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2 -// TCHECK-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// TCHECK-NEXT: call void @llvm.stackrestore(i8* [[TMP13]]) +// TCHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 2 [[VLA3]], ptr align 2 [[TMP3]], i64 [[TMP7]], i1 false) +// TCHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[B_ADDR]], align 4 +// TCHECK-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP8]] to double +// TCHECK-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 +// TCHECK-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0 +// TCHECK-NEXT: store double [[ADD]], ptr [[A]], align 8 +// TCHECK-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 +// TCHECK-NEXT: [[TMP9:%.*]] = load double, ptr [[A4]], align 8 +// TCHECK-NEXT: [[INC:%.*]] = fadd double [[TMP9]], 1.000000e+00 +// TCHECK-NEXT: store double [[INC]], ptr [[A4]], align 8 +// TCHECK-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 +// TCHECK-NEXT: [[TMP10:%.*]] = mul nsw i64 1, [[TMP2]] +// TCHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA3]], i64 [[TMP10]] +// TCHECK-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1 +// TCHECK-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2 +// TCHECK-NEXT: [[TMP11:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 +// TCHECK-NEXT: call void @llvm.stackrestore(ptr [[TMP11]]) // TCHECK-NEXT: ret void // // // TCHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128 -// TCHECK-SAME: (i64 noundef [[A:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// TCHECK-SAME: (i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // TCHECK-NEXT: entry: // TCHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// TCHECK-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// TCHECK-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 // TCHECK-NEXT: [[B1:%.*]] = alloca [10 x i32], align 4 -// TCHECK-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// TCHECK-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// TCHECK-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// TCHECK-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// TCHECK-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B1]] to i8* -// TCHECK-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8* -// TCHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i64 40, i1 false) -// TCHECK-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4 -// TCHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 -// TCHECK-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 -// TCHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], i64 0, i64 2 -// TCHECK-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// TCHECK-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], 1 -// TCHECK-NEXT: store i32 [[ADD2]], i32* [[ARRAYIDX]], align 4 +// TCHECK-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 +// TCHECK-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 +// TCHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// TCHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[B1]], ptr align 4 [[TMP0]], i64 40, i1 false) +// TCHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 +// TCHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// TCHECK-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 +// TCHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B1]], i64 0, i64 2 +// TCHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// TCHECK-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 +// TCHECK-NEXT: store i32 [[ADD2]], ptr [[ARRAYIDX]], align 4 // TCHECK-NEXT: ret void // // // TCHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63 -// TCHECK1-SAME: (i64 noundef [[A:%.*]], i32* noundef [[P:%.*]], i64 noundef [[GA:%.*]]) #[[ATTR0:[0-9]+]] { +// TCHECK1-SAME: (i64 noundef [[A:%.*]], ptr noundef [[P:%.*]], i64 noundef [[GA:%.*]]) #[[ATTR0:[0-9]+]] { // TCHECK1-NEXT: entry: // TCHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// TCHECK1-NEXT: [[P_ADDR:%.*]] = alloca i32*, align 8 +// TCHECK1-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 8 // TCHECK1-NEXT: [[GA_ADDR:%.*]] = alloca i64, align 8 -// TCHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// TCHECK1-NEXT: store i32* [[P]], i32** [[P_ADDR]], align 8 -// TCHECK1-NEXT: store i64 [[GA]], i64* [[GA_ADDR]], align 8 -// TCHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// TCHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[GA_ADDR]] to i32* +// TCHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 +// TCHECK1-NEXT: store ptr [[P]], ptr [[P_ADDR]], align 8 +// TCHECK1-NEXT: store i64 [[GA]], ptr [[GA_ADDR]], align 8 // TCHECK1-NEXT: ret void // // // TCHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70 -// TCHECK1-SAME: (i64 noundef [[AA:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { +// TCHECK1-SAME: (i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { // TCHECK1-NEXT: entry: // TCHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 -// TCHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 +// TCHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 // TCHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// TCHECK1-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 -// TCHECK1-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 +// TCHECK1-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 8 +// TCHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 // TCHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 // TCHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 -// TCHECK1-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 -// TCHECK1-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 +// TCHECK1-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 8 +// TCHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 // TCHECK1-NEXT: [[B5:%.*]] = alloca [10 x float], align 4 -// TCHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// TCHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 // TCHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 // TCHECK1-NEXT: [[C7:%.*]] = alloca [5 x [10 x double]], align 8 // TCHECK1-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 // TCHECK1-NEXT: [[__VLA_EXPR2:%.*]] = alloca i64, align 8 // TCHECK1-NEXT: [[D9:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 -// TCHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 -// TCHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 -// TCHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// TCHECK1-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 -// TCHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 -// TCHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// TCHECK1-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 -// TCHECK1-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 -// TCHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 -// TCHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* -// TCHECK1-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 -// TCHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// TCHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 -// TCHECK1-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 -// TCHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// TCHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 -// TCHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 -// TCHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 -// TCHECK1-NEXT: [[TMP8:%.*]] = bitcast [10 x float]* [[B5]] to i8* -// TCHECK1-NEXT: [[TMP9:%.*]] = bitcast [10 x float]* [[TMP0]] to i8* -// TCHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i64 40, i1 false) -// TCHECK1-NEXT: [[TMP10:%.*]] = call i8* @llvm.stacksave() -// TCHECK1-NEXT: store i8* [[TMP10]], i8** [[SAVED_STACK]], align 8 +// TCHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 +// TCHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 +// TCHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 +// TCHECK1-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 8 +// TCHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 +// TCHECK1-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 +// TCHECK1-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8 +// TCHECK1-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8 +// TCHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 +// TCHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// TCHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 +// TCHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8 +// TCHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 +// TCHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 +// TCHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8 +// TCHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8 +// TCHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8 +// TCHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[B5]], ptr align 4 [[TMP0]], i64 40, i1 false) +// TCHECK1-NEXT: [[TMP8:%.*]] = call ptr @llvm.stacksave() +// TCHECK1-NEXT: store ptr [[TMP8]], ptr [[SAVED_STACK]], align 8 // TCHECK1-NEXT: [[VLA6:%.*]] = alloca float, i64 [[TMP1]], align 4 -// TCHECK1-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// TCHECK1-NEXT: [[TMP11:%.*]] = mul nuw i64 [[TMP1]], 4 -// TCHECK1-NEXT: [[TMP12:%.*]] = bitcast float* [[VLA6]] to i8* -// TCHECK1-NEXT: [[TMP13:%.*]] = bitcast float* [[TMP2]] to i8* -// TCHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 [[TMP11]], i1 false) -// TCHECK1-NEXT: [[TMP14:%.*]] = bitcast [5 x [10 x double]]* [[C7]] to i8* -// TCHECK1-NEXT: [[TMP15:%.*]] = bitcast [5 x [10 x double]]* [[TMP3]] to i8* -// TCHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP14]], i8* align 8 [[TMP15]], i64 400, i1 false) -// TCHECK1-NEXT: [[TMP16:%.*]] = mul nuw i64 [[TMP4]], [[TMP5]] -// TCHECK1-NEXT: [[VLA8:%.*]] = alloca double, i64 [[TMP16]], align 8 -// TCHECK1-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// TCHECK1-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR2]], align 8 -// TCHECK1-NEXT: [[TMP17:%.*]] = mul nuw i64 [[TMP4]], [[TMP5]] -// TCHECK1-NEXT: [[TMP18:%.*]] = mul nuw i64 [[TMP17]], 8 -// TCHECK1-NEXT: [[TMP19:%.*]] = bitcast double* [[VLA8]] to i8* -// TCHECK1-NEXT: [[TMP20:%.*]] = bitcast double* [[TMP6]] to i8* -// TCHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP19]], i8* align 8 [[TMP20]], i64 [[TMP18]], i1 false) -// TCHECK1-NEXT: [[TMP21:%.*]] = bitcast %struct.TT* [[D9]] to i8* -// TCHECK1-NEXT: [[TMP22:%.*]] = bitcast %struct.TT* [[TMP7]] to i8* -// TCHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP21]], i8* align 8 [[TMP22]], i64 16, i1 false) -// TCHECK1-NEXT: [[TMP23:%.*]] = load i16, i16* [[CONV]], align 2 -// TCHECK1-NEXT: [[CONV10:%.*]] = sext i16 [[TMP23]] to i32 -// TCHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV10]], 1 -// TCHECK1-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD]] to i16 -// TCHECK1-NEXT: store i16 [[CONV11]], i16* [[CONV]], align 2 -// TCHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B5]], i64 0, i64 2 -// TCHECK1-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4 -// TCHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA6]], i64 3 -// TCHECK1-NEXT: store float 1.000000e+00, float* [[ARRAYIDX12]], align 4 -// TCHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C7]], i64 0, i64 1 -// TCHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], i64 0, i64 2 -// TCHECK1-NEXT: store double 1.000000e+00, double* [[ARRAYIDX14]], align 8 -// TCHECK1-NEXT: [[TMP24:%.*]] = mul nsw i64 1, [[TMP5]] -// TCHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[VLA8]], i64 [[TMP24]] -// TCHECK1-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 -// TCHECK1-NEXT: store double 1.000000e+00, double* [[ARRAYIDX16]], align 8 -// TCHECK1-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 0 -// TCHECK1-NEXT: store i64 1, i64* [[X]], align 8 -// TCHECK1-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 1 -// TCHECK1-NEXT: store i8 1, i8* [[Y]], align 8 -// TCHECK1-NEXT: [[TMP25:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// TCHECK1-NEXT: call void @llvm.stackrestore(i8* [[TMP25]]) +// TCHECK1-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 +// TCHECK1-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP1]], 4 +// TCHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VLA6]], ptr align 4 [[TMP2]], i64 [[TMP9]], i1 false) +// TCHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[C7]], ptr align 8 [[TMP3]], i64 400, i1 false) +// TCHECK1-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP4]], [[TMP5]] +// TCHECK1-NEXT: [[VLA8:%.*]] = alloca double, i64 [[TMP10]], align 8 +// TCHECK1-NEXT: store i64 [[TMP4]], ptr [[__VLA_EXPR1]], align 8 +// TCHECK1-NEXT: store i64 [[TMP5]], ptr [[__VLA_EXPR2]], align 8 +// TCHECK1-NEXT: [[TMP11:%.*]] = mul nuw i64 [[TMP4]], [[TMP5]] +// TCHECK1-NEXT: [[TMP12:%.*]] = mul nuw i64 [[TMP11]], 8 +// TCHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[VLA8]], ptr align 8 [[TMP6]], i64 [[TMP12]], i1 false) +// TCHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[D9]], ptr align 8 [[TMP7]], i64 16, i1 false) +// TCHECK1-NEXT: [[TMP13:%.*]] = load i16, ptr [[AA_ADDR]], align 2 +// TCHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP13]] to i32 +// TCHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 +// TCHECK1-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16 +// TCHECK1-NEXT: store i16 [[CONV10]], ptr [[AA_ADDR]], align 2 +// TCHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B5]], i64 0, i64 2 +// TCHECK1-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX]], align 4 +// TCHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds float, ptr [[VLA6]], i64 3 +// TCHECK1-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX11]], align 4 +// TCHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C7]], i64 0, i64 1 +// TCHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX12]], i64 0, i64 2 +// TCHECK1-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX13]], align 8 +// TCHECK1-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP5]] +// TCHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, ptr [[VLA8]], i64 [[TMP14]] +// TCHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX14]], i64 3 +// TCHECK1-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX15]], align 8 +// TCHECK1-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D9]], i32 0, i32 0 +// TCHECK1-NEXT: store i64 1, ptr [[X]], align 8 +// TCHECK1-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D9]], i32 0, i32 1 +// TCHECK1-NEXT: store i8 1, ptr [[Y]], align 8 +// TCHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 +// TCHECK1-NEXT: call void @llvm.stackrestore(ptr [[TMP15]]) // TCHECK1-NEXT: ret void // // // TCHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111 -// TCHECK1-SAME: (double* noundef [[PTR:%.*]], %struct.TT.0* noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR0]] { +// TCHECK1-SAME: (ptr noundef [[PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR0]] { // TCHECK1-NEXT: entry: -// TCHECK1-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 8 -// TCHECK1-NEXT: [[E_ADDR:%.*]] = alloca %struct.TT.0*, align 8 -// TCHECK1-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 8 -// TCHECK1-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[E_ADDR]], align 8 -// TCHECK1-NEXT: [[TMP0:%.*]] = load %struct.TT.0*, %struct.TT.0** [[E_ADDR]], align 8 -// TCHECK1-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0:%.*]], %struct.TT.0* [[TMP0]], i32 0, i32 0 -// TCHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[X]], align 4 +// TCHECK1-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8 +// TCHECK1-NEXT: [[E_ADDR:%.*]] = alloca ptr, align 8 +// TCHECK1-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 8 +// TCHECK1-NEXT: store ptr [[E]], ptr [[E_ADDR]], align 8 +// TCHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[E_ADDR]], align 8 +// TCHECK1-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0:%.*]], ptr [[TMP0]], i32 0, i32 0 +// TCHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[X]], align 4 // TCHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double -// TCHECK1-NEXT: [[TMP2:%.*]] = load double*, double** [[PTR_ADDR]], align 8 -// TCHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP2]], i64 0 -// TCHECK1-NEXT: store double [[CONV]], double* [[ARRAYIDX]], align 8 -// TCHECK1-NEXT: [[TMP3:%.*]] = load double*, double** [[PTR_ADDR]], align 8 -// TCHECK1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds double, double* [[TMP3]], i64 0 -// TCHECK1-NEXT: [[TMP4:%.*]] = load double, double* [[ARRAYIDX1]], align 8 +// TCHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8 +// TCHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[TMP2]], i64 0 +// TCHECK1-NEXT: store double [[CONV]], ptr [[ARRAYIDX]], align 8 +// TCHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8 +// TCHECK1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds double, ptr [[TMP3]], i64 0 +// TCHECK1-NEXT: [[TMP4:%.*]] = load double, ptr [[ARRAYIDX1]], align 8 // TCHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP4]], 1.000000e+00 -// TCHECK1-NEXT: store double [[INC]], double* [[ARRAYIDX1]], align 8 +// TCHECK1-NEXT: store double [[INC]], ptr [[ARRAYIDX1]], align 8 // TCHECK1-NEXT: ret void // // // TCHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142 -// TCHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// TCHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // TCHECK1-NEXT: entry: // TCHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // TCHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 -// TCHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 -// TCHECK1-NEXT: [[B2:%.*]] = alloca [10 x i32], align 4 -// TCHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// TCHECK1-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 -// TCHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// TCHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// TCHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* -// TCHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// TCHECK1-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B2]] to i8* -// TCHECK1-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8* -// TCHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i64 40, i1 false) -// TCHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4 -// TCHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 -// TCHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 -// TCHECK1-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 1 -// TCHECK1-NEXT: [[CONV3:%.*]] = sext i8 [[TMP4]] to i32 -// TCHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 -// TCHECK1-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 -// TCHECK1-NEXT: store i8 [[CONV5]], i8* [[CONV1]], align 1 -// TCHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B2]], i64 0, i64 2 -// TCHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// TCHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP5]], 1 -// TCHECK1-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 +// TCHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 +// TCHECK1-NEXT: [[B1:%.*]] = alloca [10 x i32], align 4 +// TCHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 +// TCHECK1-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8 +// TCHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 +// TCHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// TCHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[B1]], ptr align 4 [[TMP0]], i64 40, i1 false) +// TCHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 +// TCHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// TCHECK1-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 +// TCHECK1-NEXT: [[TMP2:%.*]] = load i8, ptr [[AAA_ADDR]], align 1 +// TCHECK1-NEXT: [[CONV:%.*]] = sext i8 [[TMP2]] to i32 +// TCHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 +// TCHECK1-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i8 +// TCHECK1-NEXT: store i8 [[CONV3]], ptr [[AAA_ADDR]], align 1 +// TCHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B1]], i64 0, i64 2 +// TCHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// TCHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 +// TCHECK1-NEXT: store i32 [[ADD4]], ptr [[ARRAYIDX]], align 4 // TCHECK1-NEXT: ret void // // // TCHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167 -// TCHECK1-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// TCHECK1-SAME: (ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // TCHECK1-NEXT: entry: -// TCHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// TCHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // TCHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 // TCHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 // TCHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// TCHECK1-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 -// TCHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// TCHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 +// TCHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 // TCHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 // TCHECK1-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 -// TCHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// TCHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 -// TCHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 -// TCHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 -// TCHECK1-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 -// TCHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// TCHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* -// TCHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 -// TCHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 -// TCHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 -// TCHECK1-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave() -// TCHECK1-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8 +// TCHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// TCHECK1-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 +// TCHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 +// TCHECK1-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 +// TCHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 +// TCHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// TCHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 +// TCHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 +// TCHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 +// TCHECK1-NEXT: [[TMP4:%.*]] = call ptr @llvm.stacksave() +// TCHECK1-NEXT: store ptr [[TMP4]], ptr [[SAVED_STACK]], align 8 // TCHECK1-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP2]] // TCHECK1-NEXT: [[VLA3:%.*]] = alloca i16, i64 [[TMP5]], align 2 -// TCHECK1-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// TCHECK1-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR1]], align 8 +// TCHECK1-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 +// TCHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR1]], align 8 // TCHECK1-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP1]], [[TMP2]] // TCHECK1-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP6]], 2 -// TCHECK1-NEXT: [[TMP8:%.*]] = bitcast i16* [[VLA3]] to i8* -// TCHECK1-NEXT: [[TMP9:%.*]] = bitcast i16* [[TMP3]] to i8* -// TCHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 2 [[TMP8]], i8* align 2 [[TMP9]], i64 [[TMP7]], i1 false) -// TCHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4 -// TCHECK1-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP10]] to double -// TCHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00 -// TCHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// TCHECK1-NEXT: store double [[ADD]], double* [[A]], align 8 -// TCHECK1-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 -// TCHECK1-NEXT: [[TMP11:%.*]] = load double, double* [[A5]], align 8 -// TCHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+00 -// TCHECK1-NEXT: store double [[INC]], double* [[A5]], align 8 -// TCHECK1-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 -// TCHECK1-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP2]] -// TCHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA3]], i64 [[TMP12]] -// TCHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// TCHECK1-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2 -// TCHECK1-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// TCHECK1-NEXT: call void @llvm.stackrestore(i8* [[TMP13]]) +// TCHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 2 [[VLA3]], ptr align 2 [[TMP3]], i64 [[TMP7]], i1 false) +// TCHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[B_ADDR]], align 4 +// TCHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP8]] to double +// TCHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 +// TCHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0 +// TCHECK1-NEXT: store double [[ADD]], ptr [[A]], align 8 +// TCHECK1-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 +// TCHECK1-NEXT: [[TMP9:%.*]] = load double, ptr [[A4]], align 8 +// TCHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP9]], 1.000000e+00 +// TCHECK1-NEXT: store double [[INC]], ptr [[A4]], align 8 +// TCHECK1-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 +// TCHECK1-NEXT: [[TMP10:%.*]] = mul nsw i64 1, [[TMP2]] +// TCHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA3]], i64 [[TMP10]] +// TCHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1 +// TCHECK1-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2 +// TCHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 +// TCHECK1-NEXT: call void @llvm.stackrestore(ptr [[TMP11]]) // TCHECK1-NEXT: ret void // // // TCHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128 -// TCHECK1-SAME: (i64 noundef [[A:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// TCHECK1-SAME: (i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // TCHECK1-NEXT: entry: // TCHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 -// TCHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 +// TCHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 // TCHECK1-NEXT: [[B1:%.*]] = alloca [10 x i32], align 4 -// TCHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 -// TCHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 -// TCHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* -// TCHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 -// TCHECK1-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B1]] to i8* -// TCHECK1-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8* -// TCHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i64 40, i1 false) -// TCHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4 -// TCHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 -// TCHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 -// TCHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], i64 0, i64 2 -// TCHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// TCHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], 1 -// TCHECK1-NEXT: store i32 [[ADD2]], i32* [[ARRAYIDX]], align 4 +// TCHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 +// TCHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 +// TCHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// TCHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[B1]], ptr align 4 [[TMP0]], i64 40, i1 false) +// TCHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 +// TCHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// TCHECK1-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 +// TCHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B1]], i64 0, i64 2 +// TCHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// TCHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 +// TCHECK1-NEXT: store i32 [[ADD2]], ptr [[ARRAYIDX]], align 4 // TCHECK1-NEXT: ret void // // // TCHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63 -// TCHECK2-SAME: (i32 noundef [[A:%.*]], i32* noundef [[P:%.*]], i32 noundef [[GA:%.*]]) #[[ATTR0:[0-9]+]] { +// TCHECK2-SAME: (i32 noundef [[A:%.*]], ptr noundef [[P:%.*]], i32 noundef [[GA:%.*]]) #[[ATTR0:[0-9]+]] { // TCHECK2-NEXT: entry: // TCHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// TCHECK2-NEXT: [[P_ADDR:%.*]] = alloca i32*, align 4 +// TCHECK2-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 4 // TCHECK2-NEXT: [[GA_ADDR:%.*]] = alloca i32, align 4 -// TCHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// TCHECK2-NEXT: store i32* [[P]], i32** [[P_ADDR]], align 4 -// TCHECK2-NEXT: store i32 [[GA]], i32* [[GA_ADDR]], align 4 +// TCHECK2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 +// TCHECK2-NEXT: store ptr [[P]], ptr [[P_ADDR]], align 4 +// TCHECK2-NEXT: store i32 [[GA]], ptr [[GA_ADDR]], align 4 // TCHECK2-NEXT: ret void // // // TCHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70 -// TCHECK2-SAME: (i32 noundef [[AA:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { +// TCHECK2-SAME: (i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { // TCHECK2-NEXT: entry: // TCHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// TCHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// TCHECK2-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 // TCHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// TCHECK2-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 -// TCHECK2-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// TCHECK2-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 4 +// TCHECK2-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 // TCHECK2-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 // TCHECK2-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 -// TCHECK2-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 -// TCHECK2-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// TCHECK2-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 4 +// TCHECK2-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 // TCHECK2-NEXT: [[B5:%.*]] = alloca [10 x float], align 4 -// TCHECK2-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// TCHECK2-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4 // TCHECK2-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 // TCHECK2-NEXT: [[C7:%.*]] = alloca [5 x [10 x double]], align 8 // TCHECK2-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 // TCHECK2-NEXT: [[__VLA_EXPR2:%.*]] = alloca i32, align 4 // TCHECK2-NEXT: [[D9:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 -// TCHECK2-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// TCHECK2-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 -// TCHECK2-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// TCHECK2-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 -// TCHECK2-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 -// TCHECK2-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// TCHECK2-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 -// TCHECK2-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 -// TCHECK2-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 -// TCHECK2-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// TCHECK2-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 -// TCHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// TCHECK2-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 -// TCHECK2-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 -// TCHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// TCHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 -// TCHECK2-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 -// TCHECK2-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 -// TCHECK2-NEXT: [[TMP8:%.*]] = bitcast [10 x float]* [[B5]] to i8* -// TCHECK2-NEXT: [[TMP9:%.*]] = bitcast [10 x float]* [[TMP0]] to i8* -// TCHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i32 40, i1 false) -// TCHECK2-NEXT: [[TMP10:%.*]] = call i8* @llvm.stacksave() -// TCHECK2-NEXT: store i8* [[TMP10]], i8** [[SAVED_STACK]], align 4 +// TCHECK2-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 +// TCHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 +// TCHECK2-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 +// TCHECK2-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 4 +// TCHECK2-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 +// TCHECK2-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 +// TCHECK2-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4 +// TCHECK2-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4 +// TCHECK2-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 +// TCHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 +// TCHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 +// TCHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4 +// TCHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 +// TCHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 +// TCHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4 +// TCHECK2-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4 +// TCHECK2-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4 +// TCHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[B5]], ptr align 4 [[TMP0]], i32 40, i1 false) +// TCHECK2-NEXT: [[TMP8:%.*]] = call ptr @llvm.stacksave() +// TCHECK2-NEXT: store ptr [[TMP8]], ptr [[SAVED_STACK]], align 4 // TCHECK2-NEXT: [[VLA6:%.*]] = alloca float, i32 [[TMP1]], align 4 -// TCHECK2-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// TCHECK2-NEXT: [[TMP11:%.*]] = mul nuw i32 [[TMP1]], 4 -// TCHECK2-NEXT: [[TMP12:%.*]] = bitcast float* [[VLA6]] to i8* -// TCHECK2-NEXT: [[TMP13:%.*]] = bitcast float* [[TMP2]] to i8* -// TCHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 [[TMP11]], i1 false) -// TCHECK2-NEXT: [[TMP14:%.*]] = bitcast [5 x [10 x double]]* [[C7]] to i8* -// TCHECK2-NEXT: [[TMP15:%.*]] = bitcast [5 x [10 x double]]* [[TMP3]] to i8* -// TCHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 [[TMP14]], i8* align 8 [[TMP15]], i32 400, i1 false) -// TCHECK2-NEXT: [[TMP16:%.*]] = mul nuw i32 [[TMP4]], [[TMP5]] -// TCHECK2-NEXT: [[VLA8:%.*]] = alloca double, i32 [[TMP16]], align 8 -// TCHECK2-NEXT: store i32 [[TMP4]], i32* [[__VLA_EXPR1]], align 4 -// TCHECK2-NEXT: store i32 [[TMP5]], i32* [[__VLA_EXPR2]], align 4 -// TCHECK2-NEXT: [[TMP17:%.*]] = mul nuw i32 [[TMP4]], [[TMP5]] -// TCHECK2-NEXT: [[TMP18:%.*]] = mul nuw i32 [[TMP17]], 8 -// TCHECK2-NEXT: [[TMP19:%.*]] = bitcast double* [[VLA8]] to i8* -// TCHECK2-NEXT: [[TMP20:%.*]] = bitcast double* [[TMP6]] to i8* -// TCHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 [[TMP19]], i8* align 8 [[TMP20]], i32 [[TMP18]], i1 false) -// TCHECK2-NEXT: [[TMP21:%.*]] = bitcast %struct.TT* [[D9]] to i8* -// TCHECK2-NEXT: [[TMP22:%.*]] = bitcast %struct.TT* [[TMP7]] to i8* -// TCHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP21]], i8* align 4 [[TMP22]], i32 12, i1 false) -// TCHECK2-NEXT: [[TMP23:%.*]] = load i16, i16* [[CONV]], align 2 -// TCHECK2-NEXT: [[CONV10:%.*]] = sext i16 [[TMP23]] to i32 -// TCHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV10]], 1 -// TCHECK2-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD]] to i16 -// TCHECK2-NEXT: store i16 [[CONV11]], i16* [[CONV]], align 2 -// TCHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B5]], i32 0, i32 2 -// TCHECK2-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4 -// TCHECK2-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA6]], i32 3 -// TCHECK2-NEXT: store float 1.000000e+00, float* [[ARRAYIDX12]], align 4 -// TCHECK2-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C7]], i32 0, i32 1 -// TCHECK2-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], i32 0, i32 2 -// TCHECK2-NEXT: store double 1.000000e+00, double* [[ARRAYIDX14]], align 8 -// TCHECK2-NEXT: [[TMP24:%.*]] = mul nsw i32 1, [[TMP5]] -// TCHECK2-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[VLA8]], i32 [[TMP24]] -// TCHECK2-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i32 3 -// TCHECK2-NEXT: store double 1.000000e+00, double* [[ARRAYIDX16]], align 8 -// TCHECK2-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 0 -// TCHECK2-NEXT: store i64 1, i64* [[X]], align 4 -// TCHECK2-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 1 -// TCHECK2-NEXT: store i8 1, i8* [[Y]], align 4 -// TCHECK2-NEXT: [[TMP25:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// TCHECK2-NEXT: call void @llvm.stackrestore(i8* [[TMP25]]) +// TCHECK2-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 +// TCHECK2-NEXT: [[TMP9:%.*]] = mul nuw i32 [[TMP1]], 4 +// TCHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VLA6]], ptr align 4 [[TMP2]], i32 [[TMP9]], i1 false) +// TCHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[C7]], ptr align 8 [[TMP3]], i32 400, i1 false) +// TCHECK2-NEXT: [[TMP10:%.*]] = mul nuw i32 [[TMP4]], [[TMP5]] +// TCHECK2-NEXT: [[VLA8:%.*]] = alloca double, i32 [[TMP10]], align 8 +// TCHECK2-NEXT: store i32 [[TMP4]], ptr [[__VLA_EXPR1]], align 4 +// TCHECK2-NEXT: store i32 [[TMP5]], ptr [[__VLA_EXPR2]], align 4 +// TCHECK2-NEXT: [[TMP11:%.*]] = mul nuw i32 [[TMP4]], [[TMP5]] +// TCHECK2-NEXT: [[TMP12:%.*]] = mul nuw i32 [[TMP11]], 8 +// TCHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[VLA8]], ptr align 8 [[TMP6]], i32 [[TMP12]], i1 false) +// TCHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[D9]], ptr align 4 [[TMP7]], i32 12, i1 false) +// TCHECK2-NEXT: [[TMP13:%.*]] = load i16, ptr [[AA_ADDR]], align 2 +// TCHECK2-NEXT: [[CONV:%.*]] = sext i16 [[TMP13]] to i32 +// TCHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 +// TCHECK2-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16 +// TCHECK2-NEXT: store i16 [[CONV10]], ptr [[AA_ADDR]], align 2 +// TCHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B5]], i32 0, i32 2 +// TCHECK2-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX]], align 4 +// TCHECK2-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds float, ptr [[VLA6]], i32 3 +// TCHECK2-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX11]], align 4 +// TCHECK2-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C7]], i32 0, i32 1 +// TCHECK2-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX12]], i32 0, i32 2 +// TCHECK2-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX13]], align 8 +// TCHECK2-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP5]] +// TCHECK2-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, ptr [[VLA8]], i32 [[TMP14]] +// TCHECK2-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX14]], i32 3 +// TCHECK2-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX15]], align 8 +// TCHECK2-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D9]], i32 0, i32 0 +// TCHECK2-NEXT: store i64 1, ptr [[X]], align 4 +// TCHECK2-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D9]], i32 0, i32 1 +// TCHECK2-NEXT: store i8 1, ptr [[Y]], align 4 +// TCHECK2-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 +// TCHECK2-NEXT: call void @llvm.stackrestore(ptr [[TMP15]]) // TCHECK2-NEXT: ret void // // // TCHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111 -// TCHECK2-SAME: (double* noundef [[PTR:%.*]], %struct.TT.0* noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR0]] { +// TCHECK2-SAME: (ptr noundef [[PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR0]] { // TCHECK2-NEXT: entry: -// TCHECK2-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 4 -// TCHECK2-NEXT: [[E_ADDR:%.*]] = alloca %struct.TT.0*, align 4 -// TCHECK2-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 4 -// TCHECK2-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[E_ADDR]], align 4 -// TCHECK2-NEXT: [[TMP0:%.*]] = load %struct.TT.0*, %struct.TT.0** [[E_ADDR]], align 4 -// TCHECK2-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0:%.*]], %struct.TT.0* [[TMP0]], i32 0, i32 0 -// TCHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[X]], align 4 +// TCHECK2-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 4 +// TCHECK2-NEXT: [[E_ADDR:%.*]] = alloca ptr, align 4 +// TCHECK2-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 4 +// TCHECK2-NEXT: store ptr [[E]], ptr [[E_ADDR]], align 4 +// TCHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[E_ADDR]], align 4 +// TCHECK2-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0:%.*]], ptr [[TMP0]], i32 0, i32 0 +// TCHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[X]], align 4 // TCHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double -// TCHECK2-NEXT: [[TMP2:%.*]] = load double*, double** [[PTR_ADDR]], align 4 -// TCHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP2]], i32 0 -// TCHECK2-NEXT: store double [[CONV]], double* [[ARRAYIDX]], align 4 -// TCHECK2-NEXT: [[TMP3:%.*]] = load double*, double** [[PTR_ADDR]], align 4 -// TCHECK2-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds double, double* [[TMP3]], i32 0 -// TCHECK2-NEXT: [[TMP4:%.*]] = load double, double* [[ARRAYIDX1]], align 4 +// TCHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[PTR_ADDR]], align 4 +// TCHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[TMP2]], i32 0 +// TCHECK2-NEXT: store double [[CONV]], ptr [[ARRAYIDX]], align 4 +// TCHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[PTR_ADDR]], align 4 +// TCHECK2-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds double, ptr [[TMP3]], i32 0 +// TCHECK2-NEXT: [[TMP4:%.*]] = load double, ptr [[ARRAYIDX1]], align 4 // TCHECK2-NEXT: [[INC:%.*]] = fadd double [[TMP4]], 1.000000e+00 -// TCHECK2-NEXT: store double [[INC]], double* [[ARRAYIDX1]], align 4 +// TCHECK2-NEXT: store double [[INC]], ptr [[ARRAYIDX1]], align 4 // TCHECK2-NEXT: ret void // // // TCHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142 -// TCHECK2-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// TCHECK2-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // TCHECK2-NEXT: entry: // TCHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // TCHECK2-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 -// TCHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// TCHECK2-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 // TCHECK2-NEXT: [[B1:%.*]] = alloca [10 x i32], align 4 -// TCHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// TCHECK2-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 -// TCHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// TCHECK2-NEXT: [[CONV:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* -// TCHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// TCHECK2-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B1]] to i8* -// TCHECK2-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8* -// TCHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i32 40, i1 false) -// TCHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// TCHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 -// TCHECK2-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// TCHECK2-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 1 -// TCHECK2-NEXT: [[CONV2:%.*]] = sext i8 [[TMP4]] to i32 -// TCHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 -// TCHECK2-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i8 -// TCHECK2-NEXT: store i8 [[CONV4]], i8* [[CONV]], align 1 -// TCHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], i32 0, i32 2 -// TCHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// TCHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP5]], 1 -// TCHECK2-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 +// TCHECK2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 +// TCHECK2-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4 +// TCHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 +// TCHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 +// TCHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[B1]], ptr align 4 [[TMP0]], i32 40, i1 false) +// TCHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 +// TCHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// TCHECK2-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 +// TCHECK2-NEXT: [[TMP2:%.*]] = load i8, ptr [[AAA_ADDR]], align 1 +// TCHECK2-NEXT: [[CONV:%.*]] = sext i8 [[TMP2]] to i32 +// TCHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 +// TCHECK2-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i8 +// TCHECK2-NEXT: store i8 [[CONV3]], ptr [[AAA_ADDR]], align 1 +// TCHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B1]], i32 0, i32 2 +// TCHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// TCHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 +// TCHECK2-NEXT: store i32 [[ADD4]], ptr [[ARRAYIDX]], align 4 // TCHECK2-NEXT: ret void // // // TCHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167 -// TCHECK2-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// TCHECK2-SAME: (ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // TCHECK2-NEXT: entry: -// TCHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// TCHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // TCHECK2-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 // TCHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 // TCHECK2-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// TCHECK2-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 -// TCHECK2-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// TCHECK2-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 +// TCHECK2-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4 // TCHECK2-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 // TCHECK2-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// TCHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// TCHECK2-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// TCHECK2-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// TCHECK2-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// TCHECK2-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 -// TCHECK2-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// TCHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// TCHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// TCHECK2-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 -// TCHECK2-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave() -// TCHECK2-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 4 +// TCHECK2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 +// TCHECK2-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 +// TCHECK2-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 +// TCHECK2-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 +// TCHECK2-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 +// TCHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 +// TCHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 +// TCHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 +// TCHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 +// TCHECK2-NEXT: [[TMP4:%.*]] = call ptr @llvm.stacksave() +// TCHECK2-NEXT: store ptr [[TMP4]], ptr [[SAVED_STACK]], align 4 // TCHECK2-NEXT: [[TMP5:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] // TCHECK2-NEXT: [[VLA3:%.*]] = alloca i16, i32 [[TMP5]], align 2 -// TCHECK2-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// TCHECK2-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 +// TCHECK2-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 +// TCHECK2-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 4 // TCHECK2-NEXT: [[TMP6:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] // TCHECK2-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP6]], 2 -// TCHECK2-NEXT: [[TMP8:%.*]] = bitcast i16* [[VLA3]] to i8* -// TCHECK2-NEXT: [[TMP9:%.*]] = bitcast i16* [[TMP3]] to i8* -// TCHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 2 [[TMP8]], i8* align 2 [[TMP9]], i32 [[TMP7]], i1 false) -// TCHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// TCHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP10]] to double +// TCHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 2 [[VLA3]], ptr align 2 [[TMP3]], i32 [[TMP7]], i1 false) +// TCHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[B_ADDR]], align 4 +// TCHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP8]] to double // TCHECK2-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// TCHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// TCHECK2-NEXT: store double [[ADD]], double* [[A]], align 4 -// TCHECK2-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 -// TCHECK2-NEXT: [[TMP11:%.*]] = load double, double* [[A4]], align 4 -// TCHECK2-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+00 -// TCHECK2-NEXT: store double [[INC]], double* [[A4]], align 4 +// TCHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0 +// TCHECK2-NEXT: store double [[ADD]], ptr [[A]], align 4 +// TCHECK2-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 +// TCHECK2-NEXT: [[TMP9:%.*]] = load double, ptr [[A4]], align 4 +// TCHECK2-NEXT: [[INC:%.*]] = fadd double [[TMP9]], 1.000000e+00 +// TCHECK2-NEXT: store double [[INC]], ptr [[A4]], align 4 // TCHECK2-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 -// TCHECK2-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP2]] -// TCHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA3]], i32 [[TMP12]] -// TCHECK2-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// TCHECK2-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 -// TCHECK2-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// TCHECK2-NEXT: call void @llvm.stackrestore(i8* [[TMP13]]) +// TCHECK2-NEXT: [[TMP10:%.*]] = mul nsw i32 1, [[TMP2]] +// TCHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA3]], i32 [[TMP10]] +// TCHECK2-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1 +// TCHECK2-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2 +// TCHECK2-NEXT: [[TMP11:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 +// TCHECK2-NEXT: call void @llvm.stackrestore(ptr [[TMP11]]) // TCHECK2-NEXT: ret void // // // TCHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128 -// TCHECK2-SAME: (i32 noundef [[A:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// TCHECK2-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // TCHECK2-NEXT: entry: // TCHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// TCHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// TCHECK2-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 // TCHECK2-NEXT: [[B1:%.*]] = alloca [10 x i32], align 4 -// TCHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// TCHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// TCHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// TCHECK2-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B1]] to i8* -// TCHECK2-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8* -// TCHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i32 40, i1 false) -// TCHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// TCHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 -// TCHECK2-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// TCHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], i32 0, i32 2 -// TCHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// TCHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], 1 -// TCHECK2-NEXT: store i32 [[ADD2]], i32* [[ARRAYIDX]], align 4 +// TCHECK2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 +// TCHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 +// TCHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 +// TCHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[B1]], ptr align 4 [[TMP0]], i32 40, i1 false) +// TCHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 +// TCHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// TCHECK2-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 +// TCHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B1]], i32 0, i32 2 +// TCHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// TCHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 +// TCHECK2-NEXT: store i32 [[ADD2]], ptr [[ARRAYIDX]], align 4 // TCHECK2-NEXT: ret void // // // TCHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63 -// TCHECK3-SAME: (i32 noundef [[A:%.*]], i32* noundef [[P:%.*]], i32 noundef [[GA:%.*]]) #[[ATTR0:[0-9]+]] { +// TCHECK3-SAME: (i32 noundef [[A:%.*]], ptr noundef [[P:%.*]], i32 noundef [[GA:%.*]]) #[[ATTR0:[0-9]+]] { // TCHECK3-NEXT: entry: // TCHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// TCHECK3-NEXT: [[P_ADDR:%.*]] = alloca i32*, align 4 +// TCHECK3-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 4 // TCHECK3-NEXT: [[GA_ADDR:%.*]] = alloca i32, align 4 -// TCHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// TCHECK3-NEXT: store i32* [[P]], i32** [[P_ADDR]], align 4 -// TCHECK3-NEXT: store i32 [[GA]], i32* [[GA_ADDR]], align 4 +// TCHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 +// TCHECK3-NEXT: store ptr [[P]], ptr [[P_ADDR]], align 4 +// TCHECK3-NEXT: store i32 [[GA]], ptr [[GA_ADDR]], align 4 // TCHECK3-NEXT: ret void // // // TCHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70 -// TCHECK3-SAME: (i32 noundef [[AA:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { +// TCHECK3-SAME: (i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { // TCHECK3-NEXT: entry: // TCHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 -// TCHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 +// TCHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 // TCHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// TCHECK3-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 -// TCHECK3-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 +// TCHECK3-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 4 +// TCHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 // TCHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 // TCHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 -// TCHECK3-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 -// TCHECK3-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 +// TCHECK3-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 4 +// TCHECK3-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 // TCHECK3-NEXT: [[B5:%.*]] = alloca [10 x float], align 4 -// TCHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// TCHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4 // TCHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 // TCHECK3-NEXT: [[C7:%.*]] = alloca [5 x [10 x double]], align 8 // TCHECK3-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 // TCHECK3-NEXT: [[__VLA_EXPR2:%.*]] = alloca i32, align 4 // TCHECK3-NEXT: [[D9:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 -// TCHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 -// TCHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 -// TCHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// TCHECK3-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 -// TCHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 -// TCHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// TCHECK3-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 -// TCHECK3-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 -// TCHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 -// TCHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* -// TCHECK3-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 -// TCHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// TCHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 -// TCHECK3-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 -// TCHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// TCHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 -// TCHECK3-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 -// TCHECK3-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 -// TCHECK3-NEXT: [[TMP8:%.*]] = bitcast [10 x float]* [[B5]] to i8* -// TCHECK3-NEXT: [[TMP9:%.*]] = bitcast [10 x float]* [[TMP0]] to i8* -// TCHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i32 40, i1 false) -// TCHECK3-NEXT: [[TMP10:%.*]] = call i8* @llvm.stacksave() -// TCHECK3-NEXT: store i8* [[TMP10]], i8** [[SAVED_STACK]], align 4 +// TCHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 +// TCHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 +// TCHECK3-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 +// TCHECK3-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 4 +// TCHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 +// TCHECK3-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 +// TCHECK3-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4 +// TCHECK3-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4 +// TCHECK3-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 +// TCHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 +// TCHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 +// TCHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4 +// TCHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 +// TCHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 +// TCHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4 +// TCHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4 +// TCHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4 +// TCHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[B5]], ptr align 4 [[TMP0]], i32 40, i1 false) +// TCHECK3-NEXT: [[TMP8:%.*]] = call ptr @llvm.stacksave() +// TCHECK3-NEXT: store ptr [[TMP8]], ptr [[SAVED_STACK]], align 4 // TCHECK3-NEXT: [[VLA6:%.*]] = alloca float, i32 [[TMP1]], align 4 -// TCHECK3-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// TCHECK3-NEXT: [[TMP11:%.*]] = mul nuw i32 [[TMP1]], 4 -// TCHECK3-NEXT: [[TMP12:%.*]] = bitcast float* [[VLA6]] to i8* -// TCHECK3-NEXT: [[TMP13:%.*]] = bitcast float* [[TMP2]] to i8* -// TCHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 [[TMP11]], i1 false) -// TCHECK3-NEXT: [[TMP14:%.*]] = bitcast [5 x [10 x double]]* [[C7]] to i8* -// TCHECK3-NEXT: [[TMP15:%.*]] = bitcast [5 x [10 x double]]* [[TMP3]] to i8* -// TCHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 [[TMP14]], i8* align 8 [[TMP15]], i32 400, i1 false) -// TCHECK3-NEXT: [[TMP16:%.*]] = mul nuw i32 [[TMP4]], [[TMP5]] -// TCHECK3-NEXT: [[VLA8:%.*]] = alloca double, i32 [[TMP16]], align 8 -// TCHECK3-NEXT: store i32 [[TMP4]], i32* [[__VLA_EXPR1]], align 4 -// TCHECK3-NEXT: store i32 [[TMP5]], i32* [[__VLA_EXPR2]], align 4 -// TCHECK3-NEXT: [[TMP17:%.*]] = mul nuw i32 [[TMP4]], [[TMP5]] -// TCHECK3-NEXT: [[TMP18:%.*]] = mul nuw i32 [[TMP17]], 8 -// TCHECK3-NEXT: [[TMP19:%.*]] = bitcast double* [[VLA8]] to i8* -// TCHECK3-NEXT: [[TMP20:%.*]] = bitcast double* [[TMP6]] to i8* -// TCHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 [[TMP19]], i8* align 8 [[TMP20]], i32 [[TMP18]], i1 false) -// TCHECK3-NEXT: [[TMP21:%.*]] = bitcast %struct.TT* [[D9]] to i8* -// TCHECK3-NEXT: [[TMP22:%.*]] = bitcast %struct.TT* [[TMP7]] to i8* -// TCHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP21]], i8* align 4 [[TMP22]], i32 12, i1 false) -// TCHECK3-NEXT: [[TMP23:%.*]] = load i16, i16* [[CONV]], align 2 -// TCHECK3-NEXT: [[CONV10:%.*]] = sext i16 [[TMP23]] to i32 -// TCHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV10]], 1 -// TCHECK3-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD]] to i16 -// TCHECK3-NEXT: store i16 [[CONV11]], i16* [[CONV]], align 2 -// TCHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B5]], i32 0, i32 2 -// TCHECK3-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4 -// TCHECK3-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA6]], i32 3 -// TCHECK3-NEXT: store float 1.000000e+00, float* [[ARRAYIDX12]], align 4 -// TCHECK3-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C7]], i32 0, i32 1 -// TCHECK3-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], i32 0, i32 2 -// TCHECK3-NEXT: store double 1.000000e+00, double* [[ARRAYIDX14]], align 8 -// TCHECK3-NEXT: [[TMP24:%.*]] = mul nsw i32 1, [[TMP5]] -// TCHECK3-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[VLA8]], i32 [[TMP24]] -// TCHECK3-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i32 3 -// TCHECK3-NEXT: store double 1.000000e+00, double* [[ARRAYIDX16]], align 8 -// TCHECK3-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 0 -// TCHECK3-NEXT: store i64 1, i64* [[X]], align 4 -// TCHECK3-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 1 -// TCHECK3-NEXT: store i8 1, i8* [[Y]], align 4 -// TCHECK3-NEXT: [[TMP25:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// TCHECK3-NEXT: call void @llvm.stackrestore(i8* [[TMP25]]) +// TCHECK3-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 +// TCHECK3-NEXT: [[TMP9:%.*]] = mul nuw i32 [[TMP1]], 4 +// TCHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VLA6]], ptr align 4 [[TMP2]], i32 [[TMP9]], i1 false) +// TCHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[C7]], ptr align 8 [[TMP3]], i32 400, i1 false) +// TCHECK3-NEXT: [[TMP10:%.*]] = mul nuw i32 [[TMP4]], [[TMP5]] +// TCHECK3-NEXT: [[VLA8:%.*]] = alloca double, i32 [[TMP10]], align 8 +// TCHECK3-NEXT: store i32 [[TMP4]], ptr [[__VLA_EXPR1]], align 4 +// TCHECK3-NEXT: store i32 [[TMP5]], ptr [[__VLA_EXPR2]], align 4 +// TCHECK3-NEXT: [[TMP11:%.*]] = mul nuw i32 [[TMP4]], [[TMP5]] +// TCHECK3-NEXT: [[TMP12:%.*]] = mul nuw i32 [[TMP11]], 8 +// TCHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[VLA8]], ptr align 8 [[TMP6]], i32 [[TMP12]], i1 false) +// TCHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[D9]], ptr align 4 [[TMP7]], i32 12, i1 false) +// TCHECK3-NEXT: [[TMP13:%.*]] = load i16, ptr [[AA_ADDR]], align 2 +// TCHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP13]] to i32 +// TCHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 +// TCHECK3-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD]] to i16 +// TCHECK3-NEXT: store i16 [[CONV10]], ptr [[AA_ADDR]], align 2 +// TCHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B5]], i32 0, i32 2 +// TCHECK3-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX]], align 4 +// TCHECK3-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds float, ptr [[VLA6]], i32 3 +// TCHECK3-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX11]], align 4 +// TCHECK3-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C7]], i32 0, i32 1 +// TCHECK3-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX12]], i32 0, i32 2 +// TCHECK3-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX13]], align 8 +// TCHECK3-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP5]] +// TCHECK3-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, ptr [[VLA8]], i32 [[TMP14]] +// TCHECK3-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX14]], i32 3 +// TCHECK3-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX15]], align 8 +// TCHECK3-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D9]], i32 0, i32 0 +// TCHECK3-NEXT: store i64 1, ptr [[X]], align 4 +// TCHECK3-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D9]], i32 0, i32 1 +// TCHECK3-NEXT: store i8 1, ptr [[Y]], align 4 +// TCHECK3-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 +// TCHECK3-NEXT: call void @llvm.stackrestore(ptr [[TMP15]]) // TCHECK3-NEXT: ret void // // // TCHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111 -// TCHECK3-SAME: (double* noundef [[PTR:%.*]], %struct.TT.0* noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR0]] { +// TCHECK3-SAME: (ptr noundef [[PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR0]] { // TCHECK3-NEXT: entry: -// TCHECK3-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 4 -// TCHECK3-NEXT: [[E_ADDR:%.*]] = alloca %struct.TT.0*, align 4 -// TCHECK3-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 4 -// TCHECK3-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[E_ADDR]], align 4 -// TCHECK3-NEXT: [[TMP0:%.*]] = load %struct.TT.0*, %struct.TT.0** [[E_ADDR]], align 4 -// TCHECK3-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0:%.*]], %struct.TT.0* [[TMP0]], i32 0, i32 0 -// TCHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[X]], align 4 +// TCHECK3-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 4 +// TCHECK3-NEXT: [[E_ADDR:%.*]] = alloca ptr, align 4 +// TCHECK3-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 4 +// TCHECK3-NEXT: store ptr [[E]], ptr [[E_ADDR]], align 4 +// TCHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[E_ADDR]], align 4 +// TCHECK3-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0:%.*]], ptr [[TMP0]], i32 0, i32 0 +// TCHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[X]], align 4 // TCHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double -// TCHECK3-NEXT: [[TMP2:%.*]] = load double*, double** [[PTR_ADDR]], align 4 -// TCHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP2]], i32 0 -// TCHECK3-NEXT: store double [[CONV]], double* [[ARRAYIDX]], align 4 -// TCHECK3-NEXT: [[TMP3:%.*]] = load double*, double** [[PTR_ADDR]], align 4 -// TCHECK3-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds double, double* [[TMP3]], i32 0 -// TCHECK3-NEXT: [[TMP4:%.*]] = load double, double* [[ARRAYIDX1]], align 4 +// TCHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[PTR_ADDR]], align 4 +// TCHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[TMP2]], i32 0 +// TCHECK3-NEXT: store double [[CONV]], ptr [[ARRAYIDX]], align 4 +// TCHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[PTR_ADDR]], align 4 +// TCHECK3-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds double, ptr [[TMP3]], i32 0 +// TCHECK3-NEXT: [[TMP4:%.*]] = load double, ptr [[ARRAYIDX1]], align 4 // TCHECK3-NEXT: [[INC:%.*]] = fadd double [[TMP4]], 1.000000e+00 -// TCHECK3-NEXT: store double [[INC]], double* [[ARRAYIDX1]], align 4 +// TCHECK3-NEXT: store double [[INC]], ptr [[ARRAYIDX1]], align 4 // TCHECK3-NEXT: ret void // // // TCHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142 -// TCHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// TCHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // TCHECK3-NEXT: entry: // TCHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // TCHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 -// TCHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// TCHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 // TCHECK3-NEXT: [[B1:%.*]] = alloca [10 x i32], align 4 -// TCHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// TCHECK3-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 -// TCHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// TCHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* -// TCHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// TCHECK3-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B1]] to i8* -// TCHECK3-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8* -// TCHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i32 40, i1 false) -// TCHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// TCHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 -// TCHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// TCHECK3-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 1 -// TCHECK3-NEXT: [[CONV2:%.*]] = sext i8 [[TMP4]] to i32 -// TCHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 -// TCHECK3-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i8 -// TCHECK3-NEXT: store i8 [[CONV4]], i8* [[CONV]], align 1 -// TCHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], i32 0, i32 2 -// TCHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// TCHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP5]], 1 -// TCHECK3-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 +// TCHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 +// TCHECK3-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4 +// TCHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 +// TCHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 +// TCHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[B1]], ptr align 4 [[TMP0]], i32 40, i1 false) +// TCHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 +// TCHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// TCHECK3-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 +// TCHECK3-NEXT: [[TMP2:%.*]] = load i8, ptr [[AAA_ADDR]], align 1 +// TCHECK3-NEXT: [[CONV:%.*]] = sext i8 [[TMP2]] to i32 +// TCHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 +// TCHECK3-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i8 +// TCHECK3-NEXT: store i8 [[CONV3]], ptr [[AAA_ADDR]], align 1 +// TCHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B1]], i32 0, i32 2 +// TCHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// TCHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 +// TCHECK3-NEXT: store i32 [[ADD4]], ptr [[ARRAYIDX]], align 4 // TCHECK3-NEXT: ret void // // // TCHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167 -// TCHECK3-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { +// TCHECK3-SAME: (ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { // TCHECK3-NEXT: entry: -// TCHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// TCHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // TCHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 // TCHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 // TCHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// TCHECK3-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 -// TCHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// TCHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 +// TCHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4 // TCHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 // TCHECK3-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 -// TCHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// TCHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 -// TCHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 -// TCHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 -// TCHECK3-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 -// TCHECK3-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// TCHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 -// TCHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 -// TCHECK3-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 -// TCHECK3-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave() -// TCHECK3-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 4 +// TCHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 +// TCHECK3-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 +// TCHECK3-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 +// TCHECK3-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 +// TCHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 +// TCHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 +// TCHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 +// TCHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 +// TCHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 +// TCHECK3-NEXT: [[TMP4:%.*]] = call ptr @llvm.stacksave() +// TCHECK3-NEXT: store ptr [[TMP4]], ptr [[SAVED_STACK]], align 4 // TCHECK3-NEXT: [[TMP5:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] // TCHECK3-NEXT: [[VLA3:%.*]] = alloca i16, i32 [[TMP5]], align 2 -// TCHECK3-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// TCHECK3-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 +// TCHECK3-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 +// TCHECK3-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 4 // TCHECK3-NEXT: [[TMP6:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] // TCHECK3-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP6]], 2 -// TCHECK3-NEXT: [[TMP8:%.*]] = bitcast i16* [[VLA3]] to i8* -// TCHECK3-NEXT: [[TMP9:%.*]] = bitcast i16* [[TMP3]] to i8* -// TCHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 2 [[TMP8]], i8* align 2 [[TMP9]], i32 [[TMP7]], i1 false) -// TCHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[B_ADDR]], align 4 -// TCHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP10]] to double +// TCHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 2 [[VLA3]], ptr align 2 [[TMP3]], i32 [[TMP7]], i1 false) +// TCHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[B_ADDR]], align 4 +// TCHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP8]] to double // TCHECK3-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 -// TCHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 -// TCHECK3-NEXT: store double [[ADD]], double* [[A]], align 4 -// TCHECK3-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 -// TCHECK3-NEXT: [[TMP11:%.*]] = load double, double* [[A4]], align 4 -// TCHECK3-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+00 -// TCHECK3-NEXT: store double [[INC]], double* [[A4]], align 4 +// TCHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0 +// TCHECK3-NEXT: store double [[ADD]], ptr [[A]], align 4 +// TCHECK3-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 +// TCHECK3-NEXT: [[TMP9:%.*]] = load double, ptr [[A4]], align 4 +// TCHECK3-NEXT: [[INC:%.*]] = fadd double [[TMP9]], 1.000000e+00 +// TCHECK3-NEXT: store double [[INC]], ptr [[A4]], align 4 // TCHECK3-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 -// TCHECK3-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP2]] -// TCHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA3]], i32 [[TMP12]] -// TCHECK3-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// TCHECK3-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 -// TCHECK3-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// TCHECK3-NEXT: call void @llvm.stackrestore(i8* [[TMP13]]) +// TCHECK3-NEXT: [[TMP10:%.*]] = mul nsw i32 1, [[TMP2]] +// TCHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA3]], i32 [[TMP10]] +// TCHECK3-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1 +// TCHECK3-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2 +// TCHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 +// TCHECK3-NEXT: call void @llvm.stackrestore(ptr [[TMP11]]) // TCHECK3-NEXT: ret void // // // TCHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128 -// TCHECK3-SAME: (i32 noundef [[A:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { +// TCHECK3-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // TCHECK3-NEXT: entry: // TCHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// TCHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 +// TCHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 // TCHECK3-NEXT: [[B1:%.*]] = alloca [10 x i32], align 4 -// TCHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 -// TCHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 -// TCHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 -// TCHECK3-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B1]] to i8* -// TCHECK3-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8* -// TCHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i32 40, i1 false) -// TCHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 -// TCHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 -// TCHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// TCHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], i32 0, i32 2 -// TCHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 -// TCHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], 1 -// TCHECK3-NEXT: store i32 [[ADD2]], i32* [[ARRAYIDX]], align 4 +// TCHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 +// TCHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 +// TCHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 +// TCHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[B1]], ptr align 4 [[TMP0]], i32 40, i1 false) +// TCHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 +// TCHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 +// TCHECK3-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 +// TCHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B1]], i32 0, i32 2 +// TCHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// TCHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 +// TCHECK3-NEXT: store i32 [[ADD2]], ptr [[ARRAYIDX]], align 4 // TCHECK3-NEXT: ret void // // // SIMD-ONLY1-LABEL: define {{[^@]+}}@_Z3fooiPd -// SIMD-ONLY1-SAME: (i32 noundef signext [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0:[0-9]+]] { +// SIMD-ONLY1-SAME: (i32 noundef signext [[N:%.*]], ptr noundef [[PTR:%.*]]) #[[ATTR0:[0-9]+]] { // SIMD-ONLY1-NEXT: entry: // SIMD-ONLY1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// SIMD-ONLY1-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 8 +// SIMD-ONLY1-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY1-NEXT: [[A:%.*]] = alloca i32, align 4 // SIMD-ONLY1-NEXT: [[AA:%.*]] = alloca i16, align 2 // SIMD-ONLY1-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// SIMD-ONLY1-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// SIMD-ONLY1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 // SIMD-ONLY1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 // SIMD-ONLY1-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 // SIMD-ONLY1-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 // SIMD-ONLY1-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 // SIMD-ONLY1-NEXT: [[E:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 4 -// SIMD-ONLY1-NEXT: [[P:%.*]] = alloca i32*, align 64 -// SIMD-ONLY1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// SIMD-ONLY1-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 8 -// SIMD-ONLY1-NEXT: store i32 0, i32* [[A]], align 4 -// SIMD-ONLY1-NEXT: store i16 0, i16* [[AA]], align 2 -// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// SIMD-ONLY1-NEXT: [[P:%.*]] = alloca ptr, align 64 +// SIMD-ONLY1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// SIMD-ONLY1-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 8 +// SIMD-ONLY1-NEXT: store i32 0, ptr [[A]], align 4 +// SIMD-ONLY1-NEXT: store i16 0, ptr [[AA]], align 2 +// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY1-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// SIMD-ONLY1-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// SIMD-ONLY1-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 +// SIMD-ONLY1-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() +// SIMD-ONLY1-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // SIMD-ONLY1-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// SIMD-ONLY1-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// SIMD-ONLY1-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// SIMD-ONLY1-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 +// SIMD-ONLY1-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY1-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 // SIMD-ONLY1-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] // SIMD-ONLY1-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// SIMD-ONLY1-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// SIMD-ONLY1-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 0 -// SIMD-ONLY1-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// SIMD-ONLY1-NEXT: store i32 [[TMP6]], i32* [[X]], align 4 -// SIMD-ONLY1-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 1 -// SIMD-ONLY1-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// SIMD-ONLY1-NEXT: store i32 [[TMP7]], i32* [[Y]], align 4 -// SIMD-ONLY1-NEXT: store i32* [[A]], i32** [[P]], align 64 -// SIMD-ONLY1-NEXT: [[TMP8:%.*]] = load i16, i16* [[AA]], align 2 +// SIMD-ONLY1-NEXT: store i64 [[TMP4]], ptr [[__VLA_EXPR1]], align 8 +// SIMD-ONLY1-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 0 +// SIMD-ONLY1-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// SIMD-ONLY1-NEXT: store i32 [[TMP6]], ptr [[X]], align 4 +// SIMD-ONLY1-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 1 +// SIMD-ONLY1-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// SIMD-ONLY1-NEXT: store i32 [[TMP7]], ptr [[Y]], align 4 +// SIMD-ONLY1-NEXT: store ptr [[A]], ptr [[P]], align 64 +// SIMD-ONLY1-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA]], align 2 // SIMD-ONLY1-NEXT: [[CONV:%.*]] = sext i16 [[TMP8]] to i32 // SIMD-ONLY1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 // SIMD-ONLY1-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 -// SIMD-ONLY1-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// SIMD-ONLY1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 -// SIMD-ONLY1-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4 -// SIMD-ONLY1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 -// SIMD-ONLY1-NEXT: store float 1.000000e+00, float* [[ARRAYIDX3]], align 4 -// SIMD-ONLY1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// SIMD-ONLY1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX4]], i64 0, i64 2 -// SIMD-ONLY1-NEXT: store double 1.000000e+00, double* [[ARRAYIDX5]], align 8 +// SIMD-ONLY1-NEXT: store i16 [[CONV2]], ptr [[AA]], align 2 +// SIMD-ONLY1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], i64 0, i64 2 +// SIMD-ONLY1-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX]], align 4 +// SIMD-ONLY1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[VLA]], i64 3 +// SIMD-ONLY1-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX3]], align 4 +// SIMD-ONLY1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C]], i64 0, i64 1 +// SIMD-ONLY1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX4]], i64 0, i64 2 +// SIMD-ONLY1-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX5]], align 8 // SIMD-ONLY1-NEXT: [[TMP9:%.*]] = mul nsw i64 1, [[TMP4]] -// SIMD-ONLY1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP9]] -// SIMD-ONLY1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX6]], i64 3 -// SIMD-ONLY1-NEXT: store double 1.000000e+00, double* [[ARRAYIDX7]], align 8 -// SIMD-ONLY1-NEXT: [[X8:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// SIMD-ONLY1-NEXT: store i64 1, i64* [[X8]], align 8 -// SIMD-ONLY1-NEXT: [[Y9:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// SIMD-ONLY1-NEXT: store i8 1, i8* [[Y9]], align 8 -// SIMD-ONLY1-NEXT: [[X10:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 0 -// SIMD-ONLY1-NEXT: [[TMP10:%.*]] = load i32, i32* [[X10]], align 4 +// SIMD-ONLY1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds double, ptr [[VLA1]], i64 [[TMP9]] +// SIMD-ONLY1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX6]], i64 3 +// SIMD-ONLY1-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX7]], align 8 +// SIMD-ONLY1-NEXT: [[X8:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D]], i32 0, i32 0 +// SIMD-ONLY1-NEXT: store i64 1, ptr [[X8]], align 8 +// SIMD-ONLY1-NEXT: [[Y9:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D]], i32 0, i32 1 +// SIMD-ONLY1-NEXT: store i8 1, ptr [[Y9]], align 8 +// SIMD-ONLY1-NEXT: [[X10:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 0 +// SIMD-ONLY1-NEXT: [[TMP10:%.*]] = load i32, ptr [[X10]], align 4 // SIMD-ONLY1-NEXT: [[CONV11:%.*]] = sitofp i32 [[TMP10]] to double -// SIMD-ONLY1-NEXT: [[TMP11:%.*]] = load double*, double** [[PTR_ADDR]], align 8 -// SIMD-ONLY1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds double, double* [[TMP11]], i64 0 -// SIMD-ONLY1-NEXT: store double [[CONV11]], double* [[ARRAYIDX12]], align 8 -// SIMD-ONLY1-NEXT: [[TMP12:%.*]] = load double*, double** [[PTR_ADDR]], align 8 -// SIMD-ONLY1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds double, double* [[TMP12]], i64 0 -// SIMD-ONLY1-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX13]], align 8 +// SIMD-ONLY1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8 +// SIMD-ONLY1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds double, ptr [[TMP11]], i64 0 +// SIMD-ONLY1-NEXT: store double [[CONV11]], ptr [[ARRAYIDX12]], align 8 +// SIMD-ONLY1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8 +// SIMD-ONLY1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds double, ptr [[TMP12]], i64 0 +// SIMD-ONLY1-NEXT: [[TMP13:%.*]] = load double, ptr [[ARRAYIDX13]], align 8 // SIMD-ONLY1-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// SIMD-ONLY1-NEXT: store double [[INC]], double* [[ARRAYIDX13]], align 8 -// SIMD-ONLY1-NEXT: [[TMP14:%.*]] = load i32, i32* [[A]], align 4 -// SIMD-ONLY1-NEXT: [[TMP15:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// SIMD-ONLY1-NEXT: call void @llvm.stackrestore(i8* [[TMP15]]) +// SIMD-ONLY1-NEXT: store double [[INC]], ptr [[ARRAYIDX13]], align 8 +// SIMD-ONLY1-NEXT: [[TMP14:%.*]] = load i32, ptr [[A]], align 4 +// SIMD-ONLY1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 +// SIMD-ONLY1-NEXT: call void @llvm.stackrestore(ptr [[TMP15]]) // SIMD-ONLY1-NEXT: ret i32 [[TMP14]] // // // SIMD-ONLY1-LABEL: define {{[^@]+}}@_Z3bariPd -// SIMD-ONLY1-SAME: (i32 noundef signext [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0]] { +// SIMD-ONLY1-SAME: (i32 noundef signext [[N:%.*]], ptr noundef [[PTR:%.*]]) #[[ATTR0]] { // SIMD-ONLY1-NEXT: entry: // SIMD-ONLY1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// SIMD-ONLY1-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 8 +// SIMD-ONLY1-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY1-NEXT: [[A:%.*]] = alloca i32, align 4 // SIMD-ONLY1-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// SIMD-ONLY1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// SIMD-ONLY1-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 8 -// SIMD-ONLY1-NEXT: store i32 0, i32* [[A]], align 4 -// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// SIMD-ONLY1-NEXT: [[TMP1:%.*]] = load double*, double** [[PTR_ADDR]], align 8 -// SIMD-ONLY1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooiPd(i32 noundef signext [[TMP0]], double* noundef [[TMP1]]) -// SIMD-ONLY1-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// SIMD-ONLY1-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 8 +// SIMD-ONLY1-NEXT: store i32 0, ptr [[A]], align 4 +// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// SIMD-ONLY1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8 +// SIMD-ONLY1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooiPd(i32 noundef signext [[TMP0]], ptr noundef [[TMP1]]) +// SIMD-ONLY1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CALL]] -// SIMD-ONLY1-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// SIMD-ONLY1-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// SIMD-ONLY1-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP3]]) -// SIMD-ONLY1-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY1-NEXT: store i32 [[ADD]], ptr [[A]], align 4 +// SIMD-ONLY1-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// SIMD-ONLY1-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(ptr noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP3]]) +// SIMD-ONLY1-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], [[CALL1]] -// SIMD-ONLY1-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// SIMD-ONLY1-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// SIMD-ONLY1-NEXT: store i32 [[ADD2]], ptr [[A]], align 4 +// SIMD-ONLY1-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY1-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP5]]) -// SIMD-ONLY1-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY1-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], [[CALL3]] -// SIMD-ONLY1-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// SIMD-ONLY1-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// SIMD-ONLY1-NEXT: store i32 [[ADD4]], ptr [[A]], align 4 +// SIMD-ONLY1-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY1-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP7]]) -// SIMD-ONLY1-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP8]], [[CALL5]] -// SIMD-ONLY1-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// SIMD-ONLY1-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY1-NEXT: store i32 [[ADD6]], ptr [[A]], align 4 +// SIMD-ONLY1-NEXT: [[TMP9:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY1-NEXT: ret i32 [[TMP9]] // // // SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// SIMD-ONLY1-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// SIMD-ONLY1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // SIMD-ONLY1-NEXT: entry: -// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // SIMD-ONLY1-NEXT: [[B:%.*]] = alloca i32, align 4 -// SIMD-ONLY1-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// SIMD-ONLY1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 // SIMD-ONLY1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// SIMD-ONLY1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// SIMD-ONLY1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// SIMD-ONLY1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// SIMD-ONLY1-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// SIMD-ONLY1-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// SIMD-ONLY1-NEXT: store i32 [[ADD]], ptr [[B]], align 4 +// SIMD-ONLY1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// SIMD-ONLY1-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// SIMD-ONLY1-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 +// SIMD-ONLY1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave() +// SIMD-ONLY1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8 // SIMD-ONLY1-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] // SIMD-ONLY1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// SIMD-ONLY1-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// SIMD-ONLY1-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 +// SIMD-ONLY1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 +// SIMD-ONLY1-NEXT: [[TMP5:%.*]] = load i32, ptr [[B]], align 4 // SIMD-ONLY1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double // SIMD-ONLY1-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// SIMD-ONLY1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// SIMD-ONLY1-NEXT: store double [[ADD2]], double* [[A]], align 8 -// SIMD-ONLY1-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// SIMD-ONLY1-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 8 +// SIMD-ONLY1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0 +// SIMD-ONLY1-NEXT: store double [[ADD2]], ptr [[A]], align 8 +// SIMD-ONLY1-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[THIS1]], i32 0, i32 0 +// SIMD-ONLY1-NEXT: [[TMP6:%.*]] = load double, ptr [[A3]], align 8 // SIMD-ONLY1-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// SIMD-ONLY1-NEXT: store double [[INC]], double* [[A3]], align 8 +// SIMD-ONLY1-NEXT: store double [[INC]], ptr [[A3]], align 8 // SIMD-ONLY1-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 // SIMD-ONLY1-NEXT: [[TMP7:%.*]] = mul nsw i64 1, [[TMP2]] -// SIMD-ONLY1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP7]] -// SIMD-ONLY1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// SIMD-ONLY1-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 +// SIMD-ONLY1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP7]] +// SIMD-ONLY1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1 +// SIMD-ONLY1-NEXT: store i16 [[CONV4]], ptr [[ARRAYIDX5]], align 2 // SIMD-ONLY1-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] -// SIMD-ONLY1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] -// SIMD-ONLY1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1 -// SIMD-ONLY1-NEXT: [[TMP9:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 +// SIMD-ONLY1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP8]] +// SIMD-ONLY1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX6]], i64 1 +// SIMD-ONLY1-NEXT: [[TMP9:%.*]] = load i16, ptr [[ARRAYIDX7]], align 2 // SIMD-ONLY1-NEXT: [[CONV8:%.*]] = sext i16 [[TMP9]] to i32 -// SIMD-ONLY1-NEXT: [[TMP10:%.*]] = load i32, i32* [[B]], align 4 +// SIMD-ONLY1-NEXT: [[TMP10:%.*]] = load i32, ptr [[B]], align 4 // SIMD-ONLY1-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP10]] -// SIMD-ONLY1-NEXT: [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// SIMD-ONLY1-NEXT: call void @llvm.stackrestore(i8* [[TMP11]]) +// SIMD-ONLY1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 +// SIMD-ONLY1-NEXT: call void @llvm.stackrestore(ptr [[TMP11]]) // SIMD-ONLY1-NEXT: ret i32 [[ADD9]] // // @@ -11365,22 +10975,22 @@ int bar(int n, double *ptr) { // SIMD-ONLY1-NEXT: [[A:%.*]] = alloca i32, align 4 // SIMD-ONLY1-NEXT: [[AAA:%.*]] = alloca i8, align 1 // SIMD-ONLY1-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// SIMD-ONLY1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// SIMD-ONLY1-NEXT: store i32 0, i32* [[A]], align 4 -// SIMD-ONLY1-NEXT: store i8 0, i8* [[AAA]], align 1 -// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// SIMD-ONLY1-NEXT: store i32 0, ptr [[A]], align 4 +// SIMD-ONLY1-NEXT: store i8 0, ptr [[AAA]], align 1 +// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// SIMD-ONLY1-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// SIMD-ONLY1-NEXT: [[TMP1:%.*]] = load i8, i8* [[AAA]], align 1 +// SIMD-ONLY1-NEXT: store i32 [[ADD]], ptr [[A]], align 4 +// SIMD-ONLY1-NEXT: [[TMP1:%.*]] = load i8, ptr [[AAA]], align 1 // SIMD-ONLY1-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32 // SIMD-ONLY1-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 // SIMD-ONLY1-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i8 -// SIMD-ONLY1-NEXT: store i8 [[CONV2]], i8* [[AAA]], align 1 -// SIMD-ONLY1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// SIMD-ONLY1-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// SIMD-ONLY1-NEXT: store i8 [[CONV2]], ptr [[AAA]], align 1 +// SIMD-ONLY1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i64 0, i64 2 +// SIMD-ONLY1-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // SIMD-ONLY1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// SIMD-ONLY1-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// SIMD-ONLY1-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY1-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4 +// SIMD-ONLY1-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY1-NEXT: ret i32 [[TMP3]] // // @@ -11390,172 +11000,172 @@ int bar(int n, double *ptr) { // SIMD-ONLY1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // SIMD-ONLY1-NEXT: [[A:%.*]] = alloca i32, align 4 // SIMD-ONLY1-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// SIMD-ONLY1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// SIMD-ONLY1-NEXT: store i32 0, i32* [[A]], align 4 -// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// SIMD-ONLY1-NEXT: store i32 0, ptr [[A]], align 4 +// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// SIMD-ONLY1-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// SIMD-ONLY1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// SIMD-ONLY1-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// SIMD-ONLY1-NEXT: store i32 [[ADD]], ptr [[A]], align 4 +// SIMD-ONLY1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i64 0, i64 2 +// SIMD-ONLY1-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // SIMD-ONLY1-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP1]], 1 -// SIMD-ONLY1-NEXT: store i32 [[ADD1]], i32* [[ARRAYIDX]], align 4 -// SIMD-ONLY1-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY1-NEXT: store i32 [[ADD1]], ptr [[ARRAYIDX]], align 4 +// SIMD-ONLY1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY1-NEXT: ret i32 [[TMP2]] // // // SIMD-ONLY11-LABEL: define {{[^@]+}}@_Z3fooiPd -// SIMD-ONLY11-SAME: (i32 noundef signext [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0:[0-9]+]] { +// SIMD-ONLY11-SAME: (i32 noundef signext [[N:%.*]], ptr noundef [[PTR:%.*]]) #[[ATTR0:[0-9]+]] { // SIMD-ONLY11-NEXT: entry: // SIMD-ONLY11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// SIMD-ONLY11-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 8 +// SIMD-ONLY11-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY11-NEXT: [[A:%.*]] = alloca i32, align 4 // SIMD-ONLY11-NEXT: [[AA:%.*]] = alloca i16, align 2 // SIMD-ONLY11-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// SIMD-ONLY11-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// SIMD-ONLY11-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 // SIMD-ONLY11-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 // SIMD-ONLY11-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 // SIMD-ONLY11-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 // SIMD-ONLY11-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 // SIMD-ONLY11-NEXT: [[E:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 4 -// SIMD-ONLY11-NEXT: [[P:%.*]] = alloca i32*, align 64 -// SIMD-ONLY11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// SIMD-ONLY11-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 8 -// SIMD-ONLY11-NEXT: store i32 0, i32* [[A]], align 4 -// SIMD-ONLY11-NEXT: store i16 0, i16* [[AA]], align 2 -// SIMD-ONLY11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// SIMD-ONLY11-NEXT: [[P:%.*]] = alloca ptr, align 64 +// SIMD-ONLY11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// SIMD-ONLY11-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 8 +// SIMD-ONLY11-NEXT: store i32 0, ptr [[A]], align 4 +// SIMD-ONLY11-NEXT: store i16 0, ptr [[AA]], align 2 +// SIMD-ONLY11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY11-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 -// SIMD-ONLY11-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// SIMD-ONLY11-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 +// SIMD-ONLY11-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() +// SIMD-ONLY11-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // SIMD-ONLY11-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 -// SIMD-ONLY11-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 -// SIMD-ONLY11-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// SIMD-ONLY11-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 +// SIMD-ONLY11-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY11-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 // SIMD-ONLY11-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] // SIMD-ONLY11-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 -// SIMD-ONLY11-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 -// SIMD-ONLY11-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 0 -// SIMD-ONLY11-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// SIMD-ONLY11-NEXT: store i32 [[TMP6]], i32* [[X]], align 4 -// SIMD-ONLY11-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 1 -// SIMD-ONLY11-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// SIMD-ONLY11-NEXT: store i32 [[TMP7]], i32* [[Y]], align 4 -// SIMD-ONLY11-NEXT: store i32* [[A]], i32** [[P]], align 64 -// SIMD-ONLY11-NEXT: [[TMP8:%.*]] = load i16, i16* [[AA]], align 2 +// SIMD-ONLY11-NEXT: store i64 [[TMP4]], ptr [[__VLA_EXPR1]], align 8 +// SIMD-ONLY11-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 0 +// SIMD-ONLY11-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// SIMD-ONLY11-NEXT: store i32 [[TMP6]], ptr [[X]], align 4 +// SIMD-ONLY11-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 1 +// SIMD-ONLY11-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// SIMD-ONLY11-NEXT: store i32 [[TMP7]], ptr [[Y]], align 4 +// SIMD-ONLY11-NEXT: store ptr [[A]], ptr [[P]], align 64 +// SIMD-ONLY11-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA]], align 2 // SIMD-ONLY11-NEXT: [[CONV:%.*]] = sext i16 [[TMP8]] to i32 // SIMD-ONLY11-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 // SIMD-ONLY11-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 -// SIMD-ONLY11-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// SIMD-ONLY11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 -// SIMD-ONLY11-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4 -// SIMD-ONLY11-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 -// SIMD-ONLY11-NEXT: store float 1.000000e+00, float* [[ARRAYIDX3]], align 4 -// SIMD-ONLY11-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// SIMD-ONLY11-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX4]], i64 0, i64 2 -// SIMD-ONLY11-NEXT: store double 1.000000e+00, double* [[ARRAYIDX5]], align 8 +// SIMD-ONLY11-NEXT: store i16 [[CONV2]], ptr [[AA]], align 2 +// SIMD-ONLY11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], i64 0, i64 2 +// SIMD-ONLY11-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX]], align 4 +// SIMD-ONLY11-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[VLA]], i64 3 +// SIMD-ONLY11-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX3]], align 4 +// SIMD-ONLY11-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C]], i64 0, i64 1 +// SIMD-ONLY11-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX4]], i64 0, i64 2 +// SIMD-ONLY11-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX5]], align 8 // SIMD-ONLY11-NEXT: [[TMP9:%.*]] = mul nsw i64 1, [[TMP4]] -// SIMD-ONLY11-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP9]] -// SIMD-ONLY11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX6]], i64 3 -// SIMD-ONLY11-NEXT: store double 1.000000e+00, double* [[ARRAYIDX7]], align 8 -// SIMD-ONLY11-NEXT: [[X8:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// SIMD-ONLY11-NEXT: store i64 1, i64* [[X8]], align 8 -// SIMD-ONLY11-NEXT: [[Y9:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// SIMD-ONLY11-NEXT: store i8 1, i8* [[Y9]], align 8 -// SIMD-ONLY11-NEXT: [[X10:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 0 -// SIMD-ONLY11-NEXT: [[TMP10:%.*]] = load i32, i32* [[X10]], align 4 +// SIMD-ONLY11-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds double, ptr [[VLA1]], i64 [[TMP9]] +// SIMD-ONLY11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX6]], i64 3 +// SIMD-ONLY11-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX7]], align 8 +// SIMD-ONLY11-NEXT: [[X8:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D]], i32 0, i32 0 +// SIMD-ONLY11-NEXT: store i64 1, ptr [[X8]], align 8 +// SIMD-ONLY11-NEXT: [[Y9:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D]], i32 0, i32 1 +// SIMD-ONLY11-NEXT: store i8 1, ptr [[Y9]], align 8 +// SIMD-ONLY11-NEXT: [[X10:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 0 +// SIMD-ONLY11-NEXT: [[TMP10:%.*]] = load i32, ptr [[X10]], align 4 // SIMD-ONLY11-NEXT: [[CONV11:%.*]] = sitofp i32 [[TMP10]] to double -// SIMD-ONLY11-NEXT: [[TMP11:%.*]] = load double*, double** [[PTR_ADDR]], align 8 -// SIMD-ONLY11-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds double, double* [[TMP11]], i64 0 -// SIMD-ONLY11-NEXT: store double [[CONV11]], double* [[ARRAYIDX12]], align 8 -// SIMD-ONLY11-NEXT: [[TMP12:%.*]] = load double*, double** [[PTR_ADDR]], align 8 -// SIMD-ONLY11-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds double, double* [[TMP12]], i64 0 -// SIMD-ONLY11-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX13]], align 8 +// SIMD-ONLY11-NEXT: [[TMP11:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8 +// SIMD-ONLY11-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds double, ptr [[TMP11]], i64 0 +// SIMD-ONLY11-NEXT: store double [[CONV11]], ptr [[ARRAYIDX12]], align 8 +// SIMD-ONLY11-NEXT: [[TMP12:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8 +// SIMD-ONLY11-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds double, ptr [[TMP12]], i64 0 +// SIMD-ONLY11-NEXT: [[TMP13:%.*]] = load double, ptr [[ARRAYIDX13]], align 8 // SIMD-ONLY11-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 -// SIMD-ONLY11-NEXT: store double [[INC]], double* [[ARRAYIDX13]], align 8 -// SIMD-ONLY11-NEXT: [[TMP14:%.*]] = load i32, i32* [[A]], align 4 -// SIMD-ONLY11-NEXT: [[TMP15:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// SIMD-ONLY11-NEXT: call void @llvm.stackrestore(i8* [[TMP15]]) +// SIMD-ONLY11-NEXT: store double [[INC]], ptr [[ARRAYIDX13]], align 8 +// SIMD-ONLY11-NEXT: [[TMP14:%.*]] = load i32, ptr [[A]], align 4 +// SIMD-ONLY11-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 +// SIMD-ONLY11-NEXT: call void @llvm.stackrestore(ptr [[TMP15]]) // SIMD-ONLY11-NEXT: ret i32 [[TMP14]] // // // SIMD-ONLY11-LABEL: define {{[^@]+}}@_Z3bariPd -// SIMD-ONLY11-SAME: (i32 noundef signext [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0]] { +// SIMD-ONLY11-SAME: (i32 noundef signext [[N:%.*]], ptr noundef [[PTR:%.*]]) #[[ATTR0]] { // SIMD-ONLY11-NEXT: entry: // SIMD-ONLY11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// SIMD-ONLY11-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 8 +// SIMD-ONLY11-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY11-NEXT: [[A:%.*]] = alloca i32, align 4 // SIMD-ONLY11-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 -// SIMD-ONLY11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// SIMD-ONLY11-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 8 -// SIMD-ONLY11-NEXT: store i32 0, i32* [[A]], align 4 -// SIMD-ONLY11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// SIMD-ONLY11-NEXT: [[TMP1:%.*]] = load double*, double** [[PTR_ADDR]], align 8 -// SIMD-ONLY11-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooiPd(i32 noundef signext [[TMP0]], double* noundef [[TMP1]]) -// SIMD-ONLY11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// SIMD-ONLY11-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 8 +// SIMD-ONLY11-NEXT: store i32 0, ptr [[A]], align 4 +// SIMD-ONLY11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// SIMD-ONLY11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8 +// SIMD-ONLY11-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooiPd(i32 noundef signext [[TMP0]], ptr noundef [[TMP1]]) +// SIMD-ONLY11-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CALL]] -// SIMD-ONLY11-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// SIMD-ONLY11-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// SIMD-ONLY11-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP3]]) -// SIMD-ONLY11-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY11-NEXT: store i32 [[ADD]], ptr [[A]], align 4 +// SIMD-ONLY11-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// SIMD-ONLY11-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(ptr noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP3]]) +// SIMD-ONLY11-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], [[CALL1]] -// SIMD-ONLY11-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// SIMD-ONLY11-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// SIMD-ONLY11-NEXT: store i32 [[ADD2]], ptr [[A]], align 4 +// SIMD-ONLY11-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY11-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP5]]) -// SIMD-ONLY11-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY11-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], [[CALL3]] -// SIMD-ONLY11-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// SIMD-ONLY11-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// SIMD-ONLY11-NEXT: store i32 [[ADD4]], ptr [[A]], align 4 +// SIMD-ONLY11-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY11-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP7]]) -// SIMD-ONLY11-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY11-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP8]], [[CALL5]] -// SIMD-ONLY11-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// SIMD-ONLY11-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY11-NEXT: store i32 [[ADD6]], ptr [[A]], align 4 +// SIMD-ONLY11-NEXT: [[TMP9:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY11-NEXT: ret i32 [[TMP9]] // // // SIMD-ONLY11-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// SIMD-ONLY11-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// SIMD-ONLY11-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { // SIMD-ONLY11-NEXT: entry: -// SIMD-ONLY11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 +// SIMD-ONLY11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // SIMD-ONLY11-NEXT: [[B:%.*]] = alloca i32, align 4 -// SIMD-ONLY11-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +// SIMD-ONLY11-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 // SIMD-ONLY11-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// SIMD-ONLY11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 -// SIMD-ONLY11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// SIMD-ONLY11-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 -// SIMD-ONLY11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// SIMD-ONLY11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// SIMD-ONLY11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// SIMD-ONLY11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// SIMD-ONLY11-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// SIMD-ONLY11-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// SIMD-ONLY11-NEXT: store i32 [[ADD]], ptr [[B]], align 4 +// SIMD-ONLY11-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY11-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// SIMD-ONLY11-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() -// SIMD-ONLY11-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 +// SIMD-ONLY11-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave() +// SIMD-ONLY11-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8 // SIMD-ONLY11-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] // SIMD-ONLY11-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 -// SIMD-ONLY11-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 -// SIMD-ONLY11-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 +// SIMD-ONLY11-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 +// SIMD-ONLY11-NEXT: [[TMP5:%.*]] = load i32, ptr [[B]], align 4 // SIMD-ONLY11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double // SIMD-ONLY11-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// SIMD-ONLY11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// SIMD-ONLY11-NEXT: store double [[ADD2]], double* [[A]], align 8 -// SIMD-ONLY11-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// SIMD-ONLY11-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 8 +// SIMD-ONLY11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0 +// SIMD-ONLY11-NEXT: store double [[ADD2]], ptr [[A]], align 8 +// SIMD-ONLY11-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[THIS1]], i32 0, i32 0 +// SIMD-ONLY11-NEXT: [[TMP6:%.*]] = load double, ptr [[A3]], align 8 // SIMD-ONLY11-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00 -// SIMD-ONLY11-NEXT: store double [[INC]], double* [[A3]], align 8 +// SIMD-ONLY11-NEXT: store double [[INC]], ptr [[A3]], align 8 // SIMD-ONLY11-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 // SIMD-ONLY11-NEXT: [[TMP7:%.*]] = mul nsw i64 1, [[TMP2]] -// SIMD-ONLY11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP7]] -// SIMD-ONLY11-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 -// SIMD-ONLY11-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 +// SIMD-ONLY11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP7]] +// SIMD-ONLY11-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1 +// SIMD-ONLY11-NEXT: store i16 [[CONV4]], ptr [[ARRAYIDX5]], align 2 // SIMD-ONLY11-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] -// SIMD-ONLY11-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]] -// SIMD-ONLY11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1 -// SIMD-ONLY11-NEXT: [[TMP9:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 +// SIMD-ONLY11-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP8]] +// SIMD-ONLY11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX6]], i64 1 +// SIMD-ONLY11-NEXT: [[TMP9:%.*]] = load i16, ptr [[ARRAYIDX7]], align 2 // SIMD-ONLY11-NEXT: [[CONV8:%.*]] = sext i16 [[TMP9]] to i32 -// SIMD-ONLY11-NEXT: [[TMP10:%.*]] = load i32, i32* [[B]], align 4 +// SIMD-ONLY11-NEXT: [[TMP10:%.*]] = load i32, ptr [[B]], align 4 // SIMD-ONLY11-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP10]] -// SIMD-ONLY11-NEXT: [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 -// SIMD-ONLY11-NEXT: call void @llvm.stackrestore(i8* [[TMP11]]) +// SIMD-ONLY11-NEXT: [[TMP11:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 +// SIMD-ONLY11-NEXT: call void @llvm.stackrestore(ptr [[TMP11]]) // SIMD-ONLY11-NEXT: ret i32 [[ADD9]] // // @@ -11566,22 +11176,22 @@ int bar(int n, double *ptr) { // SIMD-ONLY11-NEXT: [[A:%.*]] = alloca i32, align 4 // SIMD-ONLY11-NEXT: [[AAA:%.*]] = alloca i8, align 1 // SIMD-ONLY11-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// SIMD-ONLY11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// SIMD-ONLY11-NEXT: store i32 0, i32* [[A]], align 4 -// SIMD-ONLY11-NEXT: store i8 0, i8* [[AAA]], align 1 -// SIMD-ONLY11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// SIMD-ONLY11-NEXT: store i32 0, ptr [[A]], align 4 +// SIMD-ONLY11-NEXT: store i8 0, ptr [[AAA]], align 1 +// SIMD-ONLY11-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// SIMD-ONLY11-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// SIMD-ONLY11-NEXT: [[TMP1:%.*]] = load i8, i8* [[AAA]], align 1 +// SIMD-ONLY11-NEXT: store i32 [[ADD]], ptr [[A]], align 4 +// SIMD-ONLY11-NEXT: [[TMP1:%.*]] = load i8, ptr [[AAA]], align 1 // SIMD-ONLY11-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32 // SIMD-ONLY11-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 // SIMD-ONLY11-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i8 -// SIMD-ONLY11-NEXT: store i8 [[CONV2]], i8* [[AAA]], align 1 -// SIMD-ONLY11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// SIMD-ONLY11-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// SIMD-ONLY11-NEXT: store i8 [[CONV2]], ptr [[AAA]], align 1 +// SIMD-ONLY11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i64 0, i64 2 +// SIMD-ONLY11-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // SIMD-ONLY11-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// SIMD-ONLY11-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// SIMD-ONLY11-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY11-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4 +// SIMD-ONLY11-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY11-NEXT: ret i32 [[TMP3]] // // @@ -11591,169 +11201,169 @@ int bar(int n, double *ptr) { // SIMD-ONLY11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // SIMD-ONLY11-NEXT: [[A:%.*]] = alloca i32, align 4 // SIMD-ONLY11-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// SIMD-ONLY11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// SIMD-ONLY11-NEXT: store i32 0, i32* [[A]], align 4 -// SIMD-ONLY11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// SIMD-ONLY11-NEXT: store i32 0, ptr [[A]], align 4 +// SIMD-ONLY11-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// SIMD-ONLY11-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// SIMD-ONLY11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 -// SIMD-ONLY11-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// SIMD-ONLY11-NEXT: store i32 [[ADD]], ptr [[A]], align 4 +// SIMD-ONLY11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i64 0, i64 2 +// SIMD-ONLY11-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // SIMD-ONLY11-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP1]], 1 -// SIMD-ONLY11-NEXT: store i32 [[ADD1]], i32* [[ARRAYIDX]], align 4 -// SIMD-ONLY11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY11-NEXT: store i32 [[ADD1]], ptr [[ARRAYIDX]], align 4 +// SIMD-ONLY11-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY11-NEXT: ret i32 [[TMP2]] // // // SIMD-ONLY12-LABEL: define {{[^@]+}}@_Z3fooiPd -// SIMD-ONLY12-SAME: (i32 noundef [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0:[0-9]+]] { +// SIMD-ONLY12-SAME: (i32 noundef [[N:%.*]], ptr noundef [[PTR:%.*]]) #[[ATTR0:[0-9]+]] { // SIMD-ONLY12-NEXT: entry: // SIMD-ONLY12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// SIMD-ONLY12-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 4 +// SIMD-ONLY12-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 4 // SIMD-ONLY12-NEXT: [[A:%.*]] = alloca i32, align 4 // SIMD-ONLY12-NEXT: [[AA:%.*]] = alloca i16, align 2 // SIMD-ONLY12-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// SIMD-ONLY12-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// SIMD-ONLY12-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4 // SIMD-ONLY12-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 // SIMD-ONLY12-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 // SIMD-ONLY12-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 // SIMD-ONLY12-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 // SIMD-ONLY12-NEXT: [[E:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 4 -// SIMD-ONLY12-NEXT: [[P:%.*]] = alloca i32*, align 64 -// SIMD-ONLY12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// SIMD-ONLY12-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 4 -// SIMD-ONLY12-NEXT: store i32 0, i32* [[A]], align 4 -// SIMD-ONLY12-NEXT: store i16 0, i16* [[AA]], align 2 -// SIMD-ONLY12-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// SIMD-ONLY12-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// SIMD-ONLY12-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 +// SIMD-ONLY12-NEXT: [[P:%.*]] = alloca ptr, align 64 +// SIMD-ONLY12-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// SIMD-ONLY12-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 4 +// SIMD-ONLY12-NEXT: store i32 0, ptr [[A]], align 4 +// SIMD-ONLY12-NEXT: store i16 0, ptr [[AA]], align 2 +// SIMD-ONLY12-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// SIMD-ONLY12-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave() +// SIMD-ONLY12-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4 // SIMD-ONLY12-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// SIMD-ONLY12-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// SIMD-ONLY12-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// SIMD-ONLY12-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 +// SIMD-ONLY12-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY12-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] // SIMD-ONLY12-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// SIMD-ONLY12-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// SIMD-ONLY12-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 0 -// SIMD-ONLY12-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// SIMD-ONLY12-NEXT: store i32 [[TMP4]], i32* [[X]], align 4 -// SIMD-ONLY12-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 1 -// SIMD-ONLY12-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// SIMD-ONLY12-NEXT: store i32 [[TMP5]], i32* [[Y]], align 4 -// SIMD-ONLY12-NEXT: store i32* [[A]], i32** [[P]], align 64 -// SIMD-ONLY12-NEXT: [[TMP6:%.*]] = load i16, i16* [[AA]], align 2 +// SIMD-ONLY12-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 4 +// SIMD-ONLY12-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 0 +// SIMD-ONLY12-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// SIMD-ONLY12-NEXT: store i32 [[TMP4]], ptr [[X]], align 4 +// SIMD-ONLY12-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 1 +// SIMD-ONLY12-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// SIMD-ONLY12-NEXT: store i32 [[TMP5]], ptr [[Y]], align 4 +// SIMD-ONLY12-NEXT: store ptr [[A]], ptr [[P]], align 64 +// SIMD-ONLY12-NEXT: [[TMP6:%.*]] = load i16, ptr [[AA]], align 2 // SIMD-ONLY12-NEXT: [[CONV:%.*]] = sext i16 [[TMP6]] to i32 // SIMD-ONLY12-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 // SIMD-ONLY12-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 -// SIMD-ONLY12-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// SIMD-ONLY12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 -// SIMD-ONLY12-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4 -// SIMD-ONLY12-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 -// SIMD-ONLY12-NEXT: store float 1.000000e+00, float* [[ARRAYIDX3]], align 4 -// SIMD-ONLY12-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// SIMD-ONLY12-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX4]], i32 0, i32 2 -// SIMD-ONLY12-NEXT: store double 1.000000e+00, double* [[ARRAYIDX5]], align 8 +// SIMD-ONLY12-NEXT: store i16 [[CONV2]], ptr [[AA]], align 2 +// SIMD-ONLY12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], i32 0, i32 2 +// SIMD-ONLY12-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX]], align 4 +// SIMD-ONLY12-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[VLA]], i32 3 +// SIMD-ONLY12-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX3]], align 4 +// SIMD-ONLY12-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C]], i32 0, i32 1 +// SIMD-ONLY12-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX4]], i32 0, i32 2 +// SIMD-ONLY12-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX5]], align 8 // SIMD-ONLY12-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP2]] -// SIMD-ONLY12-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP7]] -// SIMD-ONLY12-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX6]], i32 3 -// SIMD-ONLY12-NEXT: store double 1.000000e+00, double* [[ARRAYIDX7]], align 8 -// SIMD-ONLY12-NEXT: [[X8:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// SIMD-ONLY12-NEXT: store i64 1, i64* [[X8]], align 4 -// SIMD-ONLY12-NEXT: [[Y9:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// SIMD-ONLY12-NEXT: store i8 1, i8* [[Y9]], align 4 -// SIMD-ONLY12-NEXT: [[X10:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 0 -// SIMD-ONLY12-NEXT: [[TMP8:%.*]] = load i32, i32* [[X10]], align 4 +// SIMD-ONLY12-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds double, ptr [[VLA1]], i32 [[TMP7]] +// SIMD-ONLY12-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX6]], i32 3 +// SIMD-ONLY12-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX7]], align 8 +// SIMD-ONLY12-NEXT: [[X8:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D]], i32 0, i32 0 +// SIMD-ONLY12-NEXT: store i64 1, ptr [[X8]], align 4 +// SIMD-ONLY12-NEXT: [[Y9:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D]], i32 0, i32 1 +// SIMD-ONLY12-NEXT: store i8 1, ptr [[Y9]], align 4 +// SIMD-ONLY12-NEXT: [[X10:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 0 +// SIMD-ONLY12-NEXT: [[TMP8:%.*]] = load i32, ptr [[X10]], align 4 // SIMD-ONLY12-NEXT: [[CONV11:%.*]] = sitofp i32 [[TMP8]] to double -// SIMD-ONLY12-NEXT: [[TMP9:%.*]] = load double*, double** [[PTR_ADDR]], align 4 -// SIMD-ONLY12-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds double, double* [[TMP9]], i32 0 -// SIMD-ONLY12-NEXT: store double [[CONV11]], double* [[ARRAYIDX12]], align 4 -// SIMD-ONLY12-NEXT: [[TMP10:%.*]] = load double*, double** [[PTR_ADDR]], align 4 -// SIMD-ONLY12-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds double, double* [[TMP10]], i32 0 -// SIMD-ONLY12-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 4 +// SIMD-ONLY12-NEXT: [[TMP9:%.*]] = load ptr, ptr [[PTR_ADDR]], align 4 +// SIMD-ONLY12-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds double, ptr [[TMP9]], i32 0 +// SIMD-ONLY12-NEXT: store double [[CONV11]], ptr [[ARRAYIDX12]], align 4 +// SIMD-ONLY12-NEXT: [[TMP10:%.*]] = load ptr, ptr [[PTR_ADDR]], align 4 +// SIMD-ONLY12-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds double, ptr [[TMP10]], i32 0 +// SIMD-ONLY12-NEXT: [[TMP11:%.*]] = load double, ptr [[ARRAYIDX13]], align 4 // SIMD-ONLY12-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+00 -// SIMD-ONLY12-NEXT: store double [[INC]], double* [[ARRAYIDX13]], align 4 -// SIMD-ONLY12-NEXT: [[TMP12:%.*]] = load i32, i32* [[A]], align 4 -// SIMD-ONLY12-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// SIMD-ONLY12-NEXT: call void @llvm.stackrestore(i8* [[TMP13]]) +// SIMD-ONLY12-NEXT: store double [[INC]], ptr [[ARRAYIDX13]], align 4 +// SIMD-ONLY12-NEXT: [[TMP12:%.*]] = load i32, ptr [[A]], align 4 +// SIMD-ONLY12-NEXT: [[TMP13:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 +// SIMD-ONLY12-NEXT: call void @llvm.stackrestore(ptr [[TMP13]]) // SIMD-ONLY12-NEXT: ret i32 [[TMP12]] // // // SIMD-ONLY12-LABEL: define {{[^@]+}}@_Z3bariPd -// SIMD-ONLY12-SAME: (i32 noundef [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0]] { +// SIMD-ONLY12-SAME: (i32 noundef [[N:%.*]], ptr noundef [[PTR:%.*]]) #[[ATTR0]] { // SIMD-ONLY12-NEXT: entry: // SIMD-ONLY12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// SIMD-ONLY12-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 4 +// SIMD-ONLY12-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 4 // SIMD-ONLY12-NEXT: [[A:%.*]] = alloca i32, align 4 // SIMD-ONLY12-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// SIMD-ONLY12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// SIMD-ONLY12-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 4 -// SIMD-ONLY12-NEXT: store i32 0, i32* [[A]], align 4 -// SIMD-ONLY12-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// SIMD-ONLY12-NEXT: [[TMP1:%.*]] = load double*, double** [[PTR_ADDR]], align 4 -// SIMD-ONLY12-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooiPd(i32 noundef [[TMP0]], double* noundef [[TMP1]]) -// SIMD-ONLY12-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY12-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// SIMD-ONLY12-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 4 +// SIMD-ONLY12-NEXT: store i32 0, ptr [[A]], align 4 +// SIMD-ONLY12-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// SIMD-ONLY12-NEXT: [[TMP1:%.*]] = load ptr, ptr [[PTR_ADDR]], align 4 +// SIMD-ONLY12-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooiPd(i32 noundef [[TMP0]], ptr noundef [[TMP1]]) +// SIMD-ONLY12-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CALL]] -// SIMD-ONLY12-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// SIMD-ONLY12-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// SIMD-ONLY12-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP3]]) -// SIMD-ONLY12-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY12-NEXT: store i32 [[ADD]], ptr [[A]], align 4 +// SIMD-ONLY12-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// SIMD-ONLY12-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP3]]) +// SIMD-ONLY12-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], [[CALL1]] -// SIMD-ONLY12-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// SIMD-ONLY12-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// SIMD-ONLY12-NEXT: store i32 [[ADD2]], ptr [[A]], align 4 +// SIMD-ONLY12-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY12-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP5]]) -// SIMD-ONLY12-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY12-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY12-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], [[CALL3]] -// SIMD-ONLY12-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// SIMD-ONLY12-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// SIMD-ONLY12-NEXT: store i32 [[ADD4]], ptr [[A]], align 4 +// SIMD-ONLY12-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY12-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP7]]) -// SIMD-ONLY12-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY12-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY12-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP8]], [[CALL5]] -// SIMD-ONLY12-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// SIMD-ONLY12-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY12-NEXT: store i32 [[ADD6]], ptr [[A]], align 4 +// SIMD-ONLY12-NEXT: [[TMP9:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY12-NEXT: ret i32 [[TMP9]] // // // SIMD-ONLY12-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// SIMD-ONLY12-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// SIMD-ONLY12-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { // SIMD-ONLY12-NEXT: entry: -// SIMD-ONLY12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// SIMD-ONLY12-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // SIMD-ONLY12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // SIMD-ONLY12-NEXT: [[B:%.*]] = alloca i32, align 4 -// SIMD-ONLY12-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// SIMD-ONLY12-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4 // SIMD-ONLY12-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// SIMD-ONLY12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// SIMD-ONLY12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// SIMD-ONLY12-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// SIMD-ONLY12-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// SIMD-ONLY12-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 +// SIMD-ONLY12-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// SIMD-ONLY12-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 +// SIMD-ONLY12-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// SIMD-ONLY12-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// SIMD-ONLY12-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// SIMD-ONLY12-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// SIMD-ONLY12-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 +// SIMD-ONLY12-NEXT: store i32 [[ADD]], ptr [[B]], align 4 +// SIMD-ONLY12-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// SIMD-ONLY12-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() +// SIMD-ONLY12-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 // SIMD-ONLY12-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] // SIMD-ONLY12-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// SIMD-ONLY12-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// SIMD-ONLY12-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 +// SIMD-ONLY12-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 +// SIMD-ONLY12-NEXT: [[TMP4:%.*]] = load i32, ptr [[B]], align 4 // SIMD-ONLY12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double // SIMD-ONLY12-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// SIMD-ONLY12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// SIMD-ONLY12-NEXT: store double [[ADD2]], double* [[A]], align 4 -// SIMD-ONLY12-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// SIMD-ONLY12-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 +// SIMD-ONLY12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0 +// SIMD-ONLY12-NEXT: store double [[ADD2]], ptr [[A]], align 4 +// SIMD-ONLY12-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[THIS1]], i32 0, i32 0 +// SIMD-ONLY12-NEXT: [[TMP5:%.*]] = load double, ptr [[A3]], align 4 // SIMD-ONLY12-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 -// SIMD-ONLY12-NEXT: store double [[INC]], double* [[A3]], align 4 +// SIMD-ONLY12-NEXT: store double [[INC]], ptr [[A3]], align 4 // SIMD-ONLY12-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 // SIMD-ONLY12-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP1]] -// SIMD-ONLY12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP6]] -// SIMD-ONLY12-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// SIMD-ONLY12-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 +// SIMD-ONLY12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP6]] +// SIMD-ONLY12-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1 +// SIMD-ONLY12-NEXT: store i16 [[CONV4]], ptr [[ARRAYIDX5]], align 2 // SIMD-ONLY12-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] -// SIMD-ONLY12-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] -// SIMD-ONLY12-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1 -// SIMD-ONLY12-NEXT: [[TMP8:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 +// SIMD-ONLY12-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP7]] +// SIMD-ONLY12-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX6]], i32 1 +// SIMD-ONLY12-NEXT: [[TMP8:%.*]] = load i16, ptr [[ARRAYIDX7]], align 2 // SIMD-ONLY12-NEXT: [[CONV8:%.*]] = sext i16 [[TMP8]] to i32 -// SIMD-ONLY12-NEXT: [[TMP9:%.*]] = load i32, i32* [[B]], align 4 +// SIMD-ONLY12-NEXT: [[TMP9:%.*]] = load i32, ptr [[B]], align 4 // SIMD-ONLY12-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP9]] -// SIMD-ONLY12-NEXT: [[TMP10:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// SIMD-ONLY12-NEXT: call void @llvm.stackrestore(i8* [[TMP10]]) +// SIMD-ONLY12-NEXT: [[TMP10:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 +// SIMD-ONLY12-NEXT: call void @llvm.stackrestore(ptr [[TMP10]]) // SIMD-ONLY12-NEXT: ret i32 [[ADD9]] // // @@ -11764,22 +11374,22 @@ int bar(int n, double *ptr) { // SIMD-ONLY12-NEXT: [[A:%.*]] = alloca i32, align 4 // SIMD-ONLY12-NEXT: [[AAA:%.*]] = alloca i8, align 1 // SIMD-ONLY12-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// SIMD-ONLY12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// SIMD-ONLY12-NEXT: store i32 0, i32* [[A]], align 4 -// SIMD-ONLY12-NEXT: store i8 0, i8* [[AAA]], align 1 -// SIMD-ONLY12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY12-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// SIMD-ONLY12-NEXT: store i32 0, ptr [[A]], align 4 +// SIMD-ONLY12-NEXT: store i8 0, ptr [[AAA]], align 1 +// SIMD-ONLY12-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// SIMD-ONLY12-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// SIMD-ONLY12-NEXT: [[TMP1:%.*]] = load i8, i8* [[AAA]], align 1 +// SIMD-ONLY12-NEXT: store i32 [[ADD]], ptr [[A]], align 4 +// SIMD-ONLY12-NEXT: [[TMP1:%.*]] = load i8, ptr [[AAA]], align 1 // SIMD-ONLY12-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32 // SIMD-ONLY12-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 // SIMD-ONLY12-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i8 -// SIMD-ONLY12-NEXT: store i8 [[CONV2]], i8* [[AAA]], align 1 -// SIMD-ONLY12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// SIMD-ONLY12-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// SIMD-ONLY12-NEXT: store i8 [[CONV2]], ptr [[AAA]], align 1 +// SIMD-ONLY12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i32 0, i32 2 +// SIMD-ONLY12-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // SIMD-ONLY12-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// SIMD-ONLY12-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// SIMD-ONLY12-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY12-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4 +// SIMD-ONLY12-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY12-NEXT: ret i32 [[TMP3]] // // @@ -11789,169 +11399,169 @@ int bar(int n, double *ptr) { // SIMD-ONLY12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // SIMD-ONLY12-NEXT: [[A:%.*]] = alloca i32, align 4 // SIMD-ONLY12-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// SIMD-ONLY12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// SIMD-ONLY12-NEXT: store i32 0, i32* [[A]], align 4 -// SIMD-ONLY12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY12-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// SIMD-ONLY12-NEXT: store i32 0, ptr [[A]], align 4 +// SIMD-ONLY12-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// SIMD-ONLY12-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// SIMD-ONLY12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// SIMD-ONLY12-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// SIMD-ONLY12-NEXT: store i32 [[ADD]], ptr [[A]], align 4 +// SIMD-ONLY12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i32 0, i32 2 +// SIMD-ONLY12-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // SIMD-ONLY12-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP1]], 1 -// SIMD-ONLY12-NEXT: store i32 [[ADD1]], i32* [[ARRAYIDX]], align 4 -// SIMD-ONLY12-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY12-NEXT: store i32 [[ADD1]], ptr [[ARRAYIDX]], align 4 +// SIMD-ONLY12-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY12-NEXT: ret i32 [[TMP2]] // // // SIMD-ONLY13-LABEL: define {{[^@]+}}@_Z3fooiPd -// SIMD-ONLY13-SAME: (i32 noundef [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0:[0-9]+]] { +// SIMD-ONLY13-SAME: (i32 noundef [[N:%.*]], ptr noundef [[PTR:%.*]]) #[[ATTR0:[0-9]+]] { // SIMD-ONLY13-NEXT: entry: // SIMD-ONLY13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// SIMD-ONLY13-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 4 +// SIMD-ONLY13-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 4 // SIMD-ONLY13-NEXT: [[A:%.*]] = alloca i32, align 4 // SIMD-ONLY13-NEXT: [[AA:%.*]] = alloca i16, align 2 // SIMD-ONLY13-NEXT: [[B:%.*]] = alloca [10 x float], align 4 -// SIMD-ONLY13-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// SIMD-ONLY13-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4 // SIMD-ONLY13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 // SIMD-ONLY13-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 // SIMD-ONLY13-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 // SIMD-ONLY13-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 // SIMD-ONLY13-NEXT: [[E:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 4 -// SIMD-ONLY13-NEXT: [[P:%.*]] = alloca i32*, align 64 -// SIMD-ONLY13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// SIMD-ONLY13-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 4 -// SIMD-ONLY13-NEXT: store i32 0, i32* [[A]], align 4 -// SIMD-ONLY13-NEXT: store i16 0, i16* [[AA]], align 2 -// SIMD-ONLY13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// SIMD-ONLY13-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() -// SIMD-ONLY13-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 +// SIMD-ONLY13-NEXT: [[P:%.*]] = alloca ptr, align 64 +// SIMD-ONLY13-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// SIMD-ONLY13-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 4 +// SIMD-ONLY13-NEXT: store i32 0, ptr [[A]], align 4 +// SIMD-ONLY13-NEXT: store i16 0, ptr [[AA]], align 2 +// SIMD-ONLY13-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// SIMD-ONLY13-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave() +// SIMD-ONLY13-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4 // SIMD-ONLY13-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 -// SIMD-ONLY13-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 -// SIMD-ONLY13-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// SIMD-ONLY13-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 +// SIMD-ONLY13-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY13-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] // SIMD-ONLY13-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 -// SIMD-ONLY13-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 -// SIMD-ONLY13-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 0 -// SIMD-ONLY13-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// SIMD-ONLY13-NEXT: store i32 [[TMP4]], i32* [[X]], align 4 -// SIMD-ONLY13-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 1 -// SIMD-ONLY13-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// SIMD-ONLY13-NEXT: store i32 [[TMP5]], i32* [[Y]], align 4 -// SIMD-ONLY13-NEXT: store i32* [[A]], i32** [[P]], align 64 -// SIMD-ONLY13-NEXT: [[TMP6:%.*]] = load i16, i16* [[AA]], align 2 +// SIMD-ONLY13-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 4 +// SIMD-ONLY13-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 0 +// SIMD-ONLY13-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// SIMD-ONLY13-NEXT: store i32 [[TMP4]], ptr [[X]], align 4 +// SIMD-ONLY13-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 1 +// SIMD-ONLY13-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// SIMD-ONLY13-NEXT: store i32 [[TMP5]], ptr [[Y]], align 4 +// SIMD-ONLY13-NEXT: store ptr [[A]], ptr [[P]], align 64 +// SIMD-ONLY13-NEXT: [[TMP6:%.*]] = load i16, ptr [[AA]], align 2 // SIMD-ONLY13-NEXT: [[CONV:%.*]] = sext i16 [[TMP6]] to i32 // SIMD-ONLY13-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 // SIMD-ONLY13-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 -// SIMD-ONLY13-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// SIMD-ONLY13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 -// SIMD-ONLY13-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4 -// SIMD-ONLY13-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 -// SIMD-ONLY13-NEXT: store float 1.000000e+00, float* [[ARRAYIDX3]], align 4 -// SIMD-ONLY13-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// SIMD-ONLY13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX4]], i32 0, i32 2 -// SIMD-ONLY13-NEXT: store double 1.000000e+00, double* [[ARRAYIDX5]], align 8 +// SIMD-ONLY13-NEXT: store i16 [[CONV2]], ptr [[AA]], align 2 +// SIMD-ONLY13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], i32 0, i32 2 +// SIMD-ONLY13-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX]], align 4 +// SIMD-ONLY13-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[VLA]], i32 3 +// SIMD-ONLY13-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX3]], align 4 +// SIMD-ONLY13-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C]], i32 0, i32 1 +// SIMD-ONLY13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX4]], i32 0, i32 2 +// SIMD-ONLY13-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX5]], align 8 // SIMD-ONLY13-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP2]] -// SIMD-ONLY13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP7]] -// SIMD-ONLY13-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX6]], i32 3 -// SIMD-ONLY13-NEXT: store double 1.000000e+00, double* [[ARRAYIDX7]], align 8 -// SIMD-ONLY13-NEXT: [[X8:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 -// SIMD-ONLY13-NEXT: store i64 1, i64* [[X8]], align 4 -// SIMD-ONLY13-NEXT: [[Y9:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 -// SIMD-ONLY13-NEXT: store i8 1, i8* [[Y9]], align 4 -// SIMD-ONLY13-NEXT: [[X10:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 0 -// SIMD-ONLY13-NEXT: [[TMP8:%.*]] = load i32, i32* [[X10]], align 4 +// SIMD-ONLY13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds double, ptr [[VLA1]], i32 [[TMP7]] +// SIMD-ONLY13-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX6]], i32 3 +// SIMD-ONLY13-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX7]], align 8 +// SIMD-ONLY13-NEXT: [[X8:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D]], i32 0, i32 0 +// SIMD-ONLY13-NEXT: store i64 1, ptr [[X8]], align 4 +// SIMD-ONLY13-NEXT: [[Y9:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D]], i32 0, i32 1 +// SIMD-ONLY13-NEXT: store i8 1, ptr [[Y9]], align 4 +// SIMD-ONLY13-NEXT: [[X10:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 0 +// SIMD-ONLY13-NEXT: [[TMP8:%.*]] = load i32, ptr [[X10]], align 4 // SIMD-ONLY13-NEXT: [[CONV11:%.*]] = sitofp i32 [[TMP8]] to double -// SIMD-ONLY13-NEXT: [[TMP9:%.*]] = load double*, double** [[PTR_ADDR]], align 4 -// SIMD-ONLY13-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds double, double* [[TMP9]], i32 0 -// SIMD-ONLY13-NEXT: store double [[CONV11]], double* [[ARRAYIDX12]], align 4 -// SIMD-ONLY13-NEXT: [[TMP10:%.*]] = load double*, double** [[PTR_ADDR]], align 4 -// SIMD-ONLY13-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds double, double* [[TMP10]], i32 0 -// SIMD-ONLY13-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 4 +// SIMD-ONLY13-NEXT: [[TMP9:%.*]] = load ptr, ptr [[PTR_ADDR]], align 4 +// SIMD-ONLY13-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds double, ptr [[TMP9]], i32 0 +// SIMD-ONLY13-NEXT: store double [[CONV11]], ptr [[ARRAYIDX12]], align 4 +// SIMD-ONLY13-NEXT: [[TMP10:%.*]] = load ptr, ptr [[PTR_ADDR]], align 4 +// SIMD-ONLY13-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds double, ptr [[TMP10]], i32 0 +// SIMD-ONLY13-NEXT: [[TMP11:%.*]] = load double, ptr [[ARRAYIDX13]], align 4 // SIMD-ONLY13-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+00 -// SIMD-ONLY13-NEXT: store double [[INC]], double* [[ARRAYIDX13]], align 4 -// SIMD-ONLY13-NEXT: [[TMP12:%.*]] = load i32, i32* [[A]], align 4 -// SIMD-ONLY13-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// SIMD-ONLY13-NEXT: call void @llvm.stackrestore(i8* [[TMP13]]) +// SIMD-ONLY13-NEXT: store double [[INC]], ptr [[ARRAYIDX13]], align 4 +// SIMD-ONLY13-NEXT: [[TMP12:%.*]] = load i32, ptr [[A]], align 4 +// SIMD-ONLY13-NEXT: [[TMP13:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 +// SIMD-ONLY13-NEXT: call void @llvm.stackrestore(ptr [[TMP13]]) // SIMD-ONLY13-NEXT: ret i32 [[TMP12]] // // // SIMD-ONLY13-LABEL: define {{[^@]+}}@_Z3bariPd -// SIMD-ONLY13-SAME: (i32 noundef [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0]] { +// SIMD-ONLY13-SAME: (i32 noundef [[N:%.*]], ptr noundef [[PTR:%.*]]) #[[ATTR0]] { // SIMD-ONLY13-NEXT: entry: // SIMD-ONLY13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 -// SIMD-ONLY13-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 4 +// SIMD-ONLY13-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 4 // SIMD-ONLY13-NEXT: [[A:%.*]] = alloca i32, align 4 // SIMD-ONLY13-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 -// SIMD-ONLY13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// SIMD-ONLY13-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 4 -// SIMD-ONLY13-NEXT: store i32 0, i32* [[A]], align 4 -// SIMD-ONLY13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// SIMD-ONLY13-NEXT: [[TMP1:%.*]] = load double*, double** [[PTR_ADDR]], align 4 -// SIMD-ONLY13-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooiPd(i32 noundef [[TMP0]], double* noundef [[TMP1]]) -// SIMD-ONLY13-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY13-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// SIMD-ONLY13-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 4 +// SIMD-ONLY13-NEXT: store i32 0, ptr [[A]], align 4 +// SIMD-ONLY13-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// SIMD-ONLY13-NEXT: [[TMP1:%.*]] = load ptr, ptr [[PTR_ADDR]], align 4 +// SIMD-ONLY13-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooiPd(i32 noundef [[TMP0]], ptr noundef [[TMP1]]) +// SIMD-ONLY13-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CALL]] -// SIMD-ONLY13-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// SIMD-ONLY13-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// SIMD-ONLY13-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP3]]) -// SIMD-ONLY13-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY13-NEXT: store i32 [[ADD]], ptr [[A]], align 4 +// SIMD-ONLY13-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// SIMD-ONLY13-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP3]]) +// SIMD-ONLY13-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY13-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], [[CALL1]] -// SIMD-ONLY13-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 -// SIMD-ONLY13-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// SIMD-ONLY13-NEXT: store i32 [[ADD2]], ptr [[A]], align 4 +// SIMD-ONLY13-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY13-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP5]]) -// SIMD-ONLY13-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY13-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY13-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], [[CALL3]] -// SIMD-ONLY13-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 -// SIMD-ONLY13-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// SIMD-ONLY13-NEXT: store i32 [[ADD4]], ptr [[A]], align 4 +// SIMD-ONLY13-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY13-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP7]]) -// SIMD-ONLY13-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY13-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY13-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP8]], [[CALL5]] -// SIMD-ONLY13-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 -// SIMD-ONLY13-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY13-NEXT: store i32 [[ADD6]], ptr [[A]], align 4 +// SIMD-ONLY13-NEXT: [[TMP9:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY13-NEXT: ret i32 [[TMP9]] // // // SIMD-ONLY13-LABEL: define {{[^@]+}}@_ZN2S12r1Ei -// SIMD-ONLY13-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { +// SIMD-ONLY13-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { // SIMD-ONLY13-NEXT: entry: -// SIMD-ONLY13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 +// SIMD-ONLY13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // SIMD-ONLY13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // SIMD-ONLY13-NEXT: [[B:%.*]] = alloca i32, align 4 -// SIMD-ONLY13-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 +// SIMD-ONLY13-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4 // SIMD-ONLY13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 -// SIMD-ONLY13-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 -// SIMD-ONLY13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// SIMD-ONLY13-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 -// SIMD-ONLY13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 +// SIMD-ONLY13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 +// SIMD-ONLY13-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// SIMD-ONLY13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 +// SIMD-ONLY13-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// SIMD-ONLY13-NEXT: store i32 [[ADD]], i32* [[B]], align 4 -// SIMD-ONLY13-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 -// SIMD-ONLY13-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() -// SIMD-ONLY13-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 +// SIMD-ONLY13-NEXT: store i32 [[ADD]], ptr [[B]], align 4 +// SIMD-ONLY13-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// SIMD-ONLY13-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() +// SIMD-ONLY13-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 // SIMD-ONLY13-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] // SIMD-ONLY13-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 -// SIMD-ONLY13-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 -// SIMD-ONLY13-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 +// SIMD-ONLY13-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 +// SIMD-ONLY13-NEXT: [[TMP4:%.*]] = load i32, ptr [[B]], align 4 // SIMD-ONLY13-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double // SIMD-ONLY13-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 -// SIMD-ONLY13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 -// SIMD-ONLY13-NEXT: store double [[ADD2]], double* [[A]], align 4 -// SIMD-ONLY13-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 -// SIMD-ONLY13-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 +// SIMD-ONLY13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0 +// SIMD-ONLY13-NEXT: store double [[ADD2]], ptr [[A]], align 4 +// SIMD-ONLY13-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[THIS1]], i32 0, i32 0 +// SIMD-ONLY13-NEXT: [[TMP5:%.*]] = load double, ptr [[A3]], align 4 // SIMD-ONLY13-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 -// SIMD-ONLY13-NEXT: store double [[INC]], double* [[A3]], align 4 +// SIMD-ONLY13-NEXT: store double [[INC]], ptr [[A3]], align 4 // SIMD-ONLY13-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 // SIMD-ONLY13-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP1]] -// SIMD-ONLY13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP6]] -// SIMD-ONLY13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 -// SIMD-ONLY13-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 +// SIMD-ONLY13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP6]] +// SIMD-ONLY13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1 +// SIMD-ONLY13-NEXT: store i16 [[CONV4]], ptr [[ARRAYIDX5]], align 2 // SIMD-ONLY13-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] -// SIMD-ONLY13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]] -// SIMD-ONLY13-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1 -// SIMD-ONLY13-NEXT: [[TMP8:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2 +// SIMD-ONLY13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP7]] +// SIMD-ONLY13-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX6]], i32 1 +// SIMD-ONLY13-NEXT: [[TMP8:%.*]] = load i16, ptr [[ARRAYIDX7]], align 2 // SIMD-ONLY13-NEXT: [[CONV8:%.*]] = sext i16 [[TMP8]] to i32 -// SIMD-ONLY13-NEXT: [[TMP9:%.*]] = load i32, i32* [[B]], align 4 +// SIMD-ONLY13-NEXT: [[TMP9:%.*]] = load i32, ptr [[B]], align 4 // SIMD-ONLY13-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP9]] -// SIMD-ONLY13-NEXT: [[TMP10:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 -// SIMD-ONLY13-NEXT: call void @llvm.stackrestore(i8* [[TMP10]]) +// SIMD-ONLY13-NEXT: [[TMP10:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 +// SIMD-ONLY13-NEXT: call void @llvm.stackrestore(ptr [[TMP10]]) // SIMD-ONLY13-NEXT: ret i32 [[ADD9]] // // @@ -11962,22 +11572,22 @@ int bar(int n, double *ptr) { // SIMD-ONLY13-NEXT: [[A:%.*]] = alloca i32, align 4 // SIMD-ONLY13-NEXT: [[AAA:%.*]] = alloca i8, align 1 // SIMD-ONLY13-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// SIMD-ONLY13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// SIMD-ONLY13-NEXT: store i32 0, i32* [[A]], align 4 -// SIMD-ONLY13-NEXT: store i8 0, i8* [[AAA]], align 1 -// SIMD-ONLY13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY13-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// SIMD-ONLY13-NEXT: store i32 0, ptr [[A]], align 4 +// SIMD-ONLY13-NEXT: store i8 0, ptr [[AAA]], align 1 +// SIMD-ONLY13-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// SIMD-ONLY13-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// SIMD-ONLY13-NEXT: [[TMP1:%.*]] = load i8, i8* [[AAA]], align 1 +// SIMD-ONLY13-NEXT: store i32 [[ADD]], ptr [[A]], align 4 +// SIMD-ONLY13-NEXT: [[TMP1:%.*]] = load i8, ptr [[AAA]], align 1 // SIMD-ONLY13-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32 // SIMD-ONLY13-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 // SIMD-ONLY13-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i8 -// SIMD-ONLY13-NEXT: store i8 [[CONV2]], i8* [[AAA]], align 1 -// SIMD-ONLY13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// SIMD-ONLY13-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// SIMD-ONLY13-NEXT: store i8 [[CONV2]], ptr [[AAA]], align 1 +// SIMD-ONLY13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i32 0, i32 2 +// SIMD-ONLY13-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // SIMD-ONLY13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 -// SIMD-ONLY13-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 -// SIMD-ONLY13-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY13-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4 +// SIMD-ONLY13-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY13-NEXT: ret i32 [[TMP3]] // // @@ -11987,15 +11597,15 @@ int bar(int n, double *ptr) { // SIMD-ONLY13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // SIMD-ONLY13-NEXT: [[A:%.*]] = alloca i32, align 4 // SIMD-ONLY13-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 -// SIMD-ONLY13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 -// SIMD-ONLY13-NEXT: store i32 0, i32* [[A]], align 4 -// SIMD-ONLY13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY13-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// SIMD-ONLY13-NEXT: store i32 0, ptr [[A]], align 4 +// SIMD-ONLY13-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 -// SIMD-ONLY13-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// SIMD-ONLY13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 -// SIMD-ONLY13-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 +// SIMD-ONLY13-NEXT: store i32 [[ADD]], ptr [[A]], align 4 +// SIMD-ONLY13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i32 0, i32 2 +// SIMD-ONLY13-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // SIMD-ONLY13-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP1]], 1 -// SIMD-ONLY13-NEXT: store i32 [[ADD1]], i32* [[ARRAYIDX]], align 4 -// SIMD-ONLY13-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 +// SIMD-ONLY13-NEXT: store i32 [[ADD1]], ptr [[ARRAYIDX]], align 4 +// SIMD-ONLY13-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY13-NEXT: ret i32 [[TMP2]] //