diff --git a/llvm/test/CodeGen/ARM/ssat.ll b/llvm/test/CodeGen/ARM/ssat.ll
index a2027435ed291..9d9758b0515dd 100644
--- a/llvm/test/CodeGen/ARM/ssat.ll
+++ b/llvm/test/CodeGen/ARM/ssat.ll
@@ -1,5 +1,6 @@
-; RUN: llc -mtriple=armv4t-eabi %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=V4T
-; RUN: llc -mtriple=armv6t2-eabi %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=V6T2
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=armv4t-eabi %s -o - | FileCheck %s --check-prefix=V4T
+; RUN: llc -mtriple=armv6t2-eabi %s -o - | FileCheck %s --check-prefix=V6T2
 
 ; Check for several conditions that should result in SSAT.
 ; For example, the base test is equivalent to
@@ -16,9 +17,25 @@
 ; x < -k ? -k : (x > k ? k : x)
 ; 32-bit base test
 define i32 @sat_base_32bit(i32 %x) #0 {
-; CHECK-LABEL: sat_base_32bit:
-; V6T2: ssat r0, #24, r0
-; V4T-NOT: ssat
+; V4T-LABEL: sat_base_32bit:
+; V4T:       @ %bb.0: @ %entry
+; V4T-NEXT:    ldr r1, .LCPI0_0
+; V4T-NEXT:    cmp r0, r1
+; V4T-NEXT:    movlt r1, r0
+; V4T-NEXT:    mov r0, #1065353216
+; V4T-NEXT:    orr r0, r0, #-1073741824
+; V4T-NEXT:    cmn r1, #8388608
+; V4T-NEXT:    movgt r0, r1
+; V4T-NEXT:    bx lr
+; V4T-NEXT:    .p2align 2
+; V4T-NEXT:  @ %bb.1:
+; V4T-NEXT:  .LCPI0_0:
+; V4T-NEXT:    .long 8388607 @ 0x7fffff
+;
+; V6T2-LABEL: sat_base_32bit:
+; V6T2:       @ %bb.0: @ %entry
+; V6T2-NEXT:    ssat r0, #24, r0
+; V6T2-NEXT:    bx lr
 entry:
   %0 = icmp slt i32 %x, 8388607
   %saturateUp = select i1 %0, i32 %x, i32 8388607
@@ -30,9 +47,29 @@ entry:
 ; x < -k ? -k : (x > k ? k : x)
 ; 16-bit base test
 define i16 @sat_base_16bit(i16 %x) #0 {
-; CHECK-LABEL: sat_base_16bit:
-; V6T2: ssat r0, #12, r0
-; V4T-NOT: ssat
+; V4T-LABEL: sat_base_16bit:
+; V4T:       @ %bb.0: @ %entry
+; V4T-NEXT:    mov r2, #255
+; V4T-NEXT:    lsl r1, r0, #16
+; V4T-NEXT:    orr r2, r2, #1792
+; V4T-NEXT:    asr r1, r1, #16
+; V4T-NEXT:    cmp r1, r2
+; V4T-NEXT:    movlt r2, r0
+; V4T-NEXT:    lsl r0, r2, #16
+; V4T-NEXT:    asr r1, r0, #16
+; V4T-NEXT:    ldr r0, .LCPI1_0
+; V4T-NEXT:    cmn r1, #2048
+; V4T-NEXT:    movgt r0, r2
+; V4T-NEXT:    bx lr
+; V4T-NEXT:    .p2align 2
+; V4T-NEXT:  @ %bb.1:
+; V4T-NEXT:  .LCPI1_0:
+; V4T-NEXT:    .long 4294965248 @ 0xfffff800
+;
+; V6T2-LABEL: sat_base_16bit:
+; V6T2:       @ %bb.0: @ %entry
+; V6T2-NEXT:    ssat r0, #12, r0
+; V6T2-NEXT:    bx lr
 entry:
   %0 = icmp slt i16 %x, 2047
   %saturateUp = select i1 %0, i16 %x, i16 2047
@@ -44,9 +81,22 @@ entry:
 ; x < -k ? -k : (x > k ? k : x)
 ; 8-bit base test
 define i8 @sat_base_8bit(i8 %x) #0 {
-; CHECK-LABEL: sat_base_8bit:
-; V6T2: ssat r0, #6, r0
-; V4T-NOT: ssat
+; V4T-LABEL: sat_base_8bit:
+; V4T:       @ %bb.0: @ %entry
+; V4T-NEXT:    lsl r1, r0, #24
+; V4T-NEXT:    asr r1, r1, #24
+; V4T-NEXT:    cmp r1, #31
+; V4T-NEXT:    movge r0, #31
+; V4T-NEXT:    lsl r1, r0, #24
+; V4T-NEXT:    asr r1, r1, #24
+; V4T-NEXT:    cmn r1, #32
+; V4T-NEXT:    mvnle r0, #31
+; V4T-NEXT:    bx lr
+;
+; V6T2-LABEL: sat_base_8bit:
+; V6T2:       @ %bb.0: @ %entry
+; V6T2-NEXT:    ssat r0, #6, r0
+; V6T2-NEXT:    bx lr
 entry:
   %0 = icmp slt i8 %x, 31
   %saturateUp = select i1 %0, i8 %x, i8 31
@@ -63,9 +113,25 @@ entry:
 
 ; x < -k ? -k : (x < k ? x : k)
 define i32 @sat_lower_upper_1(i32 %x) #0 {
-; CHECK-LABEL: sat_lower_upper_1:
-; V6T2: ssat r0, #24, r0
-; V4T-NOT: ssat
+; V4T-LABEL: sat_lower_upper_1:
+; V4T:       @ %bb.0: @ %entry
+; V4T-NEXT:    ldr r1, .LCPI3_0
+; V4T-NEXT:    cmp r0, r1
+; V4T-NEXT:    movlt r1, r0
+; V4T-NEXT:    mov r0, #1065353216
+; V4T-NEXT:    orr r0, r0, #-1073741824
+; V4T-NEXT:    cmn r1, #8388608
+; V4T-NEXT:    movgt r0, r1
+; V4T-NEXT:    bx lr
+; V4T-NEXT:    .p2align 2
+; V4T-NEXT:  @ %bb.1:
+; V4T-NEXT:  .LCPI3_0:
+; V4T-NEXT:    .long 8388607 @ 0x7fffff
+;
+; V6T2-LABEL: sat_lower_upper_1:
+; V6T2:       @ %bb.0: @ %entry
+; V6T2-NEXT:    ssat r0, #24, r0
+; V6T2-NEXT:    bx lr
 entry:
   %cmpUp = icmp slt i32 %x, 8388607
   %saturateUp = select i1 %cmpUp, i32 %x, i32 8388607
@@ -76,9 +142,25 @@ entry:
 
 ; x > -k ? (x > k ? k : x) : -k
 define i32 @sat_lower_upper_2(i32 %x) #0 {
-; CHECK-LABEL: sat_lower_upper_2:
-; V6T2: ssat    r0, #24, r0
-; V4T-NOT: ssat
+; V4T-LABEL: sat_lower_upper_2:
+; V4T:       @ %bb.0: @ %entry
+; V4T-NEXT:    ldr r1, .LCPI4_0
+; V4T-NEXT:    cmp r0, r1
+; V4T-NEXT:    movlt r1, r0
+; V4T-NEXT:    mov r0, #1065353216
+; V4T-NEXT:    orr r0, r0, #-1073741824
+; V4T-NEXT:    cmn r1, #8388608
+; V4T-NEXT:    movgt r0, r1
+; V4T-NEXT:    bx lr
+; V4T-NEXT:    .p2align 2
+; V4T-NEXT:  @ %bb.1:
+; V4T-NEXT:  .LCPI4_0:
+; V4T-NEXT:    .long 8388607 @ 0x7fffff
+;
+; V6T2-LABEL: sat_lower_upper_2:
+; V6T2:       @ %bb.0: @ %entry
+; V6T2-NEXT:    ssat r0, #24, r0
+; V6T2-NEXT:    bx lr
 entry:
   %0 = icmp slt i32 %x, 8388607
   %saturateUp = select i1 %0, i32 %x, i32 8388607
@@ -89,9 +171,26 @@ entry:
 
 ; x < k ? (x < -k ? -k : x) : k
 define i32 @sat_upper_lower_1(i32 %x) #0 {
-; CHECK-LABEL: sat_upper_lower_1:
-; V6T2: ssat    r0, #24, r0
-; V4T-NOT: ssat
+; V4T-LABEL: sat_upper_lower_1:
+; V4T:       @ %bb.0: @ %entry
+; V4T-NEXT:    mov r1, #1065353216
+; V4T-NEXT:    cmn r0, #8388608
+; V4T-NEXT:    orr r1, r1, #-1073741824
+; V4T-NEXT:    movgt r1, r0
+; V4T-NEXT:    ldr r0, .LCPI5_0
+; V4T-NEXT:    cmp r1, r0
+; V4T-NEXT:    movge r1, r0
+; V4T-NEXT:    mov r0, r1
+; V4T-NEXT:    bx lr
+; V4T-NEXT:    .p2align 2
+; V4T-NEXT:  @ %bb.1:
+; V4T-NEXT:  .LCPI5_0:
+; V4T-NEXT:    .long 8388607 @ 0x7fffff
+;
+; V6T2-LABEL: sat_upper_lower_1:
+; V6T2:       @ %bb.0: @ %entry
+; V6T2-NEXT:    ssat r0, #24, r0
+; V6T2-NEXT:    bx lr
 entry:
   %0 = icmp sgt i32 %x, -8388608
   %saturateLow = select i1 %0, i32 %x, i32 -8388608
@@ -102,9 +201,26 @@ entry:
 
 ; x > k ? k : (x < -k ? -k : x)
 define i32 @sat_upper_lower_2(i32 %x) #0 {
-; CHECK-LABEL: sat_upper_lower_2:
-; V6T2: ssat    r0, #24, r0
-; V4T-NOT: ssat
+; V4T-LABEL: sat_upper_lower_2:
+; V4T:       @ %bb.0: @ %entry
+; V4T-NEXT:    mov r1, #1065353216
+; V4T-NEXT:    cmn r0, #8388608
+; V4T-NEXT:    orr r1, r1, #-1073741824
+; V4T-NEXT:    movgt r1, r0
+; V4T-NEXT:    ldr r0, .LCPI6_0
+; V4T-NEXT:    cmp r1, r0
+; V4T-NEXT:    movge r1, r0
+; V4T-NEXT:    mov r0, r1
+; V4T-NEXT:    bx lr
+; V4T-NEXT:    .p2align 2
+; V4T-NEXT:  @ %bb.1:
+; V4T-NEXT:  .LCPI6_0:
+; V4T-NEXT:    .long 8388607 @ 0x7fffff
+;
+; V6T2-LABEL: sat_upper_lower_2:
+; V6T2:       @ %bb.0: @ %entry
+; V6T2-NEXT:    ssat r0, #24, r0
+; V6T2-NEXT:    bx lr
 entry:
   %0 = icmp sgt i32 %x, -8388608
   %saturateLow = select i1 %0, i32 %x, i32 -8388608
@@ -115,9 +231,26 @@ entry:
 
 ; k < x ? k : (x > -k ? x : -k)
 define i32 @sat_upper_lower_3(i32 %x) #0 {
-; CHECK-LABEL: sat_upper_lower_3:
-; V6T2: ssat    r0, #24, r0
-; V4T-NOT: ssat
+; V4T-LABEL: sat_upper_lower_3:
+; V4T:       @ %bb.0: @ %entry
+; V4T-NEXT:    mov r1, #1065353216
+; V4T-NEXT:    cmn r0, #8388608
+; V4T-NEXT:    orr r1, r1, #-1073741824
+; V4T-NEXT:    movgt r1, r0
+; V4T-NEXT:    ldr r0, .LCPI7_0
+; V4T-NEXT:    cmp r1, r0
+; V4T-NEXT:    movge r1, r0
+; V4T-NEXT:    mov r0, r1
+; V4T-NEXT:    bx lr
+; V4T-NEXT:    .p2align 2
+; V4T-NEXT:  @ %bb.1:
+; V4T-NEXT:  .LCPI7_0:
+; V4T-NEXT:    .long 8388607 @ 0x7fffff
+;
+; V6T2-LABEL: sat_upper_lower_3:
+; V6T2:       @ %bb.0: @ %entry
+; V6T2-NEXT:    ssat r0, #24, r0
+; V6T2-NEXT:    bx lr
 entry:
   %cmpLow = icmp sgt i32 %x, -8388608
   %saturateLow = select i1 %cmpLow, i32 %x, i32 -8388608
@@ -133,9 +266,26 @@ entry:
 ; Check that >= and <= work the same as > and <
 ; k <= x ? k : (x >= -k ? x : -k)
 define i32 @sat_le_ge(i32 %x) #0 {
-; CHECK-LABEL: sat_le_ge:
-; V6T2: ssat    r0, #24, r0
-; V4T-NOT: ssat
+; V4T-LABEL: sat_le_ge:
+; V4T:       @ %bb.0: @ %entry
+; V4T-NEXT:    mov r1, #1065353216
+; V4T-NEXT:    cmn r0, #8388608
+; V4T-NEXT:    orr r1, r1, #-1073741824
+; V4T-NEXT:    movgt r1, r0
+; V4T-NEXT:    ldr r0, .LCPI8_0
+; V4T-NEXT:    cmp r1, r0
+; V4T-NEXT:    movge r1, r0
+; V4T-NEXT:    mov r0, r1
+; V4T-NEXT:    bx lr
+; V4T-NEXT:    .p2align 2
+; V4T-NEXT:  @ %bb.1:
+; V4T-NEXT:  .LCPI8_0:
+; V4T-NEXT:    .long 8388607 @ 0x7fffff
+;
+; V6T2-LABEL: sat_le_ge:
+; V6T2:       @ %bb.0: @ %entry
+; V6T2-NEXT:    ssat r0, #24, r0
+; V6T2-NEXT:    bx lr
 entry:
   %0 = icmp sgt i32 %x, -8388608
   %saturateLow = select i1 %0, i32 %x, i32 -8388608
@@ -152,8 +302,33 @@ entry:
 ; x > k ? k : (x > -k ? -k : x)
 ; First condition upper-saturates, second doesn't lower-saturate.
 define i32 @no_sat_missing_lower(i32 %x) #0 {
-; CHECK-LABEL: no_sat_missing_lower
-; CHECK-NOT: ssat
+; V4T-LABEL: no_sat_missing_lower:
+; V4T:       @ %bb.0: @ %entry
+; V4T-NEXT:    mov r2, #1065353216
+; V4T-NEXT:    cmn r0, #8388608
+; V4T-NEXT:    orr r2, r2, #-1073741824
+; V4T-NEXT:    ldr r1, .LCPI9_0
+; V4T-NEXT:    movlt r2, r0
+; V4T-NEXT:    cmp r0, #8388608
+; V4T-NEXT:    movlt r1, r2
+; V4T-NEXT:    mov r0, r1
+; V4T-NEXT:    bx lr
+; V4T-NEXT:    .p2align 2
+; V4T-NEXT:  @ %bb.1:
+; V4T-NEXT:  .LCPI9_0:
+; V4T-NEXT:    .long 8388607 @ 0x7fffff
+;
+; V6T2-LABEL: no_sat_missing_lower:
+; V6T2:       @ %bb.0: @ %entry
+; V6T2-NEXT:    movw r1, #0
+; V6T2-NEXT:    cmn r0, #8388608
+; V6T2-NEXT:    movt r1, #65408
+; V6T2-NEXT:    movlt r1, r0
+; V6T2-NEXT:    cmp r0, #8388608
+; V6T2-NEXT:    movwge r1, #65535
+; V6T2-NEXT:    movtge r1, #127
+; V6T2-NEXT:    mov r0, r1
+; V6T2-NEXT:    bx lr
 entry:
   %cmpUp = icmp sgt i32 %x, 8388607
   %0 = icmp slt i32 %x, -8388608
@@ -165,8 +340,35 @@ entry:
 ; x < k ? k : (x < -k ? -k : x)
 ; Second condition lower-saturates, first doesn't upper-saturate.
 define i32 @no_sat_missing_upper(i32 %x) #0 {
-; CHECK-LABEL: no_sat_missing_upper:
-; CHECK-NOT: ssat
+; V4T-LABEL: no_sat_missing_upper:
+; V4T:       @ %bb.0: @ %entry
+; V4T-NEXT:    mov r1, #1065353216
+; V4T-NEXT:    ldr r2, .LCPI10_0
+; V4T-NEXT:    orr r1, r1, #-1073741824
+; V4T-NEXT:    cmn r0, #8388608
+; V4T-NEXT:    movgt r1, r0
+; V4T-NEXT:    cmp r0, r2
+; V4T-NEXT:    movlt r1, r2
+; V4T-NEXT:    mov r0, r1
+; V4T-NEXT:    bx lr
+; V4T-NEXT:    .p2align 2
+; V4T-NEXT:  @ %bb.1:
+; V4T-NEXT:  .LCPI10_0:
+; V4T-NEXT:    .long 8388607 @ 0x7fffff
+;
+; V6T2-LABEL: no_sat_missing_upper:
+; V6T2:       @ %bb.0: @ %entry
+; V6T2-NEXT:    movw r1, #0
+; V6T2-NEXT:    movw r2, #65535
+; V6T2-NEXT:    movt r1, #65408
+; V6T2-NEXT:    cmn r0, #8388608
+; V6T2-NEXT:    movgt r1, r0
+; V6T2-NEXT:    movt r2, #127
+; V6T2-NEXT:    cmp r0, r2
+; V6T2-NEXT:    movwlt r1, #65535
+; V6T2-NEXT:    movtlt r1, #127
+; V6T2-NEXT:    mov r0, r1
+; V6T2-NEXT:    bx lr
 entry:
   %cmpUp = icmp slt i32 %x, 8388607
   %0 = icmp sgt i32 %x, -8388608
@@ -177,8 +379,35 @@ entry:
 
 ; Lower constant is different in the select and in the compare
 define i32 @no_sat_incorrect_constant(i32 %x) #0 {
-; CHECK-LABEL: no_sat_incorrect_constant:
-; CHECK-NOT: ssat
+; V4T-LABEL: no_sat_incorrect_constant:
+; V4T:       @ %bb.0: @ %entry
+; V4T-NEXT:    mov r2, #1065353216
+; V4T-NEXT:    cmn r0, #8388608
+; V4T-NEXT:    orr r2, r2, #-1073741824
+; V4T-NEXT:    mov r1, r0
+; V4T-NEXT:    orrlt r1, r2, #1
+; V4T-NEXT:    ldr r2, .LCPI11_0
+; V4T-NEXT:    cmp r0, #8388608
+; V4T-NEXT:    movge r1, r2
+; V4T-NEXT:    mov r0, r1
+; V4T-NEXT:    bx lr
+; V4T-NEXT:    .p2align 2
+; V4T-NEXT:  @ %bb.1:
+; V4T-NEXT:  .LCPI11_0:
+; V4T-NEXT:    .long 8388607 @ 0x7fffff
+;
+; V6T2-LABEL: no_sat_incorrect_constant:
+; V6T2:       @ %bb.0: @ %entry
+; V6T2-NEXT:    movw r2, #0
+; V6T2-NEXT:    cmn r0, #8388608
+; V6T2-NEXT:    mov r1, r0
+; V6T2-NEXT:    movt r2, #65408
+; V6T2-NEXT:    orrlt r1, r2, #1
+; V6T2-NEXT:    cmp r0, #8388608
+; V6T2-NEXT:    movwge r1, #65535
+; V6T2-NEXT:    movtge r1, #127
+; V6T2-NEXT:    mov r0, r1
+; V6T2-NEXT:    bx lr
 entry:
   %cmpUp = icmp sgt i32 %x, 8388607
   %cmpLow = icmp slt i32 %x, -8388608
@@ -189,8 +418,35 @@ entry:
 
 ; The interval is not [k, ~k]
 define i32 @no_sat_incorrect_interval(i32 %x) #0 {
-; CHECK-LABEL: no_sat_incorrect_interval:
-; CHECK-NOT: ssat
+; V4T-LABEL: no_sat_incorrect_interval:
+; V4T:       @ %bb.0: @ %entry
+; V4T-NEXT:    ldr r1, .LCPI12_0
+; V4T-NEXT:    cmp r0, r1
+; V4T-NEXT:    movgt r1, r0
+; V4T-NEXT:    ldr r0, .LCPI12_1
+; V4T-NEXT:    cmp r1, r0
+; V4T-NEXT:    movge r1, r0
+; V4T-NEXT:    mov r0, r1
+; V4T-NEXT:    bx lr
+; V4T-NEXT:    .p2align 2
+; V4T-NEXT:  @ %bb.1:
+; V4T-NEXT:  .LCPI12_0:
+; V4T-NEXT:    .long 4275878552 @ 0xfedcba98
+; V4T-NEXT:  .LCPI12_1:
+; V4T-NEXT:    .long 8388607 @ 0x7fffff
+;
+; V6T2-LABEL: no_sat_incorrect_interval:
+; V6T2:       @ %bb.0: @ %entry
+; V6T2-NEXT:    movw r1, #47768
+; V6T2-NEXT:    movt r1, #65244
+; V6T2-NEXT:    cmp r0, r1
+; V6T2-NEXT:    movgt r1, r0
+; V6T2-NEXT:    movw r0, #65535
+; V6T2-NEXT:    movt r0, #127
+; V6T2-NEXT:    cmp r1, r0
+; V6T2-NEXT:    movge r1, r0
+; V6T2-NEXT:    mov r0, r1
+; V6T2-NEXT:    bx lr
 entry:
   %0 = icmp sgt i32 %x, -19088744
   %saturateLow = select i1 %0, i32 %x, i32 -19088744
@@ -201,8 +457,32 @@ entry:
 
 ; The returned value (y) is not the same as the tested value (x).
 define i32 @no_sat_incorrect_return(i32 %x, i32 %y) #0 {
-; CHECK-LABEL: no_sat_incorrect_return:
-; CHECK-NOT: ssat
+; V4T-LABEL: no_sat_incorrect_return:
+; V4T:       @ %bb.0: @ %entry
+; V4T-NEXT:    mov r2, #1065353216
+; V4T-NEXT:    cmn r0, #8388608
+; V4T-NEXT:    orr r2, r2, #-1073741824
+; V4T-NEXT:    movge r2, r1
+; V4T-NEXT:    ldr r1, .LCPI13_0
+; V4T-NEXT:    cmp r0, #8388608
+; V4T-NEXT:    movlt r1, r2
+; V4T-NEXT:    mov r0, r1
+; V4T-NEXT:    bx lr
+; V4T-NEXT:    .p2align 2
+; V4T-NEXT:  @ %bb.1:
+; V4T-NEXT:  .LCPI13_0:
+; V4T-NEXT:    .long 8388607 @ 0x7fffff
+;
+; V6T2-LABEL: no_sat_incorrect_return:
+; V6T2:       @ %bb.0: @ %entry
+; V6T2-NEXT:    cmn r0, #8388608
+; V6T2-NEXT:    movwlt r1, #0
+; V6T2-NEXT:    movtlt r1, #65408
+; V6T2-NEXT:    cmp r0, #8388608
+; V6T2-NEXT:    movwge r1, #65535
+; V6T2-NEXT:    movtge r1, #127
+; V6T2-NEXT:    mov r0, r1
+; V6T2-NEXT:    bx lr
 entry:
   %cmpUp = icmp sgt i32 %x, 8388607
   %cmpLow = icmp slt i32 %x, -8388608
@@ -214,8 +494,33 @@ entry:
 ; One of the values in a compare (y) is not the same as the rest
 ; of the compare and select values (x).
 define i32 @no_sat_incorrect_compare(i32 %x, i32 %y) #0 {
-; CHECK-LABEL: no_sat_incorrect_compare:
-; CHECK-NOT: ssat
+; V4T-LABEL: no_sat_incorrect_compare:
+; V4T:       @ %bb.0: @ %entry
+; V4T-NEXT:    mov r2, #1065353216
+; V4T-NEXT:    cmn r1, #8388608
+; V4T-NEXT:    orr r2, r2, #-1073741824
+; V4T-NEXT:    ldr r1, .LCPI14_0
+; V4T-NEXT:    movge r2, r0
+; V4T-NEXT:    cmp r0, #8388608
+; V4T-NEXT:    movlt r1, r2
+; V4T-NEXT:    mov r0, r1
+; V4T-NEXT:    bx lr
+; V4T-NEXT:    .p2align 2
+; V4T-NEXT:  @ %bb.1:
+; V4T-NEXT:  .LCPI14_0:
+; V4T-NEXT:    .long 8388607 @ 0x7fffff
+;
+; V6T2-LABEL: no_sat_incorrect_compare:
+; V6T2:       @ %bb.0: @ %entry
+; V6T2-NEXT:    cmn r1, #8388608
+; V6T2-NEXT:    mov r1, r0
+; V6T2-NEXT:    movwlt r1, #0
+; V6T2-NEXT:    movtlt r1, #65408
+; V6T2-NEXT:    cmp r0, #8388608
+; V6T2-NEXT:    movwge r1, #65535
+; V6T2-NEXT:    movtge r1, #127
+; V6T2-NEXT:    mov r0, r1
+; V6T2-NEXT:    bx lr
 entry:
   %cmpUp = icmp sgt i32 %x, 8388607
   %cmpLow = icmp slt i32 %y, -8388608
@@ -223,3 +528,102 @@ entry:
   %saturateUp = select i1 %cmpUp, i32 8388607, i32 %saturateLow
   ret i32 %saturateUp
 }
+
+define void @extended(i32 %xx, i16 signext %y, i8* nocapture %z) {
+; V4T-LABEL: extended:
+; V4T:       @ %bb.0: @ %entry
+; V4T-NEXT:    add r0, r1, r0, lsr #16
+; V4T-NEXT:    lsl r1, r0, #16
+; V4T-NEXT:    asr r1, r1, #16
+; V4T-NEXT:    cmp r1, #127
+; V4T-NEXT:    movge r0, #127
+; V4T-NEXT:    lsl r1, r0, #16
+; V4T-NEXT:    asr r1, r1, #16
+; V4T-NEXT:    cmn r1, #128
+; V4T-NEXT:    mvnle r0, #127
+; V4T-NEXT:    strb r0, [r2]
+; V4T-NEXT:    bx lr
+;
+; V6T2-LABEL: extended:
+; V6T2:       @ %bb.0: @ %entry
+; V6T2-NEXT:    add r0, r1, r0, lsr #16
+; V6T2-NEXT:    ssat r0, #8, r0
+; V6T2-NEXT:    strb r0, [r2]
+; V6T2-NEXT:    bx lr
+entry:
+  %0 = lshr i32 %xx, 16
+  %1 = trunc i32 %0 to i16
+  %conv3 = add i16 %1, %y
+  %cmp.i = icmp slt i16 %conv3, 127
+  %cond.i = select i1 %cmp.i, i16 %conv3, i16 127
+  %cmp.i11 = icmp sgt i16 %cond.i, -128
+  %cond.i12 = select i1 %cmp.i11, i16 %cond.i, i16 -128
+  %conv5 = trunc i16 %cond.i12 to i8
+  store i8 %conv5, i8* %z, align 1
+  ret void
+}
+
+
+define i32 @formulated_valid(i32 %a) {
+; V4T-LABEL: formulated_valid:
+; V4T:       @ %bb.0:
+; V4T-NEXT:    lsl r1, r0, #16
+; V4T-NEXT:    asr r1, r1, #16
+; V4T-NEXT:    cmp r1, #127
+; V4T-NEXT:    movge r0, #127
+; V4T-NEXT:    lsl r1, r0, #16
+; V4T-NEXT:    asr r1, r1, #16
+; V4T-NEXT:    cmn r1, #128
+; V4T-NEXT:    mov r1, #255
+; V4T-NEXT:    mvnle r0, #127
+; V4T-NEXT:    orr r1, r1, #65280
+; V4T-NEXT:    and r0, r0, r1
+; V4T-NEXT:    bx lr
+;
+; V6T2-LABEL: formulated_valid:
+; V6T2:       @ %bb.0:
+; V6T2-NEXT:    ssat r0, #8, r0
+; V6T2-NEXT:    uxth r0, r0
+; V6T2-NEXT:    bx lr
+  %x1 = trunc i32 %a to i16
+  %x2 = sext i16 %x1 to i32
+  %c1 = icmp slt i32 %x2, 127
+  %s1 = select i1 %c1, i32 %a, i32 127
+  %y1 = trunc i32 %s1 to i16
+  %y2 = sext i16 %y1 to i32
+  %c2 = icmp sgt i32 %y2, -128
+  %s2 = select i1 %c2, i32 %s1, i32 -128
+  %r = and i32 %s2, 65535
+  ret i32 %r
+}
+
+define i32 @formulated_invalid(i32 %a) {
+; V4T-LABEL: formulated_invalid:
+; V4T:       @ %bb.0:
+; V4T-NEXT:    lsl r1, r0, #16
+; V4T-NEXT:    asr r1, r1, #16
+; V4T-NEXT:    cmp r1, #127
+; V4T-NEXT:    movge r0, #127
+; V4T-NEXT:    lsl r1, r0, #16
+; V4T-NEXT:    asr r1, r1, #16
+; V4T-NEXT:    cmn r1, #128
+; V4T-NEXT:    mvnle r0, #127
+; V4T-NEXT:    bic r0, r0, #-16777216
+; V4T-NEXT:    bx lr
+;
+; V6T2-LABEL: formulated_invalid:
+; V6T2:       @ %bb.0:
+; V6T2-NEXT:    ssat r0, #8, r0
+; V6T2-NEXT:    bic r0, r0, #-16777216
+; V6T2-NEXT:    bx lr
+  %x1 = trunc i32 %a to i16
+  %x2 = sext i16 %x1 to i32
+  %c1 = icmp slt i32 %x2, 127
+  %s1 = select i1 %c1, i32 %a, i32 127
+  %y1 = trunc i32 %s1 to i16
+  %y2 = sext i16 %y1 to i32
+  %c2 = icmp sgt i32 %y2, -128
+  %s2 = select i1 %c2, i32 %s1, i32 -128
+  %r = and i32 %s2, 16777215
+  ret i32 %r
+}
diff --git a/llvm/test/CodeGen/ARM/usat.ll b/llvm/test/CodeGen/ARM/usat.ll
index ba4e0dd037649..ab508fc0e0323 100644
--- a/llvm/test/CodeGen/ARM/usat.ll
+++ b/llvm/test/CodeGen/ARM/usat.ll
@@ -1,6 +1,7 @@
-; RUN: llc -mtriple=armv4t-eabi %s -o -  | FileCheck %s --check-prefix=CHECK --check-prefix=V4T
-; RUN: llc -mtriple=armv6-eabi %s -o -   | FileCheck %s --check-prefix=CHECK --check-prefix=V6
-; RUN: llc -mtriple=armv6t2-eabi %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=V6T2
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=armv4t-eabi %s -o -  | FileCheck %s --check-prefix=V4T
+; RUN: llc -mtriple=armv6-eabi %s -o -   | FileCheck %s --check-prefix=V6
+; RUN: llc -mtriple=armv6t2-eabi %s -o - | FileCheck %s --check-prefix=V6T2
 
 ; Check for several conditions that should result in USAT.
 ; For example, the base test is equivalent to
@@ -17,10 +18,27 @@
 ; x < 0 ? 0 : (x > k ? k : x)
 ; 32-bit base test
 define i32 @unsigned_sat_base_32bit(i32 %x) #0 {
-; CHECK-LABEL: unsigned_sat_base_32bit:
-; V6: usat r0, #23, r0
-; V6T2: usat r0, #23, r0
-; V4T-NOT: usat
+; V4T-LABEL: unsigned_sat_base_32bit:
+; V4T:       @ %bb.0: @ %entry
+; V4T-NEXT:    ldr r1, .LCPI0_0
+; V4T-NEXT:    cmp r0, r1
+; V4T-NEXT:    movlt r1, r0
+; V4T-NEXT:    bic r0, r1, r1, asr #31
+; V4T-NEXT:    bx lr
+; V4T-NEXT:    .p2align 2
+; V4T-NEXT:  @ %bb.1:
+; V4T-NEXT:  .LCPI0_0:
+; V4T-NEXT:    .long 8388607 @ 0x7fffff
+;
+; V6-LABEL: unsigned_sat_base_32bit:
+; V6:       @ %bb.0: @ %entry
+; V6-NEXT:    usat r0, #23, r0
+; V6-NEXT:    bx lr
+;
+; V6T2-LABEL: unsigned_sat_base_32bit:
+; V6T2:       @ %bb.0: @ %entry
+; V6T2-NEXT:    usat r0, #23, r0
+; V6T2-NEXT:    bx lr
 entry:
   %0 = icmp slt i32 %x, 8388607
   %saturateUp = select i1 %0, i32 %x, i32 8388607
@@ -32,10 +50,30 @@ entry:
 ; x < 0 ? 0 : (x > k ? k : x)
 ; 16-bit base test
 define i16 @unsigned_sat_base_16bit(i16 %x) #0 {
-; CHECK-LABEL: unsigned_sat_base_16bit:
-; V6: usat r0, #11, r0
-; V6T2: usat r0, #11, r0
-; V4T-NOT: usat
+; V4T-LABEL: unsigned_sat_base_16bit:
+; V4T:       @ %bb.0: @ %entry
+; V4T-NEXT:    lsl r1, r0, #16
+; V4T-NEXT:    asr r2, r1, #16
+; V4T-NEXT:    mov r1, #255
+; V4T-NEXT:    orr r1, r1, #1792
+; V4T-NEXT:    cmp r2, r1
+; V4T-NEXT:    movlt r1, r0
+; V4T-NEXT:    lsl r0, r1, #16
+; V4T-NEXT:    asr r0, r0, #16
+; V4T-NEXT:    cmp r0, #0
+; V4T-NEXT:    movle r1, #0
+; V4T-NEXT:    mov r0, r1
+; V4T-NEXT:    bx lr
+;
+; V6-LABEL: unsigned_sat_base_16bit:
+; V6:       @ %bb.0: @ %entry
+; V6-NEXT:    usat r0, #11, r0
+; V6-NEXT:    bx lr
+;
+; V6T2-LABEL: unsigned_sat_base_16bit:
+; V6T2:       @ %bb.0: @ %entry
+; V6T2-NEXT:    usat r0, #11, r0
+; V6T2-NEXT:    bx lr
 entry:
   %0 = icmp slt i16 %x, 2047
   %saturateUp = select i1 %0, i16 %x, i16 2047
@@ -47,10 +85,27 @@ entry:
 ; x < 0 ? 0 : (x > k ? k : x)
 ; 8-bit base test
 define i8 @unsigned_sat_base_8bit(i8 %x) #0 {
-; CHECK-LABEL: unsigned_sat_base_8bit:
-; V6: usat r0, #5, r0
-; V6T2: usat r0, #5, r0
-; V4T-NOT: usat
+; V4T-LABEL: unsigned_sat_base_8bit:
+; V4T:       @ %bb.0: @ %entry
+; V4T-NEXT:    lsl r1, r0, #24
+; V4T-NEXT:    asr r1, r1, #24
+; V4T-NEXT:    cmp r1, #31
+; V4T-NEXT:    movge r0, #31
+; V4T-NEXT:    lsl r1, r0, #24
+; V4T-NEXT:    asr r1, r1, #24
+; V4T-NEXT:    cmp r1, #0
+; V4T-NEXT:    movle r0, #0
+; V4T-NEXT:    bx lr
+;
+; V6-LABEL: unsigned_sat_base_8bit:
+; V6:       @ %bb.0: @ %entry
+; V6-NEXT:    usat r0, #5, r0
+; V6-NEXT:    bx lr
+;
+; V6T2-LABEL: unsigned_sat_base_8bit:
+; V6T2:       @ %bb.0: @ %entry
+; V6T2-NEXT:    usat r0, #5, r0
+; V6T2-NEXT:    bx lr
 entry:
   %0 = icmp slt i8 %x, 31
   %saturateUp = select i1 %0, i8 %x, i8 31
@@ -66,10 +121,27 @@ entry:
 ;
 ; x < 0 ? 0 : (x < k ? x : k)
 define i32 @unsigned_sat_lower_upper_1(i32 %x) #0 {
-; CHECK-LABEL: unsigned_sat_lower_upper_1:
-; V6: usat r0, #23, r0
-; V6T2: usat r0, #23, r0
-; V4T-NOT: usat
+; V4T-LABEL: unsigned_sat_lower_upper_1:
+; V4T:       @ %bb.0: @ %entry
+; V4T-NEXT:    ldr r1, .LCPI3_0
+; V4T-NEXT:    cmp r0, r1
+; V4T-NEXT:    movlt r1, r0
+; V4T-NEXT:    bic r0, r1, r1, asr #31
+; V4T-NEXT:    bx lr
+; V4T-NEXT:    .p2align 2
+; V4T-NEXT:  @ %bb.1:
+; V4T-NEXT:  .LCPI3_0:
+; V4T-NEXT:    .long 8388607 @ 0x7fffff
+;
+; V6-LABEL: unsigned_sat_lower_upper_1:
+; V6:       @ %bb.0: @ %entry
+; V6-NEXT:    usat r0, #23, r0
+; V6-NEXT:    bx lr
+;
+; V6T2-LABEL: unsigned_sat_lower_upper_1:
+; V6T2:       @ %bb.0: @ %entry
+; V6T2-NEXT:    usat r0, #23, r0
+; V6T2-NEXT:    bx lr
 entry:
   %cmpUp = icmp slt i32 %x, 8388607
   %saturateUp = select i1 %cmpUp, i32 %x, i32 8388607
@@ -80,10 +152,27 @@ entry:
 
 ; x > 0 ? (x > k ? k : x) : 0
 define i32 @unsigned_sat_lower_upper_2(i32 %x) #0 {
-; CHECK-LABEL: unsigned_sat_lower_upper_2:
-; V6: usat    r0, #23, r0
-; V6T2: usat    r0, #23, r0
-; V4T-NOT: usat
+; V4T-LABEL: unsigned_sat_lower_upper_2:
+; V4T:       @ %bb.0: @ %entry
+; V4T-NEXT:    ldr r1, .LCPI4_0
+; V4T-NEXT:    cmp r0, r1
+; V4T-NEXT:    movlt r1, r0
+; V4T-NEXT:    bic r0, r1, r1, asr #31
+; V4T-NEXT:    bx lr
+; V4T-NEXT:    .p2align 2
+; V4T-NEXT:  @ %bb.1:
+; V4T-NEXT:  .LCPI4_0:
+; V4T-NEXT:    .long 8388607 @ 0x7fffff
+;
+; V6-LABEL: unsigned_sat_lower_upper_2:
+; V6:       @ %bb.0: @ %entry
+; V6-NEXT:    usat r0, #23, r0
+; V6-NEXT:    bx lr
+;
+; V6T2-LABEL: unsigned_sat_lower_upper_2:
+; V6T2:       @ %bb.0: @ %entry
+; V6T2-NEXT:    usat r0, #23, r0
+; V6T2-NEXT:    bx lr
 entry:
   %0 = icmp slt i32 %x, 8388607
   %saturateUp = select i1 %0, i32 %x, i32 8388607
@@ -94,10 +183,27 @@ entry:
 
 ; x < k ? (x < 0 ? 0 : x) : k
 define i32 @unsigned_sat_upper_lower_1(i32 %x) #0 {
-; CHECK-LABEL: unsigned_sat_upper_lower_1:
-; V6: usat    r0, #23, r0
-; V6T2: usat    r0, #23, r0
-; V4T-NOT: usat
+; V4T-LABEL: unsigned_sat_upper_lower_1:
+; V4T:       @ %bb.0: @ %entry
+; V4T-NEXT:    bic r1, r0, r0, asr #31
+; V4T-NEXT:    ldr r0, .LCPI5_0
+; V4T-NEXT:    cmp r1, r0
+; V4T-NEXT:    movlt r0, r1
+; V4T-NEXT:    bx lr
+; V4T-NEXT:    .p2align 2
+; V4T-NEXT:  @ %bb.1:
+; V4T-NEXT:  .LCPI5_0:
+; V4T-NEXT:    .long 8388607 @ 0x7fffff
+;
+; V6-LABEL: unsigned_sat_upper_lower_1:
+; V6:       @ %bb.0: @ %entry
+; V6-NEXT:    usat r0, #23, r0
+; V6-NEXT:    bx lr
+;
+; V6T2-LABEL: unsigned_sat_upper_lower_1:
+; V6T2:       @ %bb.0: @ %entry
+; V6T2-NEXT:    usat r0, #23, r0
+; V6T2-NEXT:    bx lr
 entry:
   %0 = icmp sgt i32 %x, 0
   %saturateLow = select i1 %0, i32 %x, i32 0
@@ -108,10 +214,27 @@ entry:
 
 ; x > k ? k : (x < 0 ? 0 : x)
 define i32 @unsigned_sat_upper_lower_2(i32 %x) #0 {
-; CHECK-LABEL: unsigned_sat_upper_lower_2:
-; V6: usat    r0, #23, r0
-; V6T2: usat    r0, #23, r0
-; V4T-NOT: usat
+; V4T-LABEL: unsigned_sat_upper_lower_2:
+; V4T:       @ %bb.0: @ %entry
+; V4T-NEXT:    bic r1, r0, r0, asr #31
+; V4T-NEXT:    ldr r0, .LCPI6_0
+; V4T-NEXT:    cmp r1, r0
+; V4T-NEXT:    movlt r0, r1
+; V4T-NEXT:    bx lr
+; V4T-NEXT:    .p2align 2
+; V4T-NEXT:  @ %bb.1:
+; V4T-NEXT:  .LCPI6_0:
+; V4T-NEXT:    .long 8388607 @ 0x7fffff
+;
+; V6-LABEL: unsigned_sat_upper_lower_2:
+; V6:       @ %bb.0: @ %entry
+; V6-NEXT:    usat r0, #23, r0
+; V6-NEXT:    bx lr
+;
+; V6T2-LABEL: unsigned_sat_upper_lower_2:
+; V6T2:       @ %bb.0: @ %entry
+; V6T2-NEXT:    usat r0, #23, r0
+; V6T2-NEXT:    bx lr
 entry:
   %0 = icmp sgt i32 %x, 0
   %saturateLow = select i1 %0, i32 %x, i32 0
@@ -122,10 +245,27 @@ entry:
 
 ; k < x ? k : (x > 0 ? x : 0)
 define i32 @unsigned_sat_upper_lower_3(i32 %x) #0 {
-; CHECK-LABEL: unsigned_sat_upper_lower_3:
-; V6: usat    r0, #23, r0
-; V6T2: usat    r0, #23, r0
-; V4T-NOT: usat
+; V4T-LABEL: unsigned_sat_upper_lower_3:
+; V4T:       @ %bb.0: @ %entry
+; V4T-NEXT:    bic r1, r0, r0, asr #31
+; V4T-NEXT:    ldr r0, .LCPI7_0
+; V4T-NEXT:    cmp r1, r0
+; V4T-NEXT:    movlt r0, r1
+; V4T-NEXT:    bx lr
+; V4T-NEXT:    .p2align 2
+; V4T-NEXT:  @ %bb.1:
+; V4T-NEXT:  .LCPI7_0:
+; V4T-NEXT:    .long 8388607 @ 0x7fffff
+;
+; V6-LABEL: unsigned_sat_upper_lower_3:
+; V6:       @ %bb.0: @ %entry
+; V6-NEXT:    usat r0, #23, r0
+; V6-NEXT:    bx lr
+;
+; V6T2-LABEL: unsigned_sat_upper_lower_3:
+; V6T2:       @ %bb.0: @ %entry
+; V6T2-NEXT:    usat r0, #23, r0
+; V6T2-NEXT:    bx lr
 entry:
   %cmpLow = icmp sgt i32 %x, 0
   %saturateLow = select i1 %cmpLow, i32 %x, i32 0
@@ -141,8 +281,38 @@ entry:
 ; x > k ? k : (x > 0 ? 0 : x)
 ; First condition upper-saturates, second doesn't lower-saturate.
 define i32 @no_unsigned_sat_missing_lower(i32 %x) #0 {
-; CHECK-LABEL: no_unsigned_sat_missing_lower
-; CHECK-NOT: usat
+; V4T-LABEL: no_unsigned_sat_missing_lower:
+; V4T:       @ %bb.0: @ %entry
+; V4T-NEXT:    ldr r1, .LCPI8_0
+; V4T-NEXT:    cmp r0, #8388608
+; V4T-NEXT:    andlt r1, r0, r0, asr #31
+; V4T-NEXT:    mov r0, r1
+; V4T-NEXT:    bx lr
+; V4T-NEXT:    .p2align 2
+; V4T-NEXT:  @ %bb.1:
+; V4T-NEXT:  .LCPI8_0:
+; V4T-NEXT:    .long 8388607 @ 0x7fffff
+;
+; V6-LABEL: no_unsigned_sat_missing_lower:
+; V6:       @ %bb.0: @ %entry
+; V6-NEXT:    ldr r1, .LCPI8_0
+; V6-NEXT:    cmp r0, #8388608
+; V6-NEXT:    andlt r1, r0, r0, asr #31
+; V6-NEXT:    mov r0, r1
+; V6-NEXT:    bx lr
+; V6-NEXT:    .p2align 2
+; V6-NEXT:  @ %bb.1:
+; V6-NEXT:  .LCPI8_0:
+; V6-NEXT:    .long 8388607 @ 0x7fffff
+;
+; V6T2-LABEL: no_unsigned_sat_missing_lower:
+; V6T2:       @ %bb.0: @ %entry
+; V6T2-NEXT:    and r1, r0, r0, asr #31
+; V6T2-NEXT:    cmp r0, #8388608
+; V6T2-NEXT:    movwge r1, #65535
+; V6T2-NEXT:    movtge r1, #127
+; V6T2-NEXT:    mov r0, r1
+; V6T2-NEXT:    bx lr
 entry:
   %cmpUp = icmp sgt i32 %x, 8388607
   %0 = icmp slt i32 %x, 0
@@ -154,8 +324,40 @@ entry:
 ; x < k ? k : (x < 0 ? 0 : x)
 ; Second condition lower-saturates, first doesn't upper-saturate.
 define i32 @no_unsigned_sat_missing_upper(i32 %x) #0 {
-; CHECK-LABEL: no_unsigned_sat_missing_upper:
-; CHECK-NOT: usat
+; V4T-LABEL: no_unsigned_sat_missing_upper:
+; V4T:       @ %bb.0: @ %entry
+; V4T-NEXT:    ldr r1, .LCPI9_0
+; V4T-NEXT:    cmp r0, r1
+; V4T-NEXT:    bicge r1, r0, r0, asr #31
+; V4T-NEXT:    mov r0, r1
+; V4T-NEXT:    bx lr
+; V4T-NEXT:    .p2align 2
+; V4T-NEXT:  @ %bb.1:
+; V4T-NEXT:  .LCPI9_0:
+; V4T-NEXT:    .long 8388607 @ 0x7fffff
+;
+; V6-LABEL: no_unsigned_sat_missing_upper:
+; V6:       @ %bb.0: @ %entry
+; V6-NEXT:    ldr r1, .LCPI9_0
+; V6-NEXT:    cmp r0, r1
+; V6-NEXT:    bicge r1, r0, r0, asr #31
+; V6-NEXT:    mov r0, r1
+; V6-NEXT:    bx lr
+; V6-NEXT:    .p2align 2
+; V6-NEXT:  @ %bb.1:
+; V6-NEXT:  .LCPI9_0:
+; V6-NEXT:    .long 8388607 @ 0x7fffff
+;
+; V6T2-LABEL: no_unsigned_sat_missing_upper:
+; V6T2:       @ %bb.0: @ %entry
+; V6T2-NEXT:    movw r2, #65535
+; V6T2-NEXT:    bic r1, r0, r0, asr #31
+; V6T2-NEXT:    movt r2, #127
+; V6T2-NEXT:    cmp r0, r2
+; V6T2-NEXT:    movwlt r1, #65535
+; V6T2-NEXT:    movtlt r1, #127
+; V6T2-NEXT:    mov r0, r1
+; V6T2-NEXT:    bx lr
 entry:
   %cmpUp = icmp slt i32 %x, 8388607
   %0 = icmp sgt i32 %x, 0
@@ -166,8 +368,38 @@ entry:
 
 ; Lower constant is different in the select and in the compare
 define i32 @no_unsigned_sat_incorrect_constant(i32 %x) #0 {
-; CHECK-LABEL: no_unsigned_sat_incorrect_constant:
-; CHECK-NOT: usat
+; V4T-LABEL: no_unsigned_sat_incorrect_constant:
+; V4T:       @ %bb.0: @ %entry
+; V4T-NEXT:    orr r1, r0, r0, asr #31
+; V4T-NEXT:    ldr r0, .LCPI10_0
+; V4T-NEXT:    cmp r1, r0
+; V4T-NEXT:    movlt r0, r1
+; V4T-NEXT:    bx lr
+; V4T-NEXT:    .p2align 2
+; V4T-NEXT:  @ %bb.1:
+; V4T-NEXT:  .LCPI10_0:
+; V4T-NEXT:    .long 8388607 @ 0x7fffff
+;
+; V6-LABEL: no_unsigned_sat_incorrect_constant:
+; V6:       @ %bb.0: @ %entry
+; V6-NEXT:    orr r1, r0, r0, asr #31
+; V6-NEXT:    ldr r0, .LCPI10_0
+; V6-NEXT:    cmp r1, r0
+; V6-NEXT:    movlt r0, r1
+; V6-NEXT:    bx lr
+; V6-NEXT:    .p2align 2
+; V6-NEXT:  @ %bb.1:
+; V6-NEXT:  .LCPI10_0:
+; V6-NEXT:    .long 8388607 @ 0x7fffff
+;
+; V6T2-LABEL: no_unsigned_sat_incorrect_constant:
+; V6T2:       @ %bb.0: @ %entry
+; V6T2-NEXT:    orr r1, r0, r0, asr #31
+; V6T2-NEXT:    movw r0, #65535
+; V6T2-NEXT:    movt r0, #127
+; V6T2-NEXT:    cmp r1, r0
+; V6T2-NEXT:    movlt r0, r1
+; V6T2-NEXT:    bx lr
 entry:
   %cmpLow.inv = icmp sgt i32 %x, -1
   %saturateLow = select i1 %cmpLow.inv, i32 %x, i32 -1
@@ -178,8 +410,32 @@ entry:
 
 ; The interval is [0, k] but k+1 is not a power of 2
 define i32 @no_unsigned_sat_incorrect_constant2(i32 %x) #0 {
-; CHECK-LABEL: no_unsigned_sat_incorrect_constant2:
-; CHECK-NOT: usat
+; V4T-LABEL: no_unsigned_sat_incorrect_constant2:
+; V4T:       @ %bb.0: @ %entry
+; V4T-NEXT:    bic r1, r0, r0, asr #31
+; V4T-NEXT:    mov r0, #1
+; V4T-NEXT:    orr r0, r0, #8388608
+; V4T-NEXT:    cmp r1, #8388608
+; V4T-NEXT:    movle r0, r1
+; V4T-NEXT:    bx lr
+;
+; V6-LABEL: no_unsigned_sat_incorrect_constant2:
+; V6:       @ %bb.0: @ %entry
+; V6-NEXT:    bic r1, r0, r0, asr #31
+; V6-NEXT:    mov r0, #1
+; V6-NEXT:    orr r0, r0, #8388608
+; V6-NEXT:    cmp r1, #8388608
+; V6-NEXT:    movle r0, r1
+; V6-NEXT:    bx lr
+;
+; V6T2-LABEL: no_unsigned_sat_incorrect_constant2:
+; V6T2:       @ %bb.0: @ %entry
+; V6T2-NEXT:    bic r1, r0, r0, asr #31
+; V6T2-NEXT:    movw r0, #1
+; V6T2-NEXT:    movt r0, #128
+; V6T2-NEXT:    cmp r1, #8388608
+; V6T2-NEXT:    movle r0, r1
+; V6T2-NEXT:    bx lr
 entry:
   %0 = icmp sgt i32 %x, 0
   %saturateLow = select i1 %0, i32 %x, i32 0
@@ -190,8 +446,41 @@ entry:
 
 ; The interval is not [0, k]
 define i32 @no_unsigned_sat_incorrect_interval(i32 %x) #0 {
-; CHECK-LABEL: no_unsigned_sat_incorrect_interval:
-; CHECK-NOT: usat
+; V4T-LABEL: no_unsigned_sat_incorrect_interval:
+; V4T:       @ %bb.0: @ %entry
+; V4T-NEXT:    ldr r1, .LCPI12_0
+; V4T-NEXT:    cmn r0, #4
+; V4T-NEXT:    mvnle r0, #3
+; V4T-NEXT:    cmp r0, r1
+; V4T-NEXT:    movge r0, r1
+; V4T-NEXT:    bx lr
+; V4T-NEXT:    .p2align 2
+; V4T-NEXT:  @ %bb.1:
+; V4T-NEXT:  .LCPI12_0:
+; V4T-NEXT:    .long 8388607 @ 0x7fffff
+;
+; V6-LABEL: no_unsigned_sat_incorrect_interval:
+; V6:       @ %bb.0: @ %entry
+; V6-NEXT:    ldr r1, .LCPI12_0
+; V6-NEXT:    cmn r0, #4
+; V6-NEXT:    mvnle r0, #3
+; V6-NEXT:    cmp r0, r1
+; V6-NEXT:    movge r0, r1
+; V6-NEXT:    bx lr
+; V6-NEXT:    .p2align 2
+; V6-NEXT:  @ %bb.1:
+; V6-NEXT:  .LCPI12_0:
+; V6-NEXT:    .long 8388607 @ 0x7fffff
+;
+; V6T2-LABEL: no_unsigned_sat_incorrect_interval:
+; V6T2:       @ %bb.0: @ %entry
+; V6T2-NEXT:    cmn r0, #4
+; V6T2-NEXT:    movw r1, #65535
+; V6T2-NEXT:    mvnle r0, #3
+; V6T2-NEXT:    movt r1, #127
+; V6T2-NEXT:    cmp r0, r1
+; V6T2-NEXT:    movge r0, r1
+; V6T2-NEXT:    bx lr
 entry:
   %0 = icmp sgt i32 %x, -4
   %saturateLow = select i1 %0, i32 %x, i32 -4
@@ -202,8 +491,43 @@ entry:
 
 ; The returned value (y) is not the same as the tested value (x).
 define i32 @no_unsigned_sat_incorrect_return(i32 %x, i32 %y) #0 {
-; CHECK-LABEL: no_unsigned_sat_incorrect_return:
-; CHECK-NOT: usat
+; V4T-LABEL: no_unsigned_sat_incorrect_return:
+; V4T:       @ %bb.0: @ %entry
+; V4T-NEXT:    cmp r0, #0
+; V4T-NEXT:    ldr r2, .LCPI13_0
+; V4T-NEXT:    movmi r1, #0
+; V4T-NEXT:    cmp r0, #8388608
+; V4T-NEXT:    movlt r2, r1
+; V4T-NEXT:    mov r0, r2
+; V4T-NEXT:    bx lr
+; V4T-NEXT:    .p2align 2
+; V4T-NEXT:  @ %bb.1:
+; V4T-NEXT:  .LCPI13_0:
+; V4T-NEXT:    .long 8388607 @ 0x7fffff
+;
+; V6-LABEL: no_unsigned_sat_incorrect_return:
+; V6:       @ %bb.0: @ %entry
+; V6-NEXT:    cmp r0, #0
+; V6-NEXT:    ldr r2, .LCPI13_0
+; V6-NEXT:    movmi r1, #0
+; V6-NEXT:    cmp r0, #8388608
+; V6-NEXT:    movlt r2, r1
+; V6-NEXT:    mov r0, r2
+; V6-NEXT:    bx lr
+; V6-NEXT:    .p2align 2
+; V6-NEXT:  @ %bb.1:
+; V6-NEXT:  .LCPI13_0:
+; V6-NEXT:    .long 8388607 @ 0x7fffff
+;
+; V6T2-LABEL: no_unsigned_sat_incorrect_return:
+; V6T2:       @ %bb.0: @ %entry
+; V6T2-NEXT:    cmp r0, #0
+; V6T2-NEXT:    movwmi r1, #0
+; V6T2-NEXT:    cmp r0, #8388608
+; V6T2-NEXT:    movwge r1, #65535
+; V6T2-NEXT:    movtge r1, #127
+; V6T2-NEXT:    mov r0, r1
+; V6T2-NEXT:    bx lr
 entry:
   %cmpUp = icmp sgt i32 %x, 8388607
   %cmpLow = icmp slt i32 %x, 0
@@ -215,8 +539,46 @@ entry:
 ; One of the values in a compare (y) is not the same as the rest
 ; of the compare and select values (x).
 define i32 @no_unsigned_sat_incorrect_compare(i32 %x, i32 %y) #0 {
-; CHECK-LABEL: no_unsigned_sat_incorrect_compare:
-; CHECK-NOT: usat
+; V4T-LABEL: no_unsigned_sat_incorrect_compare:
+; V4T:       @ %bb.0: @ %entry
+; V4T-NEXT:    ldr r2, .LCPI14_0
+; V4T-NEXT:    cmp r1, #0
+; V4T-NEXT:    mov r1, r0
+; V4T-NEXT:    movmi r1, #0
+; V4T-NEXT:    cmp r0, #8388608
+; V4T-NEXT:    movge r1, r2
+; V4T-NEXT:    mov r0, r1
+; V4T-NEXT:    bx lr
+; V4T-NEXT:    .p2align 2
+; V4T-NEXT:  @ %bb.1:
+; V4T-NEXT:  .LCPI14_0:
+; V4T-NEXT:    .long 8388607 @ 0x7fffff
+;
+; V6-LABEL: no_unsigned_sat_incorrect_compare:
+; V6:       @ %bb.0: @ %entry
+; V6-NEXT:    ldr r2, .LCPI14_0
+; V6-NEXT:    cmp r1, #0
+; V6-NEXT:    mov r1, r0
+; V6-NEXT:    movmi r1, #0
+; V6-NEXT:    cmp r0, #8388608
+; V6-NEXT:    movge r1, r2
+; V6-NEXT:    mov r0, r1
+; V6-NEXT:    bx lr
+; V6-NEXT:    .p2align 2
+; V6-NEXT:  @ %bb.1:
+; V6-NEXT:  .LCPI14_0:
+; V6-NEXT:    .long 8388607 @ 0x7fffff
+;
+; V6T2-LABEL: no_unsigned_sat_incorrect_compare:
+; V6T2:       @ %bb.0: @ %entry
+; V6T2-NEXT:    cmp r1, #0
+; V6T2-NEXT:    mov r1, r0
+; V6T2-NEXT:    movwmi r1, #0
+; V6T2-NEXT:    cmp r0, #8388608
+; V6T2-NEXT:    movwge r1, #65535
+; V6T2-NEXT:    movtge r1, #127
+; V6T2-NEXT:    mov r0, r1
+; V6T2-NEXT:    bx lr
 entry:
   %cmpUp = icmp sgt i32 %x, 8388607
   %cmpLow = icmp slt i32 %y, 0