diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 3ed0a261eb769..d4d2da55160e5 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -15527,7 +15527,7 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
       break;
     SDValue ConstOp = DAG.getConstant(Imm, dl, MVT::i32);
     SDValue NarrowAnd = DAG.getNode(ISD::AND, dl, MVT::i32, NarrowOp, ConstOp);
-    return DAG.getAnyExtOrTrunc(NarrowAnd, dl, N->getValueType(0));
+    return DAG.getZExtOrTrunc(NarrowAnd, dl, N->getValueType(0));
   }
   case ISD::SHL:
     return combineSHL(N, DCI);
diff --git a/llvm/test/CodeGen/PowerPC/and-extend-combine.ll b/llvm/test/CodeGen/PowerPC/and-extend-combine.ll
index 50604d8ef32af..1ffff5cb5fc89 100644
--- a/llvm/test/CodeGen/PowerPC/and-extend-combine.ll
+++ b/llvm/test/CodeGen/PowerPC/and-extend-combine.ll
@@ -23,11 +23,12 @@ bb:
   ret ptr %i8
 }
 
-; FIXME: This is a miscompile.
 define void @pr68783(i32 %x, ptr %p) {
 ; CHECK-LABEL: pr68783:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    li r5, 0
 ; CHECK-NEXT:    rlwinm r3, r3, 31, 24, 31
+; CHECK-NEXT:    sth r5, 4(r4)
 ; CHECK-NEXT:    stw r3, 0(r4)
 ; CHECK-NEXT:    blr
   %lshr = lshr i32 %x, 1