diff --git a/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
index 4b4a6331182a0..dc37b37b2186e 100644
--- a/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
+++ b/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
@@ -72,41 +72,25 @@ class LASX2RI8_XXI<bits<32> op, Operand ImmOpnd = uimm8>
 
 class LASX2RI8I2_XRII<bits<32> op, Operand ImmOpnd = simm8,
                      Operand IdxOpnd = uimm2>
-    : Fmt2RI8I2_XRII<op, (outs LASX256:$xd),
-                     (ins GPR:$rj, ImmOpnd:$imm8, IdxOpnd:$imm2),
+    : Fmt2RI8I2_XRII<op, (outs),
+                     (ins LASX256:$xd, GPR:$rj, ImmOpnd:$imm8, IdxOpnd:$imm2),
                      "$xd, $rj, $imm8, $imm2">;
 class LASX2RI8I3_XRII<bits<32> op, Operand ImmOpnd = simm8,
                      Operand IdxOpnd = uimm3>
-    : Fmt2RI8I3_XRII<op, (outs LASX256:$xd),
-                     (ins GPR:$rj, ImmOpnd:$imm8, IdxOpnd:$imm3),
+    : Fmt2RI8I3_XRII<op, (outs),
+                     (ins LASX256:$xd, GPR:$rj, ImmOpnd:$imm8, IdxOpnd:$imm3),
                      "$xd, $rj, $imm8, $imm3">;
 class LASX2RI8I4_XRII<bits<32> op, Operand ImmOpnd = simm8,
                      Operand IdxOpnd = uimm4>
-    : Fmt2RI8I4_XRII<op, (outs LASX256:$xd),
-                     (ins GPR:$rj, ImmOpnd:$imm8, IdxOpnd:$imm4),
+    : Fmt2RI8I4_XRII<op, (outs),
+                     (ins LASX256:$xd, GPR:$rj, ImmOpnd:$imm8, IdxOpnd:$imm4),
                      "$xd, $rj, $imm8, $imm4">;
 class LASX2RI8I5_XRII<bits<32> op, Operand ImmOpnd = simm8,
                      Operand IdxOpnd = uimm5>
-    : Fmt2RI8I5_XRII<op, (outs LASX256:$xd),
-                     (ins GPR:$rj, ImmOpnd:$imm8, IdxOpnd:$imm5),
+    : Fmt2RI8I5_XRII<op, (outs),
+                     (ins LASX256:$xd, GPR:$rj, ImmOpnd:$imm8, IdxOpnd:$imm5),
                      "$xd, $rj, $imm8, $imm5">;
 
-class LASX2RI9_XRI<bits<32> op, Operand ImmOpnd = simm9_lsl3>
-    : Fmt2RI9_XRI<op, (outs LASX256:$xd), (ins GPR:$rj, ImmOpnd:$imm9),
-                  "$xd, $rj, $imm9">;
-
-class LASX2RI10_XRI<bits<32> op, Operand ImmOpnd = simm10_lsl2>
-    : Fmt2RI10_XRI<op, (outs LASX256:$xd), (ins GPR:$rj, ImmOpnd:$imm10),
-                  "$xd, $rj, $imm10">;
-
-class LASX2RI11_XRI<bits<32> op, Operand ImmOpnd = simm11_lsl1>
-    : Fmt2RI11_XRI<op, (outs LASX256:$xd), (ins GPR:$rj, ImmOpnd:$imm11),
-                  "$xd, $rj, $imm11">;
-
-class LASX2RI12_XRI<bits<32> op, Operand ImmOpnd = simm12>
-    : Fmt2RI12_XRI<op, (outs LASX256:$xd), (ins GPR:$rj, ImmOpnd:$imm12),
-                  "$xd, $rj, $imm12">;
-
 class LASX3R_XXX<bits<32> op>
     : Fmt3R_XXX<op, (outs LASX256:$xd), (ins LASX256:$xj, LASX256:$xk),
                 "$xd, $xj, $xk">;
@@ -115,10 +99,6 @@ class LASX3R_XXR<bits<32> op>
     : Fmt3R_XXR<op, (outs LASX256:$xd), (ins LASX256:$xj, GPR:$rk),
                 "$xd, $xj, $rk">;
 
-class LASX3R_XRR<bits<32> op>
-    : Fmt3R_XRR<op, (outs LASX256:$xd), (ins GPR:$rj, GPR:$rk),
-                "$xd, $rj, $rk">;
-
 class LASX4R_XXXX<bits<32> op>
     : Fmt4R_XXXX<op, (outs LASX256:$xd),
                  (ins LASX256:$xj, LASX256:$xk, LASX256:$xa),
@@ -163,6 +143,29 @@ class LASX3R_XXXX<bits<32> op>
 
 } // Constraints = "$xd = $dst"
 
+class LASX2RI9_Load<bits<32> op, Operand ImmOpnd = simm9_lsl3>
+    : Fmt2RI9_XRI<op, (outs LASX256:$xd), (ins GPR:$rj, ImmOpnd:$imm9),
+                  "$xd, $rj, $imm9">;
+class LASX2RI10_Load<bits<32> op, Operand ImmOpnd = simm10_lsl2>
+    : Fmt2RI10_XRI<op, (outs LASX256:$xd), (ins GPR:$rj, ImmOpnd:$imm10),
+                  "$xd, $rj, $imm10">;
+class LASX2RI11_Load<bits<32> op, Operand ImmOpnd = simm11_lsl1>
+    : Fmt2RI11_XRI<op, (outs LASX256:$xd), (ins GPR:$rj, ImmOpnd:$imm11),
+                  "$xd, $rj, $imm11">;
+class LASX2RI12_Load<bits<32> op, Operand ImmOpnd = simm12>
+    : Fmt2RI12_XRI<op, (outs LASX256:$xd), (ins GPR:$rj, ImmOpnd:$imm12),
+                  "$xd, $rj, $imm12">;
+class LASX2RI12_Store<bits<32> op, Operand ImmOpnd = simm12>
+    : Fmt2RI12_XRI<op, (outs), (ins LASX256:$xd, GPR:$rj, ImmOpnd:$imm12),
+                  "$xd, $rj, $imm12">;
+
+class LASX3R_Load<bits<32> op>
+    : Fmt3R_XRR<op, (outs LASX256:$xd), (ins GPR:$rj, GPR:$rk),
+                "$xd, $rj, $rk">;
+class LASX3R_Store<bits<32> op>
+    : Fmt3R_XRR<op, (outs), (ins LASX256:$xd, GPR:$rj, GPR:$rk),
+                "$xd, $rj, $rk">;
+
 //===----------------------------------------------------------------------===//
 // Instructions
 //===----------------------------------------------------------------------===//
@@ -976,7 +979,7 @@ def XVPERM_W : LASX3R_XXX<0x757d0000>;
 def XVSHUF4I_B : LASX2RI8_XXI<0x77900000>;
 def XVSHUF4I_H : LASX2RI8_XXI<0x77940000>;
 def XVSHUF4I_W : LASX2RI8_XXI<0x77980000>;
-def XVSHUF4I_D : LASX2RI8_XXI<0x779c0000>;
+def XVSHUF4I_D : LASX2RI8_XXXI<0x779c0000>;
 
 def XVPERMI_W : LASX2RI8_XXXI<0x77e40000>;
 def XVPERMI_D : LASX2RI8_XXI<0x77e80000>;
@@ -989,18 +992,18 @@ def XVEXTRINS_B : LASX2RI8_XXXI<0x778c0000>;
 } // mayLoad = 0, mayStore = 0
 
 let mayLoad = 1, mayStore = 0 in {
-def XVLD : LASX2RI12_XRI<0x2c800000>;
-def XVLDX : LASX3R_XRR<0x38480000>;
+def XVLD : LASX2RI12_Load<0x2c800000>;
+def XVLDX : LASX3R_Load<0x38480000>;
 
-def XVLDREPL_B : LASX2RI12_XRI<0x32800000>;
-def XVLDREPL_H : LASX2RI11_XRI<0x32400000>;
-def XVLDREPL_W : LASX2RI10_XRI<0x32200000>;
-def XVLDREPL_D : LASX2RI9_XRI<0x32100000>;
+def XVLDREPL_B : LASX2RI12_Load<0x32800000>;
+def XVLDREPL_H : LASX2RI11_Load<0x32400000>;
+def XVLDREPL_W : LASX2RI10_Load<0x32200000>;
+def XVLDREPL_D : LASX2RI9_Load<0x32100000>;
 } // mayLoad = 1, mayStore = 0
 
 let mayLoad = 0, mayStore = 1 in {
-def XVST : LASX2RI12_XRI<0x2cc00000>;
-def XVSTX : LASX3R_XRR<0x384c0000>;
+def XVST : LASX2RI12_Store<0x2cc00000>;
+def XVSTX : LASX3R_Store<0x384c0000>;
 
 def XVSTELM_B : LASX2RI8I5_XRII<0x33800000>;
 def XVSTELM_H : LASX2RI8I4_XRII<0x33400000, simm8_lsl1>;
diff --git a/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
index 02a07e77faa0f..a8ed285a37cf0 100644
--- a/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
+++ b/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
@@ -91,22 +91,6 @@ class LSX2RI8I4_VRII<bits<32> op, Operand ImmOpnd = simm8,
                      (ins LSX128:$vd, GPR:$rj, ImmOpnd:$imm8, IdxOpnd:$imm4),
                      "$vd, $rj, $imm8, $imm4">;
 
-class LSX2RI9_VRI<bits<32> op, Operand ImmOpnd = simm9_lsl3>
-    : Fmt2RI9_VRI<op, (outs LSX128:$vd), (ins GPR:$rj, ImmOpnd:$imm9),
-                  "$vd, $rj, $imm9">;
-
-class LSX2RI10_VRI<bits<32> op, Operand ImmOpnd = simm10_lsl2>
-    : Fmt2RI10_VRI<op, (outs LSX128:$vd), (ins GPR:$rj, ImmOpnd:$imm10),
-                  "$vd, $rj, $imm10">;
-
-class LSX2RI11_VRI<bits<32> op, Operand ImmOpnd = simm11_lsl1>
-    : Fmt2RI11_VRI<op, (outs LSX128:$vd), (ins GPR:$rj, ImmOpnd:$imm11),
-                  "$vd, $rj, $imm11">;
-
-class LSX2RI12_VRI<bits<32> op, Operand ImmOpnd = simm12>
-    : Fmt2RI12_VRI<op, (outs LSX128:$vd), (ins GPR:$rj, ImmOpnd:$imm12),
-                  "$vd, $rj, $imm12">;
-
 class LSX3R_VVV<bits<32> op>
     : Fmt3R_VVV<op, (outs LSX128:$vd), (ins LSX128:$vj, LSX128:$vk),
                 "$vd, $vj, $vk">;
@@ -115,10 +99,6 @@ class LSX3R_VVR<bits<32> op>
     : Fmt3R_VVR<op, (outs LSX128:$vd), (ins LSX128:$vj, GPR:$rk),
                 "$vd, $vj, $rk">;
 
-class LSX3R_VRR<bits<32> op>
-    : Fmt3R_VRR<op, (outs LSX128:$vd), (ins GPR:$rj, GPR:$rk),
-                "$vd, $rj, $rk">;
-
 class LSX4R_VVVV<bits<32> op>
     : Fmt4R_VVVV<op, (outs LSX128:$vd),
                  (ins LSX128:$vj, LSX128:$vk, LSX128:$va),
@@ -162,6 +142,29 @@ class LSX3R_VVVV<bits<32> op>
 
 } // Constraints = "$vd = $dst"
 
+class LSX2RI9_Load<bits<32> op, Operand ImmOpnd = simm9_lsl3>
+    : Fmt2RI9_VRI<op, (outs LSX128:$vd), (ins GPR:$rj, ImmOpnd:$imm9),
+                  "$vd, $rj, $imm9">;
+class LSX2RI10_Load<bits<32> op, Operand ImmOpnd = simm10_lsl2>
+    : Fmt2RI10_VRI<op, (outs LSX128:$vd), (ins GPR:$rj, ImmOpnd:$imm10),
+                  "$vd, $rj, $imm10">;
+class LSX2RI11_Load<bits<32> op, Operand ImmOpnd = simm11_lsl1>
+    : Fmt2RI11_VRI<op, (outs LSX128:$vd), (ins GPR:$rj, ImmOpnd:$imm11),
+                  "$vd, $rj, $imm11">;
+class LSX2RI12_Load<bits<32> op, Operand ImmOpnd = simm12>
+    : Fmt2RI12_VRI<op, (outs LSX128:$vd), (ins GPR:$rj, ImmOpnd:$imm12),
+                  "$vd, $rj, $imm12">;
+class LSX2RI12_Store<bits<32> op, Operand ImmOpnd = simm12>
+    : Fmt2RI12_VRI<op, (outs), (ins LSX128:$vd, GPR:$rj, ImmOpnd:$imm12),
+                  "$vd, $rj, $imm12">;
+
+class LSX3R_Load<bits<32> op>
+    : Fmt3R_VRR<op, (outs LSX128:$vd), (ins GPR:$rj, GPR:$rk),
+                "$vd, $rj, $rk">;
+class LSX3R_Store<bits<32> op>
+    : Fmt3R_VRR<op, (outs), (ins LSX128:$vd, GPR:$rj, GPR:$rk),
+                "$vd, $rj, $rk">;
+
 //===----------------------------------------------------------------------===//
 // Instructions
 //===----------------------------------------------------------------------===//
@@ -950,9 +953,9 @@ def VSHUF_H : LSX3R_VVVV<0x717a8000>;
 def VSHUF_W : LSX3R_VVVV<0x717b0000>;
 def VSHUF_D : LSX3R_VVVV<0x717b8000>;
 
-def VSHUF4I_B : LSX2RI8_VVVI<0x73900000>;
-def VSHUF4I_H : LSX2RI8_VVVI<0x73940000>;
-def VSHUF4I_W : LSX2RI8_VVVI<0x73980000>;
+def VSHUF4I_B : LSX2RI8_VVI<0x73900000>;
+def VSHUF4I_H : LSX2RI8_VVI<0x73940000>;
+def VSHUF4I_W : LSX2RI8_VVI<0x73980000>;
 def VSHUF4I_D : LSX2RI8_VVVI<0x739c0000>;
 
 def VPERMI_W : LSX2RI8_VVVI<0x73e40000>;
@@ -964,18 +967,18 @@ def VEXTRINS_B : LSX2RI8_VVVI<0x738c0000>;
 } // mayLoad = 0, mayStore = 0
 
 let mayLoad = 1, mayStore = 0 in {
-def VLD : LSX2RI12_VRI<0x2c000000>;
-def VLDX : LSX3R_VRR<0x38400000>;
+def VLD : LSX2RI12_Load<0x2c000000>;
+def VLDX : LSX3R_Load<0x38400000>;
 
-def VLDREPL_B : LSX2RI12_VRI<0x30800000>;
-def VLDREPL_H : LSX2RI11_VRI<0x30400000>;
-def VLDREPL_W : LSX2RI10_VRI<0x30200000>;
-def VLDREPL_D : LSX2RI9_VRI<0x30100000>;
+def VLDREPL_B : LSX2RI12_Load<0x30800000>;
+def VLDREPL_H : LSX2RI11_Load<0x30400000>;
+def VLDREPL_W : LSX2RI10_Load<0x30200000>;
+def VLDREPL_D : LSX2RI9_Load<0x30100000>;
 } // mayLoad = 1, mayStore = 0
 
 let mayLoad = 0, mayStore = 1 in {
-def VST : LSX2RI12_VRI<0x2c400000>;
-def VSTX : LSX3R_VRR<0x38440000>;
+def VST : LSX2RI12_Store<0x2c400000>;
+def VSTX : LSX3R_Store<0x38440000>;
 
 def VSTELM_B : LSX2RI8I4_VRII<0x31800000>;
 def VSTELM_H : LSX2RI8I3_VRII<0x31400000, simm8_lsl1>;