diff --git a/clang/include/clang/Basic/BuiltinsAArch64.def b/clang/include/clang/Basic/BuiltinsAArch64.def
index ec635d4dd507b..eaae6c9ad8468 100644
--- a/clang/include/clang/Basic/BuiltinsAArch64.def
+++ b/clang/include/clang/Basic/BuiltinsAArch64.def
@@ -259,15 +259,16 @@ TARGET_HEADER_BUILTIN(__umulh, "ULLiULLiULLi", "nh", INTRIN_H, ALL_MS_LANGUAGES,
 
 TARGET_HEADER_BUILTIN(__break, "vi", "nh", INTRIN_H, ALL_MS_LANGUAGES, "")
 
-TARGET_HEADER_BUILTIN(__writex18byte,  "vULiUc", "nh", INTRIN_H, ALL_MS_LANGUAGES, "")
-TARGET_HEADER_BUILTIN(__writex18word,  "vULiUs", "nh", INTRIN_H, ALL_MS_LANGUAGES, "")
-TARGET_HEADER_BUILTIN(__writex18dword, "vULiULi", "nh", INTRIN_H, ALL_MS_LANGUAGES, "")
-TARGET_HEADER_BUILTIN(__writex18qword, "vULiULLi", "nh", INTRIN_H, ALL_MS_LANGUAGES, "")
-
-TARGET_HEADER_BUILTIN(__readx18byte,  "UcULi", "nh", INTRIN_H, ALL_MS_LANGUAGES, "")
-TARGET_HEADER_BUILTIN(__readx18word,  "UsULi", "nh", INTRIN_H, ALL_MS_LANGUAGES, "")
-TARGET_HEADER_BUILTIN(__readx18dword, "ULiULi", "nh", INTRIN_H, ALL_MS_LANGUAGES, "")
-TARGET_HEADER_BUILTIN(__readx18qword, "ULLiULi", "nh", INTRIN_H, ALL_MS_LANGUAGES, "")
+
+TARGET_HEADER_BUILTIN(__writex18byte,  "vUNiUc", "nh", INTRIN_H, ALL_MS_LANGUAGES, "")
+TARGET_HEADER_BUILTIN(__writex18word,  "vUNiUs", "nh", INTRIN_H, ALL_MS_LANGUAGES, "")
+TARGET_HEADER_BUILTIN(__writex18dword, "vUNiUNi", "nh", INTRIN_H, ALL_MS_LANGUAGES, "")
+TARGET_HEADER_BUILTIN(__writex18qword, "vUNiULLi", "nh", INTRIN_H, ALL_MS_LANGUAGES, "")
+
+TARGET_HEADER_BUILTIN(__readx18byte,  "UcUNi", "nh", INTRIN_H, ALL_MS_LANGUAGES, "")
+TARGET_HEADER_BUILTIN(__readx18word,  "UsUNi", "nh", INTRIN_H, ALL_MS_LANGUAGES, "")
+TARGET_HEADER_BUILTIN(__readx18dword, "UNiUNi", "nh", INTRIN_H, ALL_MS_LANGUAGES, "")
+TARGET_HEADER_BUILTIN(__readx18qword, "ULLiUNi", "nh", INTRIN_H, ALL_MS_LANGUAGES, "")
 
 #undef BUILTIN
 #undef LANGBUILTIN
diff --git a/clang/test/CodeGen/arm64-microsoft-intrinsics.c b/clang/test/CodeGen/arm64-microsoft-intrinsics.c
index ec5909c77b962..bd8e4cb27e526 100644
--- a/clang/test/CodeGen/arm64-microsoft-intrinsics.c
+++ b/clang/test/CodeGen/arm64-microsoft-intrinsics.c
@@ -1,9 +1,12 @@
 // RUN: %clang_cc1 -triple arm64-windows -Wno-implicit-function-declaration -fms-compatibility -emit-llvm -o - %s \
-// RUN:    | FileCheck %s -check-prefix CHECK-MSVC
+// RUN:    | FileCheck %s --check-prefix=CHECK-MSVC --check-prefix=CHECK-MSCOMPAT
 
 // RUN: not %clang_cc1 -triple arm64-linux -Werror -S -o /dev/null %s 2>&1 \
 // RUN:    | FileCheck %s -check-prefix CHECK-LINUX
 
+// RUN: %clang_cc1 -triple arm64-darwin -Wno-implicit-function-declaration -fms-compatibility -emit-llvm -o - %s \
+// RUN:    | FileCheck %s -check-prefix CHECK-MSCOMPAT
+
 long test_InterlockedAdd(long volatile *Addend, long Value) {
   return _InterlockedAdd(Addend, Value);
 }
@@ -117,128 +120,150 @@ unsigned __int64 check__getReg(void) {
   return reg;
 }
 
-// CHECK-MSVC: call i64 @llvm.read_register.i64(metadata ![[MD2:.*]])
-// CHECK-MSVC: call i64 @llvm.read_register.i64(metadata ![[MD3:.*]])
+// CHECK-MSCOMPAT: call i64 @llvm.read_register.i64(metadata ![[MD2:.*]])
+// CHECK-MSCOMPAT: call i64 @llvm.read_register.i64(metadata ![[MD3:.*]])
+
+#ifdef __LP64__
+#define LONG __int32
+#else
+#define LONG long
+#endif
 
-void check__writex18byte(unsigned long offset, unsigned char data) {
+#ifdef __LP64__
+void check__writex18byte(unsigned char data, unsigned LONG offset) {
+#else
+void check__writex18byte(unsigned LONG offset, unsigned char data) {
+#endif
   __writex18byte(offset, data);
 }
 
-// CHECK-MSVC: %[[DATA_ADDR:.*]] = alloca i8, align 1
-// CHECK-MSVC: %[[OFFSET_ADDR:.*]] = alloca i32, align 4
-// CHECK-MSVC: store i8 %data, ptr %[[DATA_ADDR]], align 1
-// CHECK-MSVC: store i32 %offset, ptr %[[OFFSET_ADDR]], align 4
-// CHECK-MSVC: %[[X18:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD2]])
-// CHECK-MSVC: %[[X18_AS_PTR:.*]] = inttoptr i64 %[[X18]] to ptr
-// CHECK-MSVC: %[[OFFSET:.*]] = load i32, ptr %[[OFFSET_ADDR]], align 4
-// CHECK-MSVC: %[[ZEXT_OFFSET:.*]] = zext i32 %[[OFFSET]] to i64
-// CHECK-MSVC: %[[PTR:.*]] = getelementptr i8, ptr %[[X18_AS_PTR]], i64 %[[ZEXT_OFFSET]]
-// CHECK-MSVC: %[[DATA:.*]] = load i8, ptr %[[DATA_ADDR]], align 1
-// CHECK-MSVC: store i8 %[[DATA]], ptr %[[PTR]], align 1
-
-void check__writex18word(unsigned long offset, unsigned short data) {
+// CHECK-MSCOMPAT: %[[DATA_ADDR:.*]] = alloca i8, align 1
+// CHECK-MSCOMPAT: %[[OFFSET_ADDR:.*]] = alloca i32, align 4
+// CHECK-MSCOMPAT: store i8 %data, ptr %[[DATA_ADDR]], align 1
+// CHECK-MSCOMPAT: store i32 %offset, ptr %[[OFFSET_ADDR]], align 4
+// CHECK-MSCOMPAT: %[[X18:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD2]])
+// CHECK-MSCOMPAT: %[[X18_AS_PTR:.*]] = inttoptr i64 %[[X18]] to ptr
+// CHECK-MSCOMPAT: %[[OFFSET:.*]] = load i32, ptr %[[OFFSET_ADDR]], align 4
+// CHECK-MSCOMPAT: %[[ZEXT_OFFSET:.*]] = zext i32 %[[OFFSET]] to i64
+// CHECK-MSCOMPAT: %[[PTR:.*]] = getelementptr i8, ptr %[[X18_AS_PTR]], i64 %[[ZEXT_OFFSET]]
+// CHECK-MSCOMPAT: %[[DATA:.*]] = load i8, ptr %[[DATA_ADDR]], align 1
+// CHECK-MSCOMPAT: store i8 %[[DATA]], ptr %[[PTR]], align 1
+
+#ifdef __LP64__
+void check__writex18word(unsigned short data, unsigned LONG offset) {
+#else
+void check__writex18word(unsigned LONG offset, unsigned short data) {
+#endif
   __writex18word(offset, data);
 }
 
-// CHECK-MSVC: %[[DATA_ADDR:.*]] = alloca i16, align 2
-// CHECK-MSVC: %[[OFFSET_ADDR:.*]] = alloca i32, align 4
-// CHECK-MSVC: store i16 %data, ptr %[[DATA_ADDR]], align 2
-// CHECK-MSVC: store i32 %offset, ptr %[[OFFSET_ADDR]], align 4
-// CHECK-MSVC: %[[X18:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD2]])
-// CHECK-MSVC: %[[X18_AS_PTR:.*]] = inttoptr i64 %[[X18]] to ptr
-// CHECK-MSVC: %[[OFFSET:.*]] = load i32, ptr %[[OFFSET_ADDR]], align 4
-// CHECK-MSVC: %[[ZEXT_OFFSET:.*]] = zext i32 %[[OFFSET]] to i64
-// CHECK-MSVC: %[[PTR:.*]] = getelementptr i8, ptr %[[X18_AS_PTR]], i64 %[[ZEXT_OFFSET]]
-// CHECK-MSVC: %[[DATA:.*]] = load i16, ptr %[[DATA_ADDR]], align 2
-// CHECK-MSVC: store i16 %[[DATA]], ptr %[[PTR]], align 1
-
-void check__writex18dword(unsigned long offset, unsigned long data) {
+// CHECK-MSCOMPAT: %[[DATA_ADDR:.*]] = alloca i16, align 2
+// CHECK-MSCOMPAT: %[[OFFSET_ADDR:.*]] = alloca i32, align 4
+// CHECK-MSCOMPAT: store i16 %data, ptr %[[DATA_ADDR]], align 2
+// CHECK-MSCOMPAT: store i32 %offset, ptr %[[OFFSET_ADDR]], align 4
+// CHECK-MSCOMPAT: %[[X18:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD2]])
+// CHECK-MSCOMPAT: %[[X18_AS_PTR:.*]] = inttoptr i64 %[[X18]] to ptr
+// CHECK-MSCOMPAT: %[[OFFSET:.*]] = load i32, ptr %[[OFFSET_ADDR]], align 4
+// CHECK-MSCOMPAT: %[[ZEXT_OFFSET:.*]] = zext i32 %[[OFFSET]] to i64
+// CHECK-MSCOMPAT: %[[PTR:.*]] = getelementptr i8, ptr %[[X18_AS_PTR]], i64 %[[ZEXT_OFFSET]]
+// CHECK-MSCOMPAT: %[[DATA:.*]] = load i16, ptr %[[DATA_ADDR]], align 2
+// CHECK-MSCOMPAT: store i16 %[[DATA]], ptr %[[PTR]], align 1
+
+#ifdef __LP64__
+void check__writex18dword(unsigned LONG data, unsigned LONG offset) {
+#else
+void check__writex18dword(unsigned LONG offset, unsigned LONG data) {
+#endif
   __writex18dword(offset, data);
 }
 
-// CHECK-MSVC: %[[DATA_ADDR:.*]] = alloca i32, align 4
-// CHECK-MSVC: %[[OFFSET_ADDR:.*]] = alloca i32, align 4
-// CHECK-MSVC: store i32 %data, ptr %[[DATA_ADDR]], align 4
-// CHECK-MSVC: store i32 %offset, ptr %[[OFFSET_ADDR]], align 4
-// CHECK-MSVC: %[[X18:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD2]])
-// CHECK-MSVC: %[[X18_AS_PTR:.*]] = inttoptr i64 %[[X18]] to ptr
-// CHECK-MSVC: %[[OFFSET:.*]] = load i32, ptr %[[OFFSET_ADDR]], align 4
-// CHECK-MSVC: %[[ZEXT_OFFSET:.*]] = zext i32 %[[OFFSET]] to i64
-// CHECK-MSVC: %[[PTR:.*]] = getelementptr i8, ptr %[[X18_AS_PTR]], i64 %[[ZEXT_OFFSET]]
-// CHECK-MSVC: %[[DATA:.*]] = load i32, ptr %[[DATA_ADDR]], align 4
-// CHECK-MSVC: store i32 %[[DATA]], ptr %[[PTR]], align 1
-
-void check__writex18qword(unsigned long offset, unsigned __int64 data) {
+// CHECK-MSCOMPAT: %[[DATA_ADDR:.*]] = alloca i32, align 4
+// CHECK-MSCOMPAT: %[[OFFSET_ADDR:.*]] = alloca i32, align 4
+// CHECK-MSCOMPAT: store i32 %data, ptr %[[DATA_ADDR]], align 4
+// CHECK-MSCOMPAT: store i32 %offset, ptr %[[OFFSET_ADDR]], align 4
+// CHECK-MSCOMPAT: %[[X18:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD2]])
+// CHECK-MSCOMPAT: %[[X18_AS_PTR:.*]] = inttoptr i64 %[[X18]] to ptr
+// CHECK-MSCOMPAT: %[[OFFSET:.*]] = load i32, ptr %[[OFFSET_ADDR]], align 4
+// CHECK-MSCOMPAT: %[[ZEXT_OFFSET:.*]] = zext i32 %[[OFFSET]] to i64
+// CHECK-MSCOMPAT: %[[PTR:.*]] = getelementptr i8, ptr %[[X18_AS_PTR]], i64 %[[ZEXT_OFFSET]]
+// CHECK-MSCOMPAT: %[[DATA:.*]] = load i32, ptr %[[DATA_ADDR]], align 4
+// CHECK-MSCOMPAT: store i32 %[[DATA]], ptr %[[PTR]], align 1
+
+#ifdef __LP64__
+void check__writex18qword(unsigned __int64 data, unsigned LONG offset) {
+#else
+void check__writex18qword(unsigned LONG offset, unsigned __int64 data) {
+#endif
   __writex18qword(offset, data);
 }
 
-// CHECK-MSVC: %[[DATA_ADDR:.*]] = alloca i64, align 8
-// CHECK-MSVC: %[[OFFSET_ADDR:.*]] = alloca i32, align 4
-// CHECK-MSVC: store i64 %data, ptr %[[DATA_ADDR]], align 8
-// CHECK-MSVC: store i32 %offset, ptr %[[OFFSET_ADDR]], align 4
-// CHECK-MSVC: %[[X18:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD2]])
-// CHECK-MSVC: %[[X18_AS_PTR:.*]] = inttoptr i64 %[[X18]] to ptr
-// CHECK-MSVC: %[[OFFSET:.*]] = load i32, ptr %[[OFFSET_ADDR]], align 4
-// CHECK-MSVC: %[[ZEXT_OFFSET:.*]] = zext i32 %[[OFFSET]] to i64
-// CHECK-MSVC: %[[PTR:.*]] = getelementptr i8, ptr %[[X18_AS_PTR]], i64 %[[ZEXT_OFFSET]]
-// CHECK-MSVC: %[[DATA:.*]] = load i64, ptr %[[DATA_ADDR]], align 8
-// CHECK-MSVC: store i64 %[[DATA]], ptr %[[PTR]], align 1
-
-unsigned char check__readx18byte(unsigned long offset) {
+// CHECK-MSCOMPAT: %[[DATA_ADDR:.*]] = alloca i64, align 8
+// CHECK-MSCOMPAT: %[[OFFSET_ADDR:.*]] = alloca i32, align 4
+// CHECK-MSCOMPAT: store i64 %data, ptr %[[DATA_ADDR]], align 8
+// CHECK-MSCOMPAT: store i32 %offset, ptr %[[OFFSET_ADDR]], align 4
+// CHECK-MSCOMPAT: %[[X18:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD2]])
+// CHECK-MSCOMPAT: %[[X18_AS_PTR:.*]] = inttoptr i64 %[[X18]] to ptr
+// CHECK-MSCOMPAT: %[[OFFSET:.*]] = load i32, ptr %[[OFFSET_ADDR]], align 4
+// CHECK-MSCOMPAT: %[[ZEXT_OFFSET:.*]] = zext i32 %[[OFFSET]] to i64
+// CHECK-MSCOMPAT: %[[PTR:.*]] = getelementptr i8, ptr %[[X18_AS_PTR]], i64 %[[ZEXT_OFFSET]]
+// CHECK-MSCOMPAT: %[[DATA:.*]] = load i64, ptr %[[DATA_ADDR]], align 8
+// CHECK-MSCOMPAT: store i64 %[[DATA]], ptr %[[PTR]], align 1
+
+unsigned char check__readx18byte(unsigned LONG offset) {
   return __readx18byte(offset);
 }
 
-// CHECK-MSVC: %[[OFFSET_ADDR:.*]] = alloca i32, align 4
-// CHECK-MSVC: store i32 %offset, ptr %[[OFFSET_ADDR]], align 4
-// CHECK-MSVC: %[[X18:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD2]])
-// CHECK-MSVC: %[[X18_AS_PTR:.*]] = inttoptr i64 %[[X18]] to ptr
-// CHECK-MSVC: %[[OFFSET:.*]] = load i32, ptr %[[OFFSET_ADDR]], align 4
-// CHECK-MSVC: %[[ZEXT_OFFSET:.*]] = zext i32 %[[OFFSET]] to i64
-// CHECK-MSVC: %[[PTR:.*]] = getelementptr i8, ptr %[[X18_AS_PTR]], i64 %[[ZEXT_OFFSET]]
-// CHECK-MSVC: %[[RETVAL:.*]] = load i8, ptr %[[PTR]], align 1
-// CHECK-MSVC: ret i8 %[[RETVAL]]
-
-unsigned short check__readx18word(unsigned long offset) {
+// CHECK-MSCOMPAT: %[[OFFSET_ADDR:.*]] = alloca i32, align 4
+// CHECK-MSCOMPAT: store i32 %offset, ptr %[[OFFSET_ADDR]], align 4
+// CHECK-MSCOMPAT: %[[X18:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD2]])
+// CHECK-MSCOMPAT: %[[X18_AS_PTR:.*]] = inttoptr i64 %[[X18]] to ptr
+// CHECK-MSCOMPAT: %[[OFFSET:.*]] = load i32, ptr %[[OFFSET_ADDR]], align 4
+// CHECK-MSCOMPAT: %[[ZEXT_OFFSET:.*]] = zext i32 %[[OFFSET]] to i64
+// CHECK-MSCOMPAT: %[[PTR:.*]] = getelementptr i8, ptr %[[X18_AS_PTR]], i64 %[[ZEXT_OFFSET]]
+// CHECK-MSCOMPAT: %[[RETVAL:.*]] = load i8, ptr %[[PTR]], align 1
+// CHECK-MSCOMPAT: ret i8 %[[RETVAL]]
+
+unsigned short check__readx18word(unsigned LONG offset) {
   return __readx18word(offset);
 }
 
-// CHECK-MSVC: %[[OFFSET_ADDR:.*]] = alloca i32, align 4
-// CHECK-MSVC: store i32 %offset, ptr %[[OFFSET_ADDR]], align 4
-// CHECK-MSVC: %[[X18:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD2]])
-// CHECK-MSVC: %[[X18_AS_PTR:.*]] = inttoptr i64 %[[X18]] to ptr
-// CHECK-MSVC: %[[OFFSET:.*]] = load i32, ptr %[[OFFSET_ADDR]], align 4
-// CHECK-MSVC: %[[ZEXT_OFFSET:.*]] = zext i32 %[[OFFSET]] to i64
-// CHECK-MSVC: %[[PTR:.*]] = getelementptr i8, ptr %[[X18_AS_PTR]], i64 %[[ZEXT_OFFSET]]
-// CHECK-MSVC: %[[RETVAL:.*]] = load i16, ptr %[[PTR]], align 1
-// CHECK-MSVC: ret i16 %[[RETVAL]]
-
-unsigned long check__readx18dword(unsigned long offset) {
+// CHECK-MSCOMPAT: %[[OFFSET_ADDR:.*]] = alloca i32, align 4
+// CHECK-MSCOMPAT: store i32 %offset, ptr %[[OFFSET_ADDR]], align 4
+// CHECK-MSCOMPAT: %[[X18:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD2]])
+// CHECK-MSCOMPAT: %[[X18_AS_PTR:.*]] = inttoptr i64 %[[X18]] to ptr
+// CHECK-MSCOMPAT: %[[OFFSET:.*]] = load i32, ptr %[[OFFSET_ADDR]], align 4
+// CHECK-MSCOMPAT: %[[ZEXT_OFFSET:.*]] = zext i32 %[[OFFSET]] to i64
+// CHECK-MSCOMPAT: %[[PTR:.*]] = getelementptr i8, ptr %[[X18_AS_PTR]], i64 %[[ZEXT_OFFSET]]
+// CHECK-MSCOMPAT: %[[RETVAL:.*]] = load i16, ptr %[[PTR]], align 1
+// CHECK-MSCOMPAT: ret i16 %[[RETVAL]]
+
+unsigned LONG check__readx18dword(unsigned LONG offset) {
   return __readx18dword(offset);
 }
 
-// CHECK-MSVC: %[[OFFSET_ADDR:.*]] = alloca i32, align 4
-// CHECK-MSVC: store i32 %offset, ptr %[[OFFSET_ADDR]], align 4
-// CHECK-MSVC: %[[X18:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD2]])
-// CHECK-MSVC: %[[X18_AS_PTR:.*]] = inttoptr i64 %[[X18]] to ptr
-// CHECK-MSVC: %[[OFFSET:.*]] = load i32, ptr %[[OFFSET_ADDR]], align 4
-// CHECK-MSVC: %[[ZEXT_OFFSET:.*]] = zext i32 %[[OFFSET]] to i64
-// CHECK-MSVC: %[[PTR:.*]] = getelementptr i8, ptr %[[X18_AS_PTR]], i64 %[[ZEXT_OFFSET]]
-// CHECK-MSVC: %[[RETVAL:.*]] = load i32, ptr %[[PTR]], align 1
-// CHECK-MSVC: ret i32 %[[RETVAL]]
-
-unsigned __int64 check__readx18qword(unsigned long offset) {
+// CHECK-MSCOMPAT: %[[OFFSET_ADDR:.*]] = alloca i32, align 4
+// CHECK-MSCOMPAT: store i32 %offset, ptr %[[OFFSET_ADDR]], align 4
+// CHECK-MSCOMPAT: %[[X18:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD2]])
+// CHECK-MSCOMPAT: %[[X18_AS_PTR:.*]] = inttoptr i64 %[[X18]] to ptr
+// CHECK-MSCOMPAT: %[[OFFSET:.*]] = load i32, ptr %[[OFFSET_ADDR]], align 4
+// CHECK-MSCOMPAT: %[[ZEXT_OFFSET:.*]] = zext i32 %[[OFFSET]] to i64
+// CHECK-MSCOMPAT: %[[PTR:.*]] = getelementptr i8, ptr %[[X18_AS_PTR]], i64 %[[ZEXT_OFFSET]]
+// CHECK-MSCOMPAT: %[[RETVAL:.*]] = load i32, ptr %[[PTR]], align 1
+// CHECK-MSCOMPAT: ret i32 %[[RETVAL]]
+
+unsigned __int64 check__readx18qword(unsigned LONG offset) {
   return __readx18qword(offset);
 }
 
-// CHECK-MSVC: %[[OFFSET_ADDR:.*]] = alloca i32, align 4
-// CHECK-MSVC: store i32 %offset, ptr %[[OFFSET_ADDR]], align 4
-// CHECK-MSVC: %[[X18:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD2]])
-// CHECK-MSVC: %[[X18_AS_PTR:.*]] = inttoptr i64 %[[X18]] to ptr
-// CHECK-MSVC: %[[OFFSET:.*]] = load i32, ptr %[[OFFSET_ADDR]], align 4
-// CHECK-MSVC: %[[ZEXT_OFFSET:.*]] = zext i32 %[[OFFSET]] to i64
-// CHECK-MSVC: %[[PTR:.*]] = getelementptr i8, ptr %[[X18_AS_PTR]], i64 %[[ZEXT_OFFSET]]
-// CHECK-MSVC: %[[RETVAL:.*]] = load i64, ptr %[[PTR]], align 1
-// CHECK-MSVC: ret i64 %[[RETVAL]]
-
-// CHECK-MSVC: ![[MD2]] = !{!"x18"}
-// CHECK-MSVC: ![[MD3]] = !{!"sp"}
+// CHECK-MSCOMPAT: %[[OFFSET_ADDR:.*]] = alloca i32, align 4
+// CHECK-MSCOMPAT: store i32 %offset, ptr %[[OFFSET_ADDR]], align 4
+// CHECK-MSCOMPAT: %[[X18:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD2]])
+// CHECK-MSCOMPAT: %[[X18_AS_PTR:.*]] = inttoptr i64 %[[X18]] to ptr
+// CHECK-MSCOMPAT: %[[OFFSET:.*]] = load i32, ptr %[[OFFSET_ADDR]], align 4
+// CHECK-MSCOMPAT: %[[ZEXT_OFFSET:.*]] = zext i32 %[[OFFSET]] to i64
+// CHECK-MSCOMPAT: %[[PTR:.*]] = getelementptr i8, ptr %[[X18_AS_PTR]], i64 %[[ZEXT_OFFSET]]
+// CHECK-MSCOMPAT: %[[RETVAL:.*]] = load i64, ptr %[[PTR]], align 1
+// CHECK-MSCOMPAT: ret i64 %[[RETVAL]]
+
+// CHECK-MSCOMPAT: ![[MD2]] = !{!"x18"}
+// CHECK-MSCOMPAT: ![[MD3]] = !{!"sp"}