diff --git a/llvm/test/CodeGen/X86/vec_insert-5.ll b/llvm/test/CodeGen/X86/vec_insert-5.ll
index 8a75881f01df27..3ad75a667eaa42 100644
--- a/llvm/test/CodeGen/X86/vec_insert-5.ll
+++ b/llvm/test/CodeGen/X86/vec_insert-5.ll
@@ -1,6 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=i386-unknown -mattr=+sse2,+ssse3 | FileCheck %s --check-prefix=X32
-; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2,+ssse3 | FileCheck %s --check-prefix=X64
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2,+ssse3 | FileCheck %s --check-prefixes=X64,ALIGN
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2,+ssse3,sse-unaligned-mem | FileCheck %s --check-prefixes=X64,UNALIGN
 
 ; There are no MMX operations in @t1
 
@@ -92,6 +93,38 @@ define <4 x float> @t4(<4 x float>* %P) nounwind {
   ret <4 x float> %tmp2
 }
 
+define <4 x float> @t4_under_aligned(<4 x float>* %P) nounwind {
+; X32-LABEL: t4_under_aligned:
+; X32:       # %bb.0:
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    movups (%eax), %xmm1
+; X32-NEXT:    xorps %xmm2, %xmm2
+; X32-NEXT:    xorps %xmm0, %xmm0
+; X32-NEXT:    shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[3,0]
+; X32-NEXT:    shufps {{.*#+}} xmm0 = xmm0[2,0],xmm2[2,3]
+; X32-NEXT:    retl
+;
+; ALIGN-LABEL: t4_under_aligned:
+; ALIGN:       # %bb.0:
+; ALIGN-NEXT:    movups (%rdi), %xmm1
+; ALIGN-NEXT:    xorps %xmm2, %xmm2
+; ALIGN-NEXT:    xorps %xmm0, %xmm0
+; ALIGN-NEXT:    shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[3,0]
+; ALIGN-NEXT:    shufps {{.*#+}} xmm0 = xmm0[2,0],xmm2[2,3]
+; ALIGN-NEXT:    retq
+;
+; UNALIGN-LABEL: t4_under_aligned:
+; UNALIGN:       # %bb.0:
+; UNALIGN-NEXT:    xorps %xmm1, %xmm1
+; UNALIGN-NEXT:    xorps %xmm0, %xmm0
+; UNALIGN-NEXT:    shufps {{.*#+}} xmm0 = xmm0[1,0],mem[3,0]
+; UNALIGN-NEXT:    shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
+; UNALIGN-NEXT:    retq
+  %tmp1 = load <4 x float>, <4 x float>* %P, align 4
+  %tmp2 = shufflevector <4 x float> zeroinitializer, <4 x float> %tmp1, <4 x i32> < i32 7, i32 0, i32 0, i32 0 >
+  ret <4 x float> %tmp2
+}
+
 define <16 x i8> @t5(<16 x i8> %x) nounwind {
 ; X32-LABEL: t5:
 ; X32:       # %bb.0: