diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-constant.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-constant.mir index db37495f052d8b..2f2c305cfac798 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-constant.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-constant.mir @@ -1,55 +1,147 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN --- - -name: constant +name: constant_v_s32 legalized: true regBankSelected: true tracksRegLiveness: true - body: | bb.0: - liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 - ; GCN-LABEL: name: constant - %0:vgpr(p1) = COPY $vgpr0_vgpr1 - %1:vgpr(p1) = COPY $vgpr2_vgpr3 - - ; GCN: %{{[0-9]+}}:sreg_32 = S_MOV_B32 1 - %2:sreg_32(s32) = G_CONSTANT i32 1 - - ; GCN: [[LO0:%[0-9]+]]:sreg_32 = S_MOV_B32 0 - ; GCN: [[HI0:%[0-9]+]]:sreg_32 = S_MOV_B32 1 - ; GCN: %{{[0-9]+}}:sreg_64 = REG_SEQUENCE [[LO0]], %subreg.sub0, [[HI0]], %subreg.sub1 - %3:sgpr(s64) = G_CONSTANT i64 4294967296 - - ; GCN: %{{[0-9]+}}:sreg_32 = S_MOV_B32 1065353216 - %4:sgpr(s32) = G_FCONSTANT float 1.0 + ; GCN-LABEL: name: constant_v_s32 + ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec + ; GCN: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec + ; GCN: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4294967295, implicit $exec + ; GCN: [[V_MOV_B32_e32_3:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4294967242, implicit $exec + ; GCN: [[V_MOV_B32_e32_4:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 27, implicit $exec + ; GCN: S_ENDPGM 0, implicit [[V_MOV_B32_e32_]], implicit [[V_MOV_B32_e32_1]], implicit [[V_MOV_B32_e32_2]], implicit [[V_MOV_B32_e32_3]], implicit [[V_MOV_B32_e32_4]] + %0:vgpr(s32) = G_CONSTANT i32 0 + %1:vgpr(s32) = G_CONSTANT i32 1 + %2:vgpr(s32) = G_CONSTANT i32 -1 + %3:vgpr(s32) = G_CONSTANT i32 -54 + %4:vgpr(s32) = G_CONSTANT i32 27 + S_ENDPGM 0, implicit %0 , implicit %1 , implicit %2, implicit %3, implicit %4 +... - ; GCN: %5:sreg_64 = S_MOV_B64 4607182418800017408 - %5:sgpr(s64) = G_FCONSTANT double 1.0 +--- +name: constant_s_s32 +legalized: true +regBankSelected: true +tracksRegLiveness: true - ; GCN: [[LO1:%[0-9]+]]:sreg_32 = S_MOV_B32 0 - ; GCN: [[HI1:%[0-9]+]]:sreg_32 = S_MOV_B32 1076101120 - ; GCN: %{{[0-9]+}}:sreg_64 = REG_SEQUENCE [[LO1]], %subreg.sub0, [[HI1]], %subreg.sub1 - %6:sgpr(s64) = G_FCONSTANT double 10.0 +body: | + bb.0: + ; GCN-LABEL: name: constant_s_s32 + ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 + ; GCN: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 1 + ; GCN: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 4294967295 + ; GCN: [[S_MOV_B32_3:%[0-9]+]]:sreg_32 = S_MOV_B32 4294967242 + ; GCN: [[S_MOV_B32_4:%[0-9]+]]:sreg_32 = S_MOV_B32 27 + ; GCN: S_ENDPGM 0, implicit [[S_MOV_B32_]], implicit [[S_MOV_B32_1]], implicit [[S_MOV_B32_2]], implicit [[S_MOV_B32_3]], implicit [[S_MOV_B32_4]] + %0:sgpr(s32) = G_CONSTANT i32 0 + %1:sgpr(s32) = G_CONSTANT i32 1 + %2:sgpr(s32) = G_CONSTANT i32 -1 + %3:sgpr(s32) = G_CONSTANT i32 -54 + %4:sgpr(s32) = G_CONSTANT i32 27 + S_ENDPGM 0, implicit %0 , implicit %1 , implicit %2, implicit %3, implicit %4 +... - ; GCN: %{{[0-9]+}}:vgpr_32 = V_MOV_B32_e32 1 - %7:vgpr(s32) = G_CONSTANT i32 1 +# FIXME +# --- +# name: constant_v_s16 +# legalized: true +# regBankSelected: true +# tracksRegLiveness: true - ; GCN: [[LO2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0 - ; GCN: [[HI2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1 - ; GCN: %{{[0-9]+}}:vreg_64 = REG_SEQUENCE [[LO2]], %subreg.sub0, [[HI2]], %subreg.sub1 - %8:vgpr(s64) = G_CONSTANT i64 4294967296 +# body: | +# bb.0: +# %0:vgpry(s16) = G_CONSTANT i16 0 +# %1:vgpr(s16) = G_CONSTANT i16 1 +# %2:vgpr(s16) = G_CONSTANT i16 -1 +# %3:vgpr(s16) = G_CONSTANT i16 -54 +# %4:vgpr(s16) = G_CONSTANT i16 27 +# S_ENDPGM 0, implicit %0 , implicit %1 , implicit %2, implicit %3, implicit %4 +# ... - ; GCN: %{{[0-9]+}}:vgpr_32 = V_MOV_B32_e32 1065353216 - %9:vgpr(s32) = G_FCONSTANT float 1.0 +--- +name: constant_v_s64 +legalized: true +regBankSelected: true +tracksRegLiveness: true - ; GCN: [[LO3:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0 - ; GCN: [[HI3:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1072693248 - ; GCN: %{{[0-9]+}}:vreg_64 = REG_SEQUENCE [[LO3]], %subreg.sub0, [[HI3]], %subreg.sub1 - %10:vgpr(s64) = G_FCONSTANT double 1.0 +body: | + bb.0: + ; GCN-LABEL: name: constant_v_s64 + ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec + ; GCN: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec + ; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1 + ; GCN: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec + ; GCN: [[V_MOV_B32_e32_3:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec + ; GCN: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_2]], %subreg.sub0, [[V_MOV_B32_e32_3]], %subreg.sub1 + ; GCN: [[V_MOV_B32_e32_4:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4294967295, implicit $exec + ; GCN: [[V_MOV_B32_e32_5:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec + ; GCN: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_4]], %subreg.sub0, [[V_MOV_B32_e32_5]], %subreg.sub1 + ; GCN: [[V_MOV_B32_e32_6:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4294967242, implicit $exec + ; GCN: [[V_MOV_B32_e32_7:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec + ; GCN: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_6]], %subreg.sub0, [[V_MOV_B32_e32_7]], %subreg.sub1 + ; GCN: [[V_MOV_B32_e32_8:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 27, implicit $exec + ; GCN: [[V_MOV_B32_e32_9:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec + ; GCN: [[REG_SEQUENCE4:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_8]], %subreg.sub0, [[V_MOV_B32_e32_9]], %subreg.sub1 + ; GCN: [[V_MOV_B32_e32_10:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4294967295, implicit $exec + ; GCN: [[V_MOV_B32_e32_11:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec + ; GCN: [[REG_SEQUENCE5:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_10]], %subreg.sub0, [[V_MOV_B32_e32_11]], %subreg.sub1 + ; GCN: [[V_MOV_B32_e32_12:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec + ; GCN: [[V_MOV_B32_e32_13:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec + ; GCN: [[REG_SEQUENCE6:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_12]], %subreg.sub0, [[V_MOV_B32_e32_13]], %subreg.sub1 + ; GCN: [[V_MOV_B32_e32_14:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 23255, implicit $exec + ; GCN: [[V_MOV_B32_e32_15:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -16, implicit $exec + ; GCN: [[REG_SEQUENCE7:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_14]], %subreg.sub0, [[V_MOV_B32_e32_15]], %subreg.sub1 + ; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]], implicit [[REG_SEQUENCE1]], implicit [[REG_SEQUENCE2]], implicit [[REG_SEQUENCE3]], implicit [[REG_SEQUENCE4]], implicit [[REG_SEQUENCE5]], implicit [[REG_SEQUENCE6]], implicit [[REG_SEQUENCE7]] + %0:vgpr(s64) = G_CONSTANT i64 0 + %1:vgpr(s64) = G_CONSTANT i64 1 + %2:vgpr(s64) = G_CONSTANT i64 -1 + %3:vgpr(s64) = G_CONSTANT i64 -54 + %4:vgpr(s64) = G_CONSTANT i64 27 + %5:vgpr(s64) = G_CONSTANT i64 4294967295 + %6:vgpr(s64) = G_CONSTANT i64 4294967296 + %7:vgpr(s64) = G_CONSTANT i64 18446744004990098135 + S_ENDPGM 0, implicit %0 , implicit %1 , implicit %2, implicit %3, implicit %4, implicit %5, implicit %6, implicit %7 +... - S_ENDPGM 0, implicit %2, implicit %4, implicit %5, implicit %6, implicit %8, implicit %3, implicit %5, implicit %7, implicit %9, implicit %10 +--- +name: constant_s_s64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + ; GCN-LABEL: name: constant_s_s64 + ; GCN: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0 + ; GCN: [[S_MOV_B64_1:%[0-9]+]]:sreg_64 = S_MOV_B64 1 + ; GCN: [[S_MOV_B64_2:%[0-9]+]]:sreg_64 = S_MOV_B64 -1 + ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4294967242 + ; GCN: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 -1 + ; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1 + ; GCN: [[S_MOV_B64_3:%[0-9]+]]:sreg_64 = S_MOV_B64 27 + ; GCN: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 4294967295 + ; GCN: [[S_MOV_B32_3:%[0-9]+]]:sreg_32 = S_MOV_B32 0 + ; GCN: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_2]], %subreg.sub0, [[S_MOV_B32_3]], %subreg.sub1 + ; GCN: [[S_MOV_B32_4:%[0-9]+]]:sreg_32 = S_MOV_B32 0 + ; GCN: [[S_MOV_B32_5:%[0-9]+]]:sreg_32 = S_MOV_B32 1 + ; GCN: [[REG_SEQUENCE2:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_4]], %subreg.sub0, [[S_MOV_B32_5]], %subreg.sub1 + ; GCN: [[S_MOV_B32_6:%[0-9]+]]:sreg_32 = S_MOV_B32 23255 + ; GCN: [[S_MOV_B32_7:%[0-9]+]]:sreg_32 = S_MOV_B32 -16 + ; GCN: [[REG_SEQUENCE3:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_6]], %subreg.sub0, [[S_MOV_B32_7]], %subreg.sub1 + ; GCN: S_ENDPGM 0, implicit [[S_MOV_B64_]], implicit [[S_MOV_B64_1]], implicit [[S_MOV_B64_2]], implicit [[REG_SEQUENCE]], implicit [[S_MOV_B64_3]], implicit [[REG_SEQUENCE1]], implicit [[REG_SEQUENCE2]], implicit [[REG_SEQUENCE3]] + %0:sgpr(s64) = G_CONSTANT i64 0 + %1:sgpr(s64) = G_CONSTANT i64 1 + %2:sgpr(s64) = G_CONSTANT i64 -1 + %3:sgpr(s64) = G_CONSTANT i64 -54 + %4:sgpr(s64) = G_CONSTANT i64 27 + %5:sgpr(s64) = G_CONSTANT i64 4294967295 + %6:sgpr(s64) = G_CONSTANT i64 4294967296 + %7:sgpr(s64) = G_CONSTANT i64 18446744004990098135 + S_ENDPGM 0, implicit %0 , implicit %1 , implicit %2, implicit %3, implicit %4, implicit %5, implicit %6, implicit %7 ... diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fconstant.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fconstant.mir new file mode 100644 index 00000000000000..9afa4b08c0ecb8 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fconstant.mir @@ -0,0 +1,159 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s + +--- +name: fconstant_v_s32 +legalized: true +regBankSelected: true +tracksRegLiveness: true + +body: | + bb.0: + ; GCN-LABEL: name: fconstant_v_s32 + ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec + ; GCN: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1090519040, implicit $exec + ; GCN: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec + ; GCN: [[V_MOV_B32_e32_3:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1090519040, implicit $exec + ; GCN: S_ENDPGM 0, implicit [[V_MOV_B32_e32_]], implicit [[V_MOV_B32_e32_1]], implicit [[V_MOV_B32_e32_2]], implicit [[V_MOV_B32_e32_3]] + %0:vgpr(s32) = G_FCONSTANT float 1.0 + %1:vgpr(s32) = G_FCONSTANT float 8.0 + %2:vgpr(s32) = G_FCONSTANT float 1.0 + %3:vgpr(s32) = G_FCONSTANT float 8.0 + S_ENDPGM 0, implicit %0 , implicit %1 , implicit %2 , implicit %3 +... + +--- +name: fconstant_s_s32 +legalized: true +regBankSelected: true +tracksRegLiveness: true + +body: | + bb.0: + ; GCN-LABEL: name: fconstant_s_s32 + ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1065353216 + ; GCN: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 1090519040 + ; GCN: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 3212836864 + ; GCN: [[S_MOV_B32_3:%[0-9]+]]:sreg_32 = S_MOV_B32 3238002688 + ; GCN: $sgpr0 = COPY [[S_MOV_B32_]] + ; GCN: $sgpr1 = COPY [[S_MOV_B32_1]] + ; GCN: S_ENDPGM 0, implicit [[S_MOV_B32_]], implicit [[S_MOV_B32_1]], implicit [[S_MOV_B32_2]], implicit [[S_MOV_B32_3]] + %0:sgpr(s32) = G_FCONSTANT float 1.0 + %1:sgpr(s32) = G_FCONSTANT float 8.0 + %2:sgpr(s32) = G_FCONSTANT float -1.0 + %3:sgpr(s32) = G_FCONSTANT float -8.0 + $sgpr0 = COPY %0 + $sgpr1 = COPY %1 + S_ENDPGM 0, implicit %0 , implicit %1 , implicit %2 , implicit %3 + +... + +--- +name: fconstant_v_s64 +legalized: true +regBankSelected: true +tracksRegLiveness: true + +body: | + bb.0: + ; GCN-LABEL: name: fconstant_v_s64 + ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec + ; GCN: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1072693248, implicit $exec + ; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1 + ; GCN: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec + ; GCN: [[V_MOV_B32_e32_3:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1075838976, implicit $exec + ; GCN: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_2]], %subreg.sub0, [[V_MOV_B32_e32_3]], %subreg.sub1 + ; GCN: [[V_MOV_B32_e32_4:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec + ; GCN: [[V_MOV_B32_e32_5:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -1073741824, implicit $exec + ; GCN: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_4]], %subreg.sub0, [[V_MOV_B32_e32_5]], %subreg.sub1 + ; GCN: [[V_MOV_B32_e32_6:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec + ; GCN: [[V_MOV_B32_e32_7:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1076101120, implicit $exec + ; GCN: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_6]], %subreg.sub0, [[V_MOV_B32_e32_7]], %subreg.sub1 + ; GCN: $vgpr0_vgpr1 = COPY [[REG_SEQUENCE]] + ; GCN: $vgpr2_vgpr3 = COPY [[REG_SEQUENCE1]] + ; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]], implicit [[REG_SEQUENCE1]], implicit [[REG_SEQUENCE2]], implicit [[REG_SEQUENCE3]] + %0:vgpr(s64) = G_FCONSTANT double 1.0 + %1:vgpr(s64) = G_FCONSTANT double 8.0 + %2:vgpr(s64) = G_FCONSTANT double -2.0 + %3:vgpr(s64) = G_FCONSTANT double 10.0 + $vgpr0_vgpr1 = COPY %0 + $vgpr2_vgpr3 = COPY %1 + S_ENDPGM 0, implicit %0 , implicit %1 , implicit %2 , implicit %3 + +... + +--- +name: fconstant_s_s64 +legalized: true +regBankSelected: true +tracksRegLiveness: true + +body: | + bb.0: + ; GCN-LABEL: name: fconstant_s_s64 + ; GCN: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 4607182418800017408 + ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 + ; GCN: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 1075838976 + ; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1 + ; GCN: [[S_MOV_B64_1:%[0-9]+]]:sreg_64 = S_MOV_B64 -4611686018427387904 + ; GCN: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 0 + ; GCN: [[S_MOV_B32_3:%[0-9]+]]:sreg_32 = S_MOV_B32 -1071382528 + ; GCN: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_2]], %subreg.sub0, [[S_MOV_B32_3]], %subreg.sub1 + ; GCN: $sgpr0_sgpr1 = COPY [[S_MOV_B64_]] + ; GCN: $sgpr2_sgpr3 = COPY [[REG_SEQUENCE]] + ; GCN: S_ENDPGM 0, implicit [[S_MOV_B64_]], implicit [[REG_SEQUENCE]], implicit [[S_MOV_B64_1]], implicit [[REG_SEQUENCE1]] + %0:sgpr(s64) = G_FCONSTANT double 1.0 + %1:sgpr(s64) = G_FCONSTANT double 8.0 + %2:sgpr(s64) = G_FCONSTANT double -2.0 + %3:sgpr(s64) = G_FCONSTANT double -10.0 + $sgpr0_sgpr1 = COPY %0 + $sgpr2_sgpr3 = COPY %1 + S_ENDPGM 0, implicit %0 , implicit %1 , implicit %2 , implicit %3 +... + +--- +name: fconstant_v_s16 +legalized: true +regBankSelected: true +tracksRegLiveness: true + +body: | + bb.0: + ; GCN-LABEL: name: fconstant_v_s16 + ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 15360, implicit $exec + ; GCN: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 18432, implicit $exec + ; GCN: $vgpr0 = COPY [[V_MOV_B32_e32_]] + ; GCN: $vgpr1 = COPY [[V_MOV_B32_e32_1]] + %0:vgpr(s16) = G_FCONSTANT half 1.0 + %1:vgpr(s16) = G_FCONSTANT half 8.0 + %2:vgpr(s32) = G_ANYEXT %0 + %3:vgpr(s32) = G_ANYEXT %1 + $vgpr0 = COPY %2 + $vgpr1 = COPY %3 + +... + +--- +name: fconstant_s_s16 +legalized: true +regBankSelected: true +tracksRegLiveness: true + +body: | + bb.0: + ; GCN-LABEL: name: fconstant_s_s16 + ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 15360 + ; GCN: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 18432 + ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] + ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]] + ; GCN: $sgpr0 = COPY [[COPY]] + ; GCN: $sgpr1 = COPY [[COPY1]] + %0:sgpr(s16) = G_FCONSTANT half 1.0 + %1:sgpr(s16) = G_FCONSTANT half 8.0 + %2:vgpr(s32) = G_ANYEXT %0 + %3:vgpr(s32) = G_ANYEXT %1 + $sgpr0 = COPY %2 + $sgpr1 = COPY %3 + +... +