diff --git a/clang/include/clang/Basic/arm_sve.td b/clang/include/clang/Basic/arm_sve.td
index a70c4d4e2dfcb2..4662b7ffdbf410 100644
--- a/clang/include/clang/Basic/arm_sve.td
+++ b/clang/include/clang/Basic/arm_sve.td
@@ -740,6 +740,8 @@ defm SVLSL : SInst_SHIFT<"svlsl", "aarch64_sve_lsl", "csilUcUsUiUl", "csiUcUsUi"
 defm SVLSR : SInst_SHIFT<"svlsr", "aarch64_sve_lsr", "UcUsUiUl", "UcUsUi">;
 
 def SVASRD_M : SInst<"svasrd[_n_{d}]", "dPdi", "csil",            MergeOp1,  "aarch64_sve_asrd", [], [ImmCheck<2, ImmCheckShiftRight, 1>]>;
+def SVASRD_X : SInst<"svasrd[_n_{d}]", "dPdi", "csil",            MergeAny,  "aarch64_sve_asrd", [], [ImmCheck<2, ImmCheckShiftRight, 1>]>;
+def SVASRD_Z : SInst<"svasrd[_n_{d}]", "dPdi", "csil",            MergeZero, "aarch64_sve_asrd", [], [ImmCheck<2, ImmCheckShiftRight, 1>]>;
 
 ////////////////////////////////////////////////////////////////////////////////
 // Integer reductions
diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_asrd.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_asrd.c
index bd0261f26189d5..99b00bba9183a2 100644
--- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_asrd.c
+++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_asrd.c
@@ -10,6 +10,84 @@
 #define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
 #endif
 
+svint8_t test_svasrd_n_s8_z(svbool_t pg, svint8_t op1)
+{
+  // CHECK-LABEL: test_svasrd_n_s8_z
+  // CHECK: %[[SEL:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.sel.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> zeroinitializer)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.asrd.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %[[SEL]], i32 1)
+  // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+  return SVE_ACLE_FUNC(svasrd,_n_s8,_z,)(pg, op1, 1);
+}
+
+svint8_t test_svasrd_n_s8_z_1(svbool_t pg, svint8_t op1)
+{
+  // CHECK-LABEL: test_svasrd_n_s8_z_1
+  // CHECK: %[[SEL:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.sel.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> zeroinitializer)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.asrd.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %[[SEL]], i32 8)
+  // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+  return SVE_ACLE_FUNC(svasrd,_n_s8,_z,)(pg, op1, 8);
+}
+
+svint16_t test_svasrd_n_s16_z(svbool_t pg, svint16_t op1)
+{
+  // CHECK-LABEL: test_svasrd_n_s16_z
+  // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+  // CHECK-DAG: %[[SEL:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.sel.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> zeroinitializer)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.asrd.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %[[SEL]], i32 1)
+  // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+  return SVE_ACLE_FUNC(svasrd,_n_s16,_z,)(pg, op1, 1);
+}
+
+svint16_t test_svasrd_n_s16_z_1(svbool_t pg, svint16_t op1)
+{
+  // CHECK-LABEL: test_svasrd_n_s16_z_1
+  // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+  // CHECK-DAG: %[[SEL:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.sel.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> zeroinitializer)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.asrd.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %[[SEL]], i32 16)
+  // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+  return SVE_ACLE_FUNC(svasrd,_n_s16,_z,)(pg, op1, 16);
+}
+
+svint32_t test_svasrd_n_s32_z(svbool_t pg, svint32_t op1)
+{
+  // CHECK-LABEL: test_svasrd_n_s32_z
+  // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+  // CHECK-DAG: %[[SEL:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sel.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> zeroinitializer)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.asrd.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %[[SEL]], i32 1)
+  // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+  return SVE_ACLE_FUNC(svasrd,_n_s32,_z,)(pg, op1, 1);
+}
+
+svint32_t test_svasrd_n_s32_z_1(svbool_t pg, svint32_t op1)
+{
+  // CHECK-LABEL: test_svasrd_n_s32_z_1
+  // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+  // CHECK-DAG: %[[SEL:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sel.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> zeroinitializer)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.asrd.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %[[SEL]], i32 32)
+  // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+  return SVE_ACLE_FUNC(svasrd,_n_s32,_z,)(pg, op1, 32);
+}
+
+svint64_t test_svasrd_n_s64_z(svbool_t pg, svint64_t op1)
+{
+  // CHECK-LABEL: test_svasrd_n_s64_z
+  // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+  // CHECK-DAG: %[[SEL:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.sel.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> zeroinitializer)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.asrd.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %[[SEL]], i32 1)
+  // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+  return SVE_ACLE_FUNC(svasrd,_n_s64,_z,)(pg, op1, 1);
+}
+
+svint64_t test_svasrd_n_s64_z_1(svbool_t pg, svint64_t op1)
+{
+  // CHECK-LABEL: test_svasrd_n_s64_z_1
+  // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+  // CHECK-DAG: %[[SEL:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.sel.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> zeroinitializer)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.asrd.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %[[SEL]], i32 64)
+  // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+  return SVE_ACLE_FUNC(svasrd,_n_s64,_z,)(pg, op1, 64);
+}
+
 svint8_t test_svasrd_n_s8_m(svbool_t pg, svint8_t op1)
 {
   // CHECK-LABEL: test_svasrd_n_s8_m
@@ -21,8 +99,8 @@ svint8_t test_svasrd_n_s8_m(svbool_t pg, svint8_t op1)
 svint16_t test_svasrd_n_s16_m(svbool_t pg, svint16_t op1)
 {
   // CHECK-LABEL: test_svasrd_n_s16_m
-  // CHECK: %[[P0:.*]] = call <vscale x 8 x i1>  @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.asrd.nxv8i16(<vscale x 8 x i1> %[[P0]], <vscale x 8 x i16> %op1, i32 1)
+  // CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.asrd.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, i32 1)
   // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svasrd,_n_s16,_m,)(pg, op1, 1);
 }
@@ -30,8 +108,8 @@ svint16_t test_svasrd_n_s16_m(svbool_t pg, svint16_t op1)
 svint32_t test_svasrd_n_s32_m(svbool_t pg, svint32_t op1)
 {
   // CHECK-LABEL: test_svasrd_n_s32_m
-  // CHECK: %[[P0:.*]] = call <vscale x 4 x i1>  @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.asrd.nxv4i32(<vscale x 4 x i1> %[[P0]], <vscale x 4 x i32> %op1, i32 1)
+  // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.asrd.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, i32 1)
   // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svasrd,_n_s32,_m,)(pg, op1, 1);
 }
@@ -39,43 +117,43 @@ svint32_t test_svasrd_n_s32_m(svbool_t pg, svint32_t op1)
 svint64_t test_svasrd_n_s64_m(svbool_t pg, svint64_t op1)
 {
   // CHECK-LABEL: test_svasrd_n_s64_m
-  // CHECK: %[[P0:.*]] = call <vscale x 2 x i1>  @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.asrd.nxv2i64(<vscale x 2 x i1> %[[P0]], <vscale x 2 x i64> %op1, i32 1)
+  // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.asrd.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, i32 1)
   // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
   return SVE_ACLE_FUNC(svasrd,_n_s64,_m,)(pg, op1, 1);
 }
 
-svint8_t test_svasrd_n_s8_max_m(svbool_t pg, svint8_t op1)
+svint8_t test_svasrd_n_s8_x(svbool_t pg, svint8_t op1)
 {
-  // CHECK-LABEL: test_svasrd_n_s8_max_m
+  // CHECK-LABEL: test_svasrd_n_s8_x
   // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.asrd.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, i32 8)
   // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
-  return SVE_ACLE_FUNC(svasrd,_n_s8,_m,)(pg, op1, 8);
+  return SVE_ACLE_FUNC(svasrd,_n_s8,_x,)(pg, op1, 8);
 }
 
-svint16_t test_svasrd_n_s16_max_m(svbool_t pg, svint16_t op1)
+svint16_t test_svasrd_n_s16_x(svbool_t pg, svint16_t op1)
 {
-  // CHECK-LABEL: test_svasrd_n_s16_max_m
-  // CHECK: %[[P0:.*]] = call <vscale x 8 x i1>  @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.asrd.nxv8i16(<vscale x 8 x i1> %[[P0]], <vscale x 8 x i16> %op1, i32 16)
+  // CHECK-LABEL: test_svasrd_n_s16_x
+  // CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.asrd.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, i32 16)
   // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
-  return SVE_ACLE_FUNC(svasrd,_n_s16,_m,)(pg, op1, 16);
+  return SVE_ACLE_FUNC(svasrd,_n_s16,_x,)(pg, op1, 16);
 }
 
-svint32_t test_svasrd_n_s32_max_m(svbool_t pg, svint32_t op1)
+svint32_t test_svasrd_n_s32_x(svbool_t pg, svint32_t op1)
 {
-  // CHECK-LABEL: test_svasrd_n_s32_max_m
-  // CHECK: %[[P0:.*]] = call <vscale x 4 x i1>  @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.asrd.nxv4i32(<vscale x 4 x i1> %[[P0]], <vscale x 4 x i32> %op1, i32 32)
+  // CHECK-LABEL: test_svasrd_n_s32_x
+  // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.asrd.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, i32 32)
   // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
-  return SVE_ACLE_FUNC(svasrd,_n_s32,_m,)(pg, op1, 32);
+  return SVE_ACLE_FUNC(svasrd,_n_s32,_x,)(pg, op1, 32);
 }
 
-svint64_t test_svasrd_n_s64_max_m(svbool_t pg, svint64_t op1)
+svint64_t test_svasrd_n_s64_x(svbool_t pg, svint64_t op1)
 {
-  // CHECK-LABEL: test_svasrd_n_s64_max_m
-  // CHECK: %[[P0:.*]] = call <vscale x 2 x i1>  @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
-  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.asrd.nxv2i64(<vscale x 2 x i1> %[[P0]], <vscale x 2 x i64> %op1, i32 64)
+  // CHECK-LABEL: test_svasrd_n_s64_x
+  // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.asrd.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, i32 64)
   // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
-  return SVE_ACLE_FUNC(svasrd,_n_s64,_m,)(pg, op1, 64);
+  return SVE_ACLE_FUNC(svasrd,_n_s64,_x,)(pg, op1, 64);
 }
diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_asrd.c b/clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_asrd.c
index 62547c3f98a2b1..f57b94393096b3 100644
--- a/clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_asrd.c
+++ b/clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_asrd.c
@@ -10,6 +10,54 @@
 
 #include <arm_sve.h>
 
+svint8_t test_svasrd_n_s8_z(svbool_t pg, svint8_t op1)
+{
+  // expected-error-re@+1 {{argument value {{[0-9]+}} is outside the valid range [1, 8]}}
+  return SVE_ACLE_FUNC(svasrd,_n_s8,_z,)(pg, op1, 0);
+}
+
+svint8_t test_svasrd_n_s8_z_1(svbool_t pg, svint8_t op1)
+{
+  // expected-error-re@+1 {{argument value {{[0-9]+}} is outside the valid range [1, 8]}}
+  return SVE_ACLE_FUNC(svasrd,_n_s8,_z,)(pg, op1, 9);
+}
+
+svint16_t test_svasrd_n_s16_z(svbool_t pg, svint16_t op1)
+{
+  // expected-error-re@+1 {{argument value {{[0-9]+}} is outside the valid range [1, 16]}}
+  return SVE_ACLE_FUNC(svasrd,_n_s16,_z,)(pg, op1, 0);
+}
+
+svint16_t test_svasrd_n_s16_z_1(svbool_t pg, svint16_t op1)
+{
+  // expected-error-re@+1 {{argument value {{[0-9]+}} is outside the valid range [1, 16]}}
+  return SVE_ACLE_FUNC(svasrd,_n_s16,_z,)(pg, op1, 17);
+}
+
+svint32_t test_svasrd_n_s32_z(svbool_t pg, svint32_t op1)
+{
+  // expected-error-re@+1 {{argument value {{[0-9]+}} is outside the valid range [1, 32]}}
+  return SVE_ACLE_FUNC(svasrd,_n_s32,_z,)(pg, op1, 0);
+}
+
+svint32_t test_svasrd_n_s32_z_1(svbool_t pg, svint32_t op1)
+{
+  // expected-error-re@+1 {{argument value {{[0-9]+}} is outside the valid range [1, 32]}}
+  return SVE_ACLE_FUNC(svasrd,_n_s32,_z,)(pg, op1, 33);
+}
+
+svint64_t test_svasrd_n_s64_z(svbool_t pg, svint64_t op1)
+{
+  // expected-error-re@+1 {{argument value {{[0-9]+}} is outside the valid range [1, 64]}}
+  return SVE_ACLE_FUNC(svasrd,_n_s64,_z,)(pg, op1, 0);
+}
+
+svint64_t test_svasrd_n_s64_z_1(svbool_t pg, svint64_t op1)
+{
+  // expected-error-re@+1 {{argument value {{[0-9]+}} is outside the valid range [1, 64]}}
+  return SVE_ACLE_FUNC(svasrd,_n_s64,_z,)(pg, op1, 65);
+}
+
 svint8_t test_svasrd_n_s8_m(svbool_t pg, svint8_t op1)
 {
   // expected-error-re@+1 {{argument value {{[0-9]+}} is outside the valid range [1, 8]}}
@@ -33,3 +81,27 @@ svint64_t test_svasrd_n_s64_m(svbool_t pg, svint64_t op1)
   // expected-error-re@+1 {{argument value {{[0-9]+}} is outside the valid range [1, 64]}}
   return SVE_ACLE_FUNC(svasrd,_n_s64,_m,)(pg, op1, 65);
 }
+
+svint8_t test_svasrd_n_s8_x(svbool_t pg, svint8_t op1)
+{
+  // expected-error-re@+1 {{argument value {{[0-9]+}} is outside the valid range [1, 8]}}
+  return SVE_ACLE_FUNC(svasrd,_n_s8,_x,)(pg, op1, 0);
+}
+
+svint16_t test_svasrd_n_s16_x(svbool_t pg, svint16_t op1)
+{
+  // expected-error-re@+1 {{argument value {{[0-9]+}} is outside the valid range [1, 16]}}
+  return SVE_ACLE_FUNC(svasrd,_n_s16,_x,)(pg, op1, 17);
+}
+
+svint32_t test_svasrd_n_s32_x(svbool_t pg, svint32_t op1)
+{
+  // expected-error-re@+1 {{argument value {{[0-9]+}} is outside the valid range [1, 32]}}
+  return SVE_ACLE_FUNC(svasrd,_n_s32,_x,)(pg, op1, 0);
+}
+
+svint64_t test_svasrd_n_s64_x(svbool_t pg, svint64_t op1)
+{
+  // expected-error-re@+1 {{argument value {{[0-9]+}} is outside the valid range [1, 64]}}
+  return SVE_ACLE_FUNC(svasrd,_n_s64,_x,)(pg, op1, 65);
+}