From 5102028f63b585bab42b2641bc9fcce71bb6ca99 Mon Sep 17 00:00:00 2001 From: Hiroshi Inoue Date: Tue, 27 Jun 2017 04:52:17 +0000 Subject: [PATCH] [PowerPC] set optimization level in SelectionDAGISel PowerPC backend does not pass the current optimization level to SelectionDAGISel and so SelectionDAGISel works with the default optimization level regardless of the current optimization level. This patch makes the PowerPC backend set the optimization level correctly. Differential Revision: https://reviews.llvm.org/D34615 llvm-svn: 306367 --- llvm/lib/Target/PowerPC/PPC.h | 3 +- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 9 +-- llvm/lib/Target/PowerPC/PPCTargetMachine.cpp | 2 +- llvm/test/CodeGen/PowerPC/anon_aggr.ll | 62 +++++++++---------- llvm/test/CodeGen/PowerPC/floatPSA.ll | 2 +- .../PowerPC/ppc64-align-long-double.ll | 24 +++---- llvm/test/CodeGen/PowerPC/tls.ll | 2 +- 7 files changed, 53 insertions(+), 51 deletions(-) diff --git a/llvm/lib/Target/PowerPC/PPC.h b/llvm/lib/Target/PowerPC/PPC.h index 07c9c1f9f84c0..476dfc0c86543 100644 --- a/llvm/lib/Target/PowerPC/PPC.h +++ b/llvm/lib/Target/PowerPC/PPC.h @@ -15,6 +15,7 @@ #ifndef LLVM_LIB_TARGET_POWERPC_PPC_H #define LLVM_LIB_TARGET_POWERPC_PPC_H +#include "llvm/Support/CodeGen.h" #include "MCTargetDesc/PPCMCTargetDesc.h" // GCC #defines PPC on Linux but we use it as our namespace name @@ -41,7 +42,7 @@ namespace llvm { FunctionPass *createPPCMIPeepholePass(); FunctionPass *createPPCBranchSelectionPass(); FunctionPass *createPPCQPXLoadSplatPass(); - FunctionPass *createPPCISelDag(PPCTargetMachine &TM); + FunctionPass *createPPCISelDag(PPCTargetMachine &TM, CodeGenOpt::Level OL); FunctionPass *createPPCTLSDynamicCallPass(); FunctionPass *createPPCBoolRetToIntPass(); FunctionPass *createPPCExpandISELPass(); diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index afd2e87078a96..535b9deaefac3 100644 --- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -114,8 +114,8 @@ namespace { unsigned GlobalBaseReg; public: - explicit PPCDAGToDAGISel(PPCTargetMachine &tm) - : SelectionDAGISel(tm), TM(tm) {} + explicit PPCDAGToDAGISel(PPCTargetMachine &tm, CodeGenOpt::Level OptLevel) + : SelectionDAGISel(tm, OptLevel), TM(tm) {} bool runOnMachineFunction(MachineFunction &MF) override { // Make sure we re-emit a set of the global base reg if necessary @@ -5116,6 +5116,7 @@ void PPCDAGToDAGISel::PeepholePPC64() { /// createPPCISelDag - This pass converts a legalized DAG into a /// PowerPC-specific DAG, ready for instruction scheduling. /// -FunctionPass *llvm::createPPCISelDag(PPCTargetMachine &TM) { - return new PPCDAGToDAGISel(TM); +FunctionPass *llvm::createPPCISelDag(PPCTargetMachine &TM, + CodeGenOpt::Level OptLevel) { + return new PPCDAGToDAGISel(TM, OptLevel); } diff --git a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp index a88a6541e8d00..f6bef33fd1351 100644 --- a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp +++ b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp @@ -352,7 +352,7 @@ bool PPCPassConfig::addILPOpts() { bool PPCPassConfig::addInstSelector() { // Install an instruction selector. - addPass(createPPCISelDag(getPPCTargetMachine())); + addPass(createPPCISelDag(getPPCTargetMachine(), getOptLevel())); #ifndef NDEBUG if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None) diff --git a/llvm/test/CodeGen/PowerPC/anon_aggr.ll b/llvm/test/CodeGen/PowerPC/anon_aggr.ll index 9b32a8f55f34c..5ad6adaa4ed61 100644 --- a/llvm/test/CodeGen/PowerPC/anon_aggr.ll +++ b/llvm/test/CodeGen/PowerPC/anon_aggr.ll @@ -22,7 +22,7 @@ unequal: ; CHECK-LABEL: func1: ; CHECK: cmpld {{([0-9]+,)?}}4, 5 -; CHECK-DAG: std 4, -[[OFFSET1:[0-9]+]] +; CHECK-DAG: std 3, -[[OFFSET1:[0-9]+]] ; CHECK-DAG: std 5, -[[OFFSET2:[0-9]+]] ; CHECK: ld 3, -[[OFFSET1]](1) ; CHECK: ld 3, -[[OFFSET2]](1) @@ -31,19 +31,19 @@ unequal: ; DARWIN32: mr ; DARWIN32: mr r[[REG1:[0-9]+]], r[[REGA:[0-9]+]] ; DARWIN32: mr r[[REG2:[0-9]+]], r[[REGB:[0-9]+]] -; DARWIN32: cmplw {{(cr[0-9]+,)?}}r[[REGA]], r[[REGB]] +; DARWIN32: cmplw {{(cr[0-9]+,)?}}r[[REGB]], r[[REGA]] ; DARWIN32: stw r[[REG1]], -[[OFFSET1:[0-9]+]] ; DARWIN32: stw r[[REG2]], -[[OFFSET2:[0-9]+]] -; DARWIN32: lwz r3, -[[OFFSET1]] ; DARWIN32: lwz r3, -[[OFFSET2]] +; DARWIN32: lwz r3, -[[OFFSET1]] ; DARWIN64: _func1: ; DARWIN64: mr ; DARWIN64: mr r[[REG1:[0-9]+]], r[[REGA:[0-9]+]] ; DARWIN64: mr r[[REG2:[0-9]+]], r[[REGB:[0-9]+]] -; DARWIN64: cmpld {{(cr[0-9]+,)?}}r[[REGA]], r[[REGB]] -; DARWIN64: std r[[REG1]], -[[OFFSET1:[0-9]+]] -; DARWIN64: std r[[REG2]], -[[OFFSET2:[0-9]+]] +; DARWIN64: cmpld {{(cr[0-9]+,)?}}r[[REGB]], r[[REGA]] +; DARWIN64: std r[[REG1]], -[[OFFSET2:[0-9]+]] +; DARWIN64: std r[[REG2]], -[[OFFSET1:[0-9]+]] ; DARWIN64: ld r3, -[[OFFSET1]] ; DARWIN64: ld r3, -[[OFFSET2]] @@ -61,19 +61,19 @@ unequal: ret i8* %array2_ptr } ; CHECK-LABEL: func2: -; CHECK: cmpld {{([0-9]+,)?}}4, 6 +; CHECK-DAG: cmpld {{([0-9]+,)?}}4, 6 ; CHECK-DAG: std 6, 72(1) ; CHECK-DAG: std 5, 64(1) ; CHECK-DAG: std 6, -[[OFFSET1:[0-9]+]] -; CHECK-DAG: std 4, -[[OFFSET2:[0-9]+]] +; CHECK-DAG: std 5, -[[OFFSET2:[0-9]+]] ; CHECK: ld 3, -[[OFFSET2]](1) ; CHECK: ld 3, -[[OFFSET1]](1) ; DARWIN32-LABEL: _func2 -; DARWIN32-DAG: addi r[[REG8:[0-9]+]], r[[REGSP:[0-9]+]], 36 -; DARWIN32-DAG: lwz r[[REG2:[0-9]+]], 44(r[[REGSP]]) ; DARWIN32: mr +; DARWIN32: addi r[[REG8:[0-9]+]], r[[REGSP:[0-9]+]], 36 ; DARWIN32: mr r[[REG7:[0-9]+]], r5 +; DARWIN32: lwz r[[REG2:[0-9]+]], 44(r[[REGSP]]) ; DARWIN32-DAG: cmplw {{(cr[0-9]+,)?}}r5, r[[REG2]] ; DARWIN32-DAG: stw r[[REG7]], -[[OFFSET1:[0-9]+]] ; DARWIN32-DAG: stw r[[REG2]], -[[OFFSET2:[0-9]+]] @@ -82,9 +82,9 @@ unequal: ; DARWIN64: _func2: -; DARWIN64: ld r[[REG2:[0-9]+]], 72(r1) ; DARWIN64: mr ; DARWIN64: mr r[[REG3:[0-9]+]], r[[REGA:[0-9]+]] +; DARWIN64: ld r[[REG2:[0-9]+]], 72(r1) ; DARWIN64: cmpld {{(cr[0-9]+,)?}}r[[REGA]], r[[REG2]] ; DARWIN64: std r[[REG2]], -[[OFFSET2:[0-9]+]] ; DARWIN64: std r[[REG3]], -[[OFFSET1:[0-9]+]] @@ -107,9 +107,9 @@ unequal: } ; CHECK-LABEL: func3: -; CHECK: cmpld {{([0-9]+,)?}}4, 6 -; CHECK-DAG: std 4, -[[OFFSET2:[0-9]+]](1) -; CHECK-DAG: std 6, -[[OFFSET1:[0-9]+]](1) +; CHECK-DAG: cmpld {{([0-9]+,)?}}3, 4 +; CHECK-DAG: std 3, -[[OFFSET2:[0-9]+]](1) +; CHECK-DAG: std 4, -[[OFFSET1:[0-9]+]](1) ; CHECK: ld 3, -[[OFFSET2]](1) ; CHECK: ld 3, -[[OFFSET1]](1) @@ -127,13 +127,13 @@ unequal: ; DARWIN32-DAG: lwz r3, -[[OFFSET2:[0-9]+]] ; DARWIN64: _func3: -; DARWIN64: ld r[[REG3:[0-9]+]], 72(r1) -; DARWIN64: ld r[[REG4:[0-9]+]], 56(r1) +; DARWIN64-DAG: ld r[[REG3:[0-9]+]], 72(r1) +; DARWIN64-DAG: ld r[[REG4:[0-9]+]], 56(r1) ; DARWIN64: cmpld {{(cr[0-9]+,)?}}r[[REG4]], r[[REG3]] -; DARWIN64: std r[[REG3]], -[[OFFSET1:[0-9]+]] -; DARWIN64: std r[[REG4]], -[[OFFSET2:[0-9]+]] -; DARWIN64: ld r3, -[[OFFSET2]] +; DARWIN64: std r[[REG4]], -[[OFFSET1:[0-9]+]] +; DARWIN64: std r[[REG3]], -[[OFFSET2:[0-9]+]] ; DARWIN64: ld r3, -[[OFFSET1]] +; DARWIN64: ld r3, -[[OFFSET2]] define i8* @func4(i64 %p1, i64 %p2, i64 %p3, i64 %p4, @@ -152,31 +152,31 @@ unequal: } ; CHECK-LABEL: func4: -; CHECK: ld [[REG3:[0-9]+]], 136(1) -; CHECK: ld [[REG2:[0-9]+]], 120(1) -; CHECK: cmpld {{([0-9]+,)?}}[[REG2]], [[REG3]] -; CHECK: std [[REG3]], -[[OFFSET2:[0-9]+]](1) +; CHECK-DAG: ld [[REG2:[0-9]+]], 120(1) +; CHECK-DAG: ld [[REG3:[0-9]+]], 136(1) +; CHECK-DAG: cmpld {{([0-9]+,)?}}[[REG2]], [[REG3]] ; CHECK: std [[REG2]], -[[OFFSET1:[0-9]+]](1) +; CHECK: std [[REG3]], -[[OFFSET2:[0-9]+]](1) ; CHECK: ld 3, -[[OFFSET1]](1) ; CHECK: ld 3, -[[OFFSET2]](1) ; DARWIN32: _func4: ; DARWIN32: lwz r[[REG4:[0-9]+]], 96(r1) ; DARWIN32: addi r[[REG1:[0-9]+]], r1, 100 -; DARWIN32: lwz r[[REG3:[0-9]+]], 108(r1) ; DARWIN32: mr r[[REG2:[0-9]+]], r[[REG4]] +; DARWIN32: lwz r[[REG3:[0-9]+]], 108(r1) ; DARWIN32: cmplw {{(cr[0-9]+,)?}}r[[REG4]], r[[REG3]] -; DARWIN32: stw r[[REG2]], -[[OFFSET1:[0-9]+]] -; DARWIN32: stw r[[REG3]], -[[OFFSET2:[0-9]+]] -; DARWIN32: lwz r[[REG1]], -[[OFFSET1]] -; DARWIN32: lwz r[[REG1]], -[[OFFSET2]] +; DARWIN32-DAG: stw r[[REG2]], -[[OFFSET1:[0-9]+]] +; DARWIN32-DAG: stw r[[REG3]], -[[OFFSET2:[0-9]+]] +; DARWIN32: lwz r3, -[[OFFSET1]] +; DARWIN32: lwz r3, -[[OFFSET2]] ; DARWIN64: _func4: ; DARWIN64: ld r[[REG2:[0-9]+]], 120(r1) -; DARWIN64: ld r[[REG3:[0-9]+]], 136(r1) -; DARWIN64: mr r[[REG4:[0-9]+]], r[[REG2]] +; DARWIN64-DAG: ld r[[REG3:[0-9]+]], 136(r1) +; DARWIN64-DAG: mr r[[REG4:[0-9]+]], r[[REG2]] ; DARWIN64: cmpld {{(cr[0-9]+,)?}}r[[REG2]], r[[REG3]] -; DARWIN64: std r[[REG4]], -[[OFFSET1:[0-9]+]] ; DARWIN64: std r[[REG3]], -[[OFFSET2:[0-9]+]] +; DARWIN64: std r[[REG4]], -[[OFFSET1:[0-9]+]] ; DARWIN64: ld r3, -[[OFFSET1]] ; DARWIN64: ld r3, -[[OFFSET2]] diff --git a/llvm/test/CodeGen/PowerPC/floatPSA.ll b/llvm/test/CodeGen/PowerPC/floatPSA.ll index ccda9d56a147c..73dea19adbd5e 100644 --- a/llvm/test/CodeGen/PowerPC/floatPSA.ll +++ b/llvm/test/CodeGen/PowerPC/floatPSA.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=powerpc64-unknown-linux-gnu -fast-isel=false < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -O2 -mtriple=powerpc64-unknown-linux-gnu -fast-isel=false < %s | FileCheck %s ; This verifies that single-precision floating point values that can't ; be passed in registers are stored in the rightmost word of the parameter diff --git a/llvm/test/CodeGen/PowerPC/ppc64-align-long-double.ll b/llvm/test/CodeGen/PowerPC/ppc64-align-long-double.ll index d59dc64dcf857..ba56dbaa83d0c 100644 --- a/llvm/test/CodeGen/PowerPC/ppc64-align-long-double.ll +++ b/llvm/test/CodeGen/PowerPC/ppc64-align-long-double.ll @@ -1,6 +1,6 @@ -; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -fast-isel=false -mattr=-vsx < %s | FileCheck %s -; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -fast-isel=false -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-VSX %s -; RUN: llc -verify-machineinstrs -mcpu=pwr9 -O0 -fast-isel=false -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-P9 %s +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O2 -fast-isel=false -mattr=-vsx < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O2 -fast-isel=false -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-VSX %s +; RUN: llc -verify-machineinstrs -mcpu=pwr9 -O2 -fast-isel=false -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-P9 %s ; Verify internal alignment of long double in a struct. The double ; argument comes in in GPR3; GPR4 is skipped; GPRs 5 and 6 contain @@ -44,9 +44,9 @@ entry: ; CHECK-VSX-DAG: std 3, 48(1) ; CHECK-VSX-DAG: std 5, -16(1) ; CHECK-VSX-DAG: std 6, -8(1) -; CHECK-VSX: addi 3, 1, -16 -; CHECK-VSX: lxsdx 1, 0, 3 -; CHECK-VSX: addi 3, 1, -8 +; CHECK-VSX-DAG: addi [[REG1:[0-9]+]], 1, -16 +; CHECK-VSX-DAG: addi 3, 1, -8 +; CHECK-VSX: lxsdx 1, 0, [[REG1]] ; CHECK-VSX: lxsdx 2, 0, 3 ; FIXME-VSX: addi 4, 1, 48 @@ -54,9 +54,9 @@ entry: ; FIXME-VSX: li 3, 24 ; FIXME-VSX: lxsdx 2, 4, 3 -; CHECK-P9: std 6, 72(1) -; CHECK-P9: std 5, 64(1) -; CHECK-P9: std 4, 56(1) -; CHECK-P9: std 3, 48(1) -; CHECK-P9: mtvsrd 1, 5 -; CHECK-P9: mtvsrd 2, 6 +; CHECK-P9-DAG: std 6, 72(1) +; CHECK-P9-DAG: std 5, 64(1) +; CHECK-P9-DAG: std 4, 56(1) +; CHECK-P9-DAG: std 3, 48(1) +; CHECK-P9-DAG: mtvsrd 1, 5 +; CHECK-P9-DAG: mtvsrd 2, 6 diff --git a/llvm/test/CodeGen/PowerPC/tls.ll b/llvm/test/CodeGen/PowerPC/tls.ll index 55df71b537617..63f498c1662c5 100644 --- a/llvm/test/CodeGen/PowerPC/tls.ll +++ b/llvm/test/CodeGen/PowerPC/tls.ll @@ -11,8 +11,8 @@ target triple = "powerpc64-unknown-linux-gnu" define i32 @localexec() nounwind { entry: ;OPT0: addis [[REG1:[0-9]+]], 13, a@tprel@ha -;OPT0-NEXT: li [[REG2:[0-9]+]], 42 ;OPT0-NEXT: addi [[REG1]], [[REG1]], a@tprel@l +;OPT0-NEXT: li [[REG2:[0-9]+]], 42 ;OPT0: stw [[REG2]], 0([[REG1]]) ;OPT1: addis [[REG1:[0-9]+]], 13, a@tprel@ha ;OPT1-NEXT: li [[REG2:[0-9]+]], 42