diff --git a/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp b/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp index 2ec7a57093f4ba..f738746ecd779b 100644 --- a/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp +++ b/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp @@ -206,6 +206,10 @@ static bool isREX(struct InternalInstruction *insn, uint8_t prefix) { return insn->mode == MODE_64BIT && prefix >= 0x40 && prefix <= 0x4f; } +static bool isREX2(struct InternalInstruction *insn, uint8_t prefix) { + return insn->mode == MODE_64BIT && prefix == 0xd5; +} + // Consumes all of an instruction's prefix bytes, and marks the // instruction as having them. Also sets the instruction's default operand, // address, and other relevant data sizes to report operands correctly. @@ -337,8 +341,7 @@ static int readPrefixes(struct InternalInstruction *insn) { return -1; } - if ((insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0) && - ((~byte1 & 0x8) == 0x8) && ((byte2 & 0x4) == 0x4)) { + if ((insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0)) { insn->vectorExtensionType = TYPE_EVEX; } else { --insn->readerCursor; // unconsume byte1 @@ -357,13 +360,19 @@ static int readPrefixes(struct InternalInstruction *insn) { return -1; } - // We simulate the REX prefix for simplicity's sake if (insn->mode == MODE_64BIT) { + // We simulate the REX prefix for simplicity's sake insn->rexPrefix = 0x40 | (wFromEVEX3of4(insn->vectorExtensionPrefix[2]) << 3) | (rFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 2) | (xFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 1) | (bFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 0); + + // We simulate the REX2 prefix for simplicity's sake + insn->rex2ExtensionPrefix[1] = + (r2FromEVEX2of4(insn->vectorExtensionPrefix[1]) << 6) | + (x2FromEVEX3of4(insn->vectorExtensionPrefix[2]) << 5) | + (b2FromEVEX2of4(insn->vectorExtensionPrefix[1]) << 4); } LLVM_DEBUG( @@ -474,6 +483,23 @@ static int readPrefixes(struct InternalInstruction *insn) { insn->vectorExtensionPrefix[1], insn->vectorExtensionPrefix[2])); } + } else if (isREX2(insn, byte)) { + uint8_t byte1; + if (peek(insn, byte1)) { + LLVM_DEBUG(dbgs() << "Couldn't read second byte of REX2"); + return -1; + } + insn->rex2ExtensionPrefix[0] = byte; + consume(insn, insn->rex2ExtensionPrefix[1]); + + // We simulate the REX prefix for simplicity's sake + insn->rexPrefix = 0x40 | (wFromREX2(insn->rex2ExtensionPrefix[1]) << 3) | + (rFromREX2(insn->rex2ExtensionPrefix[1]) << 2) | + (xFromREX2(insn->rex2ExtensionPrefix[1]) << 1) | + (bFromREX2(insn->rex2ExtensionPrefix[1]) << 0); + LLVM_DEBUG(dbgs() << format("Found REX2 prefix 0x%hhx 0x%hhx", + insn->rex2ExtensionPrefix[0], + insn->rex2ExtensionPrefix[1])); } else if (isREX(insn, byte)) { if (peek(insn, nextByte)) return -1; @@ -532,7 +558,8 @@ static int readSIB(struct InternalInstruction *insn) { if (consume(insn, insn->sib)) return -1; - index = indexFromSIB(insn->sib) | (xFromREX(insn->rexPrefix) << 3); + index = indexFromSIB(insn->sib) | (xFromREX(insn->rexPrefix) << 3) | + (x2FromREX2(insn->rex2ExtensionPrefix[1]) << 4); if (index == 0x4) { insn->sibIndex = SIB_INDEX_NONE; @@ -542,7 +569,8 @@ static int readSIB(struct InternalInstruction *insn) { insn->sibScale = 1 << scaleFromSIB(insn->sib); - base = baseFromSIB(insn->sib) | (bFromREX(insn->rexPrefix) << 3); + base = baseFromSIB(insn->sib) | (bFromREX(insn->rexPrefix) << 3) | + (b2FromREX2(insn->rex2ExtensionPrefix[1]) << 4); switch (base) { case 0x5: @@ -604,7 +632,7 @@ static int readDisplacement(struct InternalInstruction *insn) { // Consumes all addressing information (ModR/M byte, SIB byte, and displacement. static int readModRM(struct InternalInstruction *insn) { - uint8_t mod, rm, reg, evexrm; + uint8_t mod, rm, reg; LLVM_DEBUG(dbgs() << "readModRM()"); if (insn->consumedModRM) @@ -636,14 +664,13 @@ static int readModRM(struct InternalInstruction *insn) { break; } - reg |= rFromREX(insn->rexPrefix) << 3; - rm |= bFromREX(insn->rexPrefix) << 3; + reg |= (rFromREX(insn->rexPrefix) << 3) | + (r2FromREX2(insn->rex2ExtensionPrefix[1]) << 4); + rm |= (bFromREX(insn->rexPrefix) << 3) | + (b2FromREX2(insn->rex2ExtensionPrefix[1]) << 4); - evexrm = 0; - if (insn->vectorExtensionType == TYPE_EVEX && insn->mode == MODE_64BIT) { + if (insn->vectorExtensionType == TYPE_EVEX && insn->mode == MODE_64BIT) reg |= r2FromEVEX2of4(insn->vectorExtensionPrefix[1]) << 4; - evexrm = xFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 4; - } insn->reg = (Reg)(insn->regBase + reg); @@ -731,7 +758,7 @@ static int readModRM(struct InternalInstruction *insn) { break; case 0x3: insn->eaDisplacement = EA_DISP_NONE; - insn->eaBase = (EABase)(insn->eaRegBase + rm + evexrm); + insn->eaBase = (EABase)(insn->eaRegBase + rm); break; } break; @@ -741,7 +768,7 @@ static int readModRM(struct InternalInstruction *insn) { return 0; } -#define GENERIC_FIXUP_FUNC(name, base, prefix, mask) \ +#define GENERIC_FIXUP_FUNC(name, base, prefix) \ static uint16_t name(struct InternalInstruction *insn, OperandType type, \ uint8_t index, uint8_t *valid) { \ *valid = 1; \ @@ -753,28 +780,15 @@ static int readModRM(struct InternalInstruction *insn) { case TYPE_Rv: \ return base + index; \ case TYPE_R8: \ - index &= mask; \ - if (index > 0xf) \ - *valid = 0; \ - if (insn->rexPrefix && index >= 4 && index <= 7) { \ + if (insn->rexPrefix && index >= 4 && index <= 7) \ return prefix##_SPL + (index - 4); \ - } else { \ + else \ return prefix##_AL + index; \ - } \ case TYPE_R16: \ - index &= mask; \ - if (index > 0xf) \ - *valid = 0; \ return prefix##_AX + index; \ case TYPE_R32: \ - index &= mask; \ - if (index > 0xf) \ - *valid = 0; \ return prefix##_EAX + index; \ case TYPE_R64: \ - index &= mask; \ - if (index > 0xf) \ - *valid = 0; \ return prefix##_RAX + index; \ case TYPE_ZMM: \ return prefix##_ZMM0 + index; \ @@ -824,8 +838,8 @@ static int readModRM(struct InternalInstruction *insn) { // @param valid - The address of a uint8_t. The target is set to 1 if the // field is valid for the register class; 0 if not. // @return - The proper value. -GENERIC_FIXUP_FUNC(fixupRegValue, insn->regBase, MODRM_REG, 0x1f) -GENERIC_FIXUP_FUNC(fixupRMValue, insn->eaRegBase, EA_REG, 0xf) +GENERIC_FIXUP_FUNC(fixupRegValue, insn->regBase, MODRM_REG) +GENERIC_FIXUP_FUNC(fixupRMValue, insn->eaRegBase, EA_REG) // Consult an operand specifier to determine which of the fixup*Value functions // to use in correcting readModRM()'ss interpretation. @@ -855,8 +869,31 @@ static int fixupReg(struct InternalInstruction *insn, if (!valid) return -1; break; - case ENCODING_SIB: CASE_ENCODING_RM: + if (insn->vectorExtensionType == TYPE_EVEX && insn->mode == MODE_64BIT && + modFromModRM(insn->modRM) == 3) { + // EVEX_X can extend the register id to 32 for a non-GPR register that is + // encoded in RM. + // mode : MODE_64_BIT + // Only 8 vector registers are available in 32 bit mode + // mod : 3 + // RM encodes a register + switch (op->type) { + case TYPE_Rv: + case TYPE_R8: + case TYPE_R16: + case TYPE_R32: + case TYPE_R64: + break; + default: + insn->eaBase = + (EABase)(insn->eaBase + + (xFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 4)); + break; + } + } + [[fallthrough]]; + case ENCODING_SIB: if (insn->eaBase >= insn->eaRegBase) { insn->eaBase = (EABase)fixupRMValue( insn, (OperandType)op->type, insn->eaBase - insn->eaRegBase, &valid); @@ -945,6 +982,10 @@ static bool readOpcode(struct InternalInstruction *insn) { insn->opcodeType = XOPA_MAP; return consume(insn, insn->opcode); } + } else if (mFromREX2(insn->rex2ExtensionPrefix[1])) { + // m bit indicates opcode map 1 + insn->opcodeType = TWOBYTE; + return consume(insn, insn->opcode); } if (consume(insn, current)) @@ -1388,10 +1429,16 @@ static int readOpcodeRegister(struct InternalInstruction *insn, uint8_t size) { if (size == 0) size = insn->registerSize; + auto setOpcodeRegister = [&](unsigned base) { + insn->opcodeRegister = + (Reg)(base + ((bFromREX(insn->rexPrefix) << 3) | + (b2FromREX2(insn->rex2ExtensionPrefix[1]) << 4) | + (insn->opcode & 7))); + }; + switch (size) { case 1: - insn->opcodeRegister = (Reg)( - MODRM_REG_AL + ((bFromREX(insn->rexPrefix) << 3) | (insn->opcode & 7))); + setOpcodeRegister(MODRM_REG_AL); if (insn->rexPrefix && insn->opcodeRegister >= MODRM_REG_AL + 0x4 && insn->opcodeRegister < MODRM_REG_AL + 0x8) { insn->opcodeRegister = @@ -1400,18 +1447,13 @@ static int readOpcodeRegister(struct InternalInstruction *insn, uint8_t size) { break; case 2: - insn->opcodeRegister = (Reg)( - MODRM_REG_AX + ((bFromREX(insn->rexPrefix) << 3) | (insn->opcode & 7))); + setOpcodeRegister(MODRM_REG_AX); break; case 4: - insn->opcodeRegister = - (Reg)(MODRM_REG_EAX + - ((bFromREX(insn->rexPrefix) << 3) | (insn->opcode & 7))); + setOpcodeRegister(MODRM_REG_EAX); break; case 8: - insn->opcodeRegister = - (Reg)(MODRM_REG_RAX + - ((bFromREX(insn->rexPrefix) << 3) | (insn->opcode & 7))); + setOpcodeRegister(MODRM_REG_RAX); break; } diff --git a/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h b/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h index 074f14dbeac581..d75f049a6b8d6f 100644 --- a/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h +++ b/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h @@ -34,6 +34,7 @@ namespace X86Disassembler { #define threeBitsFromOffset0(val) ((val) & 0x7) #define threeBitsFromOffset3(val) (((val) >> 3) & 0x7) #define fiveBitsFromOffset0(val) ((val) & 0x1f) +#define invertedBitFromOffset2(val) (((~(val)) >> 2) & 0x1) #define invertedBitFromOffset3(val) (((~(val)) >> 3) & 0x1) #define invertedBitFromOffset4(val) (((~(val)) >> 4) & 0x1) #define invertedBitFromOffset5(val) (((~(val)) >> 5) & 0x1) @@ -53,6 +54,15 @@ namespace X86Disassembler { #define rFromREX(rex) bitFromOffset2(rex) #define xFromREX(rex) bitFromOffset1(rex) #define bFromREX(rex) bitFromOffset0(rex) +// REX2 +#define mFromREX2(rex2) bitFromOffset7(rex2) +#define r2FromREX2(rex2) bitFromOffset6(rex2) +#define x2FromREX2(rex2) bitFromOffset5(rex2) +#define b2FromREX2(rex2) bitFromOffset4(rex2) +#define wFromREX2(rex2) bitFromOffset3(rex2) +#define rFromREX2(rex2) bitFromOffset2(rex2) +#define xFromREX2(rex2) bitFromOffset1(rex2) +#define bFromREX2(rex2) bitFromOffset0(rex2) // XOP #define rFromXOP2of3(xop) invertedBitFromOffset7(xop) #define xFromXOP2of3(xop) invertedBitFromOffset6(xop) @@ -81,9 +91,11 @@ namespace X86Disassembler { #define xFromEVEX2of4(evex) invertedBitFromOffset6(evex) #define bFromEVEX2of4(evex) invertedBitFromOffset5(evex) #define r2FromEVEX2of4(evex) invertedBitFromOffset4(evex) +#define b2FromEVEX2of4(evex) bitFromOffset3(evex) #define mmmFromEVEX2of4(evex) threeBitsFromOffset0(evex) #define wFromEVEX3of4(evex) bitFromOffset7(evex) #define vvvvFromEVEX3of4(evex) invertedFourBitsFromOffset3(evex) +#define x2FromEVEX3of4(evex) invertedBitFromOffset2(evex) #define ppFromEVEX3of4(evex) twoBitsFromOffset0(evex) #define zFromEVEX4of4(evex) bitFromOffset7(evex) #define l2FromEVEX4of4(evex) bitFromOffset6(evex) @@ -93,135 +105,247 @@ namespace X86Disassembler { #define aaaFromEVEX4of4(evex) threeBitsFromOffset0(evex) // These enums represent Intel registers for use by the decoder. -#define REGS_8BIT \ - ENTRY(AL) \ - ENTRY(CL) \ - ENTRY(DL) \ - ENTRY(BL) \ - ENTRY(AH) \ - ENTRY(CH) \ - ENTRY(DH) \ - ENTRY(BH) \ - ENTRY(R8B) \ - ENTRY(R9B) \ - ENTRY(R10B) \ - ENTRY(R11B) \ - ENTRY(R12B) \ - ENTRY(R13B) \ - ENTRY(R14B) \ - ENTRY(R15B) \ - ENTRY(SPL) \ - ENTRY(BPL) \ - ENTRY(SIL) \ +#define REGS_8BIT \ + ENTRY(AL) \ + ENTRY(CL) \ + ENTRY(DL) \ + ENTRY(BL) \ + ENTRY(AH) \ + ENTRY(CH) \ + ENTRY(DH) \ + ENTRY(BH) \ + ENTRY(R8B) \ + ENTRY(R9B) \ + ENTRY(R10B) \ + ENTRY(R11B) \ + ENTRY(R12B) \ + ENTRY(R13B) \ + ENTRY(R14B) \ + ENTRY(R15B) \ + ENTRY(R16B) \ + ENTRY(R17B) \ + ENTRY(R18B) \ + ENTRY(R19B) \ + ENTRY(R20B) \ + ENTRY(R21B) \ + ENTRY(R22B) \ + ENTRY(R23B) \ + ENTRY(R24B) \ + ENTRY(R25B) \ + ENTRY(R26B) \ + ENTRY(R27B) \ + ENTRY(R28B) \ + ENTRY(R29B) \ + ENTRY(R30B) \ + ENTRY(R31B) \ + ENTRY(SPL) \ + ENTRY(BPL) \ + ENTRY(SIL) \ ENTRY(DIL) -#define EA_BASES_16BIT \ - ENTRY(BX_SI) \ - ENTRY(BX_DI) \ - ENTRY(BP_SI) \ - ENTRY(BP_DI) \ - ENTRY(SI) \ - ENTRY(DI) \ - ENTRY(BP) \ - ENTRY(BX) \ - ENTRY(R8W) \ - ENTRY(R9W) \ - ENTRY(R10W) \ - ENTRY(R11W) \ - ENTRY(R12W) \ - ENTRY(R13W) \ - ENTRY(R14W) \ - ENTRY(R15W) - -#define REGS_16BIT \ - ENTRY(AX) \ - ENTRY(CX) \ - ENTRY(DX) \ - ENTRY(BX) \ - ENTRY(SP) \ - ENTRY(BP) \ - ENTRY(SI) \ - ENTRY(DI) \ - ENTRY(R8W) \ - ENTRY(R9W) \ - ENTRY(R10W) \ - ENTRY(R11W) \ - ENTRY(R12W) \ - ENTRY(R13W) \ - ENTRY(R14W) \ - ENTRY(R15W) - -#define EA_BASES_32BIT \ - ENTRY(EAX) \ - ENTRY(ECX) \ - ENTRY(EDX) \ - ENTRY(EBX) \ - ENTRY(sib) \ - ENTRY(EBP) \ - ENTRY(ESI) \ - ENTRY(EDI) \ - ENTRY(R8D) \ - ENTRY(R9D) \ - ENTRY(R10D) \ - ENTRY(R11D) \ - ENTRY(R12D) \ - ENTRY(R13D) \ - ENTRY(R14D) \ - ENTRY(R15D) - -#define REGS_32BIT \ - ENTRY(EAX) \ - ENTRY(ECX) \ - ENTRY(EDX) \ - ENTRY(EBX) \ - ENTRY(ESP) \ - ENTRY(EBP) \ - ENTRY(ESI) \ - ENTRY(EDI) \ - ENTRY(R8D) \ - ENTRY(R9D) \ - ENTRY(R10D) \ - ENTRY(R11D) \ - ENTRY(R12D) \ - ENTRY(R13D) \ - ENTRY(R14D) \ - ENTRY(R15D) - -#define EA_BASES_64BIT \ - ENTRY(RAX) \ - ENTRY(RCX) \ - ENTRY(RDX) \ - ENTRY(RBX) \ - ENTRY(sib64) \ - ENTRY(RBP) \ - ENTRY(RSI) \ - ENTRY(RDI) \ - ENTRY(R8) \ - ENTRY(R9) \ - ENTRY(R10) \ - ENTRY(R11) \ - ENTRY(R12) \ - ENTRY(R13) \ - ENTRY(R14) \ - ENTRY(R15) - -#define REGS_64BIT \ - ENTRY(RAX) \ - ENTRY(RCX) \ - ENTRY(RDX) \ - ENTRY(RBX) \ - ENTRY(RSP) \ - ENTRY(RBP) \ - ENTRY(RSI) \ - ENTRY(RDI) \ - ENTRY(R8) \ - ENTRY(R9) \ - ENTRY(R10) \ - ENTRY(R11) \ - ENTRY(R12) \ - ENTRY(R13) \ - ENTRY(R14) \ - ENTRY(R15) +#define EA_BASES_16BIT \ + ENTRY(BX_SI) \ + ENTRY(BX_DI) \ + ENTRY(BP_SI) \ + ENTRY(BP_DI) \ + ENTRY(SI) \ + ENTRY(DI) \ + ENTRY(BP) \ + ENTRY(BX) \ + ENTRY(R8W) \ + ENTRY(R9W) \ + ENTRY(R10W) \ + ENTRY(R11W) \ + ENTRY(R12W) \ + ENTRY(R13W) \ + ENTRY(R14W) \ + ENTRY(R15W) \ + ENTRY(R16W) \ + ENTRY(R17W) \ + ENTRY(R18W) \ + ENTRY(R19W) \ + ENTRY(R20W) \ + ENTRY(R21W) \ + ENTRY(R22W) \ + ENTRY(R23W) \ + ENTRY(R24W) \ + ENTRY(R25W) \ + ENTRY(R26W) \ + ENTRY(R27W) \ + ENTRY(R28W) \ + ENTRY(R29W) \ + ENTRY(R30W) \ + ENTRY(R31W) + +#define REGS_16BIT \ + ENTRY(AX) \ + ENTRY(CX) \ + ENTRY(DX) \ + ENTRY(BX) \ + ENTRY(SP) \ + ENTRY(BP) \ + ENTRY(SI) \ + ENTRY(DI) \ + ENTRY(R8W) \ + ENTRY(R9W) \ + ENTRY(R10W) \ + ENTRY(R11W) \ + ENTRY(R12W) \ + ENTRY(R13W) \ + ENTRY(R14W) \ + ENTRY(R15W) \ + ENTRY(R16W) \ + ENTRY(R17W) \ + ENTRY(R18W) \ + ENTRY(R19W) \ + ENTRY(R20W) \ + ENTRY(R21W) \ + ENTRY(R22W) \ + ENTRY(R23W) \ + ENTRY(R24W) \ + ENTRY(R25W) \ + ENTRY(R26W) \ + ENTRY(R27W) \ + ENTRY(R28W) \ + ENTRY(R29W) \ + ENTRY(R30W) \ + ENTRY(R31W) + +#define EA_BASES_32BIT \ + ENTRY(EAX) \ + ENTRY(ECX) \ + ENTRY(EDX) \ + ENTRY(EBX) \ + ENTRY(sib) \ + ENTRY(EBP) \ + ENTRY(ESI) \ + ENTRY(EDI) \ + ENTRY(R8D) \ + ENTRY(R9D) \ + ENTRY(R10D) \ + ENTRY(R11D) \ + ENTRY(R12D) \ + ENTRY(R13D) \ + ENTRY(R14D) \ + ENTRY(R15D) \ + ENTRY(R16D) \ + ENTRY(R17D) \ + ENTRY(R18D) \ + ENTRY(R19D) \ + ENTRY(R20D) \ + ENTRY(R21D) \ + ENTRY(R22D) \ + ENTRY(R23D) \ + ENTRY(R24D) \ + ENTRY(R25D) \ + ENTRY(R26D) \ + ENTRY(R27D) \ + ENTRY(R28D) \ + ENTRY(R29D) \ + ENTRY(R30D) \ + ENTRY(R31D) + +#define REGS_32BIT \ + ENTRY(EAX) \ + ENTRY(ECX) \ + ENTRY(EDX) \ + ENTRY(EBX) \ + ENTRY(ESP) \ + ENTRY(EBP) \ + ENTRY(ESI) \ + ENTRY(EDI) \ + ENTRY(R8D) \ + ENTRY(R9D) \ + ENTRY(R10D) \ + ENTRY(R11D) \ + ENTRY(R12D) \ + ENTRY(R13D) \ + ENTRY(R14D) \ + ENTRY(R15D) \ + ENTRY(R16D) \ + ENTRY(R17D) \ + ENTRY(R18D) \ + ENTRY(R19D) \ + ENTRY(R20D) \ + ENTRY(R21D) \ + ENTRY(R22D) \ + ENTRY(R23D) \ + ENTRY(R24D) \ + ENTRY(R25D) \ + ENTRY(R26D) \ + ENTRY(R27D) \ + ENTRY(R28D) \ + ENTRY(R29D) \ + ENTRY(R30D) \ + ENTRY(R31D) + +#define EA_BASES_64BIT \ + ENTRY(RAX) \ + ENTRY(RCX) \ + ENTRY(RDX) \ + ENTRY(RBX) \ + ENTRY(sib64) \ + ENTRY(RBP) \ + ENTRY(RSI) \ + ENTRY(RDI) \ + ENTRY(R8) \ + ENTRY(R9) \ + ENTRY(R10) \ + ENTRY(R11) \ + ENTRY(R12) \ + ENTRY(R13) \ + ENTRY(R14) \ + ENTRY(R15) \ + ENTRY(R16) \ + ENTRY(R17) \ + ENTRY(R18) \ + ENTRY(R19) \ + ENTRY(R20) \ + ENTRY(R21) \ + ENTRY(R22) \ + ENTRY(R23) \ + ENTRY(R24) \ + ENTRY(R25) \ + ENTRY(R26) \ + ENTRY(R27) \ + ENTRY(R28) \ + ENTRY(R29) \ + ENTRY(R30) \ + ENTRY(R31) + +#define REGS_64BIT \ + ENTRY(RAX) \ + ENTRY(RCX) \ + ENTRY(RDX) \ + ENTRY(RBX) \ + ENTRY(RSP) \ + ENTRY(RBP) \ + ENTRY(RSI) \ + ENTRY(RDI) \ + ENTRY(R8) \ + ENTRY(R9) \ + ENTRY(R10) \ + ENTRY(R11) \ + ENTRY(R12) \ + ENTRY(R13) \ + ENTRY(R14) \ + ENTRY(R15) \ + ENTRY(R16) \ + ENTRY(R17) \ + ENTRY(R18) \ + ENTRY(R19) \ + ENTRY(R20) \ + ENTRY(R21) \ + ENTRY(R22) \ + ENTRY(R23) \ + ENTRY(R24) \ + ENTRY(R25) \ + ENTRY(R26) \ + ENTRY(R27) \ + ENTRY(R28) \ + ENTRY(R29) \ + ENTRY(R30) \ + ENTRY(R31) #define REGS_MMX \ ENTRY(MM0) \ @@ -561,6 +685,8 @@ struct InternalInstruction { uint8_t vectorExtensionPrefix[4]; // The type of the vector extension prefix VectorExtensionType vectorExtensionType; + // The value of the REX2 prefix, if present + uint8_t rex2ExtensionPrefix[2]; // The value of the REX prefix, if present uint8_t rexPrefix; // The segment override type diff --git a/llvm/test/MC/Disassembler/X86/apx/evex-format.txt b/llvm/test/MC/Disassembler/X86/apx/evex-format.txt new file mode 100644 index 00000000000000..ee2c2c5bdf909c --- /dev/null +++ b/llvm/test/MC/Disassembler/X86/apx/evex-format.txt @@ -0,0 +1,69 @@ +## NOTE: This file needs to be updated after promoted instruction is supported +# RUN: llvm-mc -triple x86_64 -disassemble %s | FileCheck %s --check-prefix=ATT +# RUN: llvm-mc -triple x86_64 -disassemble -output-asm-variant=1 %s | FileCheck %s --check-prefix=INTEL + +## MRMDestMem + +# ATT: vextractf32x4 $1, %zmm0, (%r16,%r17) +# INTEL: vextractf32x4 xmmword ptr [r16 + r17], zmm0, 1 +0x62,0xfb,0x79,0x48,0x19,0x04,0x08,0x01 + +## MRMSrcMem + +# ATT: vbroadcasti32x4 (%r16,%r17), %zmm0 +# INTEL: vbroadcasti32x4 zmm0, xmmword ptr [r16 + r17] +0x62,0xfa,0x79,0x48,0x5a,0x04,0x08 + +## MRM0m + +# ATT: vprorq $0, (%r16,%r17), %zmm0 +# INTEL: vprorq zmm0, zmmword ptr [r16 + r17], 0 +0x62,0xf9,0xf9,0x48,0x72,0x04,0x08,0x00 + +## MRM1m + +# ATT: vprolq $0, (%r16,%r17), %zmm0 +# INTEL: vprolq zmm0, zmmword ptr [r16 + r17], 0 +0x62,0xf9,0xf9,0x48,0x72,0x0c,0x08,0x00 + +## MRM2m + +# ATT: vpsrlq $0, (%r16,%r17), %zmm0 +# INTEL: vpsrlq zmm0, zmmword ptr [r16 + r17], 0 +0x62,0xf9,0xf9,0x48,0x73,0x14,0x08,0x00 + +## MRM3m + +# ATT: vpsrldq $0, (%r16,%r17), %zmm0 +# INTEL: vpsrldq zmm0, zmmword ptr [r16 + r17], 0 +0x62,0xf9,0x79,0x48,0x73,0x1c,0x08,0x00 + +## MRM4m + +# ATT: vpsraq $0, (%r16,%r17), %zmm0 +# INTEL: vpsraq zmm0, zmmword ptr [r16 + r17], 0 +0x62,0xf9,0xf9,0x48,0x72,0x24,0x08,0x00 + +## MRM5m + +# ATT: vscatterpf0dps (%r16,%zmm0) {%k1} +# INTEL: vscatterpf0dps {k1}, zmmword ptr [r16 + zmm0] +0x62,0xfa,0x7d,0x49,0xc6,0x2c,0x00 + +## MRM6m + +# ATT: vpsllq $0, (%r16,%r17), %zmm0 +# INTEL: vpsllq zmm0, zmmword ptr [r16 + r17], 0 +0x62,0xf9,0xf9,0x48,0x73,0x34,0x08,0x00 + +## MRM7m + +# ATT: vpslldq $0, (%r16,%r17), %zmm0 +# INTEL: vpslldq zmm0, zmmword ptr [r16 + r17], 0 +0x62,0xf9,0x79,0x48,0x73,0x3c,0x08,0x00 + +## MRMDestReg + +# ATT: vextractps $1, %xmm16, %r16d +# INTEL: vextractps r16d, xmm16, 1 +0x62,0xeb,0x7d,0x08,0x17,0xc0,0x01 diff --git a/llvm/test/MC/Disassembler/X86/apx/rex2-bit.txt b/llvm/test/MC/Disassembler/X86/apx/rex2-bit.txt new file mode 100644 index 00000000000000..d7fafbed3070db --- /dev/null +++ b/llvm/test/MC/Disassembler/X86/apx/rex2-bit.txt @@ -0,0 +1,238 @@ +# RUN: llvm-mc -triple x86_64 -disassemble %s | FileCheck %s --check-prefix=ATT +# RUN: llvm-mc -triple x86_64 -disassemble -output-asm-variant=1 %s | FileCheck %s --check-prefix=INTEL + +## R bit + +# ATT: leal (%rax), %r16d +# INTEL: lea r16d, [rax] +0xd5,0x40,0x8d,0x00 + +# ATT: leal (%rax), %r17d +# INTEL: lea r17d, [rax] +0xd5,0x40,0x8d,0x08 + +# ATT: leal (%rax), %r18d +# INTEL: lea r18d, [rax] +0xd5,0x40,0x8d,0x10 + +# ATT: leal (%rax), %r19d +# INTEL: lea r19d, [rax] +0xd5,0x40,0x8d,0x18 + +# ATT: leal (%rax), %r20d +# INTEL: lea r20d, [rax] +0xd5,0x40,0x8d,0x20 + +# ATT: leal (%rax), %r21d +# INTEL: lea r21d, [rax] +0xd5,0x40,0x8d,0x28 + +# ATT: leal (%rax), %r22d +# INTEL: lea r22d, [rax] +0xd5,0x40,0x8d,0x30 + +# ATT: leal (%rax), %r23d +# INTEL: lea r23d, [rax] +0xd5,0x40,0x8d,0x38 + +# ATT: leal (%rax), %r24d +# INTEL: lea r24d, [rax] +0xd5,0x44,0x8d,0x00 + +# ATT: leal (%rax), %r25d +# INTEL: lea r25d, [rax] +0xd5,0x44,0x8d,0x08 + +# ATT: leal (%rax), %r26d +# INTEL: lea r26d, [rax] +0xd5,0x44,0x8d,0x10 + +# ATT: leal (%rax), %r27d +# INTEL: lea r27d, [rax] +0xd5,0x44,0x8d,0x18 + +# ATT: leal (%rax), %r28d +# INTEL: lea r28d, [rax] +0xd5,0x44,0x8d,0x20 + +# ATT: leal (%rax), %r29d +# INTEL: lea r29d, [rax] +0xd5,0x44,0x8d,0x28 + +# ATT: leal (%rax), %r30d +# INTEL: lea r30d, [rax] +0xd5,0x44,0x8d,0x30 + +# ATT: leal (%rax), %r31d +# INTEL: lea r31d, [rax] +0xd5,0x44,0x8d,0x38 + +## X bit + +# ATT: leal (,%r16), %eax +# INTEL: lea eax, [1*r16] +0xd5,0x20,0x8d,0x04,0x05,0x00,0x00,0x00,0x00 + +# ATT: leal (,%r17), %eax +# INTEL: lea eax, [1*r17] +0xd5,0x20,0x8d,0x04,0x0d,0x00,0x00,0x00,0x00 + +# ATT: leal (,%r18), %eax +# INTEL: lea eax, [1*r18] +0xd5,0x20,0x8d,0x04,0x15,0x00,0x00,0x00,0x00 + +# ATT: leal (,%r19), %eax +# INTEL: lea eax, [1*r19] +0xd5,0x20,0x8d,0x04,0x1d,0x00,0x00,0x00,0x00 + +# ATT: leal (,%r20), %eax +# INTEL: lea eax, [1*r20] +0xd5,0x20,0x8d,0x04,0x25,0x00,0x00,0x00,0x00 + +# ATT: leal (,%r21), %eax +# INTEL: lea eax, [1*r21] +0xd5,0x20,0x8d,0x04,0x2d,0x00,0x00,0x00,0x00 + +# ATT: leal (,%r22), %eax +# INTEL: lea eax, [1*r22] +0xd5,0x20,0x8d,0x04,0x35,0x00,0x00,0x00,0x00 + +# ATT: leal (,%r23), %eax +# INTEL: lea eax, [1*r23] +0xd5,0x20,0x8d,0x04,0x3d,0x00,0x00,0x00,0x00 + +# ATT: leal (,%r24), %eax +# INTEL: lea eax, [1*r24] +0xd5,0x22,0x8d,0x04,0x05,0x00,0x00,0x00,0x00 + +# ATT: leal (,%r25), %eax +# INTEL: lea eax, [1*r25] +0xd5,0x22,0x8d,0x04,0x0d,0x00,0x00,0x00,0x00 + +# ATT: leal (,%r26), %eax +# INTEL: lea eax, [1*r26] +0xd5,0x22,0x8d,0x04,0x15,0x00,0x00,0x00,0x00 + +# ATT: leal (,%r27), %eax +# INTEL: lea eax, [1*r27] +0xd5,0x22,0x8d,0x04,0x1d,0x00,0x00,0x00,0x00 + +# ATT: leal (,%r28), %eax +# INTEL: lea eax, [1*r28] +0xd5,0x22,0x8d,0x04,0x25,0x00,0x00,0x00,0x00 + +# ATT: leal (,%r29), %eax +# INTEL: lea eax, [1*r29] +0xd5,0x22,0x8d,0x04,0x2d,0x00,0x00,0x00,0x00 + +# ATT: leal (,%r30), %eax +# INTEL: lea eax, [1*r30] +0xd5,0x22,0x8d,0x04,0x35,0x00,0x00,0x00,0x00 + +# ATT: leal (,%r31), %eax +# INTEL: lea eax, [1*r31] +0xd5,0x22,0x8d,0x04,0x3d,0x00,0x00,0x00,0x00 + +## B bit + +# ATT: leal (%r16), %eax +# INTEL: lea eax, [r16] +0xd5,0x10,0x8d,0x00 + +# ATT: leal (%r17), %eax +# INTEL: lea eax, [r17] +0xd5,0x10,0x8d,0x01 + +# ATT: leal (%r18), %eax +# INTEL: lea eax, [r18] +0xd5,0x10,0x8d,0x02 + +# ATT: leal (%r19), %eax +# INTEL: lea eax, [r19] +0xd5,0x10,0x8d,0x03 + +# ATT: leal (%r20,%riz), %eax +# INTEL: lea eax, [r20 + riz] +0xd5,0x10,0x8d,0x04,0x24 + +# ATT: leal (%r21), %eax +# INTEL: lea eax, [r21] +0xd5,0x10,0x8d,0x45,0x00 + +# ATT: leal (%r22), %eax +# INTEL: lea eax, [r22] +0xd5,0x10,0x8d,0x06 + +# ATT: leal (%r23), %eax +# INTEL: lea eax, [r23] +0xd5,0x10,0x8d,0x07 + +# ATT: leal (%r24), %eax +# INTEL: lea eax, [r24] +0xd5,0x11,0x8d,0x00 + +# ATT: leal (%r25), %eax +# INTEL: lea eax, [r25] +0xd5,0x11,0x8d,0x01 + +# ATT: leal (%r26), %eax +# INTEL: lea eax, [r26] +0xd5,0x11,0x8d,0x02 + +# ATT: leal (%r27), %eax +# INTEL: lea eax, [r27] +0xd5,0x11,0x8d,0x03 + +# ATT: leal (%r28,%riz), %eax +# INTEL: lea eax, [r28 + riz] +0xd5,0x11,0x8d,0x04,0x24 + +# ATT: leal (%r29), %eax +# INTEL: lea eax, [r29] +0xd5,0x11,0x8d,0x45,0x00 + +# ATT: leal (%r30), %eax +# INTEL: lea eax, [r30] +0xd5,0x11,0x8d,0x06 + +# ATT: leal (%r31), %eax +# INTEL: lea eax, [r31] +0xd5,0x11,0x8d,0x07 + +## SIB + +# ATT: leal 1(%r20,%riz), %eax +# INTEL: lea eax, [r20 + riz + 1] +0xd5,0x10,0x8d,0x44,0x24,0x01 + +# ATT: leal 1(%r28,%riz), %eax +# INTEL: lea eax, [r28 + riz + 1] +0xd5,0x11,0x8d,0x44,0x24,0x01 + +# ATT: leal 129(%r20,%riz), %eax +# INTEL: lea eax, [r20 + riz + 129] +0xd5,0x10,0x8d,0x84,0x24,0x81,0x00,0x00,0x00 + +# ATT: leal 129(%r28,%riz), %eax +# INTEL: lea eax, [r28 + riz + 129] +0xd5,0x11,0x8d,0x84,0x24,0x81,0x00,0x00,0x00 + +## W bit + +# ATT: leaq (%rax), %r16 +# INTEL: lea r16, [rax] +0xd5,0x48,0x8d,0x00 + +# ATT: leaq (%r16), %rax +# INTEL: lea rax, [r16] +0xd5,0x18,0x8d,0x00 + +# ATT: leaq (,%r16), %rax +# INTEL: lea rax, [1*r16] +0xd5,0x28,0x8d,0x04,0x05,0x00,0x00,0x00,0x00 + +## M bit + +# ATT: imull %eax, %r16d +# INTEL: imul r16d, eax +0xd5,0xc0,0xaf,0xc0 diff --git a/llvm/test/MC/Disassembler/X86/apx/rex2-format.txt b/llvm/test/MC/Disassembler/X86/apx/rex2-format.txt new file mode 100644 index 00000000000000..1ac057c62a87c9 --- /dev/null +++ b/llvm/test/MC/Disassembler/X86/apx/rex2-format.txt @@ -0,0 +1,344 @@ +# RUN: llvm-mc -triple x86_64 -disassemble %s | FileCheck %s --check-prefix=ATT +# RUN: llvm-mc -triple x86_64 -disassemble -output-asm-variant=1 %s | FileCheck %s --check-prefix=INTEL + +## AddRegFrm + +# ATT: movl $1, %r16d +# INTEL: mov r16d, 1 +0xd5,0x10,0xb8,0x01,0x00,0x00,0x00 + +## MRMSrcReg + +# ATT: movslq %r16d, %rax +# INTEL: movsxd rax, r16d +0xd5,0x18,0x63,0xc0 + +# ATT: movslq %eax, %r16 +# INTEL: movsxd r16, eax +0xd5,0x48,0x63,0xc0 + +# ATT: movslq %r16d, %r17 +# INTEL: movsxd r17, r16d +0xd5,0x58,0x63,0xc8 + +## MRMSrcRegCC + +# ATT: cmovll %r16d, %eax +# INTEL: cmovl eax, r16d +0xd5,0x90,0x4c,0xc0 + +# ATT: cmovll %eax, %r16d +# INTEL: cmovl r16d, eax +0xd5,0xc0,0x4c,0xc0 + +# ATT: cmovll %r16d, %r17d +# INTEL: cmovl r17d, r16d +0xd5,0xd0,0x4c,0xc8 + +## MRMSrcMem + +# ATT: imull (%r16,%rax), %ebx +# INTEL: imul ebx, dword ptr [r16 + rax] +0xd5,0x90,0xaf,0x1c,0x00 + +# ATT: imull (%rax,%r16), %ebx +# INTEL: imul ebx, dword ptr [rax + r16] +0xd5,0xa0,0xaf,0x1c,0x00 + +# ATT: imull (%rax,%rbx), %r16d +# INTEL: imul r16d, dword ptr [rax + rbx] +0xd5,0xc0,0xaf,0x04,0x18 + +# ATT: imull (%r16,%r17), %eax +# INTEL: imul eax, dword ptr [r16 + r17] +0xd5,0xb0,0xaf,0x04,0x08 + +# ATT: imull (%rax,%r16), %r17d +# INTEL: imul r17d, dword ptr [rax + r16] +0xd5,0xe0,0xaf,0x0c,0x00 + +# ATT: imull (%r16,%rax), %r17d +# INTEL: imul r17d, dword ptr [r16 + rax] +0xd5,0xd0,0xaf,0x0c,0x00 + +# ATT: imull (%r16,%r17), %r18d +# INTEL: imul r18d, dword ptr [r16 + r17] +0xd5,0xf0,0xaf,0x14,0x08 + +## MRMSrcMemCC + +# ATT: cmovll (%r16,%rax), %ebx +# INTEL: cmovl ebx, dword ptr [r16 + rax] +0xd5,0x90,0x4c,0x1c,0x00 + +# ATT: cmovll (%rax,%r16), %ebx +# INTEL: cmovl ebx, dword ptr [rax + r16] +0xd5,0xa0,0x4c,0x1c,0x00 + +# ATT: cmovll (%rax,%rbx), %r16d +# INTEL: cmovl r16d, dword ptr [rax + rbx] +0xd5,0xc0,0x4c,0x04,0x18 + +# ATT: cmovll (%r16,%r17), %eax +# INTEL: cmovl eax, dword ptr [r16 + r17] +0xd5,0xb0,0x4c,0x04,0x08 + +# ATT: cmovll (%rax,%r16), %r17d +# INTEL: cmovl r17d, dword ptr [rax + r16] +0xd5,0xe0,0x4c,0x0c,0x00 + +# ATT: cmovll (%r16,%rax), %r17d +# INTEL: cmovl r17d, dword ptr [r16 + rax] +0xd5,0xd0,0x4c,0x0c,0x00 + +# ATT: cmovll (%r16,%r17), %r18d +# INTEL: cmovl r18d, dword ptr [r16 + r17] +0xd5,0xf0,0x4c,0x14,0x08 + +## MRMDestReg + +# ATT: movl %eax, %r16d +# INTEL: mov r16d, eax +0xd5,0x10,0x89,0xc0 + +# ATT: movl %r16d, %eax +# INTEL: mov eax, r16d +0xd5,0x40,0x89,0xc0 + +# ATT: movl %r16d, %r17d +# INTEL: mov r17d, r16d +0xd5,0x50,0x89,0xc1 + +## MRMDestMem + +# ATT: movl %ebx, (%r16,%rax) +# INTEL: mov dword ptr [r16 + rax], ebx +0xd5,0x10,0x89,0x1c,0x00 + +# ATT: movl %ebx, (%rax,%r16) +# INTEL: mov dword ptr [rax + r16], ebx +0xd5,0x20,0x89,0x1c,0x00 + +# ATT: movl %r16d, (%rax,%rbx) +# INTEL: mov dword ptr [rax + rbx], r16d +0xd5,0x40,0x89,0x04,0x18 + +# ATT: movl %eax, (%r16,%r17) +# INTEL: mov dword ptr [r16 + r17], eax +0xd5,0x30,0x89,0x04,0x08 + +# ATT: movl %r17d, (%rax,%r16) +# INTEL: mov dword ptr [rax + r16], r17d +0xd5,0x60,0x89,0x0c,0x00 + +# ATT: movl %r17d, (%r16,%rax) +# INTEL: mov dword ptr [r16 + rax], r17d +0xd5,0x50,0x89,0x0c,0x00 + +# ATT: movl %r18d, (%r16,%r17) +# INTEL: mov dword ptr [r16 + r17], r18d +0xd5,0x70,0x89,0x14,0x08 + +# ATT: movb %bpl, (%r16,%r14) +# INTEL: mov byte ptr [r16 + r14], bpl +0xd5,0x12,0x88,0x2c,0x30 + +## MRMXmCC + +# ATT: sete (%rax,%r16) +# INTEL: sete byte ptr [rax + r16] +0xd5,0xa0,0x94,0x04,0x00 + +# ATT: sete (%r16,%rax) +# INTEL: sete byte ptr [r16 + rax] +0xd5,0x90,0x94,0x04,0x00 + +# ATT: sete (%r16,%r17) +# INTEL: sete byte ptr [r16 + r17] +0xd5,0xb0,0x94,0x04,0x08 + +## MRMXm + +# ATT: nopl (%rax,%r16) +# INTEL: nop dword ptr [rax + r16] +0xd5,0xa0,0x1f,0x04,0x00 + +# ATT: nopl (%r16,%rax) +# INTEL: nop dword ptr [r16 + rax] +0xd5,0x90,0x1f,0x04,0x00 + +# ATT: nopl (%r16,%r17) +# INTEL: nop dword ptr [r16 + r17] +0xd5,0xb0,0x1f,0x04,0x08 + +## MRM0m + +# ATT: incl (%rax,%r16) +# INTEL: inc dword ptr [rax + r16] +0xd5,0x20,0xff,0x04,0x00 + +# ATT: incl (%r16,%rax) +# INTEL: inc dword ptr [r16 + rax] +0xd5,0x10,0xff,0x04,0x00 + +# ATT: incl (%r16,%r17) +# INTEL: inc dword ptr [r16 + r17] +0xd5,0x30,0xff,0x04,0x08 + +## MRM1m + +# ATT: decl (%rax,%r16) +# INTEL: dec dword ptr [rax + r16] +0xd5,0x20,0xff,0x0c,0x00 + +# ATT: decl (%r16,%rax) +# INTEL: dec dword ptr [r16 + rax] +0xd5,0x10,0xff,0x0c,0x00 + +# ATT: decl (%r16,%r17) +# INTEL: dec dword ptr [r16 + r17] +0xd5,0x30,0xff,0x0c,0x08 + +## MRM2m + +# ATT: notl (%rax,%r16) +# INTEL: not dword ptr [rax + r16] +0xd5,0x20,0xf7,0x14,0x00 + +# ATT: notl (%r16,%rax) +# INTEL: not dword ptr [r16 + rax] +0xd5,0x10,0xf7,0x14,0x00 + +# ATT: notl (%r16,%r17) +# INTEL: not dword ptr [r16 + r17] +0xd5,0x30,0xf7,0x14,0x08 + +## MRM3m + +# ATT: negl (%rax,%r16) +# INTEL: neg dword ptr [rax + r16] +0xd5,0x20,0xf7,0x1c,0x00 + +# ATT: negl (%r16,%rax) +# INTEL: neg dword ptr [r16 + rax] +0xd5,0x10,0xf7,0x1c,0x00 + +# ATT: negl (%r16,%r17) +# INTEL: neg dword ptr [r16 + r17] +0xd5,0x30,0xf7,0x1c,0x08 + +## MRM4m + +# ATT: mull (%rax,%r16) +# INTEL: mul dword ptr [rax + r16] +0xd5,0x20,0xf7,0x24,0x00 + +# ATT: mull (%r16,%rax) +# INTEL: mul dword ptr [r16 + rax] +0xd5,0x10,0xf7,0x24,0x00 + +# ATT: mull (%r16,%r17) +# INTEL: mul dword ptr [r16 + r17] +0xd5,0x30,0xf7,0x24,0x08 + +## MRM5m + +# ATT: imull (%rax,%r16) +# INTEL: imul dword ptr [rax + r16] +0xd5,0x20,0xf7,0x2c,0x00 + +# ATT: imull (%r16,%rax) +# INTEL: imul dword ptr [r16 + rax] +0xd5,0x10,0xf7,0x2c,0x00 + +# ATT: imull (%r16,%r17) +# INTEL: imul dword ptr [r16 + r17] +0xd5,0x30,0xf7,0x2c,0x08 + +## MRM6m + +# ATT: divl (%rax,%r16) +# INTEL: div dword ptr [rax + r16] +0xd5,0x20,0xf7,0x34,0x00 + +# ATT: divl (%r16,%rax) +# INTEL: div dword ptr [r16 + rax] +0xd5,0x10,0xf7,0x34,0x00 + +# ATT: divl (%r16,%r17) +# INTEL: div dword ptr [r16 + r17] +0xd5,0x30,0xf7,0x34,0x08 + +## MRM7m + +# ATT: idivl (%rax,%r16) +# INTEL: idiv dword ptr [rax + r16] +0xd5,0x20,0xf7,0x3c,0x00 + +# ATT: idivl (%r16,%rax) +# INTEL: idiv dword ptr [r16 + rax] +0xd5,0x10,0xf7,0x3c,0x00 + +# ATT: idivl (%r16,%r17) +# INTEL: idiv dword ptr [r16 + r17] +0xd5,0x30,0xf7,0x3c,0x08 + +## MRMXrCC + +# ATT: sete %r16b +# INTEL: sete r16b +0xd5,0x90,0x94,0xc0 + +## MRMXr + +# ATT: nopl %r16d +# INTEL: nop r16d +0xd5,0x90,0x1f,0xc0 + +## MRM0r + +# ATT: incl %r16d +# INTEL: inc r16d +0xd5,0x10,0xff,0xc0 + +## MRM1r + +# ATT: decl %r16d +# INTEL: dec r16d +0xd5,0x10,0xff,0xc8 + +## MRM2r + +# ATT: notl %r16d +# INTEL: not r16d +0xd5,0x10,0xf7,0xd0 + +## MRM3r + +# ATT: negl %r16d +# INTEL: neg r16d +0xd5,0x10,0xf7,0xd8 + +## MRM4r + +# ATT: mull %r16d +# INTEL: mul r16d +0xd5,0x10,0xf7,0xe0 + +## MRM5r + +# ATT: imull %r16d +# INTEL: imul r16d +0xd5,0x10,0xf7,0xe8 + +## MRM6r + +# ATT: divl %r16d +# INTEL: div r16d +0xd5,0x10,0xf7,0xf0 + +## MRM7r + +# ATT: idivl %r16d +# INTEL: idiv r16d +0xd5,0x10,0xf7,0xf8 diff --git a/llvm/test/MC/Disassembler/X86/invalid-EVEX-R2.txt b/llvm/test/MC/Disassembler/X86/invalid-EVEX-R2.txt deleted file mode 100644 index 70272463a7a5b1..00000000000000 --- a/llvm/test/MC/Disassembler/X86/invalid-EVEX-R2.txt +++ /dev/null @@ -1,4 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=x86_64-apple-darwin9 2>&1 | grep "invalid instruction encoding" - -# This instruction would decode as vcvtsd2usi if the EVEX.R' field weren't 0. -0x62 0xe1 0xff 0x08 0x79 0xc0 diff --git a/llvm/test/MC/Disassembler/X86/x86-64-err.txt b/llvm/test/MC/Disassembler/X86/x86-64-err.txt index 9674ea0528e98d..3eca239e60f5c7 100644 --- a/llvm/test/MC/Disassembler/X86/x86-64-err.txt +++ b/llvm/test/MC/Disassembler/X86/x86-64-err.txt @@ -10,8 +10,6 @@ # 64: invalid instruction encoding 0xc4,0x62,0xfd,0x18,0x20 # 64: invalid instruction encoding -0xc4,0xc2,0xfd,0x19,0xcc -# 64: invalid instruction encoding 0xc4,0xe2,0xfd,0x1a,0x08 # 64: invalid instruction encoding 0xc4,0xe3,0xfd,0x39,0xc5,0x01