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MIR: Reject non-power-of-4 alignments in MMO parsing

llvm-svn: 352686
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arsenm committed Jan 30, 2019
1 parent 10f5940 commit 547a83b4ebd1cbbe90b092634bf1d909ded48555
Showing with 167 additions and 151 deletions.
  1. +4 −0 llvm/lib/CodeGen/MIRParser/MIParser.cpp
  2. +1 −1 llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
  3. +4 −4 llvm/test/CodeGen/ARM/fp16-litpool3-arm.mir
  4. +12 −0 llvm/test/CodeGen/MIR/X86/expected-power-of-2-after-align.mir
  5. +2 −2 llvm/test/CodeGen/Mips/GlobalISel/instruction-select/pointers.mir
  6. +4 −4 llvm/test/CodeGen/Mips/GlobalISel/instruction-select/stack_args.mir
  7. +12 −12 llvm/test/CodeGen/Mips/GlobalISel/legalizer/add.mir
  8. +2 −2 llvm/test/CodeGen/Mips/GlobalISel/legalizer/pointers.mir
  9. +4 −4 llvm/test/CodeGen/Mips/GlobalISel/legalizer/stack_args.mir
  10. +12 −12 llvm/test/CodeGen/Mips/GlobalISel/legalizer/sub.mir
  11. +2 −2 llvm/test/CodeGen/Mips/GlobalISel/regbankselect/pointers.mir
  12. +4 −4 llvm/test/CodeGen/Mips/GlobalISel/regbankselect/stack_args.mir
  13. +24 −24 llvm/test/CodeGen/X86/GlobalISel/select-memop-scalar-x32.mir
  14. +2 −2 llvm/test/CodeGen/X86/GlobalISel/x86-legalize-inttoptr.mir
  15. +8 −8 llvm/test/CodeGen/X86/GlobalISel/x86-legalize-ptrtoint.mir
  16. +12 −12 llvm/test/CodeGen/X86/GlobalISel/x86-legalize-srem.mir
  17. +12 −12 llvm/test/CodeGen/X86/GlobalISel/x86-legalize-urem.mir
  18. +2 −2 llvm/test/CodeGen/X86/GlobalISel/x86-select-inttoptr.mir
  19. +8 −8 llvm/test/CodeGen/X86/GlobalISel/x86-select-ptrtoint.mir
  20. +12 −12 llvm/test/CodeGen/X86/GlobalISel/x86-select-srem.mir
  21. +12 −12 llvm/test/CodeGen/X86/GlobalISel/x86-select-udiv.mir
  22. +12 −12 llvm/test/CodeGen/X86/GlobalISel/x86-select-urem.mir
@@ -2324,6 +2324,10 @@ bool MIParser::parseAlignment(unsigned &Alignment) {
if (getUnsigned(Alignment))
return true;
lex();

if (!isPowerOf2_32(Alignment))
return error("expected a power-of-2 literal after 'align'");

return false;
}

@@ -474,7 +474,7 @@ fixedStack:
body: |
bb.0:
%0(p0) = G_FRAME_INDEX %fixed-stack.0
%1(s32) = G_LOAD %0(p0) :: (load 4 from %fixed-stack.0, align 0)
%1(s32) = G_LOAD %0(p0) :: (load 4 from %fixed-stack.0, align 4)
%2(p0) = COPY $sp
%3(s32) = G_CONSTANT i32 8
@@ -82,11 +82,11 @@ constants:
#CHECK: CONSTPOOL_ENTRY 1, %const{{.*}}, 2
#
# We don't want to decrease alignment if the block already has been
# aligned; this can e.g. be an existing CPE that has been carefully
# aligned. Here BB.1.LA has already an 8-byte alignment, and we are
# aligned; this can e.g. be an existing CPE that has been carefully
# aligned. Here BB.1.LA has already an 8-byte alignment, and we are
# checking we don't set it to 4:
#
#CHECK: bb.{{.*}}.LA (align 3):
#CHECK: bb.{{.*}}.LA (align 8):

body: |
bb.0.entry:
@@ -100,7 +100,7 @@ body: |
FMSTAT 14, $noreg, implicit-def $cpsr, implicit killed $fpscr_nzcv
Bcc %bb.2, 0, killed $cpsr
bb.1.LA (align 3):
bb.1.LA (align 8):
successors: %bb.2(0x80000000)
dead renamable $r0 = SPACE 1000, undef renamable $r0
@@ -0,0 +1,12 @@
# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s

---
name: align_0
body: |
bb.0:
%0:_(p0) = IMPLICIT_DEF
; CHECK: [[@LINE+1]]:50: expected a power-of-2 literal after 'align'
%1:_(s64) = G_LOAD %0(p0) :: (load 8, align 0)
...

@@ -44,7 +44,7 @@ body: |
; MIPS32-LABEL: name: ptr_arg_on_stack
; MIPS32: liveins: $a0, $a1, $a2, $a3
; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.0, 0
; MIPS32: [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (load 4 from %fixed-stack.0, align 0)
; MIPS32: [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (load 4 from %fixed-stack.0, align 8)
; MIPS32: [[LW1:%[0-9]+]]:gpr32 = LW [[LW]], 0 :: (load 4 from %ir.p)
; MIPS32: $v0 = COPY [[LW1]]
; MIPS32: RetRA implicit $v0
@@ -53,7 +53,7 @@ body: |
%2:gprb(s32) = COPY $a2
%3:gprb(s32) = COPY $a3
%5:gprb(p0) = G_FRAME_INDEX %fixed-stack.0
%4:gprb(p0) = G_LOAD %5(p0) :: (load 4 from %fixed-stack.0, align 0)
%4:gprb(p0) = G_LOAD %5(p0) :: (load 4 from %fixed-stack.0, align 8)
%6:gprb(s32) = G_LOAD %4(p0) :: (load 4 from %ir.p)
$v0 = COPY %6(s32)
RetRA implicit $v0
@@ -25,7 +25,7 @@ body: |
; MIPS32: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
; MIPS32: [[COPY3:%[0-9]+]]:gpr32 = COPY $a3
; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.0, 0
; MIPS32: [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (load 4 from %fixed-stack.0, align 0)
; MIPS32: [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (load 4 from %fixed-stack.0, align 8)
; MIPS32: ADJCALLSTACKDOWN 24, 0, implicit-def $sp, implicit $sp
; MIPS32: $a0 = COPY [[COPY]]
; MIPS32: $a1 = COPY [[COPY1]]
@@ -35,7 +35,7 @@ body: |
; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi 0
; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 16
; MIPS32: [[ADDu:%[0-9]+]]:gpr32 = ADDu [[COPY4]], [[ORi]]
; MIPS32: SW [[LW]], [[ADDu]], 0 :: (store 4 into stack + 16, align 0)
; MIPS32: SW [[LW]], [[ADDu]], 0 :: (store 4 into stack + 16)
; MIPS32: JAL @f, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $v0
; MIPS32: [[COPY5:%[0-9]+]]:gpr32 = COPY $v0
; MIPS32: ADJCALLSTACKUP 24, 0, implicit-def $sp, implicit $sp
@@ -46,7 +46,7 @@ body: |
%2:gprb(s32) = COPY $a2
%3:gprb(s32) = COPY $a3
%5:gprb(p0) = G_FRAME_INDEX %fixed-stack.0
%4:gprb(s32) = G_LOAD %5(p0) :: (load 4 from %fixed-stack.0, align 0)
%4:gprb(s32) = G_LOAD %5(p0) :: (load 4 from %fixed-stack.0, align 8)
ADJCALLSTACKDOWN 24, 0, implicit-def $sp, implicit $sp
$a0 = COPY %0(s32)
$a1 = COPY %1(s32)
@@ -55,7 +55,7 @@ body: |
%7:gprb(p0) = COPY $sp
%8:gprb(s32) = G_CONSTANT i32 16
%9:gprb(p0) = G_GEP %7, %8(s32)
G_STORE %4(s32), %9(p0) :: (store 4 into stack + 16, align 0)
G_STORE %4(s32), %9(p0) :: (store 4 into stack + 16, align 4)
JAL @f, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $v0
%6:gprb(s32) = COPY $v0
ADJCALLSTACKUP 24, 0, implicit-def $sp, implicit $sp
@@ -52,8 +52,8 @@ body: |
; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY3]]
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]]
; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]]
; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32)
; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; MIPS32: $v0 = COPY [[ASHR]](s32)
; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
@@ -141,8 +141,8 @@ body: |
; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY3]]
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]]
; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]]
; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32)
; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; MIPS32: $v0 = COPY [[ASHR]](s32)
; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
@@ -275,13 +275,13 @@ body: |
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
; MIPS32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load 4 from %fixed-stack.0, align 0)
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load 4 from %fixed-stack.0)
; MIPS32: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
; MIPS32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (load 4 from %fixed-stack.1, align 0)
; MIPS32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (load 4 from %fixed-stack.1)
; MIPS32: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2
; MIPS32: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX2]](p0) :: (load 4 from %fixed-stack.2, align 0)
; MIPS32: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX2]](p0) :: (load 4 from %fixed-stack.2)
; MIPS32: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3
; MIPS32: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX3]](p0) :: (load 4 from %fixed-stack.3, align 0)
; MIPS32: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX3]](p0) :: (load 4 from %fixed-stack.3)
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD]], [[COPY]]
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
@@ -317,13 +317,13 @@ body: |
%5:_(s32) = COPY $a3
%0:_(s128) = G_MERGE_VALUES %2(s32), %3(s32), %4(s32), %5(s32)
%10:_(p0) = G_FRAME_INDEX %fixed-stack.3
%6:_(s32) = G_LOAD %10(p0) :: (load 4 from %fixed-stack.3, align 0)
%6:_(s32) = G_LOAD %10(p0) :: (load 4 from %fixed-stack.3, align 4)
%11:_(p0) = G_FRAME_INDEX %fixed-stack.2
%7:_(s32) = G_LOAD %11(p0) :: (load 4 from %fixed-stack.2, align 0)
%7:_(s32) = G_LOAD %11(p0) :: (load 4 from %fixed-stack.2, align 4)
%12:_(p0) = G_FRAME_INDEX %fixed-stack.1
%8:_(s32) = G_LOAD %12(p0) :: (load 4 from %fixed-stack.1, align 0)
%8:_(s32) = G_LOAD %12(p0) :: (load 4 from %fixed-stack.1, align 4)
%13:_(p0) = G_FRAME_INDEX %fixed-stack.0
%9:_(s32) = G_LOAD %13(p0) :: (load 4 from %fixed-stack.0, align 0)
%9:_(s32) = G_LOAD %13(p0) :: (load 4 from %fixed-stack.0, align 4)
%1:_(s128) = G_MERGE_VALUES %6(s32), %7(s32), %8(s32), %9(s32)
%14:_(s128) = G_ADD %1, %0
%15:_(s32), %16:_(s32), %17:_(s32), %18:_(s32) = G_UNMERGE_VALUES %14(s128)
@@ -44,7 +44,7 @@ body: |
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
; MIPS32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
; MIPS32: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (load 4 from %fixed-stack.0, align 0)
; MIPS32: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (load 4 from %fixed-stack.0)
; MIPS32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[LOAD]](p0) :: (load 4 from %ir.p)
; MIPS32: $v0 = COPY [[LOAD1]](s32)
; MIPS32: RetRA implicit $v0
@@ -53,7 +53,7 @@ body: |
%2:_(s32) = COPY $a2
%3:_(s32) = COPY $a3
%5:_(p0) = G_FRAME_INDEX %fixed-stack.0
%4:_(p0) = G_LOAD %5(p0) :: (load 4 from %fixed-stack.0, align 0)
%4:_(p0) = G_LOAD %5(p0) :: (load 4 from %fixed-stack.0, align 4)
%6:_(s32) = G_LOAD %4(p0) :: (load 4 from %ir.p)
$v0 = COPY %6(s32)
RetRA implicit $v0
@@ -23,7 +23,7 @@ body: |
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
; MIPS32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load 4 from %fixed-stack.0, align 0)
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load 4 from %fixed-stack.0, align 8)
; MIPS32: ADJCALLSTACKDOWN 24, 0, implicit-def $sp, implicit $sp
; MIPS32: $a0 = COPY [[COPY]](s32)
; MIPS32: $a1 = COPY [[COPY1]](s32)
@@ -32,7 +32,7 @@ body: |
; MIPS32: [[COPY4:%[0-9]+]]:_(p0) = COPY $sp
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; MIPS32: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY4]], [[C]](s32)
; MIPS32: G_STORE [[LOAD]](s32), [[GEP]](p0) :: (store 4 into stack + 16, align 0)
; MIPS32: G_STORE [[LOAD]](s32), [[GEP]](p0) :: (store 4 into stack + 16)
; MIPS32: JAL @f, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $v0
; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY $v0
; MIPS32: ADJCALLSTACKUP 24, 0, implicit-def $sp, implicit $sp
@@ -43,7 +43,7 @@ body: |
%2:_(s32) = COPY $a2
%3:_(s32) = COPY $a3
%5:_(p0) = G_FRAME_INDEX %fixed-stack.0
%4:_(s32) = G_LOAD %5(p0) :: (load 4 from %fixed-stack.0, align 0)
%4:_(s32) = G_LOAD %5(p0) :: (load 4 from %fixed-stack.0, align 8)
ADJCALLSTACKDOWN 24, 0, implicit-def $sp, implicit $sp
$a0 = COPY %0(s32)
$a1 = COPY %1(s32)
@@ -52,7 +52,7 @@ body: |
%7:_(p0) = COPY $sp
%8:_(s32) = G_CONSTANT i32 16
%9:_(p0) = G_GEP %7, %8(s32)
G_STORE %4(s32), %9(p0) :: (store 4 into stack + 16, align 0)
G_STORE %4(s32), %9(p0) :: (store 4 into stack + 16, align 4)
JAL @f, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $v0
%6:_(s32) = COPY $v0
ADJCALLSTACKUP 24, 0, implicit-def $sp, implicit $sp
@@ -52,8 +52,8 @@ body: |
; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[COPY3]]
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]]
; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]]
; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32)
; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; MIPS32: $v0 = COPY [[ASHR]](s32)
; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
@@ -141,8 +141,8 @@ body: |
; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[COPY3]]
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]]
; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]]
; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32)
; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; MIPS32: $v0 = COPY [[ASHR]](s32)
; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
@@ -270,13 +270,13 @@ body: |
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
; MIPS32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load 4 from %fixed-stack.0, align 0)
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load 4 from %fixed-stack.0, align 8)
; MIPS32: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
; MIPS32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (load 4 from %fixed-stack.1, align 0)
; MIPS32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (load 4 from %fixed-stack.1)
; MIPS32: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2
; MIPS32: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX2]](p0) :: (load 4 from %fixed-stack.2, align 0)
; MIPS32: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX2]](p0) :: (load 4 from %fixed-stack.2, align 8)
; MIPS32: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3
; MIPS32: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX3]](p0) :: (load 4 from %fixed-stack.3, align 0)
; MIPS32: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX3]](p0) :: (load 4 from %fixed-stack.3)
; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[LOAD]], [[COPY]]
; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[LOAD]](s32), [[COPY]]
; MIPS32: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
@@ -323,13 +323,13 @@ body: |
%5:_(s32) = COPY $a3
%0:_(s128) = G_MERGE_VALUES %2(s32), %3(s32), %4(s32), %5(s32)
%10:_(p0) = G_FRAME_INDEX %fixed-stack.3
%6:_(s32) = G_LOAD %10(p0) :: (load 4 from %fixed-stack.3, align 0)
%6:_(s32) = G_LOAD %10(p0) :: (load 4 from %fixed-stack.3, align 8)
%11:_(p0) = G_FRAME_INDEX %fixed-stack.2
%7:_(s32) = G_LOAD %11(p0) :: (load 4 from %fixed-stack.2, align 0)
%7:_(s32) = G_LOAD %11(p0) :: (load 4 from %fixed-stack.2, align 4)
%12:_(p0) = G_FRAME_INDEX %fixed-stack.1
%8:_(s32) = G_LOAD %12(p0) :: (load 4 from %fixed-stack.1, align 0)
%8:_(s32) = G_LOAD %12(p0) :: (load 4 from %fixed-stack.1, align 8)
%13:_(p0) = G_FRAME_INDEX %fixed-stack.0
%9:_(s32) = G_LOAD %13(p0) :: (load 4 from %fixed-stack.0, align 0)
%9:_(s32) = G_LOAD %13(p0) :: (load 4 from %fixed-stack.0, align 4)
%1:_(s128) = G_MERGE_VALUES %6(s32), %7(s32), %8(s32), %9(s32)
%14:_(s128) = G_SUB %1, %0
%15:_(s32), %16:_(s32), %17:_(s32), %18:_(s32) = G_UNMERGE_VALUES %14(s128)
@@ -46,7 +46,7 @@ body: |
; MIPS32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $a2
; MIPS32: [[COPY3:%[0-9]+]]:gprb(s32) = COPY $a3
; MIPS32: [[FRAME_INDEX:%[0-9]+]]:gprb(p0) = G_FRAME_INDEX %fixed-stack.0
; MIPS32: [[LOAD:%[0-9]+]]:gprb(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (load 4 from %fixed-stack.0, align 0)
; MIPS32: [[LOAD:%[0-9]+]]:gprb(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (load 4 from %fixed-stack.0, align 8)
; MIPS32: [[LOAD1:%[0-9]+]]:gprb(s32) = G_LOAD [[LOAD]](p0) :: (load 4 from %ir.p)
; MIPS32: $v0 = COPY [[LOAD1]](s32)
; MIPS32: RetRA implicit $v0
@@ -55,7 +55,7 @@ body: |
%2:_(s32) = COPY $a2
%3:_(s32) = COPY $a3
%5:_(p0) = G_FRAME_INDEX %fixed-stack.0
%4:_(p0) = G_LOAD %5(p0) :: (load 4 from %fixed-stack.0, align 0)
%4:_(p0) = G_LOAD %5(p0) :: (load 4 from %fixed-stack.0, align 8)
%6:_(s32) = G_LOAD %4(p0) :: (load 4 from %ir.p)
$v0 = COPY %6(s32)
RetRA implicit $v0
@@ -24,7 +24,7 @@ body: |
; MIPS32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $a2
; MIPS32: [[COPY3:%[0-9]+]]:gprb(s32) = COPY $a3
; MIPS32: [[FRAME_INDEX:%[0-9]+]]:gprb(p0) = G_FRAME_INDEX %fixed-stack.0
; MIPS32: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load 4 from %fixed-stack.0, align 0)
; MIPS32: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load 4 from %fixed-stack.0, align 8)
; MIPS32: ADJCALLSTACKDOWN 24, 0, implicit-def $sp, implicit $sp
; MIPS32: $a0 = COPY [[COPY]](s32)
; MIPS32: $a1 = COPY [[COPY1]](s32)
@@ -33,7 +33,7 @@ body: |
; MIPS32: [[COPY4:%[0-9]+]]:gprb(p0) = COPY $sp
; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 16
; MIPS32: [[GEP:%[0-9]+]]:gprb(p0) = G_GEP [[COPY4]], [[C]](s32)
; MIPS32: G_STORE [[LOAD]](s32), [[GEP]](p0) :: (store 4 into stack + 16, align 0)
; MIPS32: G_STORE [[LOAD]](s32), [[GEP]](p0) :: (store 4 into stack + 16)
; MIPS32: JAL @f, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $v0
; MIPS32: [[COPY5:%[0-9]+]]:gprb(s32) = COPY $v0
; MIPS32: ADJCALLSTACKUP 24, 0, implicit-def $sp, implicit $sp
@@ -44,7 +44,7 @@ body: |
%2:_(s32) = COPY $a2
%3:_(s32) = COPY $a3
%5:_(p0) = G_FRAME_INDEX %fixed-stack.0
%4:_(s32) = G_LOAD %5(p0) :: (load 4 from %fixed-stack.0, align 0)
%4:_(s32) = G_LOAD %5(p0) :: (load 4 from %fixed-stack.0, align 8)
ADJCALLSTACKDOWN 24, 0, implicit-def $sp, implicit $sp
$a0 = COPY %0(s32)
$a1 = COPY %1(s32)
@@ -53,7 +53,7 @@ body: |
%7:_(p0) = COPY $sp
%8:_(s32) = G_CONSTANT i32 16
%9:_(p0) = G_GEP %7, %8(s32)
G_STORE %4(s32), %9(p0) :: (store 4 into stack + 16, align 0)
G_STORE %4(s32), %9(p0) :: (store 4 into stack + 16, align 4)
JAL @f, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $v0
%6:_(s32) = COPY $v0
ADJCALLSTACKUP 24, 0, implicit-def $sp, implicit $sp

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