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ARMv7k: implement ABI changes for watchOS from standard iOS.
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llvm-svn: 251710
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TNorthover committed Oct 30, 2015
1 parent e931f9f commit 5627d39
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Showing 9 changed files with 473 additions and 18 deletions.
50 changes: 40 additions & 10 deletions clang/lib/Basic/Targets.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -3702,6 +3702,11 @@ class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> {
LongDoubleWidth = 128;
LongDoubleAlign = 128;
SuitableAlign = 128;
MaxVectorAlign = 256;
// The watchOS simulator uses the builtin bool type for Objective-C.
llvm::Triple T = llvm::Triple(Triple);
if (T.isWatchOS())
UseSignedCharForObjCBool = false;
SizeType = UnsignedLong;
IntPtrType = SignedLong;
DataLayoutString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128";
Expand Down Expand Up @@ -4243,12 +4248,15 @@ class ARMTargetInfo : public TargetInfo {
// FIXME: Enumerated types are variable width in straight AAPCS.
}

void setABIAPCS() {
void setABIAPCS(bool IsAAPCS16) {
const llvm::Triple &T = getTriple();

IsAAPCS = false;

DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32;
if (IsAAPCS16)
DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64;
else
DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32;

// size_t is unsigned int on FreeBSD.
if (T.getOS() == llvm::Triple::FreeBSD)
Expand All @@ -4268,7 +4276,10 @@ class ARMTargetInfo : public TargetInfo {
/// gcc.
ZeroLengthBitfieldBoundary = 32;

if (T.isOSBinFormatMachO())
if (T.isOSBinFormatMachO() && IsAAPCS16) {
assert(!BigEndian && "AAPCS16 does not support big-endian");
DataLayoutString = "e-m:o-p:32:32-i64:64-a:0:32-n32-S128";
} else if (T.isOSBinFormatMachO())
DataLayoutString =
BigEndian
? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
Expand Down Expand Up @@ -4413,6 +4424,8 @@ class ARMTargetInfo : public TargetInfo {
Triple.getOS() == llvm::Triple::UnknownOS ||
StringRef(CPU).startswith("cortex-m")) {
setABI("aapcs");
} else if (Triple.isWatchOS()) {
setABI("aapcs16");
} else {
setABI("apcs-gnu");
}
Expand Down Expand Up @@ -4465,10 +4478,8 @@ class ARMTargetInfo : public TargetInfo {
//
// FIXME: We need support for -meabi... we could just mangle it into the
// name.
// FIXME: aapcs16 isn't really the same as APCS, this allows tests to pass
// until the real ABI is committed.
if (Name == "apcs-gnu" || Name == "aapcs16") {
setABIAPCS();
setABIAPCS(Name == "aapcs16");
return true;
}
if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") {
Expand Down Expand Up @@ -4625,6 +4636,12 @@ class ARMTargetInfo : public TargetInfo {

// Target properties.
Builder.defineMacro("__REGISTER_PREFIX__", "");

// Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU
// happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__.
if (getTriple().isWatchOS())
Builder.defineMacro("__ARM_ARCH_7K__", "2");

if (!CPUAttr.empty())
Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__");

Expand Down Expand Up @@ -4806,7 +4823,10 @@ class ARMTargetInfo : public TargetInfo {
}
bool isCLZForZeroUndef() const override { return false; }
BuiltinVaListKind getBuiltinVaListKind() const override {
return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList;
return IsAAPCS
? AAPCSABIBuiltinVaList
: (getTriple().isWatchOS() ? TargetInfo::CharPtrBuiltinVaList
: TargetInfo::VoidPtrBuiltinVaList);
}
ArrayRef<const char *> getGCCRegNames() const override;
ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
Expand Down Expand Up @@ -5147,8 +5167,18 @@ class DarwinARMTargetInfo :
// ARMleTargetInfo.
MaxAtomicInlineWidth = 64;

// Darwin on iOS uses a variant of the ARM C++ ABI.
TheCXXABI.set(TargetCXXABI::iOS);
if (Triple.isWatchOS()) {
// Darwin on iOS uses a variant of the ARM C++ ABI.
TheCXXABI.set(TargetCXXABI::WatchOS);

// The 32-bit ABI is silent on what ptrdiff_t should be, but given that
// size_t is long, it's a bit weird for it to be int.
PtrDiffType = SignedLong;

// BOOL should be a real boolean on the new ABI
UseSignedCharForObjCBool = false;
} else
TheCXXABI.set(TargetCXXABI::iOS);
}
};

Expand Down Expand Up @@ -5204,7 +5234,7 @@ class AArch64TargetInfo : public TargetInfo {
// contributes to the alignment of the containing aggregate in the same way
// a plain (non bit-field) member of that type would, without exception for
// zero-sized or anonymous bit-fields."
UseBitFieldTypeAlignment = true;
assert(UseBitFieldTypeAlignment && "bitfields affect type alignment");
UseZeroLengthBitfieldAlignment = true;

// AArch64 targets default to using the ARM C++ ABI.
Expand Down
71 changes: 63 additions & 8 deletions clang/lib/CodeGen/TargetInfo.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -4693,7 +4693,8 @@ class ARMABIInfo : public ABIInfo {
enum ABIKind {
APCS = 0,
AAPCS = 1,
AAPCS_VFP
AAPCS_VFP = 2,
AAPCS16_VFP = 3,
};

private:
Expand Down Expand Up @@ -4803,7 +4804,8 @@ class ARMTargetCodeGenInfo : public TargetCodeGenInfo {

Fn->addFnAttr("interrupt", Kind);

if (cast<ARMABIInfo>(getABIInfo()).getABIKind() == ARMABIInfo::APCS)
ARMABIInfo::ABIKind ABI = cast<ARMABIInfo>(getABIInfo()).getABIKind();
if (ABI == ARMABIInfo::APCS)
return;

// AAPCS guarantees that sp will be 8-byte aligned on any public interface,
Expand Down Expand Up @@ -4869,7 +4871,7 @@ void ARMABIInfo::computeInfo(CGFunctionInfo &FI) const {
/// Return the default calling convention that LLVM will use.
llvm::CallingConv::ID ARMABIInfo::getLLVMDefaultCC() const {
// The default calling convention that LLVM will infer.
if (isEABIHF())
if (isEABIHF() || getTarget().getTriple().isWatchOS())
return llvm::CallingConv::ARM_AAPCS_VFP;
else if (isEABI())
return llvm::CallingConv::ARM_AAPCS;
Expand All @@ -4884,6 +4886,7 @@ llvm::CallingConv::ID ARMABIInfo::getABIDefaultCC() const {
case APCS: return llvm::CallingConv::ARM_APCS;
case AAPCS: return llvm::CallingConv::ARM_AAPCS;
case AAPCS_VFP: return llvm::CallingConv::ARM_AAPCS_VFP;
case AAPCS16_VFP: return llvm::CallingConv::ARM_AAPCS_VFP;
}
llvm_unreachable("bad ABI kind");
}
Expand All @@ -4897,8 +4900,20 @@ void ARMABIInfo::setCCs() {
if (abiCC != getLLVMDefaultCC())
RuntimeCC = abiCC;

BuiltinCC = (getABIKind() == APCS ?
llvm::CallingConv::ARM_APCS : llvm::CallingConv::ARM_AAPCS);
// AAPCS apparently requires runtime support functions to be soft-float, but
// that's almost certainly for historic reasons (Thumb1 not supporting VFP
// most likely). It's more convenient for AAPCS16_VFP to be hard-float.
switch (getABIKind()) {
case APCS:
case AAPCS16_VFP:
if (abiCC != getLLVMDefaultCC())
BuiltinCC = abiCC;
break;
case AAPCS:
case AAPCS_VFP:
BuiltinCC = llvm::CallingConv::ARM_AAPCS;
break;
}
}

ABIArgInfo ARMABIInfo::classifyArgumentType(QualType Ty,
Expand Down Expand Up @@ -4973,6 +4988,27 @@ ABIArgInfo ARMABIInfo::classifyArgumentType(QualType Ty,
// Base can be a floating-point or a vector.
return ABIArgInfo::getDirect(nullptr, 0, nullptr, false);
}
} else if (getABIKind() == ARMABIInfo::AAPCS16_VFP) {
// WatchOS does have homogeneous aggregates. Note that we intentionally use
// this convention even for a variadic function: the backend will use GPRs
// if needed.
const Type *Base = nullptr;
uint64_t Members = 0;
if (isHomogeneousAggregate(Ty, Base, Members)) {
assert(Base && Members <= 4 && "unexpected homogeneous aggregate");
llvm::Type *Ty =
llvm::ArrayType::get(CGT.ConvertType(QualType(Base, 0)), Members);
return ABIArgInfo::getDirect(Ty, 0, nullptr, false);
}
}

if (getABIKind() == ARMABIInfo::AAPCS16_VFP &&
getContext().getTypeSizeInChars(Ty) > CharUnits::fromQuantity(16)) {
// WatchOS is adopting the 64-bit AAPCS rule on composite types: if they're
// bigger than 128-bits, they get placed in space allocated by the caller,
// and a pointer is passed.
return ABIArgInfo::getIndirect(
CharUnits::fromQuantity(getContext().getTypeAlign(Ty) / 8), false);
}

// Support byval for ARM.
Expand All @@ -4986,6 +5022,7 @@ ABIArgInfo ARMABIInfo::classifyArgumentType(QualType Ty,
ABIAlign = std::min(std::max(TyAlign, (uint64_t)4), (uint64_t)8);

if (getContext().getTypeSizeInChars(Ty) > CharUnits::fromQuantity(64)) {
assert(getABIKind() != ARMABIInfo::AAPCS16_VFP && "unexpected byval");
return ABIArgInfo::getIndirect(CharUnits::fromQuantity(ABIAlign),
/*ByVal=*/true,
/*Realign=*/TyAlign > ABIAlign);
Expand Down Expand Up @@ -5094,7 +5131,8 @@ static bool isIntegerLikeType(QualType Ty, ASTContext &Context,

ABIArgInfo ARMABIInfo::classifyReturnType(QualType RetTy,
bool isVariadic) const {
bool IsEffectivelyAAPCS_VFP = getABIKind() == AAPCS_VFP && !isVariadic;
bool IsEffectivelyAAPCS_VFP =
(getABIKind() == AAPCS_VFP || getABIKind() == AAPCS16_VFP) && !isVariadic;

if (RetTy->isVoidType())
return ABIArgInfo::getIgnore();
Expand Down Expand Up @@ -5159,7 +5197,7 @@ ABIArgInfo ARMABIInfo::classifyReturnType(QualType RetTy,
// Check for homogeneous aggregates with AAPCS-VFP.
if (IsEffectivelyAAPCS_VFP) {
const Type *Base = nullptr;
uint64_t Members;
uint64_t Members = 0;
if (isHomogeneousAggregate(RetTy, Base, Members)) {
assert(Base && "Base class should be set for homogeneous aggregate");
// Homogeneous Aggregates are returned directly.
Expand All @@ -5181,6 +5219,11 @@ ABIArgInfo ARMABIInfo::classifyReturnType(QualType RetTy,
if (Size <= 16)
return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext()));
return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext()));
} else if (Size <= 128 && getABIKind() == AAPCS16_VFP) {
llvm::Type *Int32Ty = llvm::Type::getInt32Ty(getVMContext());
llvm::Type *CoerceTy =
llvm::ArrayType::get(Int32Ty, llvm::RoundUpToAlignment(Size, 32) / 32);
return ABIArgInfo::getDirect(CoerceTy);
}

return getNaturalAlignIndirect(RetTy);
Expand Down Expand Up @@ -5238,9 +5281,18 @@ Address ARMABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,

// Use indirect if size of the illegal vector is bigger than 16 bytes.
bool IsIndirect = false;
const Type *Base = nullptr;
uint64_t Members = 0;
if (TyInfo.first > CharUnits::fromQuantity(16) && isIllegalVectorType(Ty)) {
IsIndirect = true;

// ARMv7k passes structs bigger than 16 bytes indirectly, in space
// allocated by the caller.
} else if (TyInfo.first > CharUnits::fromQuantity(16) &&
getABIKind() == ARMABIInfo::AAPCS16_VFP &&
!isHomogeneousAggregate(Ty, Base, Members)) {
IsIndirect = true;

// Otherwise, bound the type's ABI alignment.
// The ABI alignment for 64-bit or 128-bit vectors is 8 for AAPCS and 4 for
// APCS. For AAPCS, the ABI alignment is at least 4-byte and at most 8-byte.
Expand Down Expand Up @@ -7362,8 +7414,11 @@ const TargetCodeGenInfo &CodeGenModule::getTargetCodeGenInfo() {
}

ARMABIInfo::ABIKind Kind = ARMABIInfo::AAPCS;
if (getTarget().getABI() == "apcs-gnu")
StringRef ABIStr = getTarget().getABI();
if (ABIStr == "apcs-gnu")
Kind = ARMABIInfo::APCS;
else if (ABIStr == "aapcs16")
Kind = ARMABIInfo::AAPCS16_VFP;
else if (CodeGenOpts.FloatABI == "hard" ||
(CodeGenOpts.FloatABI != "soft" &&
Triple.getEnvironment() == llvm::Triple::GNUEABIHF))
Expand Down
88 changes: 88 additions & 0 deletions clang/test/CodeGen/armv7k-abi.c
Original file line number Diff line number Diff line change
@@ -0,0 +1,88 @@
// RUN: %clang_cc1 -triple thumbv7k-apple-watchos2.0 -target-abi aapcs16 %s -o - -emit-llvm | FileCheck %s

// Make sure 64 and 128 bit types are naturally aligned by the v7k ABI:

// CHECK: target datalayout = "e-m:o-p:32:32-i64:64-a:0:32-n32-S128"

typedef struct {
float arr[4];
} HFA;

// CHECK: define void @simple_hfa([4 x float] %h.coerce)
void simple_hfa(HFA h) {}

// CHECK: define %struct.HFA @return_simple_hfa
HFA return_simple_hfa() {}

typedef struct {
double arr[4];
} BigHFA;

// We don't want any padding type to be included by Clang when using the
// APCS-VFP ABI, that needs to be handled by LLVM if needed.

// CHECK: void @no_padding(i32 %r0, i32 %r1, i32 %r2, [4 x double] %d0_d3.coerce, [4 x double] %d4_d7.coerce, [4 x double] %sp.coerce, i64 %split)
void no_padding(int r0, int r1, int r2, BigHFA d0_d3, BigHFA d4_d7, BigHFA sp,
long long split) {}

// Structs larger than 16 bytes should be passed indirectly in space allocated
// by the caller (a pointer to this storage should be what occurs in the arg
// list).

typedef struct {
float x;
long long y;
double z;
} BigStruct;

// CHECK: define void @big_struct_indirect(%struct.BigStruct* %b)
void big_struct_indirect(BigStruct b) {}

// CHECK: define void @return_big_struct_indirect(%struct.BigStruct* noalias sret
BigStruct return_big_struct_indirect() {}

// Structs smaller than 16 bytes should be passed directly, and coerced to
// either [N x i32] or [N x i64] depending on alignment requirements.

typedef struct {
float x;
int y;
double z;
} SmallStruct;

// CHECK: define void @small_struct_direct([2 x i64] %s.coerce)
void small_struct_direct(SmallStruct s) {}

// CHECK: define [4 x i32] @return_small_struct_direct()
SmallStruct return_small_struct_direct() {}

typedef struct {
float x;
int y;
int z;
} SmallStructSmallAlign;

// CHECK: define void @small_struct_align_direct([3 x i32] %s.coerce)
void small_struct_align_direct(SmallStructSmallAlign s) {}

typedef struct {
char x;
short y;
} PaddedSmallStruct;

// CHECK: define i32 @return_padded_small_struct()
PaddedSmallStruct return_padded_small_struct() {}

typedef struct {
char arr[7];
} OddlySizedStruct;

// CHECK: define [2 x i32] @return_oddly_sized_struct()
OddlySizedStruct return_oddly_sized_struct() {}

// CHECK: define double @test_va_arg(i8* %l)
// CHECK: load double, double*
double test_va_arg(__builtin_va_list l) {
return __builtin_va_arg(l, double);
}

4 changes: 4 additions & 0 deletions clang/test/CodeGen/complex-math.c
Original file line number Diff line number Diff line change
Expand Up @@ -3,6 +3,7 @@
// RUN: %clang_cc1 %s -O1 -emit-llvm -triple i686-unknown-unknown -o - | FileCheck %s --check-prefix=X86
// RUN: %clang_cc1 %s -O1 -emit-llvm -triple powerpc-unknown-unknown -o - | FileCheck %s --check-prefix=PPC
// RUN: %clang_cc1 %s -O1 -emit-llvm -triple armv7-none-linux-gnueabihf -o - | FileCheck %s --check-prefix=ARM
// RUN: %clang_cc1 %s -O1 -emit-llvm -triple thumbv7k-apple-watchos2.0 -o - -target-abi aapcs16 | FileCheck %s --check-prefix=ARM7K

float _Complex add_float_rr(float a, float b) {
// X86-LABEL: @add_float_rr(
Expand Down Expand Up @@ -477,5 +478,8 @@ _Bool ne_float_cc(float _Complex a, float _Complex b) {
_Complex double foo(_Complex double a, _Complex double b) {
// ARM-LABEL: @foo(
// ARM: call arm_aapcscc { double, double } @__muldc3

// ARM7K-LABEL: @foo(
// ARM7K: call { double, double } @__muldc3
return a*b;
}
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