diff --git a/llvm/docs/AMDGPU/AMDGPUAsmGFX8.rst b/llvm/docs/AMDGPU/AMDGPUAsmGFX8.rst index bfd18c8095e7f3..2f3dcfa36137b1 100644 --- a/llvm/docs/AMDGPU/AMDGPUAsmGFX8.rst +++ b/llvm/docs/AMDGPU/AMDGPUAsmGFX8.rst @@ -190,7 +190,7 @@ EXP **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - exp :ref:`tgt`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`vsrc2`, :ref:`vsrc3` :ref:`done` :ref:`compr` :ref:`vm` + exp :ref:`tgt`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`vsrc2`, :ref:`vsrc3` :ref:`done` :ref:`compr` :ref:`vm` FLAT ---- @@ -247,95 +247,95 @@ MIMG **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - image_atomic_add :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` - image_atomic_and :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` - image_atomic_cmpswap :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` - image_atomic_dec :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` - image_atomic_inc :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` - image_atomic_or :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` - image_atomic_smax :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` - image_atomic_smin :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` - image_atomic_sub :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` - image_atomic_swap :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` - image_atomic_umax :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` - image_atomic_umin :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` - image_atomic_xor :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` - image_gather4 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_gather4_b :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_gather4_b_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_gather4_b_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_gather4_b_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_gather4_c :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_gather4_c_b :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_gather4_c_b_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_gather4_c_b_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_gather4_c_b_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_gather4_c_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_gather4_c_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_gather4_c_l :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_gather4_c_l_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_gather4_c_lz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_gather4_c_lz_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_gather4_c_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_gather4_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_gather4_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_gather4_l :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_gather4_l_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_gather4_lz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_gather4_lz_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_gather4_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_get_lod :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_get_resinfo :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_load :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_load_mip :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_load_mip_pck :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_load_mip_pck_sgn :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_load_pck :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_load_pck_sgn :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` - image_sample :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_b :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_b_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_b_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_b_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_c :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_c_b :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_c_b_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_c_b_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_c_b_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_c_cd :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_c_cd_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_c_cd_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_c_cd_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_c_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_c_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_c_d :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_c_d_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_c_d_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_c_d_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_c_l :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_c_l_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_c_lz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_c_lz_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_c_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_cd :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_cd_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_cd_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_cd_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_d :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_d_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_d_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_d_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_l :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_l_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_lz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_lz_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_sample_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` - image_store :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` :ref:`d16` - image_store_mip :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` :ref:`d16` - image_store_mip_pck :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` - image_store_pck :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + image_atomic_add :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + image_atomic_and :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + image_atomic_cmpswap :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + image_atomic_dec :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + image_atomic_inc :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + image_atomic_or :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + image_atomic_smax :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + image_atomic_smin :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + image_atomic_sub :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + image_atomic_swap :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + image_atomic_umax :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + image_atomic_umin :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + image_atomic_xor :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + image_gather4 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_gather4_b :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_gather4_b_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_gather4_b_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_gather4_b_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_gather4_c :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_gather4_c_b :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_gather4_c_b_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_gather4_c_b_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_gather4_c_b_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_gather4_c_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_gather4_c_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_gather4_c_l :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_gather4_c_l_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_gather4_c_lz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_gather4_c_lz_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_gather4_c_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_gather4_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_gather4_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_gather4_l :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_gather4_l_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_gather4_lz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_gather4_lz_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_gather4_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_get_lod :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_get_resinfo :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_load :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_load_mip :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_load_mip_pck :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_load_mip_pck_sgn :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_load_pck :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_load_pck_sgn :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` + image_sample :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_b :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_b_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_b_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_b_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_c :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_c_b :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_c_b_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_c_b_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_c_b_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_c_cd :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_c_cd_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_c_cd_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_c_cd_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_c_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_c_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_c_d :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_c_d_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_c_d_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_c_d_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_c_l :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_c_l_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_c_lz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_c_lz_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_c_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_cd :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_cd_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_cd_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_cd_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_d :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_d_cl :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_d_cl_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_d_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_l :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_l_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_lz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_lz_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_sample_o :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`ssamp` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16` + image_store :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` :ref:`d16` + image_store_mip :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` :ref:`d16` + image_store_mip_pck :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` + image_store_pck :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc` :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` MTBUF ----- @@ -344,22 +344,22 @@ MTBUF **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - tbuffer_load_format_d16_x :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - tbuffer_load_format_d16_xy :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - tbuffer_load_format_d16_xyz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - tbuffer_load_format_d16_xyzw :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - tbuffer_load_format_x :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - tbuffer_load_format_xy :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - tbuffer_load_format_xyz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - tbuffer_load_format_xyzw :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - tbuffer_store_format_d16_x :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - tbuffer_store_format_d16_xy :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - tbuffer_store_format_d16_xyz :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - tbuffer_store_format_d16_xyzw :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - tbuffer_store_format_x :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - tbuffer_store_format_xy :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - tbuffer_store_format_xyz :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - tbuffer_store_format_xyzw :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + tbuffer_load_format_d16_x :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + tbuffer_load_format_d16_xy :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + tbuffer_load_format_d16_xyz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + tbuffer_load_format_d16_xyzw :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + tbuffer_load_format_x :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + tbuffer_load_format_xy :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + tbuffer_load_format_xyz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + tbuffer_load_format_xyzw :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + tbuffer_store_format_d16_x :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + tbuffer_store_format_d16_xy :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + tbuffer_store_format_d16_xyz :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + tbuffer_store_format_d16_xyzw :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + tbuffer_store_format_x :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + tbuffer_store_format_xy :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + tbuffer_store_format_xyz :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + tbuffer_store_format_xyzw :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`fmt` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` MUBUF ----- @@ -367,64 +367,64 @@ MUBUF .. parsed-literal:: **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS** - \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - buffer_atomic_add :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_add_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_and :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_and_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_cmpswap :ref:`vdata`::ref:`dst`::ref:`b32x2`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_cmpswap_x2 :ref:`vdata`::ref:`dst`::ref:`b64x2`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_dec :ref:`vdata`::ref:`dst`::ref:`u32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_dec_x2 :ref:`vdata`::ref:`dst`::ref:`u64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_inc :ref:`vdata`::ref:`dst`::ref:`u32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_inc_x2 :ref:`vdata`::ref:`dst`::ref:`u64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_or :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_or_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_smax :ref:`vdata`::ref:`dst`::ref:`i32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_smax_x2 :ref:`vdata`::ref:`dst`::ref:`i64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_smin :ref:`vdata`::ref:`dst`::ref:`i32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_smin_x2 :ref:`vdata`::ref:`dst`::ref:`i64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_sub :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_sub_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_swap :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_swap_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_umax :ref:`vdata`::ref:`dst`::ref:`u32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_umax_x2 :ref:`vdata`::ref:`dst`::ref:`u64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_umin :ref:`vdata`::ref:`dst`::ref:`u32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_umin_x2 :ref:`vdata`::ref:`dst`::ref:`u64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_xor :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_atomic_xor_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_load_dword :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`lds` - buffer_load_dwordx2 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_load_dwordx3 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_load_dwordx4 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_load_format_d16_x :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_load_format_d16_xy :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_load_format_d16_xyz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_load_format_d16_xyzw :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_load_format_x :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`lds` - buffer_load_format_xy :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_load_format_xyz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_load_format_xyzw :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_load_sbyte :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`lds` - buffer_load_sshort :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`lds` - buffer_load_ubyte :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`lds` - buffer_load_ushort :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`lds` - buffer_store_byte :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_dword :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_dwordx2 :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_dwordx3 :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_dwordx4 :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_format_d16_x :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_format_d16_xy :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_format_d16_xyz :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_format_d16_xyzw :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_format_x :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_format_xy :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_format_xyz :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_format_xyzw :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` - buffer_store_lds_dword :ref:`srsrc`, :ref:`soffset` :ref:`offset12` :ref:`lds` :ref:`glc` :ref:`slc` - buffer_store_short :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| + buffer_atomic_add :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_add_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_and :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_and_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_cmpswap :ref:`vdata`::ref:`dst`::ref:`b32x2`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_cmpswap_x2 :ref:`vdata`::ref:`dst`::ref:`b64x2`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_dec :ref:`vdata`::ref:`dst`::ref:`u32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_dec_x2 :ref:`vdata`::ref:`dst`::ref:`u64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_inc :ref:`vdata`::ref:`dst`::ref:`u32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_inc_x2 :ref:`vdata`::ref:`dst`::ref:`u64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_or :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_or_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_smax :ref:`vdata`::ref:`dst`::ref:`i32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_smax_x2 :ref:`vdata`::ref:`dst`::ref:`i64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_smin :ref:`vdata`::ref:`dst`::ref:`i32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_smin_x2 :ref:`vdata`::ref:`dst`::ref:`i64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_sub :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_sub_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_swap :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_swap_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_umax :ref:`vdata`::ref:`dst`::ref:`u32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_umax_x2 :ref:`vdata`::ref:`dst`::ref:`u64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_umin :ref:`vdata`::ref:`dst`::ref:`u32`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_umin_x2 :ref:`vdata`::ref:`dst`::ref:`u64`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_xor :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_atomic_xor_x2 :ref:`vdata`::ref:`dst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_load_dword :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`lds` :ref:`tfe` + buffer_load_dwordx2 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`tfe` + buffer_load_dwordx3 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`tfe` + buffer_load_dwordx4 :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`tfe` + buffer_load_format_d16_x :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`tfe` + buffer_load_format_d16_xy :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`tfe` + buffer_load_format_d16_xyz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`tfe` + buffer_load_format_d16_xyzw :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`tfe` + buffer_load_format_x :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`lds` :ref:`tfe` + buffer_load_format_xy :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`tfe` + buffer_load_format_xyz :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`tfe` + buffer_load_format_xyzw :ref:`vdst`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`tfe` + buffer_load_sbyte :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`lds` :ref:`tfe` + buffer_load_sshort :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`lds` :ref:`tfe` + buffer_load_ubyte :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`lds` :ref:`tfe` + buffer_load_ushort :ref:`vdst`::ref:`opt`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` :ref:`lds` :ref:`tfe` + buffer_store_byte :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_dword :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_dwordx2 :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_dwordx3 :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_dwordx4 :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_format_d16_x :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_format_d16_xy :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_format_d16_xyz :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_format_d16_xyzw :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_format_x :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_format_xy :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_format_xyz :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_format_xyzw :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` + buffer_store_lds_dword :ref:`srsrc`, :ref:`soffset` :ref:`offset12` :ref:`lds` :ref:`glc` :ref:`slc` + buffer_store_short :ref:`vdata`, :ref:`vaddr`, :ref:`srsrc`, :ref:`soffset` :ref:`idxen` :ref:`offen` :ref:`offset12` :ref:`glc` :ref:`slc` buffer_wbinvl1 buffer_wbinvl1_vol @@ -435,30 +435,30 @@ SMEM **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - s_atc_probe :ref:`probe`, :ref:`sbase`, :ref:`soffset` - s_atc_probe_buffer :ref:`probe`, :ref:`sbase`, :ref:`soffset` - s_buffer_load_dword :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_load_dwordx16 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_load_dwordx2 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_load_dwordx4 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_load_dwordx8 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_store_dword :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_store_dwordx2 :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_buffer_store_dwordx4 :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_atc_probe :ref:`probe`, :ref:`sbase`, :ref:`soffset` + s_atc_probe_buffer :ref:`probe`, :ref:`sbase`, :ref:`soffset` + s_buffer_load_dword :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_load_dwordx16 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_load_dwordx2 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_load_dwordx4 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_load_dwordx8 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_store_dword :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_store_dwordx2 :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_buffer_store_dwordx4 :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`glc` s_dcache_inv s_dcache_inv_vol s_dcache_wb s_dcache_wb_vol - s_load_dword :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_load_dwordx16 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_load_dwordx2 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_load_dwordx4 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_load_dwordx8 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_load_dword :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_load_dwordx16 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_load_dwordx2 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_load_dwordx4 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_load_dwordx8 :ref:`sdst`, :ref:`sbase`, :ref:`soffset` :ref:`glc` s_memrealtime :ref:`sdst`::ref:`b64` s_memtime :ref:`sdst`::ref:`b64` - s_store_dword :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_store_dwordx2 :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`glc` - s_store_dwordx4 :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_store_dword :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_store_dwordx2 :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`glc` + s_store_dwordx4 :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`glc` SOP1 ---- @@ -604,24 +604,24 @@ SOPK **INSTRUCTION** **DST** **SRC0** **SRC1** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - s_addk_i32 :ref:`sdst`, :ref:`imm16` + s_addk_i32 :ref:`sdst`, :ref:`imm16` s_cbranch_i_fork :ref:`ssrc`, :ref:`label` - s_cmovk_i32 :ref:`sdst`, :ref:`imm16` - s_cmpk_eq_i32 :ref:`ssrc`, :ref:`imm16` - s_cmpk_eq_u32 :ref:`ssrc`, :ref:`imm16` - s_cmpk_ge_i32 :ref:`ssrc`, :ref:`imm16` - s_cmpk_ge_u32 :ref:`ssrc`, :ref:`imm16` - s_cmpk_gt_i32 :ref:`ssrc`, :ref:`imm16` - s_cmpk_gt_u32 :ref:`ssrc`, :ref:`imm16` - s_cmpk_le_i32 :ref:`ssrc`, :ref:`imm16` - s_cmpk_le_u32 :ref:`ssrc`, :ref:`imm16` - s_cmpk_lg_i32 :ref:`ssrc`, :ref:`imm16` - s_cmpk_lg_u32 :ref:`ssrc`, :ref:`imm16` - s_cmpk_lt_i32 :ref:`ssrc`, :ref:`imm16` - s_cmpk_lt_u32 :ref:`ssrc`, :ref:`imm16` + s_cmovk_i32 :ref:`sdst`, :ref:`imm16` + s_cmpk_eq_i32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_eq_u32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_ge_i32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_ge_u32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_gt_i32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_gt_u32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_le_i32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_le_u32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_lg_i32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_lg_u32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_lt_i32 :ref:`ssrc`, :ref:`imm16` + s_cmpk_lt_u32 :ref:`ssrc`, :ref:`imm16` s_getreg_b32 :ref:`sdst`, :ref:`hwreg` - s_movk_i32 :ref:`sdst`, :ref:`imm16` - s_mulk_i32 :ref:`sdst`, :ref:`imm16` + s_movk_i32 :ref:`sdst`, :ref:`imm16` + s_mulk_i32 :ref:`sdst`, :ref:`imm16` s_setreg_b32 :ref:`hwreg`, :ref:`ssrc` s_setreg_imm32_b32 :ref:`hwreg`, :ref:`simm32` @@ -644,21 +644,21 @@ SOPP s_cbranch_scc1 :ref:`label` s_cbranch_vccnz :ref:`label` s_cbranch_vccz :ref:`label` - s_decperflevel :ref:`imm16` + s_decperflevel :ref:`imm16` s_endpgm s_endpgm_saved s_icache_inv - s_incperflevel :ref:`imm16` - s_nop :ref:`imm16` + s_incperflevel :ref:`imm16` + s_nop :ref:`imm16` s_sendmsg :ref:`msg` s_sendmsghalt :ref:`msg` s_set_gpr_idx_mode :ref:`imask` s_set_gpr_idx_off - s_sethalt :ref:`imm16` - s_setkill :ref:`imm16` - s_setprio :ref:`imm16` - s_sleep :ref:`imm16` - s_trap :ref:`imm16` + s_sethalt :ref:`imm16` + s_setkill :ref:`imm16` + s_setprio :ref:`imm16` + s_sleep :ref:`imm16` + s_trap :ref:`imm16` s_ttracedata s_waitcnt :ref:`waitcnt` s_wakeup @@ -683,184 +683,184 @@ VOP1 \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| v_bfrev_b32 :ref:`vdst`, :ref:`src` v_bfrev_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_bfrev_b32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_bfrev_b32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_ceil_f16 :ref:`vdst`, :ref:`src` - v_ceil_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_ceil_f16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_ceil_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_ceil_f16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_ceil_f32 :ref:`vdst`, :ref:`src` - v_ceil_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_ceil_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_ceil_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_ceil_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_ceil_f64 :ref:`vdst`, :ref:`src` v_clrexcp v_cos_f16 :ref:`vdst`, :ref:`src` - v_cos_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_cos_f16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cos_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_cos_f16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_cos_f32 :ref:`vdst`, :ref:`src` - v_cos_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_cos_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cos_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_cos_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_cvt_f16_f32 :ref:`vdst`, :ref:`src` - v_cvt_f16_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_cvt_f16_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_f16_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_cvt_f16_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_cvt_f16_i16 :ref:`vdst`, :ref:`src` v_cvt_f16_i16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_cvt_f16_i16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_f16_i16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_cvt_f16_u16 :ref:`vdst`, :ref:`src` v_cvt_f16_u16_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_cvt_f16_u16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_f16_u16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_cvt_f32_f16 :ref:`vdst`, :ref:`src` - v_cvt_f32_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_cvt_f32_f16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_f32_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_cvt_f32_f16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_cvt_f32_f64 :ref:`vdst`, :ref:`src` v_cvt_f32_i32 :ref:`vdst`, :ref:`src` v_cvt_f32_i32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_cvt_f32_i32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_f32_i32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_cvt_f32_u32 :ref:`vdst`, :ref:`src` v_cvt_f32_u32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_cvt_f32_u32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_f32_u32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_cvt_f32_ubyte0 :ref:`vdst`, :ref:`src` v_cvt_f32_ubyte0_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_cvt_f32_ubyte0_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_f32_ubyte0_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_cvt_f32_ubyte1 :ref:`vdst`, :ref:`src` v_cvt_f32_ubyte1_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_cvt_f32_ubyte1_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_f32_ubyte1_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_cvt_f32_ubyte2 :ref:`vdst`, :ref:`src` v_cvt_f32_ubyte2_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_cvt_f32_ubyte2_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_f32_ubyte2_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_cvt_f32_ubyte3 :ref:`vdst`, :ref:`src` v_cvt_f32_ubyte3_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_cvt_f32_ubyte3_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_f32_ubyte3_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_cvt_f64_f32 :ref:`vdst`, :ref:`src` v_cvt_f64_i32 :ref:`vdst`, :ref:`src` v_cvt_f64_u32 :ref:`vdst`, :ref:`src` v_cvt_flr_i32_f32 :ref:`vdst`, :ref:`src` - v_cvt_flr_i32_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_cvt_flr_i32_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_flr_i32_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_cvt_flr_i32_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_cvt_i16_f16 :ref:`vdst`, :ref:`src` - v_cvt_i16_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_cvt_i16_f16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_i16_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_cvt_i16_f16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_cvt_i32_f32 :ref:`vdst`, :ref:`src` - v_cvt_i32_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_cvt_i32_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_i32_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_cvt_i32_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_cvt_i32_f64 :ref:`vdst`, :ref:`src` v_cvt_off_f32_i4 :ref:`vdst`, :ref:`src` v_cvt_off_f32_i4_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_cvt_off_f32_i4_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_off_f32_i4_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_cvt_rpi_i32_f32 :ref:`vdst`, :ref:`src` - v_cvt_rpi_i32_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_cvt_rpi_i32_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_rpi_i32_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_cvt_rpi_i32_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_cvt_u16_f16 :ref:`vdst`, :ref:`src` - v_cvt_u16_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_cvt_u16_f16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_u16_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_cvt_u16_f16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_cvt_u32_f32 :ref:`vdst`, :ref:`src` - v_cvt_u32_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_cvt_u32_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_cvt_u32_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_cvt_u32_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_cvt_u32_f64 :ref:`vdst`, :ref:`src` v_exp_f16 :ref:`vdst`, :ref:`src` - v_exp_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_exp_f16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_exp_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_exp_f16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_exp_f32 :ref:`vdst`, :ref:`src` - v_exp_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_exp_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_exp_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_exp_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_exp_legacy_f32 :ref:`vdst`, :ref:`src` - v_exp_legacy_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_exp_legacy_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_exp_legacy_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_exp_legacy_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_ffbh_i32 :ref:`vdst`, :ref:`src` v_ffbh_i32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_ffbh_i32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_ffbh_i32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_ffbh_u32 :ref:`vdst`, :ref:`src` v_ffbh_u32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_ffbh_u32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_ffbh_u32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_ffbl_b32 :ref:`vdst`, :ref:`src` v_ffbl_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_ffbl_b32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_ffbl_b32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_floor_f16 :ref:`vdst`, :ref:`src` - v_floor_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_floor_f16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_floor_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_floor_f16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_floor_f32 :ref:`vdst`, :ref:`src` - v_floor_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_floor_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_floor_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_floor_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_floor_f64 :ref:`vdst`, :ref:`src` v_fract_f16 :ref:`vdst`, :ref:`src` - v_fract_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_fract_f16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_fract_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_fract_f16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_fract_f32 :ref:`vdst`, :ref:`src` - v_fract_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_fract_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_fract_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_fract_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_fract_f64 :ref:`vdst`, :ref:`src` v_frexp_exp_i16_f16 :ref:`vdst`, :ref:`src` - v_frexp_exp_i16_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_frexp_exp_i16_f16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_frexp_exp_i16_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_frexp_exp_i16_f16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_frexp_exp_i32_f32 :ref:`vdst`, :ref:`src` - v_frexp_exp_i32_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_frexp_exp_i32_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_frexp_exp_i32_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_frexp_exp_i32_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_frexp_exp_i32_f64 :ref:`vdst`, :ref:`src` v_frexp_mant_f16 :ref:`vdst`, :ref:`src` - v_frexp_mant_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_frexp_mant_f16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_frexp_mant_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_frexp_mant_f16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_frexp_mant_f32 :ref:`vdst`, :ref:`src` - v_frexp_mant_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_frexp_mant_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_frexp_mant_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_frexp_mant_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_frexp_mant_f64 :ref:`vdst`, :ref:`src` v_log_f16 :ref:`vdst`, :ref:`src` - v_log_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_log_f16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_log_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_log_f16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_log_f32 :ref:`vdst`, :ref:`src` - v_log_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_log_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_log_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_log_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_log_legacy_f32 :ref:`vdst`, :ref:`src` - v_log_legacy_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_log_legacy_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_log_legacy_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_log_legacy_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_mov_b32 :ref:`vdst`, :ref:`src` v_mov_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_mov_b32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_mov_b32_sdwa :ref:`vdst`, :ref:`vsrc` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_nop v_not_b32 :ref:`vdst`, :ref:`src` v_not_b32_dpp :ref:`vdst`, :ref:`vsrc` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_not_b32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_not_b32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_rcp_f16 :ref:`vdst`, :ref:`src` - v_rcp_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_rcp_f16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_rcp_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_rcp_f16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_rcp_f32 :ref:`vdst`, :ref:`src` - v_rcp_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_rcp_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_rcp_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_rcp_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_rcp_f64 :ref:`vdst`, :ref:`src` v_rcp_iflag_f32 :ref:`vdst`, :ref:`src` - v_rcp_iflag_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_rcp_iflag_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_rcp_iflag_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_rcp_iflag_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_readfirstlane_b32 :ref:`sdst`, :ref:`src` v_rndne_f16 :ref:`vdst`, :ref:`src` - v_rndne_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_rndne_f16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_rndne_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_rndne_f16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_rndne_f32 :ref:`vdst`, :ref:`src` - v_rndne_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_rndne_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_rndne_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_rndne_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_rndne_f64 :ref:`vdst`, :ref:`src` v_rsq_f16 :ref:`vdst`, :ref:`src` - v_rsq_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_rsq_f16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_rsq_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_rsq_f16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_rsq_f32 :ref:`vdst`, :ref:`src` - v_rsq_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_rsq_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_rsq_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_rsq_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_rsq_f64 :ref:`vdst`, :ref:`src` v_sin_f16 :ref:`vdst`, :ref:`src` - v_sin_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_sin_f16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_sin_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_sin_f16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_sin_f32 :ref:`vdst`, :ref:`src` - v_sin_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_sin_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_sin_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_sin_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_sqrt_f16 :ref:`vdst`, :ref:`src` - v_sqrt_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_sqrt_f16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_sqrt_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_sqrt_f16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_sqrt_f32 :ref:`vdst`, :ref:`src` - v_sqrt_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_sqrt_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_sqrt_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_sqrt_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_sqrt_f64 :ref:`vdst`, :ref:`src` v_trunc_f16 :ref:`vdst`, :ref:`src` - v_trunc_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_trunc_f16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_trunc_f16_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_trunc_f16_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_trunc_f32 :ref:`vdst`, :ref:`src` - v_trunc_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_trunc_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` + v_trunc_f32_dpp :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_trunc_f32_sdwa :ref:`vdst`, :ref:`vsrc`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` v_trunc_f64 :ref:`vdst`, :ref:`src` VOP2 @@ -871,153 +871,153 @@ VOP2 **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIFIERS** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| v_add_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_add_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_add_f16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_add_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_add_f16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_add_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_add_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_add_f32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_add_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_add_f32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_add_u16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` v_add_u16_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_add_u16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_add_u16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_add_u32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` v_add_u32_dpp :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_add_u32_sdwa :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_add_u32_sdwa :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_addc_u32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`, :ref:`vcc` v_addc_u32_dpp :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`vcc` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_addc_u32_sdwa :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`, :ref:`vcc` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_addc_u32_sdwa :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`, :ref:`vcc` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_and_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` v_and_b32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_and_b32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_and_b32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_ashrrev_i16 :ref:`vdst`, :ref:`src0`::ref:`u16`, :ref:`vsrc1` v_ashrrev_i16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`u16`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_ashrrev_i16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`u16`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_ashrrev_i16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`u16`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_ashrrev_i32 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`vsrc1` v_ashrrev_i32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`u32`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_ashrrev_i32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`u32`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_ashrrev_i32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`u32`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_cndmask_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`, :ref:`vcc` - v_cndmask_b32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`vcc` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_cndmask_b32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`, :ref:`vcc` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_cndmask_b32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`, :ref:`vcc` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_cndmask_b32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`, :ref:`vcc` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_ldexp_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`::ref:`i16` - v_ldexp_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`i16` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_ldexp_f16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`::ref:`i16` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_ldexp_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`i16` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_ldexp_f16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`::ref:`i16` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_lshlrev_b16 :ref:`vdst`, :ref:`src0`::ref:`u16`, :ref:`vsrc1` v_lshlrev_b16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`u16`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_lshlrev_b16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`u16`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_lshlrev_b16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`u16`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_lshlrev_b32 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`vsrc1` v_lshlrev_b32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`u32`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_lshlrev_b32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`u32`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_lshlrev_b32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`u32`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_lshrrev_b16 :ref:`vdst`, :ref:`src0`::ref:`u16`, :ref:`vsrc1` v_lshrrev_b16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`u16`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_lshrrev_b16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`u16`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_lshrrev_b16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`u16`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_lshrrev_b32 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`vsrc1` v_lshrrev_b32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`u32`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_lshrrev_b32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`u32`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_lshrrev_b32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`u32`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_mac_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_mac_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_mac_f16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_mac_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_mac_f16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_mac_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_mac_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_mac_f32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_mac_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_mac_f32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_madak_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`, :ref:`simm32` v_madak_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1`, :ref:`simm32` v_madmk_f16 :ref:`vdst`, :ref:`src0`, :ref:`simm32`, :ref:`vsrc2` v_madmk_f32 :ref:`vdst`, :ref:`src0`, :ref:`simm32`, :ref:`vsrc2` v_max_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_max_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_max_f16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_max_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_max_f16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_max_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_max_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_max_f32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_max_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_max_f32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_max_i16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` v_max_i16_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_max_i16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_max_i16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_max_i32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` v_max_i32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_max_i32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_max_i32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_max_u16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` v_max_u16_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_max_u16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_max_u16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_max_u32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` v_max_u32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_max_u32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_max_u32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_min_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_min_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_min_f16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_min_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_min_f16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_min_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_min_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_min_f32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_min_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_min_f32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_min_i16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` v_min_i16_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_min_i16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_min_i16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_min_i32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` v_min_i32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_min_i32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_min_i32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_min_u16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` v_min_u16_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_min_u16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_min_u16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_min_u32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` v_min_u32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_min_u32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_min_u32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_mul_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_mul_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_mul_f16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_mul_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_mul_f16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_mul_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_mul_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_mul_f32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_mul_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_mul_f32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_mul_hi_i32_i24 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` v_mul_hi_i32_i24_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_mul_hi_i32_i24_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_mul_hi_i32_i24_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_mul_hi_u32_u24 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` v_mul_hi_u32_u24_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_mul_hi_u32_u24_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_mul_hi_u32_u24_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_mul_i32_i24 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` v_mul_i32_i24_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_mul_i32_i24_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_mul_i32_i24_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_mul_legacy_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_mul_legacy_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_mul_legacy_f32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_mul_legacy_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_mul_legacy_f32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_mul_lo_u16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` v_mul_lo_u16_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_mul_lo_u16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_mul_lo_u16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_mul_u32_u24 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` v_mul_u32_u24_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_mul_u32_u24_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_mul_u32_u24_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_or_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` v_or_b32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_or_b32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_or_b32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_sub_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_sub_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_sub_f16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_sub_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_sub_f16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_sub_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_sub_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_sub_f32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_sub_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_sub_f32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_sub_u16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` v_sub_u16_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_sub_u16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_sub_u16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_sub_u32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` v_sub_u32_dpp :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_sub_u32_sdwa :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_sub_u32_sdwa :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_subb_u32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`, :ref:`vcc` v_subb_u32_dpp :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`vcc` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_subb_u32_sdwa :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`, :ref:`vcc` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_subb_u32_sdwa :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`, :ref:`vcc` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_subbrev_u32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`, :ref:`vcc` v_subbrev_u32_dpp :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`vcc` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_subbrev_u32_sdwa :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`, :ref:`vcc` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_subbrev_u32_sdwa :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`, :ref:`vcc` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_subrev_f16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_subrev_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_subrev_f16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_subrev_f16_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_subrev_f16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_subrev_f32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` - v_subrev_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_subrev_f32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_subrev_f32_dpp :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` + v_subrev_f32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_subrev_u16 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` v_subrev_u16_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_subrev_u16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_subrev_u16_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_subrev_u32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` v_subrev_u32_dpp :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_subrev_u32_sdwa :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_subrev_u32_sdwa :ref:`vdst`, :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` v_xor_b32 :ref:`vdst`, :ref:`src0`, :ref:`vsrc1` v_xor_b32_dpp :ref:`vdst`, :ref:`vsrc0`, :ref:`vsrc1` :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl` - v_xor_b32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` + v_xor_b32_sdwa :ref:`vdst`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel` VOP3 ---- @@ -1026,9 +1026,9 @@ VOP3 **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIFIERS** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| - v_add_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_add_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_add_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_add_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_add_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_add_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` v_add_u16_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` v_add_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` v_addc_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`ssrc2` :ref:`clamp` @@ -1044,64 +1044,64 @@ VOP3 v_bfi_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` v_bfm_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1` v_bfrev_b32_e64 :ref:`vdst`, :ref:`src` - v_ceil_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_ceil_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_ceil_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_ceil_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_ceil_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_ceil_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` v_clrexcp_e64 - v_cmp_class_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` - v_cmp_class_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` - v_cmp_class_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` - v_cmp_eq_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_eq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_eq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_class_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` + v_cmp_class_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` + v_cmp_class_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` + v_cmp_eq_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_eq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_eq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` v_cmp_eq_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` v_cmp_eq_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` v_cmp_eq_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` v_cmp_eq_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` v_cmp_eq_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` v_cmp_eq_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_f_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_f_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_f_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_f_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_f_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_f_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` v_cmp_f_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` v_cmp_f_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` v_cmp_f_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` v_cmp_f_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` v_cmp_f_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` v_cmp_f_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_ge_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_ge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_ge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_ge_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_ge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_ge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` v_cmp_ge_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` v_cmp_ge_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` v_cmp_ge_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` v_cmp_ge_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` v_cmp_ge_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` v_cmp_ge_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_gt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_gt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_gt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_gt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_gt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_gt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` v_cmp_gt_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` v_cmp_gt_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` v_cmp_gt_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` v_cmp_gt_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` v_cmp_gt_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` v_cmp_gt_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_le_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_le_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_le_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_le_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_le_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_le_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` v_cmp_le_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` v_cmp_le_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` v_cmp_le_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` v_cmp_le_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` v_cmp_le_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` v_cmp_le_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_lg_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_lg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_lg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_lt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_lt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_lt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_lg_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_lg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_lg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_lt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_lt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_lt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` v_cmp_lt_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` v_cmp_lt_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` v_cmp_lt_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` @@ -1114,93 +1114,93 @@ VOP3 v_cmp_ne_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` v_cmp_ne_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` v_cmp_ne_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_neq_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_neq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_neq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nge_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_ngt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_ngt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_ngt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nle_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nle_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nle_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nlg_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nlg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nlg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nlt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nlt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_nlt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_o_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_o_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_o_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_neq_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_neq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_neq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nge_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_ngt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_ngt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_ngt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nle_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nle_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nle_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nlg_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nlg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nlg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nlt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nlt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_nlt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_o_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_o_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_o_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` v_cmp_t_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` v_cmp_t_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` v_cmp_t_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` v_cmp_t_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` v_cmp_t_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` v_cmp_t_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmp_tru_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_tru_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_tru_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_u_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_u_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmp_u_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_class_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` - v_cmpx_class_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` - v_cmpx_class_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` - v_cmpx_eq_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_eq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_eq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_tru_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_tru_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_tru_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_u_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_u_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmp_u_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_class_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` + v_cmpx_class_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` + v_cmpx_class_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`b32` + v_cmpx_eq_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_eq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_eq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` v_cmpx_eq_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` v_cmpx_eq_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` v_cmpx_eq_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` v_cmpx_eq_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` v_cmpx_eq_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` v_cmpx_eq_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_f_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_f_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_f_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_f_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_f_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_f_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` v_cmpx_f_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` v_cmpx_f_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` v_cmpx_f_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` v_cmpx_f_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` v_cmpx_f_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` v_cmpx_f_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_ge_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_ge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_ge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_ge_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_ge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_ge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` v_cmpx_ge_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` v_cmpx_ge_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` v_cmpx_ge_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` v_cmpx_ge_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` v_cmpx_ge_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` v_cmpx_ge_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_gt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_gt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_gt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_gt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_gt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_gt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` v_cmpx_gt_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` v_cmpx_gt_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` v_cmpx_gt_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` v_cmpx_gt_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` v_cmpx_gt_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` v_cmpx_gt_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_le_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_le_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_le_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_le_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_le_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_le_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` v_cmpx_le_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` v_cmpx_le_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` v_cmpx_le_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` v_cmpx_le_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` v_cmpx_le_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` v_cmpx_le_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_lg_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_lg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_lg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_lt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_lt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_lt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_lg_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_lg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_lg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_lt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_lt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_lt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` v_cmpx_lt_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` v_cmpx_lt_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` v_cmpx_lt_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` @@ -1213,155 +1213,155 @@ VOP3 v_cmpx_ne_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` v_cmpx_ne_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` v_cmpx_ne_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_neq_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_neq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_neq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nge_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_ngt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_ngt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_ngt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nle_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nle_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nle_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nlg_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nlg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nlg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nlt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nlt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_nlt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_o_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_o_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_o_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_neq_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_neq_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_neq_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nge_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nge_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nge_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_ngt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_ngt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_ngt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nle_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nle_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nle_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nlg_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nlg_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nlg_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nlt_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nlt_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_nlt_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_o_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_o_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_o_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` v_cmpx_t_i16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` v_cmpx_t_i32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` v_cmpx_t_i64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` v_cmpx_t_u16_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` v_cmpx_t_u32_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` v_cmpx_t_u64_e64 :ref:`sdst`, :ref:`src0`, :ref:`src1` - v_cmpx_tru_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_tru_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_tru_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_u_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_u_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cmpx_u_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` - v_cndmask_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`ssrc2` - v_cos_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_cos_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_cubeid_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_cubema_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_cubesc_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_cubetc_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_cvt_f16_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_cmpx_tru_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_tru_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_tru_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_u_f16_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_u_f32_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cmpx_u_f64_e64 :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` + v_cndmask_b32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`ssrc2` + v_cos_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_cos_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_cubeid_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_cubema_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_cubesc_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_cubetc_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_cvt_f16_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` v_cvt_f16_i16_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` v_cvt_f16_u16_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` - v_cvt_f32_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_cvt_f32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_cvt_f32_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_cvt_f32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` v_cvt_f32_i32_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` v_cvt_f32_u32_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` v_cvt_f32_ubyte0_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` v_cvt_f32_ubyte1_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` v_cvt_f32_ubyte2_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` v_cvt_f32_ubyte3_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` - v_cvt_f64_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_cvt_f64_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` v_cvt_f64_i32_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` v_cvt_f64_u32_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` - v_cvt_flr_i32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` - v_cvt_i16_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` - v_cvt_i32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` - v_cvt_i32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` + v_cvt_flr_i32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` + v_cvt_i16_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` + v_cvt_i32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` + v_cvt_i32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` v_cvt_off_f32_i4_e64 :ref:`vdst`, :ref:`src` :ref:`clamp` :ref:`omod` v_cvt_pk_i16_i32 :ref:`vdst`, :ref:`src0`::ref:`i32`, :ref:`src1`::ref:`i32` v_cvt_pk_u16_u32 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1`::ref:`u32` - v_cvt_pk_u8_f32 :ref:`vdst`::ref:`b32`, :ref:`src0`::ref:`m`::ref:`f32`, :ref:`src1`::ref:`u32`, :ref:`src2`::ref:`u32` - v_cvt_pkaccum_u8_f32 :ref:`vdst`::ref:`b32`, :ref:`src0`::ref:`m`::ref:`f32`, :ref:`src1`::ref:`u32` - v_cvt_pknorm_i16_f32 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`f32`, :ref:`src1`::ref:`m`::ref:`f32` - v_cvt_pknorm_u16_f32 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`f32`, :ref:`src1`::ref:`m`::ref:`f32` - v_cvt_pkrtz_f16_f32 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`f32`, :ref:`src1`::ref:`m`::ref:`f32` - v_cvt_rpi_i32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` - v_cvt_u16_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` - v_cvt_u32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` - v_cvt_u32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` - v_div_fixup_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_div_fixup_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_div_fixup_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_div_fmas_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_div_fmas_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_cvt_pk_u8_f32 :ref:`vdst`::ref:`b32`, :ref:`src0`::ref:`m`::ref:`f32`, :ref:`src1`::ref:`u32`, :ref:`src2`::ref:`u32` + v_cvt_pkaccum_u8_f32 :ref:`vdst`::ref:`b32`, :ref:`src0`::ref:`m`::ref:`f32`, :ref:`src1`::ref:`u32` + v_cvt_pknorm_i16_f32 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`f32`, :ref:`src1`::ref:`m`::ref:`f32` + v_cvt_pknorm_u16_f32 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`f32`, :ref:`src1`::ref:`m`::ref:`f32` + v_cvt_pkrtz_f16_f32 :ref:`vdst`, :ref:`src0`::ref:`m`::ref:`f32`, :ref:`src1`::ref:`m`::ref:`f32` + v_cvt_rpi_i32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` + v_cvt_u16_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` + v_cvt_u32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` + v_cvt_u32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` + v_div_fixup_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_div_fixup_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_div_fixup_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_div_fmas_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_div_fmas_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` v_div_scale_f32 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`src1`, :ref:`src2` v_div_scale_f64 :ref:`vdst`, :ref:`vcc`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_exp_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_exp_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_exp_legacy_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_exp_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_exp_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_exp_legacy_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` v_ffbh_i32_e64 :ref:`vdst`, :ref:`src` v_ffbh_u32_e64 :ref:`vdst`, :ref:`src` v_ffbl_b32_e64 :ref:`vdst`, :ref:`src` - v_floor_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_floor_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_floor_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_fma_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_fma_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_fma_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_fract_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_fract_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_fract_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_frexp_exp_i16_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` - v_frexp_exp_i32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` - v_frexp_exp_i32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` - v_frexp_mant_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_frexp_mant_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_frexp_mant_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_floor_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_floor_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_floor_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_fma_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_fma_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_fma_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_fract_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_fract_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_fract_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_frexp_exp_i16_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` + v_frexp_exp_i32_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` + v_frexp_exp_i32_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` + v_frexp_mant_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_frexp_mant_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_frexp_mant_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` v_interp_mov_f32_e64 :ref:`vdst`, :ref:`param`::ref:`b32`, :ref:`attr`::ref:`b32` :ref:`clamp` :ref:`omod` - v_interp_p1_f32_e64 :ref:`vdst`, :ref:`vsrc`::ref:`m`, :ref:`attr`::ref:`b32` :ref:`clamp` :ref:`omod` - v_interp_p1ll_f16 :ref:`vdst`::ref:`f32`, :ref:`vsrc`::ref:`m`::ref:`f32`, :ref:`attr`::ref:`b32` :ref:`high` :ref:`clamp` :ref:`omod` - v_interp_p1lv_f16 :ref:`vdst`::ref:`f32`, :ref:`vsrc0`::ref:`m`::ref:`f32`, :ref:`attr`::ref:`b32`, :ref:`vsrc2`::ref:`m`::ref:`f16x2` :ref:`high` :ref:`clamp` :ref:`omod` - v_interp_p2_f16 :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`f32`, :ref:`attr`::ref:`b32`, :ref:`vsrc2`::ref:`m`::ref:`f32` :ref:`high` :ref:`clamp` - v_interp_p2_f32_e64 :ref:`vdst`, :ref:`vsrc`::ref:`m`, :ref:`attr`::ref:`b32` :ref:`clamp` :ref:`omod` - v_ldexp_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`i16` :ref:`clamp` :ref:`omod` - v_ldexp_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`i32` :ref:`clamp` :ref:`omod` - v_ldexp_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`i32` :ref:`clamp` :ref:`omod` + v_interp_p1_f32_e64 :ref:`vdst`, :ref:`vsrc`::ref:`m`, :ref:`attr`::ref:`b32` :ref:`clamp` :ref:`omod` + v_interp_p1ll_f16 :ref:`vdst`::ref:`f32`, :ref:`vsrc`::ref:`m`::ref:`f32`, :ref:`attr`::ref:`b32` :ref:`high` :ref:`clamp` :ref:`omod` + v_interp_p1lv_f16 :ref:`vdst`::ref:`f32`, :ref:`vsrc0`::ref:`m`::ref:`f32`, :ref:`attr`::ref:`b32`, :ref:`vsrc2`::ref:`m`::ref:`f16x2` :ref:`high` :ref:`clamp` :ref:`omod` + v_interp_p2_f16 :ref:`vdst`, :ref:`vsrc0`::ref:`m`::ref:`f32`, :ref:`attr`::ref:`b32`, :ref:`vsrc2`::ref:`m`::ref:`f32` :ref:`high` :ref:`clamp` + v_interp_p2_f32_e64 :ref:`vdst`, :ref:`vsrc`::ref:`m`, :ref:`attr`::ref:`b32` :ref:`clamp` :ref:`omod` + v_ldexp_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`i16` :ref:`clamp` :ref:`omod` + v_ldexp_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`i32` :ref:`clamp` :ref:`omod` + v_ldexp_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`i32` :ref:`clamp` :ref:`omod` v_lerp_u8 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`b32`, :ref:`src1`::ref:`b32`, :ref:`src2`::ref:`b32` - v_log_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_log_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_log_legacy_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_log_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_log_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_log_legacy_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` v_lshlrev_b16_e64 :ref:`vdst`, :ref:`src0`::ref:`u16`, :ref:`src1` v_lshlrev_b32_e64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` v_lshlrev_b64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` v_lshrrev_b16_e64 :ref:`vdst`, :ref:`src0`::ref:`u16`, :ref:`src1` v_lshrrev_b32_e64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` v_lshrrev_b64 :ref:`vdst`, :ref:`src0`::ref:`u32`, :ref:`src1` - v_mac_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_mac_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_mad_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` - v_mad_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_mac_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_mac_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_mad_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_mad_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` v_mad_i16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`clamp` v_mad_i32_i24 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`i32` :ref:`clamp` v_mad_i64_i32 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`i64` :ref:`clamp` - v_mad_legacy_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_mad_legacy_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` v_mad_u16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`clamp` v_mad_u32_u24 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`u32` :ref:`clamp` v_mad_u64_u32 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`src2`::ref:`u64` :ref:`clamp` - v_max3_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_max3_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` v_max3_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` v_max3_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_max_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_max_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_max_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_max_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_max_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_max_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` v_max_i16_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` v_max_i32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` v_max_u16_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` v_max_u32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` v_mbcnt_hi_u32_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1` v_mbcnt_lo_u32_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1` - v_med3_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_med3_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` v_med3_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` v_med3_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_min3_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` + v_min3_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`clamp` :ref:`omod` v_min3_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` v_min3_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` - v_min_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_min_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_min_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_min_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_min_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_min_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` v_min_i16_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` v_min_i32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` v_min_u16_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` @@ -1370,15 +1370,15 @@ VOP3 v_mqsad_pk_u16_u8 :ref:`vdst`::ref:`u16x4`, :ref:`src0`::ref:`u8x8`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u16x4` :ref:`clamp` v_mqsad_u32_u8 :ref:`vdst`::ref:`u32x4`, :ref:`src0`::ref:`u8x8`, :ref:`src1`::ref:`u8x4`, :ref:`vsrc2`::ref:`u32x4` :ref:`clamp` v_msad_u8 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`u8x4`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u32` :ref:`clamp` - v_mul_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_mul_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_mul_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_mul_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_mul_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_mul_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` v_mul_hi_i32 :ref:`vdst`, :ref:`src0`, :ref:`src1` v_mul_hi_i32_i24_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` v_mul_hi_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1` v_mul_hi_u32_u24_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` v_mul_i32_i24_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` - v_mul_legacy_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_mul_legacy_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` v_mul_lo_u16_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` v_mul_lo_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1` v_mul_u32_u24_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` @@ -1387,40 +1387,40 @@ VOP3 v_or_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` v_perm_b32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` v_qsad_pk_u16_u8 :ref:`vdst`::ref:`u16x4`, :ref:`src0`::ref:`u8x8`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u16x4` :ref:`clamp` - v_rcp_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_rcp_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_rcp_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_rcp_iflag_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rcp_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rcp_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rcp_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rcp_iflag_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` v_readlane_b32 :ref:`sdst`, :ref:`src0`, :ref:`ssrc1` - v_rndne_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_rndne_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_rndne_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_rsq_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_rsq_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_rsq_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rndne_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rndne_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rndne_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rsq_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rsq_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_rsq_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` v_sad_hi_u8 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`u8x4`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u32` :ref:`clamp` v_sad_u16 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`u16x2`, :ref:`src1`::ref:`u16x2`, :ref:`src2`::ref:`u32` :ref:`clamp` v_sad_u32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`clamp` v_sad_u8 :ref:`vdst`::ref:`u32`, :ref:`src0`::ref:`u8x4`, :ref:`src1`::ref:`u8x4`, :ref:`src2`::ref:`u32` :ref:`clamp` - v_sin_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_sin_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_sqrt_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_sqrt_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_sqrt_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_sub_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_sub_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_sin_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_sin_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_sqrt_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_sqrt_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_sqrt_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_sub_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_sub_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` v_sub_u16_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` v_sub_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` v_subb_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`ssrc2` :ref:`clamp` v_subbrev_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1`, :ref:`ssrc2` :ref:`clamp` - v_subrev_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` - v_subrev_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_subrev_f16_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` + v_subrev_f32_e64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`clamp` :ref:`omod` v_subrev_u16_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` v_subrev_u32_e64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`, :ref:`src1` :ref:`clamp` - v_trig_preop_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`u32` :ref:`clamp` :ref:`omod` - v_trunc_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_trunc_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` - v_trunc_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_trig_preop_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`u32` :ref:`clamp` :ref:`omod` + v_trunc_f16_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_trunc_f32_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` + v_trunc_f64_e64 :ref:`vdst`, :ref:`src`::ref:`m` :ref:`clamp` :ref:`omod` v_writelane_b32 :ref:`vdst`, :ref:`ssrc0`, :ref:`ssrc1` v_xor_b32_e64 :ref:`vdst`, :ref:`src0`, :ref:`src1` @@ -1432,334 +1432,334 @@ VOPC **INSTRUCTION** **DST** **SRC0** **SRC1** **MODIFIERS** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| v_cmp_class_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`::ref:`b32` - v_cmp_class_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`::ref:`b32` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_class_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`::ref:`b32` :ref:`src0_sel` :ref:`src1_sel` v_cmp_class_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`::ref:`b32` - v_cmp_class_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`::ref:`b32` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_class_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`::ref:`b32` :ref:`src0_sel` :ref:`src1_sel` v_cmp_class_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`::ref:`b32` v_cmp_eq_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_eq_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_eq_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` v_cmp_eq_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_eq_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_eq_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` v_cmp_eq_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` v_cmp_eq_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_eq_i16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_eq_i16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` v_cmp_eq_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_eq_i32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_eq_i32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` v_cmp_eq_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` v_cmp_eq_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_eq_u16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_eq_u16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` v_cmp_eq_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_eq_u32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_eq_u32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` v_cmp_eq_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` v_cmp_f_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_f_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_f_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` v_cmp_f_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_f_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_f_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` v_cmp_f_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` v_cmp_f_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_f_i16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_f_i16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` v_cmp_f_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_f_i32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_f_i32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` v_cmp_f_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` v_cmp_f_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_f_u16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_f_u16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` v_cmp_f_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_f_u32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_f_u32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` v_cmp_f_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` v_cmp_ge_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ge_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_ge_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` v_cmp_ge_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ge_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_ge_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` v_cmp_ge_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` v_cmp_ge_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ge_i16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_ge_i16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` v_cmp_ge_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ge_i32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_ge_i32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` v_cmp_ge_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` v_cmp_ge_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ge_u16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_ge_u16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` v_cmp_ge_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ge_u32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_ge_u32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` v_cmp_ge_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` v_cmp_gt_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_gt_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_gt_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` v_cmp_gt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_gt_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_gt_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` v_cmp_gt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` v_cmp_gt_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_gt_i16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_gt_i16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` v_cmp_gt_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_gt_i32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_gt_i32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` v_cmp_gt_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` v_cmp_gt_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_gt_u16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_gt_u16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` v_cmp_gt_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_gt_u32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_gt_u32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` v_cmp_gt_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` v_cmp_le_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_le_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_le_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` v_cmp_le_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_le_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_le_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` v_cmp_le_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` v_cmp_le_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_le_i16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_le_i16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` v_cmp_le_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_le_i32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_le_i32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` v_cmp_le_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` v_cmp_le_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_le_u16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_le_u16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` v_cmp_le_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_le_u32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_le_u32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` v_cmp_le_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` v_cmp_lg_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_lg_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_lg_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` v_cmp_lg_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_lg_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_lg_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` v_cmp_lg_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` v_cmp_lt_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_lt_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_lt_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` v_cmp_lt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_lt_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_lt_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` v_cmp_lt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` v_cmp_lt_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_lt_i16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_lt_i16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` v_cmp_lt_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_lt_i32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_lt_i32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` v_cmp_lt_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` v_cmp_lt_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_lt_u16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_lt_u16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` v_cmp_lt_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_lt_u32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_lt_u32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` v_cmp_lt_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` v_cmp_ne_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ne_i16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_ne_i16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` v_cmp_ne_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ne_i32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_ne_i32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` v_cmp_ne_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` v_cmp_ne_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ne_u16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_ne_u16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` v_cmp_ne_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ne_u32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_ne_u32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` v_cmp_ne_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` v_cmp_neq_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_neq_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_neq_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` v_cmp_neq_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_neq_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_neq_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` v_cmp_neq_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` v_cmp_nge_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_nge_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_nge_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` v_cmp_nge_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_nge_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_nge_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` v_cmp_nge_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` v_cmp_ngt_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ngt_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_ngt_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` v_cmp_ngt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_ngt_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_ngt_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` v_cmp_ngt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` v_cmp_nle_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_nle_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_nle_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` v_cmp_nle_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_nle_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_nle_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` v_cmp_nle_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` v_cmp_nlg_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_nlg_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_nlg_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` v_cmp_nlg_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_nlg_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_nlg_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` v_cmp_nlg_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` v_cmp_nlt_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_nlt_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_nlt_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` v_cmp_nlt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_nlt_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_nlt_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` v_cmp_nlt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` v_cmp_o_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_o_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_o_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` v_cmp_o_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_o_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_o_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` v_cmp_o_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` v_cmp_t_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_t_i16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_t_i16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` v_cmp_t_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_t_i32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_t_i32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` v_cmp_t_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` v_cmp_t_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_t_u16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_t_u16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` v_cmp_t_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_t_u32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_t_u32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` v_cmp_t_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` v_cmp_tru_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_tru_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_tru_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` v_cmp_tru_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_tru_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_tru_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` v_cmp_tru_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` v_cmp_u_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_u_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_u_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` v_cmp_u_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmp_u_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmp_u_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` v_cmp_u_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` v_cmpx_class_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`::ref:`b32` - v_cmpx_class_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`::ref:`b32` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_class_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`::ref:`b32` :ref:`src0_sel` :ref:`src1_sel` v_cmpx_class_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`::ref:`b32` - v_cmpx_class_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`::ref:`b32` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_class_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m`::ref:`b32` :ref:`src0_sel` :ref:`src1_sel` v_cmpx_class_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1`::ref:`b32` v_cmpx_eq_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_eq_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_eq_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` v_cmpx_eq_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_eq_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_eq_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` v_cmpx_eq_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` v_cmpx_eq_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_eq_i16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_eq_i16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` v_cmpx_eq_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_eq_i32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_eq_i32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` v_cmpx_eq_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` v_cmpx_eq_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_eq_u16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_eq_u16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` v_cmpx_eq_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_eq_u32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_eq_u32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` v_cmpx_eq_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` v_cmpx_f_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_f_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_f_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` v_cmpx_f_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_f_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_f_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` v_cmpx_f_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` v_cmpx_f_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_f_i16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_f_i16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` v_cmpx_f_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_f_i32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_f_i32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` v_cmpx_f_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` v_cmpx_f_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_f_u16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_f_u16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` v_cmpx_f_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_f_u32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_f_u32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` v_cmpx_f_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` v_cmpx_ge_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_ge_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_ge_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` v_cmpx_ge_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_ge_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_ge_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` v_cmpx_ge_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` v_cmpx_ge_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_ge_i16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_ge_i16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` v_cmpx_ge_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_ge_i32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_ge_i32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` v_cmpx_ge_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` v_cmpx_ge_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_ge_u16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_ge_u16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` v_cmpx_ge_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_ge_u32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_ge_u32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` v_cmpx_ge_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` v_cmpx_gt_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_gt_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_gt_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` v_cmpx_gt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_gt_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_gt_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` v_cmpx_gt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` v_cmpx_gt_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_gt_i16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_gt_i16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` v_cmpx_gt_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_gt_i32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_gt_i32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` v_cmpx_gt_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` v_cmpx_gt_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_gt_u16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_gt_u16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` v_cmpx_gt_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_gt_u32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_gt_u32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` v_cmpx_gt_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` v_cmpx_le_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_le_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_le_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` v_cmpx_le_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_le_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_le_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` v_cmpx_le_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` v_cmpx_le_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_le_i16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_le_i16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` v_cmpx_le_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_le_i32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_le_i32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` v_cmpx_le_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` v_cmpx_le_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_le_u16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_le_u16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` v_cmpx_le_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_le_u32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_le_u32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` v_cmpx_le_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` v_cmpx_lg_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_lg_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_lg_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` v_cmpx_lg_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_lg_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_lg_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` v_cmpx_lg_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` v_cmpx_lt_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_lt_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_lt_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` v_cmpx_lt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_lt_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_lt_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` v_cmpx_lt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` v_cmpx_lt_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_lt_i16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_lt_i16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` v_cmpx_lt_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_lt_i32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_lt_i32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` v_cmpx_lt_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` v_cmpx_lt_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_lt_u16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_lt_u16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` v_cmpx_lt_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_lt_u32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_lt_u32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` v_cmpx_lt_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` v_cmpx_ne_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_ne_i16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_ne_i16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` v_cmpx_ne_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_ne_i32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_ne_i32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` v_cmpx_ne_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` v_cmpx_ne_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_ne_u16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_ne_u16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` v_cmpx_ne_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_ne_u32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_ne_u32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` v_cmpx_ne_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` v_cmpx_neq_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_neq_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_neq_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` v_cmpx_neq_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_neq_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_neq_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` v_cmpx_neq_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` v_cmpx_nge_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_nge_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_nge_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` v_cmpx_nge_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_nge_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_nge_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` v_cmpx_nge_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` v_cmpx_ngt_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_ngt_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_ngt_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` v_cmpx_ngt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_ngt_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_ngt_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` v_cmpx_ngt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` v_cmpx_nle_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_nle_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_nle_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` v_cmpx_nle_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_nle_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_nle_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` v_cmpx_nle_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` v_cmpx_nlg_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_nlg_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_nlg_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` v_cmpx_nlg_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_nlg_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_nlg_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` v_cmpx_nlg_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` v_cmpx_nlt_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_nlt_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_nlt_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` v_cmpx_nlt_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_nlt_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_nlt_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` v_cmpx_nlt_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` v_cmpx_o_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_o_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_o_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` v_cmpx_o_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_o_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_o_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` v_cmpx_o_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` v_cmpx_t_i16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_t_i16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_t_i16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` v_cmpx_t_i32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_t_i32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_t_i32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` v_cmpx_t_i64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` v_cmpx_t_u16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_t_u16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_t_u16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` v_cmpx_t_u32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_t_u32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_t_u32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`src0_sel` :ref:`src1_sel` v_cmpx_t_u64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` v_cmpx_tru_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_tru_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_tru_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` v_cmpx_tru_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_tru_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_tru_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` v_cmpx_tru_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` v_cmpx_u_f16 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_u_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_u_f16_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` v_cmpx_u_f32 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` - v_cmpx_u_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` + v_cmpx_u_f32_sdwa :ref:`vcc`, :ref:`vsrc0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`clamp` :ref:`src0_sel` :ref:`src1_sel` v_cmpx_u_f64 :ref:`vcc`, :ref:`src0`, :ref:`vsrc1` .. |---| unicode:: U+02014 .. em dash @@ -1771,18 +1771,18 @@ VOPC gfx8_dst gfx8_hwreg gfx8_imask - gfx8_imm16_73139a - gfx8_imm16_a04fb3 + gfx8_imm16_0533c2 + gfx8_imm16_169952 gfx8_label - gfx8_m_254bcb - gfx8_m_f5d306 + gfx8_m_28b494 + gfx8_m_c141fc gfx8_msg gfx8_opt_0d447d gfx8_opt_847aed gfx8_param gfx8_probe - gfx8_sbase_010ce0 gfx8_sbase_589eed + gfx8_sbase_b0aa25 gfx8_sdata_7cbd60 gfx8_sdata_c8788e gfx8_sdata_e587f5 @@ -1797,9 +1797,9 @@ VOPC gfx8_simm32_6f0844 gfx8_simm32_a3e80c gfx8_simm32_be0c1c - gfx8_soffset_499d5b + gfx8_soffset_32c2a9 gfx8_soffset_abb420 - gfx8_soffset_ac5750 + gfx8_soffset_b5af46 gfx8_src_021c9b gfx8_src_2dcf49 gfx8_src_39a989 @@ -1811,8 +1811,8 @@ VOPC gfx8_src_b38805 gfx8_src_d9175b gfx8_src_df6b53 + gfx8_srsrc_80eef6 gfx8_srsrc_cf7132 - gfx8_srsrc_e73d16 gfx8_ssamp gfx8_ssrc_0eec95 gfx8_ssrc_133cbc @@ -1825,50 +1825,57 @@ VOPC gfx8_ssrc_f48190 gfx8_tgt gfx8_type_deviation + gfx8_vaddr_887f26 gfx8_vaddr_9f7133 gfx8_vaddr_b73dc0 - gfx8_vaddr_e9b690 gfx8_vaddr_f20ee4 gfx8_vcc gfx8_vdata0_6802ce gfx8_vdata0_fd235e gfx8_vdata1_6802ce gfx8_vdata1_fd235e - gfx8_vdata_325b78 - gfx8_vdata_4d8ecf + gfx8_vdata_2d6239 + gfx8_vdata_4b260e gfx8_vdata_4f639e gfx8_vdata_56f215 + gfx8_vdata_629a92 gfx8_vdata_6802ce - gfx8_vdata_87fb90 + gfx8_vdata_84fab6 gfx8_vdata_886702 - gfx8_vdata_a9eee3 + gfx8_vdata_aa5a53 + gfx8_vdata_ad559c gfx8_vdata_aeb804 - gfx8_vdata_b2a787 gfx8_vdata_c08393 - gfx8_vdata_c61803 gfx8_vdata_e016a1 gfx8_vdata_f2bf57 gfx8_vdata_fd235e - gfx8_vdst_0b9599 - gfx8_vdst_3c54c3 - gfx8_vdst_3c6fb6 - gfx8_vdst_3d7dcf + gfx8_vdst_0ae2f9 + gfx8_vdst_2d89ba gfx8_vdst_463513 + gfx8_vdst_4730df gfx8_vdst_48e42f - gfx8_vdst_5d50a1 gfx8_vdst_69a144 - gfx8_vdst_7eb33e + gfx8_vdst_6f591e + gfx8_vdst_709347 + gfx8_vdst_81a6ed + gfx8_vdst_829fc5 gfx8_vdst_875645 gfx8_vdst_89680f + gfx8_vdst_9c54fe gfx8_vdst_a49b76 + gfx8_vdst_b61114 gfx8_vdst_bdb32f + gfx8_vdst_c360a5 gfx8_vdst_d0dc43 + gfx8_vdst_d71f1c gfx8_vdst_d7c57e - gfx8_vdst_d85497 - gfx8_vdst_e0515f + gfx8_vdst_d809e2 + gfx8_vdst_dd8a32 + gfx8_vdst_de9309 + gfx8_vdst_dfa6da gfx8_vdst_f47754 - gfx8_vsrc_533a4e gfx8_vsrc_6802ce + gfx8_vsrc_ba3116 gfx8_vsrc_e016a1 gfx8_vsrc_fd235e gfx8_waitcnt diff --git a/llvm/docs/AMDGPU/gfx8_hwreg.rst b/llvm/docs/AMDGPU/gfx8_hwreg.rst index 22cc81f4e820f6..2edca4ef54072b 100644 --- a/llvm/docs/AMDGPU/gfx8_hwreg.rst +++ b/llvm/docs/AMDGPU/gfx8_hwreg.rst @@ -24,27 +24,27 @@ The bits of this operand have the following meaning: This operand may be specified as one of the following: -* An :ref:`integer_number` or an :ref:`absolute_expression`. The value must be in the range 0..0xFFFF. -* An *hwreg* value described below. +* An :ref:`integer_number` or an :ref:`absolute_expression`. The value must be in the range from 0 to 0xFFFF. +* An *hwreg* value which is described below. - ==================================== ============================================================================ + ==================================== =============================================================================== Hwreg Value Syntax Description - ==================================== ============================================================================ - hwreg({0..63}) All bits of a register indicated by its *id*. - hwreg(<*name*>) All bits of a register indicated by its *name*. - hwreg({0..63}, {0..31}, {1..32}) Register bits indicated by register *id*, first bit *offset* and *size*. - hwreg(<*name*>, {0..31}, {1..32}) Register bits indicated by register *name*, first bit *offset* and *size*. - ==================================== ============================================================================ + ==================================== =============================================================================== + hwreg({0..63}) All bits of a register indicated by the register *id*. + hwreg(<*name*>) All bits of a register indicated by the register *name*. + hwreg({0..63}, {0..31}, {1..32}) Register bits indicated by the register *id*, first bit *offset* and *size*. + hwreg(<*name*>, {0..31}, {1..32}) Register bits indicated by the register *name*, first bit *offset* and *size*. + ==================================== =============================================================================== Numeric values may be specified as positive :ref:`integer numbers` or :ref:`absolute expressions`. -Defined register *names* include: +Predefined register *names* include: ============================== ========================================== Name Description ============================== ========================================== - HW_REG_MODE Shader writeable mode bits. + HW_REG_MODE Shader writable mode bits. HW_REG_STATUS Shader read-only status. HW_REG_TRAPSTS Trap status. HW_REG_HW_ID Id of wave, simd, compute unit, etc. diff --git a/llvm/docs/AMDGPU/gfx8_imask.rst b/llvm/docs/AMDGPU/gfx8_imask.rst index 7ee1d16e111aa0..b93895ad84600a 100644 --- a/llvm/docs/AMDGPU/gfx8_imask.rst +++ b/llvm/docs/AMDGPU/gfx8_imask.rst @@ -12,7 +12,7 @@ imask This operand is a mask which controls indexing mode for operands of subsequent instructions. Bits 0, 1 and 2 control indexing of *src0*, *src1* and *src2*, while bit 3 controls indexing of *dst*. -Value 1 enables indexing and value 0 disables it. +Value 1 enables indexing, and value 0 disables it. ===== ======================================== Bit Meaning @@ -25,31 +25,31 @@ Value 1 enables indexing and value 0 disables it. This operand may be specified as one of the following: -* An :ref:`integer_number` or an :ref:`absolute_expression`. The value must be in the range 0..15. -* A *gpr_idx* value described below. +* An :ref:`integer_number` or an :ref:`absolute_expression`. The value must be in the range from 0 to 15. +* A *gpr_idx* value which is described below. - ==================================== =========================================== + ==================================== ============================================= Gpr_idx Value Syntax Description - ==================================== =========================================== - gpr_idx(**) Enable indexing for specified *operands* + ==================================== ============================================= + gpr_idx(**) Enable indexing for the specified *operands* and disable it for the rest. - *Operands* is a comma-separated list of + *Operand list* is a comma-separated list of values which may include: - * "SRC0" - enable *src0* indexing. + * SRC0 - enable *src0* indexing. - * "SRC1" - enable *src1* indexing. + * SRC1 - enable *src1* indexing. - * "SRC2" - enable *src2* indexing. + * SRC2 - enable *src2* indexing. - * "DST" - enable *dst* indexing. + * DST - enable *dst* indexing. Each of these values may be specified only once. - *Operands* list may be empty; this syntax + *Operand list* may be empty; this syntax disables indexing for all operands. - ==================================== =========================================== + ==================================== ============================================= Examples: diff --git a/llvm/docs/AMDGPU/gfx8_imm16_a04fb3.rst b/llvm/docs/AMDGPU/gfx8_imm16_0533c2.rst similarity index 83% rename from llvm/docs/AMDGPU/gfx8_imm16_a04fb3.rst rename to llvm/docs/AMDGPU/gfx8_imm16_0533c2.rst index 606ca09f2fcaa8..f6301f1e56e721 100644 --- a/llvm/docs/AMDGPU/gfx8_imm16_a04fb3.rst +++ b/llvm/docs/AMDGPU/gfx8_imm16_0533c2.rst @@ -5,9 +5,9 @@ * * ************************************************** -.. _amdgpu_synid_gfx8_imm16_a04fb3: +.. _amdgpu_synid_gfx8_imm16_0533c2: imm16 ===== -An :ref:`integer_number` or an :ref:`absolute_expression`. The value must be in the range 0..65535. +An :ref:`integer_number` or an :ref:`absolute_expression`. The value must be in the range from -32768 to 65535. diff --git a/llvm/docs/AMDGPU/gfx8_imm16_73139a.rst b/llvm/docs/AMDGPU/gfx8_imm16_169952.rst similarity index 84% rename from llvm/docs/AMDGPU/gfx8_imm16_73139a.rst rename to llvm/docs/AMDGPU/gfx8_imm16_169952.rst index 13e48226055ed5..6af803bbbaf015 100644 --- a/llvm/docs/AMDGPU/gfx8_imm16_73139a.rst +++ b/llvm/docs/AMDGPU/gfx8_imm16_169952.rst @@ -5,9 +5,9 @@ * * ************************************************** -.. _amdgpu_synid_gfx8_imm16_73139a: +.. _amdgpu_synid_gfx8_imm16_169952: imm16 ===== -An :ref:`integer_number` or an :ref:`absolute_expression`. The value must be in the range -32768..65535. +An :ref:`integer_number` or an :ref:`absolute_expression`. The value must be in the range from 0 to 65535. diff --git a/llvm/docs/AMDGPU/gfx8_label.rst b/llvm/docs/AMDGPU/gfx8_label.rst index a3d3597021f734..844b320987c4f1 100644 --- a/llvm/docs/AMDGPU/gfx8_label.rst +++ b/llvm/docs/AMDGPU/gfx8_label.rst @@ -10,11 +10,11 @@ label ===== -A branch target which is a 16-bit signed integer treated as a PC-relative dword offset. +A branch target, which is a 16-bit signed integer treated as a PC-relative dword offset. This operand may be specified as one of the following: -* An :ref:`integer_number` or an :ref:`absolute_expression`. The value must be in the range -32768..65535. +* An :ref:`integer_number` or an :ref:`absolute_expression`. The value must be in the range from -32768 to 65535. * A :ref:`symbol` (for example, a label) representing a relocatable address in the same compilation unit where it is referred from. The value is handled as a 16-bit PC-relative dword offset to be resolved by a linker. Examples: diff --git a/llvm/docs/AMDGPU/gfx8_m_254bcb.rst b/llvm/docs/AMDGPU/gfx8_m_28b494.rst similarity index 70% rename from llvm/docs/AMDGPU/gfx8_m_254bcb.rst rename to llvm/docs/AMDGPU/gfx8_m_28b494.rst index f10e9f90c36684..ea00c2527f914e 100644 --- a/llvm/docs/AMDGPU/gfx8_m_254bcb.rst +++ b/llvm/docs/AMDGPU/gfx8_m_28b494.rst @@ -5,9 +5,9 @@ * * ************************************************** -.. _amdgpu_synid_gfx8_m_254bcb: +.. _amdgpu_synid_gfx8_m_28b494: m = -This operand may be used with integer operand modifier :ref:`sext`. +This operand may be used with an integer operand modifier :ref:`sext`. diff --git a/llvm/docs/AMDGPU/gfx8_m_f5d306.rst b/llvm/docs/AMDGPU/gfx8_m_c141fc.rst similarity index 78% rename from llvm/docs/AMDGPU/gfx8_m_f5d306.rst rename to llvm/docs/AMDGPU/gfx8_m_c141fc.rst index a4640e416fd5fa..39b11abd97c1ee 100644 --- a/llvm/docs/AMDGPU/gfx8_m_f5d306.rst +++ b/llvm/docs/AMDGPU/gfx8_m_c141fc.rst @@ -5,9 +5,9 @@ * * ************************************************** -.. _amdgpu_synid_gfx8_m_f5d306: +.. _amdgpu_synid_gfx8_m_c141fc: m = -This operand may be used with floating point operand modifiers :ref:`abs` and :ref:`neg`. +This operand may be used with floating-point operand modifiers :ref:`abs` and :ref:`neg`. diff --git a/llvm/docs/AMDGPU/gfx8_msg.rst b/llvm/docs/AMDGPU/gfx8_msg.rst index 5790e401439175..dec1839ee146a6 100644 --- a/llvm/docs/AMDGPU/gfx8_msg.rst +++ b/llvm/docs/AMDGPU/gfx8_msg.rst @@ -24,8 +24,8 @@ A 16-bit message code. The bits of this operand have the following meaning: This operand may be specified as one of the following: -* An :ref:`integer_number` or an :ref:`absolute_expression`. The value must be in the range 0..0xFFFF. -* A *sendmsg* value described below. +* An :ref:`integer_number` or an :ref:`absolute_expression`. The value must be in the range from 0 to 0xFFFF. +* A *sendmsg* value which is described below. ==================================== ==================================================== Sendmsg Value Syntax Description @@ -40,7 +40,7 @@ This operand may be specified as one of the following: *Op* may be specified using operation *name* or operation *id*. -Stream *id* is an integer in the range 0..3. +Stream *id* is an integer in the range from 0 to 3. Numeric values may be specified as positive :ref:`integer numbers` or :ref:`absolute expressions`. @@ -68,7 +68,7 @@ Each message type supports specific operations: *Sendmsg* arguments are validated depending on how *type* value is specified: * If message *type* is specified by name, arguments values must satisfy limitations detailed in the table above. -* If message *type* is specified as a number, each argument must not exceed corresponding value range (see the first table). +* If message *type* is specified as a number, each argument must not exceed the corresponding value range (see the first table). Examples: diff --git a/llvm/docs/AMDGPU/gfx8_sbase_010ce0.rst b/llvm/docs/AMDGPU/gfx8_sbase_b0aa25.rst similarity index 83% rename from llvm/docs/AMDGPU/gfx8_sbase_010ce0.rst rename to llvm/docs/AMDGPU/gfx8_sbase_b0aa25.rst index 28cd3af1ea55ba..ce56d1ff5c3d87 100644 --- a/llvm/docs/AMDGPU/gfx8_sbase_010ce0.rst +++ b/llvm/docs/AMDGPU/gfx8_sbase_b0aa25.rst @@ -5,12 +5,12 @@ * * ************************************************** -.. _amdgpu_synid_gfx8_sbase_010ce0: +.. _amdgpu_synid_gfx8_sbase_b0aa25: sbase ===== -A 128-bit buffer resource constant for scalar memory operations which provides a base address, a size and a stride. +A 128-bit buffer resource constant for scalar memory operations which provides a base address, a size, and a stride. *Size:* 4 dwords. diff --git a/llvm/docs/AMDGPU/gfx8_soffset_499d5b.rst b/llvm/docs/AMDGPU/gfx8_soffset_32c2a9.rst similarity index 75% rename from llvm/docs/AMDGPU/gfx8_soffset_499d5b.rst rename to llvm/docs/AMDGPU/gfx8_soffset_32c2a9.rst index 8bedf8b26cf24a..e192126dd5d974 100644 --- a/llvm/docs/AMDGPU/gfx8_soffset_499d5b.rst +++ b/llvm/docs/AMDGPU/gfx8_soffset_32c2a9.rst @@ -5,12 +5,12 @@ * * ************************************************** -.. _amdgpu_synid_gfx8_soffset_499d5b: +.. _amdgpu_synid_gfx8_soffset_32c2a9: soffset ======= -An unsigned byte offset added to the base address to get memory address. +An unsigned byte offset, which is added to the base address to get the memory address. *Size:* 1 dword. diff --git a/llvm/docs/AMDGPU/gfx8_soffset_ac5750.rst b/llvm/docs/AMDGPU/gfx8_soffset_b5af46.rst similarity index 82% rename from llvm/docs/AMDGPU/gfx8_soffset_ac5750.rst rename to llvm/docs/AMDGPU/gfx8_soffset_b5af46.rst index f31651f06af88a..8da9df8155d3b8 100644 --- a/llvm/docs/AMDGPU/gfx8_soffset_ac5750.rst +++ b/llvm/docs/AMDGPU/gfx8_soffset_b5af46.rst @@ -5,12 +5,12 @@ * * ************************************************** -.. _amdgpu_synid_gfx8_soffset_ac5750: +.. _amdgpu_synid_gfx8_soffset_b5af46: soffset ======= -An unsigned byte offset added to the base address to get memory address. +An unsigned byte offset, which is added to the base address to get the memory address. *Size:* 1 dword. diff --git a/llvm/docs/AMDGPU/gfx8_srsrc_e73d16.rst b/llvm/docs/AMDGPU/gfx8_srsrc_80eef6.rst similarity index 74% rename from llvm/docs/AMDGPU/gfx8_srsrc_e73d16.rst rename to llvm/docs/AMDGPU/gfx8_srsrc_80eef6.rst index 2400220c619637..579bb01854dbc0 100644 --- a/llvm/docs/AMDGPU/gfx8_srsrc_e73d16.rst +++ b/llvm/docs/AMDGPU/gfx8_srsrc_80eef6.rst @@ -5,12 +5,12 @@ * * ************************************************** -.. _amdgpu_synid_gfx8_srsrc_e73d16: +.. _amdgpu_synid_gfx8_srsrc_80eef6: srsrc ===== -Buffer resource constant which defines the address and characteristics of the buffer in memory. +Buffer resource constant, which defines the address and characteristics of the buffer in memory. *Size:* 4 dwords. diff --git a/llvm/docs/AMDGPU/gfx8_tgt.rst b/llvm/docs/AMDGPU/gfx8_tgt.rst index 0c3331367effc4..7da0a69d4812f5 100644 --- a/llvm/docs/AMDGPU/gfx8_tgt.rst +++ b/llvm/docs/AMDGPU/gfx8_tgt.rst @@ -21,3 +21,10 @@ An export target: mrtz Copy pixel depth (Z) data. null Copy nothing. ================== =================================== + +Examples: + +.. parsed-literal:: + + exp pos3 v1, v2, v3, v4 + exp mrt0 v1, v2, v3, v4 diff --git a/llvm/docs/AMDGPU/gfx8_type_deviation.rst b/llvm/docs/AMDGPU/gfx8_type_deviation.rst index c9de90bbe9d396..6f482370591432 100644 --- a/llvm/docs/AMDGPU/gfx8_type_deviation.rst +++ b/llvm/docs/AMDGPU/gfx8_type_deviation.rst @@ -10,4 +10,4 @@ Type Deviation ============== -*Type* of this operand differs from *type* :ref:`implied by the opcode`. This tag specifies actual operand *type*. +The *type* of this operand differs from the *type* :ref:`implied by the opcode`. This tag specifies the actual operand *type*. diff --git a/llvm/docs/AMDGPU/gfx8_vaddr_e9b690.rst b/llvm/docs/AMDGPU/gfx8_vaddr_887f26.rst similarity index 54% rename from llvm/docs/AMDGPU/gfx8_vaddr_e9b690.rst rename to llvm/docs/AMDGPU/gfx8_vaddr_887f26.rst index 391b44ce872406..8b0c706139c8f0 100644 --- a/llvm/docs/AMDGPU/gfx8_vaddr_e9b690.rst +++ b/llvm/docs/AMDGPU/gfx8_vaddr_887f26.rst @@ -5,17 +5,15 @@ * * ************************************************** -.. _amdgpu_synid_gfx8_vaddr_e9b690: +.. _amdgpu_synid_gfx8_vaddr_887f26: vaddr ===== Image address which includes from one to four dimensional coordinates and other data used to locate a position in the image. -*Size:* 1, 2, 3, 4, 8 or 16 dwords. Actual size depends on opcode and specific image being handled. +*Size:* 1-12 dwords. Actual size depends on opcode and specific image being handled. - Note 1. Image format and dimensions are encoded in the image resource constant but not in the instruction. - - Note 2. Actually image address size may vary from 1 to 13 dwords, but assembler currently supports a limited range of register sequences. + Note. Image format and dimensions are encoded in the image resource constant, but not in the instruction. *Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx8_vdata_c61803.rst b/llvm/docs/AMDGPU/gfx8_vdata_2d6239.rst similarity index 74% rename from llvm/docs/AMDGPU/gfx8_vdata_c61803.rst rename to llvm/docs/AMDGPU/gfx8_vdata_2d6239.rst index 5a7cc57317c714..bea256bd786981 100644 --- a/llvm/docs/AMDGPU/gfx8_vdata_c61803.rst +++ b/llvm/docs/AMDGPU/gfx8_vdata_2d6239.rst @@ -5,17 +5,17 @@ * * ************************************************** -.. _amdgpu_synid_gfx8_vdata_c61803: +.. _amdgpu_synid_gfx8_vdata_2d6239: vdata ===== Input data for an atomic instruction. -Optionally may serve as an output data: +Optionally, this operand may be used to store output data: * If :ref:`glc` is specified, gets the memory value before the operation. -*Size:* 1 dword by default. :ref:`tfe` adds 1 dword if specified. +*Size:* 4 dwords. *Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx8_vdata_87fb90.rst b/llvm/docs/AMDGPU/gfx8_vdata_4b260e.rst similarity index 74% rename from llvm/docs/AMDGPU/gfx8_vdata_87fb90.rst rename to llvm/docs/AMDGPU/gfx8_vdata_4b260e.rst index e83f36709c87f9..5c22d5e99341ae 100644 --- a/llvm/docs/AMDGPU/gfx8_vdata_87fb90.rst +++ b/llvm/docs/AMDGPU/gfx8_vdata_4b260e.rst @@ -5,17 +5,17 @@ * * ************************************************** -.. _amdgpu_synid_gfx8_vdata_87fb90: +.. _amdgpu_synid_gfx8_vdata_4b260e: vdata ===== Input data for an atomic instruction. -Optionally may serve as an output data: +Optionally, this operand may be used to store output data: * If :ref:`glc` is specified, gets the memory value before the operation. -*Size:* 4 dwords by default. :ref:`tfe` adds 1 dword if specified. +*Size:* 2 dwords. *Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx8_vdata_a9eee3.rst b/llvm/docs/AMDGPU/gfx8_vdata_629a92.rst similarity index 51% rename from llvm/docs/AMDGPU/gfx8_vdata_a9eee3.rst rename to llvm/docs/AMDGPU/gfx8_vdata_629a92.rst index 15e681593770d3..debf712a102995 100644 --- a/llvm/docs/AMDGPU/gfx8_vdata_a9eee3.rst +++ b/llvm/docs/AMDGPU/gfx8_vdata_629a92.rst @@ -5,7 +5,7 @@ * * ************************************************** -.. _amdgpu_synid_gfx8_vdata_a9eee3: +.. _amdgpu_synid_gfx8_vdata_629a92: vdata ===== @@ -14,10 +14,10 @@ Image data to store by an *image_store* instruction. *Size:* depends on :ref:`dmask` and :ref:`d16`: -* :ref:`dmask` may specify from 1 to 4 data elements. Each data element occupies either 32 bits or 16 bits depending on :ref:`d16`. -* :ref:`d16` has different meaning for GFX8.0 and GFX8.1: +* :ref:`dmask` may specify from 1 to 4 data elements. Each data element occupies either 32 bits or 16 bits, depending on :ref:`d16`. +* :ref:`d16` has different meanings for GFX8.0 and GFX8.1: - * For GFX8.0 this modifier does not affect size of data elements in registers. Data in registers are stored in low 16 bits, high 16 bits are unused. There is no packing. - * Starting from GFX8.1 this modifier specifies that data elements in registers are packed; each value occupies 16 bits. + * For GFX8.0, this modifier does not affect the size of data elements in registers. Values in registers are stored in low 16 bits, high 16 bits are unused. There is no packing. + * Starting from GFX8.1, this modifier specifies that values in registers are packed; each value occupies 16 bits. *Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx8_vdata_4d8ecf.rst b/llvm/docs/AMDGPU/gfx8_vdata_84fab6.rst similarity index 73% rename from llvm/docs/AMDGPU/gfx8_vdata_4d8ecf.rst rename to llvm/docs/AMDGPU/gfx8_vdata_84fab6.rst index 62fb38b729b488..295e70d5681103 100644 --- a/llvm/docs/AMDGPU/gfx8_vdata_4d8ecf.rst +++ b/llvm/docs/AMDGPU/gfx8_vdata_84fab6.rst @@ -5,22 +5,22 @@ * * ************************************************** -.. _amdgpu_synid_gfx8_vdata_4d8ecf: +.. _amdgpu_synid_gfx8_vdata_84fab6: vdata ===== Input data for an atomic instruction. -Optionally may serve as an output data: +Optionally, this operand may be used to store output data: * If :ref:`glc` is specified, gets the memory value before the operation. -*Size:* depends on :ref:`dmask` and :ref:`tfe`: +*Size:* depends on :ref:`dmask`: * :ref:`dmask` may specify 2 data elements for 32-bit-per-pixel surfaces or 4 data elements for 64-bit-per-pixel surfaces. Each data element occupies 1 dword. -* :ref:`tfe` adds 1 dword if specified. - Note: the surface data format is indicated in the image resource constant but not in the instruction. + + Note: the surface data format is indicated in the image resource constant, but not in the instruction. *Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx8_vdata_325b78.rst b/llvm/docs/AMDGPU/gfx8_vdata_aa5a53.rst similarity index 73% rename from llvm/docs/AMDGPU/gfx8_vdata_325b78.rst rename to llvm/docs/AMDGPU/gfx8_vdata_aa5a53.rst index 0389fc170ad73a..f2dec0b453b773 100644 --- a/llvm/docs/AMDGPU/gfx8_vdata_325b78.rst +++ b/llvm/docs/AMDGPU/gfx8_vdata_aa5a53.rst @@ -5,22 +5,22 @@ * * ************************************************** -.. _amdgpu_synid_gfx8_vdata_325b78: +.. _amdgpu_synid_gfx8_vdata_aa5a53: vdata ===== Input data for an atomic instruction. -Optionally may serve as an output data: +Optionally, this operand may be used to store output data: * If :ref:`glc` is specified, gets the memory value before the operation. -*Size:* depends on :ref:`dmask` and :ref:`tfe`: +*Size:* depends on :ref:`dmask`: * :ref:`dmask` may specify 1 data element for 32-bit-per-pixel surfaces or 2 data elements for 64-bit-per-pixel surfaces. Each data element occupies 1 dword. -* :ref:`tfe` adds 1 dword if specified. - Note: the surface data format is indicated in the image resource constant but not in the instruction. + + Note: the surface data format is indicated in the image resource constant, but not in the instruction. *Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx8_vdata_b2a787.rst b/llvm/docs/AMDGPU/gfx8_vdata_ad559c.rst similarity index 74% rename from llvm/docs/AMDGPU/gfx8_vdata_b2a787.rst rename to llvm/docs/AMDGPU/gfx8_vdata_ad559c.rst index bb232d58d815cd..aa2123157eb025 100644 --- a/llvm/docs/AMDGPU/gfx8_vdata_b2a787.rst +++ b/llvm/docs/AMDGPU/gfx8_vdata_ad559c.rst @@ -5,17 +5,17 @@ * * ************************************************** -.. _amdgpu_synid_gfx8_vdata_b2a787: +.. _amdgpu_synid_gfx8_vdata_ad559c: vdata ===== Input data for an atomic instruction. -Optionally may serve as an output data: +Optionally, this operand may be used to store output data: * If :ref:`glc` is specified, gets the memory value before the operation. -*Size:* 2 dwords by default. :ref:`tfe` adds 1 dword if specified. +*Size:* 1 dword. *Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx8_vdst_0ae2f9.rst b/llvm/docs/AMDGPU/gfx8_vdst_0ae2f9.rst new file mode 100644 index 00000000000000..5cc1243aa441cb --- /dev/null +++ b/llvm/docs/AMDGPU/gfx8_vdst_0ae2f9.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx8_vdst_0ae2f9: + +vdst +==== + +Instruction output: data read from a memory buffer and converted to 16-bit format. + +*Size:* 1 dword. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx8_vdst_7eb33e.rst b/llvm/docs/AMDGPU/gfx8_vdst_2d89ba.rst similarity index 83% rename from llvm/docs/AMDGPU/gfx8_vdst_7eb33e.rst rename to llvm/docs/AMDGPU/gfx8_vdst_2d89ba.rst index bbb3f0770ba223..0b5d1767141e59 100644 --- a/llvm/docs/AMDGPU/gfx8_vdst_7eb33e.rst +++ b/llvm/docs/AMDGPU/gfx8_vdst_2d89ba.rst @@ -5,17 +5,17 @@ * * ************************************************** -.. _amdgpu_synid_gfx8_vdst_7eb33e: +.. _amdgpu_synid_gfx8_vdst_2d89ba: vdst ==== -Instruction output: data read from a memory buffer and converted to a 16-bit format. +Instruction output: data read from a memory buffer and converted to 16-bit format. *Size:* depends on GFX8 GPU revision and :ref:`tfe`: * 4 dwords for GFX8.0. This H/W supports no packing. * 2 dwords for GFX8.1+. This H/W supports data packing. -* :ref:`tfe` adds one dword if specified. +* :ref:`tfe` adds 1 dword if specified. *Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx8_vdst_0b9599.rst b/llvm/docs/AMDGPU/gfx8_vdst_4730df.rst similarity index 50% rename from llvm/docs/AMDGPU/gfx8_vdst_0b9599.rst rename to llvm/docs/AMDGPU/gfx8_vdst_4730df.rst index 05b2017dd79e46..18ce3e2dd0602a 100644 --- a/llvm/docs/AMDGPU/gfx8_vdst_0b9599.rst +++ b/llvm/docs/AMDGPU/gfx8_vdst_4730df.rst @@ -5,20 +5,20 @@ * * ************************************************** -.. _amdgpu_synid_gfx8_vdst_0b9599: +.. _amdgpu_synid_gfx8_vdst_4730df: vdst ==== -Image data to load by an image instruction. +Image data to be loaded by an image instruction. *Size:* depends on :ref:`dmask`, :ref:`tfe` and :ref:`d16`: -* :ref:`dmask` may specify from 1 to 4 data elements. Each data element occupies either 32 bits or 16 bits depending on :ref:`d16`. -* :ref:`d16` has different meaning for GFX8.0 and GFX8.1: +* :ref:`dmask` may specify from 1 to 4 data elements. Each data element occupies either 32 bits or 16 bits, depending on :ref:`d16`. +* :ref:`d16` has different meanings for GFX8.0 and GFX8.1: - * For GFX8.0 this modifier does not affect size of data elements in registers. Data in registers are stored in low 16 bits, high 16 bits are unused. There is no packing. - * Starting from GFX8.1 this modifier specifies that data elements in registers are packed; each value occupies 16 bits. + * For GFX8.0, this modifier does not affect the size of data elements in registers. Values in registers are stored in low 16 bits, high 16 bits are unused. There is no packing. + * Starting from GFX8.1, this modifier specifies that values in registers are packed; each value occupies 16 bits. * :ref:`tfe` adds 1 dword if specified. diff --git a/llvm/docs/AMDGPU/gfx8_vdst_6f591e.rst b/llvm/docs/AMDGPU/gfx8_vdst_6f591e.rst new file mode 100644 index 00000000000000..a86a066a7e3216 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx8_vdst_6f591e.rst @@ -0,0 +1,20 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx8_vdst_6f591e: + +vdst +==== + +Instruction output: data read from a memory buffer and converted to 16-bit format. + +*Size:* depends on GFX8 GPU revision: + +* 4 dwords for GFX8.0. This H/W supports no packing. +* 2 dwords for GFX8.1+. This H/W supports data packing. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx8_vdst_5d50a1.rst b/llvm/docs/AMDGPU/gfx8_vdst_709347.rst similarity index 76% rename from llvm/docs/AMDGPU/gfx8_vdst_5d50a1.rst rename to llvm/docs/AMDGPU/gfx8_vdst_709347.rst index 3d9ebfc4e261a4..b1522fd4c00015 100644 --- a/llvm/docs/AMDGPU/gfx8_vdst_5d50a1.rst +++ b/llvm/docs/AMDGPU/gfx8_vdst_709347.rst @@ -5,13 +5,13 @@ * * ************************************************** -.. _amdgpu_synid_gfx8_vdst_5d50a1: +.. _amdgpu_synid_gfx8_vdst_709347: vdst ==== Instruction output: data read from a memory buffer. -*Size:* 1 dword by default. :ref:`tfe` adds 1 dword if specified. +*Size:* 1 dword. *Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx8_vdst_81a6ed.rst b/llvm/docs/AMDGPU/gfx8_vdst_81a6ed.rst new file mode 100644 index 00000000000000..2a84f1d5cc708e --- /dev/null +++ b/llvm/docs/AMDGPU/gfx8_vdst_81a6ed.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx8_vdst_81a6ed: + +vdst +==== + +Instruction output: data read from a memory buffer. + +*Size:* 3 dwords. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx8_vdst_829fc5.rst b/llvm/docs/AMDGPU/gfx8_vdst_829fc5.rst new file mode 100644 index 00000000000000..fe4f6e7899bf5a --- /dev/null +++ b/llvm/docs/AMDGPU/gfx8_vdst_829fc5.rst @@ -0,0 +1,26 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx8_vdst_829fc5: + +vdst +==== + +Image data to be loaded by an *image_gather4* instruction. + +*Size:* 4 data elements by default. Each data element occupies either 32 bits or 16 bits, depending on :ref:`d16`. + +:ref:`d16` and :ref:`tfe` affect operand size as follows: + +* :ref:`d16` has different meanings for GFX8.0 and GFX8.1: + + * For GFX8.0, this modifier does not affect the size of data elements in registers. Values in registers are stored in low 16 bits, high 16 bits are unused. There is no packing. + * Starting from GFX8.1, this modifier specifies that values in registers are packed; each value occupies 16 bits. + +* :ref:`tfe` adds 1 dword if specified. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx8_vdst_d85497.rst b/llvm/docs/AMDGPU/gfx8_vdst_9c54fe.rst similarity index 89% rename from llvm/docs/AMDGPU/gfx8_vdst_d85497.rst rename to llvm/docs/AMDGPU/gfx8_vdst_9c54fe.rst index 6e8f8817c715b2..bd05deede28743 100644 --- a/llvm/docs/AMDGPU/gfx8_vdst_d85497.rst +++ b/llvm/docs/AMDGPU/gfx8_vdst_9c54fe.rst @@ -5,12 +5,12 @@ * * ************************************************** -.. _amdgpu_synid_gfx8_vdst_d85497: +.. _amdgpu_synid_gfx8_vdst_9c54fe: vdst ==== -Instruction output: data read from a memory buffer and converted to a 16-bit format. +Instruction output: data read from a memory buffer and converted to 16-bit format. *Size:* 1 dword by default. :ref:`tfe` adds 1 dword if specified. diff --git a/llvm/docs/AMDGPU/gfx8_vdst_3c54c3.rst b/llvm/docs/AMDGPU/gfx8_vdst_b61114.rst similarity index 83% rename from llvm/docs/AMDGPU/gfx8_vdst_3c54c3.rst rename to llvm/docs/AMDGPU/gfx8_vdst_b61114.rst index b65417f81f6f9c..a60cd20f006fd2 100644 --- a/llvm/docs/AMDGPU/gfx8_vdst_3c54c3.rst +++ b/llvm/docs/AMDGPU/gfx8_vdst_b61114.rst @@ -5,17 +5,17 @@ * * ************************************************** -.. _amdgpu_synid_gfx8_vdst_3c54c3: +.. _amdgpu_synid_gfx8_vdst_b61114: vdst ==== -Instruction output: data read from a memory buffer and converted to a 16-bit format. +Instruction output: data read from a memory buffer and converted to 16-bit format. *Size:* depends on GFX8 GPU revision and :ref:`tfe`: * 2 dwords for GFX8.0. This H/W supports no packing. * 1 dword for GFX8.1+. This H/W supports data packing. -* :ref:`tfe` adds one dword if specified. +* :ref:`tfe` adds 1 dword if specified. *Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx8_vdst_c360a5.rst b/llvm/docs/AMDGPU/gfx8_vdst_c360a5.rst new file mode 100644 index 00000000000000..ed5f5ae44d6a60 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx8_vdst_c360a5.rst @@ -0,0 +1,20 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx8_vdst_c360a5: + +vdst +==== + +Instruction output: data read from a memory buffer and converted to 16-bit format. + +*Size:* depends on GFX8 GPU revision: + +* 3 dwords for GFX8.0. This H/W supports no packing. +* 2 dwords for GFX8.1+. This H/W supports data packing. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx8_vdst_d71f1c.rst b/llvm/docs/AMDGPU/gfx8_vdst_d71f1c.rst new file mode 100644 index 00000000000000..f20401d7612fbc --- /dev/null +++ b/llvm/docs/AMDGPU/gfx8_vdst_d71f1c.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx8_vdst_d71f1c: + +vdst +==== + +Instruction output: data read from a memory buffer. + +*Size:* 2 dwords. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx8_vdst_d809e2.rst b/llvm/docs/AMDGPU/gfx8_vdst_d809e2.rst new file mode 100644 index 00000000000000..e27b01c4618eb0 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx8_vdst_d809e2.rst @@ -0,0 +1,20 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx8_vdst_d809e2: + +vdst +==== + +Instruction output: data read from a memory buffer and converted to 16-bit format. + +*Size:* depends on GFX8 GPU revision: + +* 2 dwords for GFX8.0. This H/W supports no packing. +* 1 dword for GFX8.1+. This H/W supports data packing. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx8_vdst_dd8a32.rst b/llvm/docs/AMDGPU/gfx8_vdst_dd8a32.rst new file mode 100644 index 00000000000000..330c8ca16f74d0 --- /dev/null +++ b/llvm/docs/AMDGPU/gfx8_vdst_dd8a32.rst @@ -0,0 +1,17 @@ +.. + ************************************************** + * * + * Automatically generated file, do not edit! * + * * + ************************************************** + +.. _amdgpu_synid_gfx8_vdst_dd8a32: + +vdst +==== + +Instruction output: data read from a memory buffer. + +*Size:* 4 dwords. + +*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx8_vdst_3c6fb6.rst b/llvm/docs/AMDGPU/gfx8_vdst_de9309.rst similarity index 83% rename from llvm/docs/AMDGPU/gfx8_vdst_3c6fb6.rst rename to llvm/docs/AMDGPU/gfx8_vdst_de9309.rst index 8cad996a5a9049..03879b37f1d6d4 100644 --- a/llvm/docs/AMDGPU/gfx8_vdst_3c6fb6.rst +++ b/llvm/docs/AMDGPU/gfx8_vdst_de9309.rst @@ -5,17 +5,17 @@ * * ************************************************** -.. _amdgpu_synid_gfx8_vdst_3c6fb6: +.. _amdgpu_synid_gfx8_vdst_de9309: vdst ==== -Instruction output: data read from a memory buffer and converted to a 16-bit format. +Instruction output: data read from a memory buffer and converted to 16-bit format. *Size:* depends on GFX8 GPU revision and :ref:`tfe`: * 3 dwords for GFX8.0. This H/W supports no packing. * 2 dwords for GFX8.1+. This H/W supports data packing. -* :ref:`tfe` adds one dword if specified. +* :ref:`tfe` adds 1 dword if specified. *Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx8_vdst_3d7dcf.rst b/llvm/docs/AMDGPU/gfx8_vdst_dfa6da.rst similarity index 87% rename from llvm/docs/AMDGPU/gfx8_vdst_3d7dcf.rst rename to llvm/docs/AMDGPU/gfx8_vdst_dfa6da.rst index 5e49be7f50c177..73ce3fc422c4e5 100644 --- a/llvm/docs/AMDGPU/gfx8_vdst_3d7dcf.rst +++ b/llvm/docs/AMDGPU/gfx8_vdst_dfa6da.rst @@ -5,12 +5,12 @@ * * ************************************************** -.. _amdgpu_synid_gfx8_vdst_3d7dcf: +.. _amdgpu_synid_gfx8_vdst_dfa6da: vdst ==== -Image data to load by an image instruction. +Image data to be loaded by an image instruction. *Size:* depends on :ref:`dmask` and :ref:`tfe`: diff --git a/llvm/docs/AMDGPU/gfx8_vdst_e0515f.rst b/llvm/docs/AMDGPU/gfx8_vdst_e0515f.rst deleted file mode 100644 index 1366d844827b3c..00000000000000 --- a/llvm/docs/AMDGPU/gfx8_vdst_e0515f.rst +++ /dev/null @@ -1,26 +0,0 @@ -.. - ************************************************** - * * - * Automatically generated file, do not edit! * - * * - ************************************************** - -.. _amdgpu_synid_gfx8_vdst_e0515f: - -vdst -==== - -Image data to load by an *image_gather4* instruction. - -*Size:* 4 data elements by default. Each data element occupies either 32 bits or 16 bits depending on :ref:`d16`. - -:ref:`d16` and :ref:`tfe` affect operand size as follows: - -* :ref:`d16` has different meaning for GFX8.0 and GFX8.1: - - * For GFX8.0 this modifier does not affect size of data elements in registers. Data in registers are stored in low 16 bits, high 16 bits are unused. There is no packing. - * Starting from GFX8.1 this modifier specifies that data elements in registers are packed; each value occupies 16 bits. - -* :ref:`tfe` adds one dword if specified. - -*Operands:* :ref:`v` diff --git a/llvm/docs/AMDGPU/gfx8_vsrc_533a4e.rst b/llvm/docs/AMDGPU/gfx8_vsrc_ba3116.rst similarity index 79% rename from llvm/docs/AMDGPU/gfx8_vsrc_533a4e.rst rename to llvm/docs/AMDGPU/gfx8_vsrc_ba3116.rst index e3b89aea27a376..cc5de2d949e9e2 100644 --- a/llvm/docs/AMDGPU/gfx8_vsrc_533a4e.rst +++ b/llvm/docs/AMDGPU/gfx8_vsrc_ba3116.rst @@ -5,14 +5,14 @@ * * ************************************************** -.. _amdgpu_synid_gfx8_vsrc_533a4e: +.. _amdgpu_synid_gfx8_vsrc_ba3116: vsrc ==== Data to copy to export buffers. This is an optional operand. Must be specified as :ref:`off` if not used. -:ref:`compr` modifier indicates use of compressed (16-bit) data. This limits number of source operands from 4 to 2: +The :ref:`compr` modifier indicates the use of compressed (16-bit) data, thus decreasing the number of source operands from 4 to 2: * src0 and src1 must specify the first register (or :ref:`off`). * src2 and src3 must specify the second register (or :ref:`off`). diff --git a/llvm/docs/AMDGPU/gfx8_waitcnt.rst b/llvm/docs/AMDGPU/gfx8_waitcnt.rst index 63dd2570bbf869..b8bb13bb47e7f3 100644 --- a/llvm/docs/AMDGPU/gfx8_waitcnt.rst +++ b/llvm/docs/AMDGPU/gfx8_waitcnt.rst @@ -24,7 +24,7 @@ The bits of this operand have the following meaning: This operand may be specified as one of the following: -* An :ref:`integer_number` or an :ref:`absolute_expression`. The value must be in the range 0..0xFFFF. +* An :ref:`integer_number` or an :ref:`absolute_expression`. The value must be in the range from 0 to 0xFFFF. * A combination of *vmcnt*, *expcnt*, *lgkmcnt* and other values described below. ====================== ====================================================================== @@ -38,7 +38,8 @@ This operand may be specified as one of the following: lgkmcnt_sat(<*N*>) An LGKM_CNT value computed as min(*N*, the largest LGKM_CNT value). ====================== ====================================================================== -These values may be specified in any order. Spaces, ampersands and commas may be used as optional separators. +These values may be specified in any order. Spaces, ampersands, and commas may be used as optional separators. +If some values are omitted, the corresponding fields will default to their maximum value. *N* is either an :ref:`integer number` or an