diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c index 35d112bcd070f..f81ec7ac4532f 100644 --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -19,9 +19,26 @@ // CHECK-NOT: __riscv_m {{.*$}} // CHECK-NOT: __riscv_mul {{.*$}} // CHECK-NOT: __riscv_muldiv {{.*$}} +// CHECK-NOT: __riscv_shcounterenw {{.*$}} +// CHECK-NOT: __riscv_shgatpa {{.*$}} +// CHECK-NOT: __riscv_shtvala {{.*$}} +// CHECK-NOT: __riscv_shvsatpa {{.*$}} +// CHECK-NOT: __riscv_shvstvala {{.*$}} +// CHECK-NOT: __riscv_shvstvecd {{.*$}} // CHECK-NOT: __riscv_smaia {{.*$}} -// CHECK-NOT: __riscv_ssaia {{.*$}} // CHECK-NOT: __riscv_smepmp {{.*$}} +// CHECK-NOT: __riscv_ssaia {{.*$}} +// CHECK-NOT: __riscv_ssccptr {{.*$}} +// CHECK-NOT: __riscv_sscounterenw {{.*$}} +// CHECK-NOT: __riscv_ssstateen {{.*$}} +// CHECK-NOT: __riscv_ssstrict {{.*$}} +// CHECK-NOT: __riscv_sstc {{.*$}} +// CHECK-NOT: __riscv_sstvala {{.*$}} +// CHECK-NOT: __riscv_sstvecd {{.*$}} +// CHECK-NOT: __riscv_ssu64xl {{.*$}} +// CHECK-NOT: __riscv_svade {{.*$}} +// CHECK-NOT: __riscv_svadu {{.*$}} +// CHECK-NOT: __riscv_svbare {{.*$}} // CHECK-NOT: __riscv_svinval {{.*$}} // CHECK-NOT: __riscv_svnapot {{.*$}} // CHECK-NOT: __riscv_svpbmt {{.*$}} @@ -272,6 +289,142 @@ // CHECK-M-EXT: __riscv_mul 1 // CHECK-M-EXT: __riscv_muldiv 1 +// RUN: %clang --target=riscv32-unknown-linux-gnu \ +// RUN: -march=rv32ishcounterenw -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SHCOUNTERENW-EXT %s +// RUN: %clang --target=riscv64-unknown-linux-gnu \ +// RUN: -march=rv64ishcounterenw -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SHCOUNTERENW-EXT %s +// CHECK-SHCOUNTERENW-EXT: __riscv_shcounterenw 1000000{{$}} + +// RUN: %clang --target=riscv32-unknown-linux-gnu \ +// RUN: -march=rv32ishgatpa -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SHGATPA-EXT %s +// RUN: %clang --target=riscv64-unknown-linux-gnu \ +// RUN: -march=rv64ishgatpa -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SHGATPA-EXT %s +// CHECK-SHGATPA-EXT: __riscv_shgatpa 1000000{{$}} + +// RUN: %clang --target=riscv32-unknown-linux-gnu \ +// RUN: -march=rv32ishtvala -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SHTVALA-EXT %s +// RUN: %clang --target=riscv64-unknown-linux-gnu \ +// RUN: -march=rv64ishtvala -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SHTVALA-EXT %s +// CHECK-SHTVALA-EXT: __riscv_shtvala 1000000{{$}} + +// RUN: %clang --target=riscv32-unknown-linux-gnu \ +// RUN: -march=rv32ishvsatpa -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SHVSATPA-EXT %s +// RUN: %clang --target=riscv64-unknown-linux-gnu \ +// RUN: -march=rv64ishvsatpa -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SHVSATPA-EXT %s +// CHECK-SHVSATPA-EXT: __riscv_shvsatpa 1000000{{$}} + +// RUN: %clang --target=riscv32-unknown-linux-gnu \ +// RUN: -march=rv32ishvstvala -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SHVSTVALA-EXT %s +// RUN: %clang --target=riscv64-unknown-linux-gnu \ +// RUN: -march=rv64ishvstvala -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SHVSTVALA-EXT %s +// CHECK-SHVSTVALA-EXT: __riscv_shvstvala 1000000{{$}} + +// RUN: %clang --target=riscv32-unknown-linux-gnu \ +// RUN: -march=rv32ishvstvecd -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SHVSTVECD-EXT %s +// RUN: %clang --target=riscv64-unknown-linux-gnu \ +// RUN: -march=rv64ishvstvecd -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SHVSTVECD-EXT %s +// CHECK-SHVSTVECD-EXT: __riscv_shvstvecd 1000000{{$}} + +// RUN: %clang --target=riscv32-unknown-linux-gnu \ +// RUN: -march=rv32issccptr -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SSCCPTR-EXT %s +// RUN: %clang --target=riscv64-unknown-linux-gnu \ +// RUN: -march=rv64issccptr -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SSCCPTR-EXT %s +// CHECK-SSCCPTR-EXT: __riscv_ssccptr 1000000{{$}} + +// RUN: %clang --target=riscv32-unknown-linux-gnu \ +// RUN: -march=rv32isscounterenw -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SSCOUNTERENW-EXT %s +// RUN: %clang --target=riscv64-unknown-linux-gnu \ +// RUN: -march=rv64isscounterenw -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SSCOUNTERENW-EXT %s +// CHECK-SSCOUNTERENW-EXT: __riscv_sscounterenw 1000000{{$}} + +// RUN: %clang --target=riscv32-unknown-linux-gnu \ +// RUN: -march=rv32issstateen -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SSSTATEEN-EXT %s +// RUN: %clang --target=riscv64-unknown-linux-gnu \ +// RUN: -march=rv64issstateen -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SSSTATEEN-EXT %s +// CHECK-SSSTATEEN-EXT: __riscv_ssstateen 1000000{{$}} + +// RUN: %clang --target=riscv32-unknown-linux-gnu \ +// RUN: -march=rv32issstrict -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SSSTRICT-EXT %s +// RUN: %clang --target=riscv64-unknown-linux-gnu \ +// RUN: -march=rv64issstrict -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SSSTRICT-EXT %s +// CHECK-SSSTRICT-EXT: __riscv_ssstrict 1000000{{$}} + +// RUN: %clang --target=riscv32-unknown-linux-gnu \ +// RUN: -march=rv32isstc -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SSTC-EXT %s +// RUN: %clang --target=riscv64-unknown-linux-gnu \ +// RUN: -march=rv64isstc -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SSTC-EXT %s +// CHECK-SSTC-EXT: __riscv_sstc 1000000{{$}} + +// RUN: %clang --target=riscv32-unknown-linux-gnu \ +// RUN: -march=rv32isstvala -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SSTVALA-EXT %s +// RUN: %clang --target=riscv64-unknown-linux-gnu \ +// RUN: -march=rv64isstvala -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SSTVALA-EXT %s +// CHECK-SSTVALA-EXT: __riscv_sstvala 1000000{{$}} + +// RUN: %clang --target=riscv32-unknown-linux-gnu \ +// RUN: -march=rv32isstvecd -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SSTVECD-EXT %s +// RUN: %clang --target=riscv64-unknown-linux-gnu \ +// RUN: -march=rv64isstvecd -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SSTVECD-EXT %s +// CHECK-SSTVECD-EXT: __riscv_sstvecd 1000000{{$}} + +// RUN: %clang --target=riscv32-unknown-linux-gnu \ +// RUN: -march=rv32issu64xl -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SSU64XL-EXT %s +// RUN: %clang --target=riscv64-unknown-linux-gnu \ +// RUN: -march=rv64issu64xl -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SSU64XL-EXT %s +// CHECK-SSU64XL-EXT: __riscv_ssu64xl 1000000{{$}} + +// RUN: %clang --target=riscv32-unknown-linux-gnu \ +// RUN: -march=rv32isvade -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SVADE-EXT %s +// RUN: %clang --target=riscv64-unknown-linux-gnu \ +// RUN: -march=rv64isvade -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SVADE-EXT %s +// CHECK-SVADE-EXT: __riscv_svade 1000000{{$}} + +// RUN: %clang --target=riscv32-unknown-linux-gnu \ +// RUN: -march=rv32isvadu -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SVADU-EXT %s +// RUN: %clang --target=riscv64-unknown-linux-gnu \ +// RUN: -march=rv64isvadu -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SVADU-EXT %s +// CHECK-SVADU-EXT: __riscv_svadu 1000000{{$}} + +// RUN: %clang --target=riscv32-unknown-linux-gnu \ +// RUN: -march=rv32isvbare -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SVBARE-EXT %s +// RUN: %clang --target=riscv64-unknown-linux-gnu \ +// RUN: -march=rv64isvbare -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SVBARE-EXT %s +// CHECK-SVBARE-EXT: __riscv_svbare 1000000{{$}} + // RUN: %clang --target=riscv32-unknown-linux-gnu \ // RUN: -march=rv32isvinval -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-SVINVAL-EXT %s diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index a957a8dfba95b..e6d1f41849302 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -81,107 +81,124 @@ on support follow. .. table:: Ratified Extensions by Status - =============== ========================================================= - Extension Status - =============== ========================================================= - ``A`` Supported - ``C`` Supported - ``D`` Supported - ``F`` Supported - ``E`` Supported (`See note <#riscv-rve-note>`__) - ``H`` Assembly Support - ``M`` Supported - ``Smaia`` Supported - ``Smepmp`` Supported - ``Ssaia`` Supported - ``Svinval`` Assembly Support - ``Svnapot`` Assembly Support - ``Svpbmt`` Supported - ``V`` Supported - ``Za128rs`` Supported (`See note <#riscv-profiles-extensions-note>`__) - ``Za64rs`` Supported (`See note <#riscv-profiles-extensions-note>`__) - ``Zawrs`` Assembly Support - ``Zba`` Supported - ``Zbb`` Supported - ``Zbc`` Supported - ``Zbkb`` Supported (`See note <#riscv-scalar-crypto-note1>`__) - ``Zbkc`` Supported - ``Zbkx`` Supported (`See note <#riscv-scalar-crypto-note1>`__) - ``Zbs`` Supported - ``Zca`` Supported - ``Zcb`` Supported - ``Zcd`` Supported - ``Zcf`` Supported - ``Zcmp`` Supported - ``Zcmt`` Assembly Support - ``Zdinx`` Supported - ``Zfa`` Supported - ``Zfh`` Supported - ``Zfhmin`` Supported - ``Zfinx`` Supported - ``Zhinx`` Supported - ``Zhinxmin`` Supported - ``Zic64b`` Supported (`See note <#riscv-profiles-extensions-note>`__) - ``Zicbom`` Assembly Support - ``Zicbop`` Supported - ``Zicboz`` Assembly Support - ``Ziccamoa`` Supported (`See note <#riscv-profiles-extensions-note>`__) - ``Ziccif`` Supported (`See note <#riscv-profiles-extensions-note>`__) - ``Zicclsm`` Supported (`See note <#riscv-profiles-extensions-note>`__) - ``Ziccrse`` Supported (`See note <#riscv-profiles-extensions-note>`__) - ``Zicntr`` (`See Note <#riscv-i2p1-note>`__) - ``Zicond`` Supported - ``Zicsr`` (`See Note <#riscv-i2p1-note>`__) - ``Zifencei`` (`See Note <#riscv-i2p1-note>`__) - ``Zihintntl`` Supported - ``Zihintpause`` Assembly Support - ``Zihpm`` (`See Note <#riscv-i2p1-note>`__) - ``Zkn`` Supported - ``Zknd`` Supported (`See note <#riscv-scalar-crypto-note2>`__) - ``Zkne`` Supported (`See note <#riscv-scalar-crypto-note2>`__) - ``Zknh`` Supported (`See note <#riscv-scalar-crypto-note2>`__) - ``Zksed`` Supported (`See note <#riscv-scalar-crypto-note2>`__) - ``Zksh`` Supported (`See note <#riscv-scalar-crypto-note2>`__) - ``Zk`` Supported - ``Zkr`` Supported - ``Zks`` Supported - ``Zkt`` Supported - ``Zmmul`` Supported - ``Zvbb`` Assembly Support - ``Zvbc`` Assembly Support - ``Zve32x`` (`Partially <#riscv-vlen-32-note>`__) Supported - ``Zve32f`` (`Partially <#riscv-vlen-32-note>`__) Supported - ``Zve64x`` Supported - ``Zve64f`` Supported - ``Zve64d`` Supported - ``Zvfh`` Supported - ``Zvkb`` Assembly Support - ``Zvkg`` Assembly Support - ``Zvkn`` Assembly Support - ``Zvknc`` Assembly Support - ``Zvkned`` Assembly Support - ``Zvkng`` Assembly Support - ``Zvknha`` Assembly Support - ``Zvknhb`` Assembly Support - ``Zvks`` Assembly Support - ``Zvksc`` Assembly Support - ``Zvksed`` Assembly Support - ``Zvksg`` Assembly Support - ``Zvksh`` Assembly Support - ``Zvkt`` Assembly Support - ``Zvl32b`` (`Partially <#riscv-vlen-32-note>`__) Supported - ``Zvl64b`` Supported - ``Zvl128b`` Supported - ``Zvl256b`` Supported - ``Zvl512b`` Supported - ``Zvl1024b`` Supported - ``Zvl2048b`` Supported - ``Zvl4096b`` Supported - ``Zvl8192b`` Supported - ``Zvl16384b`` Supported - ``Zvl32768b`` Supported - ``Zvl65536b`` Supported - =============== ========================================================= + ================ ================================================================= + Extension Status + ================ ================================================================= + ``A`` Supported + ``C`` Supported + ``D`` Supported + ``F`` Supported + ``E`` Supported (`See note <#riscv-rve-note>`__) + ``H`` Assembly Support + ``M`` Supported + ``Shcounterenw`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__) + ``Shgatpa`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__) + ``Shtvala`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__) + ``Shvsatpa`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__) + ``Shvstvala`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__) + ``Shvstvecd`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__) + ``Smaia`` Supported + ``Smepmp`` Supported + ``Ssaia`` Supported + ``Ssccptr`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__) + ``Sscounterenw`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__) + ``Ssstateen`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__) + ``Ssstrict`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__) + ``Sstc`` Assembly Support + ``Sstvala`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__) + ``Sstvecd`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__) + ``Ssu64xl`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__) + ``Svade`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__) + ``Svadu`` Assembly Support + ``Svbare`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__) + ``Svinval`` Assembly Support + ``Svnapot`` Assembly Support + ``Svpbmt`` Supported + ``V`` Supported + ``Za128rs`` Supported (`See note <#riscv-profiles-extensions-note>`__) + ``Za64rs`` Supported (`See note <#riscv-profiles-extensions-note>`__) + ``Zawrs`` Assembly Support + ``Zba`` Supported + ``Zbb`` Supported + ``Zbc`` Supported + ``Zbkb`` Supported (`See note <#riscv-scalar-crypto-note1>`__) + ``Zbkc`` Supported + ``Zbkx`` Supported (`See note <#riscv-scalar-crypto-note1>`__) + ``Zbs`` Supported + ``Zca`` Supported + ``Zcb`` Supported + ``Zcd`` Supported + ``Zcf`` Supported + ``Zcmp`` Supported + ``Zcmt`` Assembly Support + ``Zdinx`` Supported + ``Zfa`` Supported + ``Zfh`` Supported + ``Zfhmin`` Supported + ``Zfinx`` Supported + ``Zhinx`` Supported + ``Zhinxmin`` Supported + ``Zic64b`` Supported (`See note <#riscv-profiles-extensions-note>`__) + ``Zicbom`` Assembly Support + ``Zicbop`` Supported + ``Zicboz`` Assembly Support + ``Ziccamoa`` Supported (`See note <#riscv-profiles-extensions-note>`__) + ``Ziccif`` Supported (`See note <#riscv-profiles-extensions-note>`__) + ``Zicclsm`` Supported (`See note <#riscv-profiles-extensions-note>`__) + ``Ziccrse`` Supported (`See note <#riscv-profiles-extensions-note>`__) + ``Zicntr`` (`See Note <#riscv-i2p1-note>`__) + ``Zicond`` Supported + ``Zicsr`` (`See Note <#riscv-i2p1-note>`__) + ``Zifencei`` (`See Note <#riscv-i2p1-note>`__) + ``Zihintntl`` Supported + ``Zihintpause`` Assembly Support + ``Zihpm`` (`See Note <#riscv-i2p1-note>`__) + ``Zkn`` Supported + ``Zknd`` Supported (`See note <#riscv-scalar-crypto-note2>`__) + ``Zkne`` Supported (`See note <#riscv-scalar-crypto-note2>`__) + ``Zknh`` Supported (`See note <#riscv-scalar-crypto-note2>`__) + ``Zksed`` Supported (`See note <#riscv-scalar-crypto-note2>`__) + ``Zksh`` Supported (`See note <#riscv-scalar-crypto-note2>`__) + ``Zk`` Supported + ``Zkr`` Supported + ``Zks`` Supported + ``Zkt`` Supported + ``Zmmul`` Supported + ``Zvbb`` Assembly Support + ``Zvbc`` Assembly Support + ``Zve32x`` (`Partially <#riscv-vlen-32-note>`__) Supported + ``Zve32f`` (`Partially <#riscv-vlen-32-note>`__) Supported + ``Zve64x`` Supported + ``Zve64f`` Supported + ``Zve64d`` Supported + ``Zvfh`` Supported + ``Zvkb`` Assembly Support + ``Zvkg`` Assembly Support + ``Zvkn`` Assembly Support + ``Zvknc`` Assembly Support + ``Zvkned`` Assembly Support + ``Zvkng`` Assembly Support + ``Zvknha`` Assembly Support + ``Zvknhb`` Assembly Support + ``Zvks`` Assembly Support + ``Zvksc`` Assembly Support + ``Zvksed`` Assembly Support + ``Zvksg`` Assembly Support + ``Zvksh`` Assembly Support + ``Zvkt`` Assembly Support + ``Zvl32b`` (`Partially <#riscv-vlen-32-note>`__) Supported + ``Zvl64b`` Supported + ``Zvl128b`` Supported + ``Zvl256b`` Supported + ``Zvl512b`` Supported + ``Zvl1024b`` Supported + ``Zvl2048b`` Supported + ``Zvl4096b`` Supported + ``Zvl8192b`` Supported + ``Zvl16384b`` Supported + ``Zvl32768b`` Supported + ``Zvl65536b`` Supported + ================ ================================================================= Assembly Support LLVM supports the associated instructions in assembly. All assembly related tools (e.g. assembler, disassembler, llvm-objdump, etc..) are supported. Compiler and linker will accept extension names, and linked binaries will contain appropriate ELF flags and attributes to reflect use of named extension. @@ -216,7 +233,7 @@ Supported .. _riscv-profiles-extensions-note: -``Za128rs``, ``Za64rs``, ``Zic64b``, ``Ziccamoa``, ``Ziccif``, ``Zicclsm``, ``Ziccrse`` +``Za128rs``, ``Za64rs``, ``Zic64b``, ``Ziccamoa``, ``Ziccif``, ``Zicclsm``, ``Ziccrse``, ``Shcounterenvw``, ``Shgatpa``, ``Shtvala``, ``Shvsatpa``, ``Shvstvala``, ``Shvstvecd``, ``Ssccptr``, ``Sscounterenw``, ``Ssstateen``, ``Ssstrict``, ``Sstvala``, ``Sstvecd``, ``Ssu64xl``, ``Svade``, ``Svbare`` These extensions are defined as part of the `RISC-V Profiles specification `_. They do not introduce any new features themselves, but instead describe existing hardware features. Experimental Extensions diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp index 8f31b0f40d5c9..b4fa20d202d3e 100644 --- a/llvm/lib/Support/RISCVISAInfo.cpp +++ b/llvm/lib/Support/RISCVISAInfo.cpp @@ -55,9 +55,26 @@ static const RISCVSupportedExtension SupportedExtensions[] = { {"i", {2, 1}}, {"m", {2, 0}}, + {"shcounterenw", {1, 0}}, + {"shgatpa", {1, 0}}, + {"shtvala", {1, 0}}, + {"shvsatpa", {1, 0}}, + {"shvstvala", {1, 0}}, + {"shvstvecd", {1, 0}}, {"smaia", {1, 0}}, {"smepmp", {1, 0}}, {"ssaia", {1, 0}}, + {"ssccptr", {1, 0}}, + {"sscounterenw", {1, 0}}, + {"ssstateen", {1, 0}}, + {"ssstrict", {1, 0}}, + {"sstc", {1, 0}}, + {"sstvala", {1, 0}}, + {"sstvecd", {1, 0}}, + {"ssu64xl", {1, 0}}, + {"svade", {1, 0}}, + {"svadu", {1, 0}}, + {"svbare", {1, 0}}, {"svinval", {1, 0}}, {"svnapot", {1, 0}}, {"svpbmt", {1, 0}}, diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 6f87eae101f04..6525176670c92 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -783,6 +783,13 @@ def HasStdExtH : Predicate<"Subtarget->hasStdExtH()">, // Supervisor extensions +def FeatureStdExtShgatpa + : SubtargetFeature<"shgatpa", "HasStdExtShgatpa", "true", + "'Sgatpa' (SvNNx4 mode supported for all modes supported by satp, as well as Bare)", []>; +def FeatureStdExtShvsatpa + : SubtargetFeature<"shvsatpa", "HasStdExtSvsatpa", "true", + "'Svsatpa' (vsatp supports all modes supported by satp)", []>; + def FeatureStdExtSmaia : SubtargetFeature<"smaia", "HasStdExtSmaia", "true", "'Smaia' (Advanced Interrupt Architecture Machine " @@ -796,6 +803,64 @@ def FeatureStdExtSmepmp : SubtargetFeature<"smepmp", "HasStdExtSmepmp", "true", "'Smepmp' (Enhanced Physical Memory Protection)", []>; +def FeatureStdExtSsccptr + : SubtargetFeature<"ssccptr", "HasStdExtSsccptr", "true", + "'Ssccptr' (Main memory supports page table reads)", []>; + +def FeatureStdExtShcounterenw + : SubtargetFeature<"shcounterenw", "HasStdExtShcounterenw", "true", + "'Shcounterenw' (Support writeable hcounteren enable " + "bit for any hpmcounter that is not read-only zero)", []>; +def FeatureStdExtSscounterenw + : SubtargetFeature<"sscounterenw", "HasStdExtSscounterenw", "true", + "'Sscounterenw' (Support writeable scounteren enable " + "bit for any hpmcounter that is not read-only zero)", []>; + +def FeatureStdExtSsstateen + : SubtargetFeature<"ssstateen", "HasStdExtSsstateen", "true", + "'Ssstateen' (Supervisor-mode view of the state-enable extension)", []>; + +def FeatureStdExtSsstrict + : SubtargetFeature<"ssstrict", "HasStdExtSsstrict", "true", + "'Ssstrict' (No non-conforming extensions are present.", []>; + +def FeatureStdExtSstc + : SubtargetFeature<"sstc", "HasStdExtSstc", "true", + "'Sstc' (Supervisor-mode timer interrupts)", []>; + +def FeatureStdExtShtvala + : SubtargetFeature<"shtvala", "HasStdExtShtvala", "true", + "'Shtvala' (htval provides all needed values)", []>; +def FeatureStdExtShvstvala + : SubtargetFeature<"shvstvala", "HasStdExtShvstvala", "true", + "'Shvstvala' (vstval provides all needed values)", []>; +def FeatureStdExtSstvala + : SubtargetFeature<"sstvala", "HasStdExtSstvala", "true", + "'Sstvala' (stval provides all needed values)", []>; + +def FeatureStdExtShvstvecd + : SubtargetFeature<"shvstvecd", "HasStdExtShvstvecd", "true", + "'Shvstvecd' (vstvec supports Direct mode)", []>; +def FeatureStdExtSstvecd + : SubtargetFeature<"sstvecd", "HasStdExtSstvecd", "true", + "'Sstvecd' (stvec supports Direct mode)", []>; + +def FeatureStdExtSsu64xl + : SubtargetFeature<"ssu64xl", "HasStdExtSsu64xl", "true", + "'Ssu64xl' (UXLEN=64 supported)", []>; + +def FeaturesStdExtSvade + : SubtargetFeature<"svade", "HasStdExtSvade", "true", + "'Svade' (Raise exceptions on improper A/D bits)", []>; + +def FeaturesStdExtSvadu + : SubtargetFeature<"svadu", "HasStdExtSvadu", "true", + "'Svadu' (Hardware A/D updates)", []>; + +def FeaturesStdExtSvbare + : SubtargetFeature<"svbare", "HasStdExtSvbare", "true", + "'Svbare' $(satp mode Bare supported)", []>; + def FeatureStdExtSvinval : SubtargetFeature<"svinval", "HasStdExtSvinval", "true", "'Svinval' (Fine-Grained Address-Translation Cache Invalidation)">; diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index f7b53d6de27f2..89b2190310f77 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -38,6 +38,23 @@ ; RUN: llc -mtriple=riscv32 -mattr=+zicbom %s -o - | FileCheck --check-prefixes=CHECK,RV32ZICBOM %s ; RUN: llc -mtriple=riscv32 -mattr=+zicboz %s -o - | FileCheck --check-prefixes=CHECK,RV32ZICBOZ %s ; RUN: llc -mtriple=riscv32 -mattr=+zicbop %s -o - | FileCheck --check-prefixes=CHECK,RV32ZICBOP %s +; RUN: llc -mtriple=riscv32 -mattr=+shcounterenw %s -o - | FileCheck --check-prefixes=CHECK,RV32SHCOUNTERENW %s +; RUN: llc -mtriple=riscv32 -mattr=+shgatpa %s -o - | FileCheck --check-prefixes=CHECK,RV32SHGATPA %s +; RUN: llc -mtriple=riscv32 -mattr=+shvsatpa %s -o - | FileCheck --check-prefixes=CHECK,RV32SHVSATPA %s +; RUN: llc -mtriple=riscv32 -mattr=+ssccptr %s -o - | FileCheck --check-prefixes=CHECK,RV32SSCCPTR %s +; RUN: llc -mtriple=riscv32 -mattr=+sscounterenw %s -o - | FileCheck --check-prefixes=CHECK,RV32SSCOUNTERENW %s +; RUN: llc -mtriple=riscv32 -mattr=+ssstateen %s -o - | FileCheck --check-prefixes=CHECK,RV32SSSTATEEN %s +; RUN: llc -mtriple=riscv32 -mattr=+ssstrict %s -o - | FileCheck --check-prefixes=CHECK,RV32SSSTRICT %s +; RUN: llc -mtriple=riscv32 -mattr=+sstc %s -o - | FileCheck --check-prefixes=CHECK,RV32SSTC %s +; RUN: llc -mtriple=riscv32 -mattr=+shtvala %s -o - | FileCheck --check-prefixes=CHECK,RV32SHTVALA %s +; RUN: llc -mtriple=riscv32 -mattr=+shvstvala %s -o - | FileCheck --check-prefixes=CHECK,RV32SHVSTVALA %s +; RUN: llc -mtriple=riscv32 -mattr=+shvstvecd %s -o - | FileCheck --check-prefixes=CHECK,RV32SHVSTVECD %s +; RUN: llc -mtriple=riscv32 -mattr=+sstvala %s -o - | FileCheck --check-prefixes=CHECK,RV32SSTVALA %s +; RUN: llc -mtriple=riscv32 -mattr=+sstvecd %s -o - | FileCheck --check-prefixes=CHECK,RV32SSTVECD %s +; RUN: llc -mtriple=riscv32 -mattr=+ssu64xl %s -o - | FileCheck --check-prefixes=CHECK,RV32SSU64XL %s +; RUN: llc -mtriple=riscv32 -mattr=+svade %s -o - | FileCheck --check-prefixes=CHECK,RV32SVADE %s +; RUN: llc -mtriple=riscv32 -mattr=+svadu %s -o - | FileCheck --check-prefixes=CHECK,RV32SVADU %s +; RUN: llc -mtriple=riscv32 -mattr=+svbare %s -o - | FileCheck --check-prefixes=CHECK,RV32SVBARE %s ; RUN: llc -mtriple=riscv32 -mattr=+svnapot %s -o - | FileCheck --check-prefixes=CHECK,RV32SVNAPOT %s ; RUN: llc -mtriple=riscv32 -mattr=+svpbmt %s -o - | FileCheck --check-prefixes=CHECK,RV32SVPBMT %s ; RUN: llc -mtriple=riscv32 -mattr=+svinval %s -o - | FileCheck --check-prefixes=CHECK,RV32SVINVAL %s @@ -139,6 +156,23 @@ ; RUN: llc -mtriple=riscv64 -mattr=+zicbom %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICBOM %s ; RUN: llc -mtriple=riscv64 -mattr=+zicboz %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICBOZ %s ; RUN: llc -mtriple=riscv64 -mattr=+zicbop %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICBOP %s +; RUN: llc -mtriple=riscv64 -mattr=+shcounterenw %s -o - | FileCheck --check-prefixes=CHECK,RV64SHCOUNTERENW %s +; RUN: llc -mtriple=riscv64 -mattr=+shgatpa %s -o - | FileCheck --check-prefixes=CHECK,RV64SHGATPA %s +; RUN: llc -mtriple=riscv64 -mattr=+shvsatpa %s -o - | FileCheck --check-prefixes=CHECK,RV64SHVSATPA %s +; RUN: llc -mtriple=riscv64 -mattr=+ssccptr %s -o - | FileCheck --check-prefixes=CHECK,RV64SSCCPTR %s +; RUN: llc -mtriple=riscv64 -mattr=+sscounterenw %s -o - | FileCheck --check-prefixes=CHECK,RV64SSCOUNTERENW %s +; RUN: llc -mtriple=riscv64 -mattr=+ssstateen %s -o - | FileCheck --check-prefixes=CHECK,RV64SSSTATEEN %s +; RUN: llc -mtriple=riscv64 -mattr=+ssstrict %s -o - | FileCheck --check-prefixes=CHECK,RV64SSSTRICT %s +; RUN: llc -mtriple=riscv64 -mattr=+sstc %s -o - | FileCheck --check-prefixes=CHECK,RV64SSTC %s +; RUN: llc -mtriple=riscv64 -mattr=+shtvala %s -o - | FileCheck --check-prefixes=CHECK,RV64SHTVALA %s +; RUN: llc -mtriple=riscv64 -mattr=+shvstvala %s -o - | FileCheck --check-prefixes=CHECK,RV64SHVSTVALA %s +; RUN: llc -mtriple=riscv64 -mattr=+shvstvecd %s -o - | FileCheck --check-prefixes=CHECK,RV64SHVSTVECD %s +; RUN: llc -mtriple=riscv64 -mattr=+sstvala %s -o - | FileCheck --check-prefixes=CHECK,RV64SSTVALA %s +; RUN: llc -mtriple=riscv64 -mattr=+sstvecd %s -o - | FileCheck --check-prefixes=CHECK,RV64SSTVECD %s +; RUN: llc -mtriple=riscv64 -mattr=+ssu64xl %s -o - | FileCheck --check-prefixes=CHECK,RV64SSU64XL %s +; RUN: llc -mtriple=riscv64 -mattr=+svade %s -o - | FileCheck --check-prefixes=CHECK,RV64SVADE %s +; RUN: llc -mtriple=riscv64 -mattr=+svadu %s -o - | FileCheck --check-prefixes=CHECK,RV64SVADU %s +; RUN: llc -mtriple=riscv64 -mattr=+svbare %s -o - | FileCheck --check-prefixes=CHECK,RV64SVBARE %s ; RUN: llc -mtriple=riscv64 -mattr=+svnapot %s -o - | FileCheck --check-prefixes=CHECK,RV64SVNAPOT %s ; RUN: llc -mtriple=riscv64 -mattr=+svpbmt %s -o - | FileCheck --check-prefixes=CHECK,RV64SVPBMT %s ; RUN: llc -mtriple=riscv64 -mattr=+svinval %s -o - | FileCheck --check-prefixes=CHECK,RV64SVINVAL %s @@ -245,6 +279,23 @@ ; RV32ZICBOM: .attribute 5, "rv32i2p1_zicbom1p0" ; RV32ZICBOZ: .attribute 5, "rv32i2p1_zicboz1p0" ; RV32ZICBOP: .attribute 5, "rv32i2p1_zicbop1p0" +; RV32SHCOUNTERENW: .attribute 5, "rv32i2p1_shcounterenw1p0" +; RV32SHGATPA: .attribute 5, "rv32i2p1_shgatpa1p0" +; RV32SHVSATPA: .attribute 5, "rv32i2p1_shvsatpa1p0" +; RV32SSCCPTR: .attribute 5, "rv32i2p1_ssccptr1p0" +; RV32SSCOUNTERENW: .attribute 5, "rv32i2p1_sscounterenw1p0" +; RV32SSSTATEEN: .attribute 5, "rv32i2p1_ssstateen1p0" +; RV32SSSTRICT: .attribute 5, "rv32i2p1_ssstrict1p0" +; RV32SSTC: .attribute 5, "rv32i2p1_sstc1p0" +; RV32SHTVALA: .attribute 5, "rv32i2p1_shtvala1p0" +; RV32SHVSTVALA: .attribute 5, "rv32i2p1_shvstvala1p0" +; RV32SHVSTVECD: .attribute 5, "rv32i2p1_shvstvecd1p0" +; RV32SSTVALA: .attribute 5, "rv32i2p1_sstvala1p0" +; RV32SSTVECD: .attribute 5, "rv32i2p1_sstvecd1p0" +; RV32SSU64XL: .attribute 5, "rv32i2p1_ssu64xl1p0" +; RV32SVADE: .attribute 5, "rv32i2p1_svade1p0" +; RV32SVADU: .attribute 5, "rv32i2p1_svadu1p0" +; RV32SVBARE: .attribute 5, "rv32i2p1_svbare1p0" ; RV32SVNAPOT: .attribute 5, "rv32i2p1_svnapot1p0" ; RV32SVPBMT: .attribute 5, "rv32i2p1_svpbmt1p0" ; RV32SVINVAL: .attribute 5, "rv32i2p1_svinval1p0" @@ -348,6 +399,23 @@ ; RV64ZA128RS: .attribute 5, "rv64i2p1_za128rs1p0" ; RV64ZAWRS: .attribute 5, "rv64i2p1_zawrs1p0" ; RV64ZICBOP: .attribute 5, "rv64i2p1_zicbop1p0" +; RV64SHCOUNTERENW: .attribute 5, "rv64i2p1_shcounterenw1p0" +; RV64SHGATPA: .attribute 5, "rv64i2p1_shgatpa1p0" +; RV64SHVSATPA: .attribute 5, "rv64i2p1_shvsatpa1p0" +; RV64SSCCPTR: .attribute 5, "rv64i2p1_ssccptr1p0" +; RV64SSCOUNTERENW: .attribute 5, "rv64i2p1_sscounterenw1p0" +; RV64SSSTATEEN: .attribute 5, "rv64i2p1_ssstateen1p0" +; RV64SSSTRICT: .attribute 5, "rv64i2p1_ssstrict1p0" +; RV64SSTC: .attribute 5, "rv64i2p1_sstc1p0" +; RV64SHTVALA: .attribute 5, "rv64i2p1_shtvala1p0" +; RV64SHVSTVALA: .attribute 5, "rv64i2p1_shvstvala1p0" +; RV64SHVSTVECD: .attribute 5, "rv64i2p1_shvstvecd1p0" +; RV64SSTVALA: .attribute 5, "rv64i2p1_sstvala1p0" +; RV64SSTVECD: .attribute 5, "rv64i2p1_sstvecd1p0" +; RV64SSU64XL: .attribute 5, "rv64i2p1_ssu64xl1p0" +; RV64SVADE: .attribute 5, "rv64i2p1_svade1p0" +; RV64SVADU: .attribute 5, "rv64i2p1_svadu1p0" +; RV64SVBARE: .attribute 5, "rv64i2p1_svbare1p0" ; RV64SVNAPOT: .attribute 5, "rv64i2p1_svnapot1p0" ; RV64SVPBMT: .attribute 5, "rv64i2p1_svpbmt1p0" ; RV64SVINVAL: .attribute 5, "rv64i2p1_svinval1p0" diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s index 8810ca6781cff..34b7ee52da320 100644 --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -288,6 +288,24 @@ .attribute arch, "rv32izicond1p0" # CHECK: attribute 5, "rv32i2p1_zicond1p0" +.attribute arch, "rv32i_shcounterenw1p0" +# CHECK: attribute 5, "rv32i2p1_shcounterenw1p0" + +.attribute arch, "rv32i_shgatpa1p0" +# CHECK: attribute 5, "rv32i2p1_shgatpa1p0" + +.attribute arch, "rv32i_shvsatpa1p0" +# CHECK: attribute 5, "rv32i2p1_shvsatpa1p0" + +.attribute arch, "rv32i_shtvala1p0" +# CHECK: attribute 5, "rv32i2p1_shtvala1p0" + +.attribute arch, "rv32i_shvstvala1p0" +# CHECK: attribute 5, "rv32i2p1_shvstvala1p0" + +.attribute arch, "rv32i_shvstvecd1p0" +# CHECK: attribute 5, "rv32i2p1_shvstvecd1p0" + .attribute arch, "rv32i_smaia1p0" # CHECK: attribute 5, "rv32i2p1_smaia1p0" @@ -297,6 +315,39 @@ .attribute arch, "rv32i_smepmp1p0" # CHECK: attribute 5, "rv32i2p1_smepmp1p0" +.attribute arch, "rv32i_ssccptr1p0" +# CHECK: attribute 5, "rv32i2p1_ssccptr1p0" + +.attribute arch, "rv32i_sscounterenw1p0" +# CHECK: attribute 5, "rv32i2p1_sscounterenw1p0" + +.attribute arch, "rv32i_ssstateen1p0" +# CHECK: attribute 5, "rv32i2p1_ssstateen1p0" + +.attribute arch, "rv32i_ssstrict1p0" +# CHECK: attribute 5, "rv32i2p1_ssstrict1p0" + +.attribute arch, "rv32i_sstc1p0" +# CHECK: attribute 5, "rv32i2p1_sstc1p0" + +.attribute arch, "rv32i_sstvala1p0" +# CHECK: attribute 5, "rv32i2p1_sstvala1p0" + +.attribute arch, "rv32i_sstvecd1p0" +# CHECK: attribute 5, "rv32i2p1_sstvecd1p0" + +.attribute arch, "rv32i_ssu64xl1p0" +# CHECK: attribute 5, "rv32i2p1_ssu64xl1p0" + +.attribute arch, "rv32i_svade1p0" +# CHECK: attribute 5, "rv32i2p1_svade1p0" + +.attribute arch, "rv32i_svadu1p0" +# CHECK: attribute 5, "rv32i2p1_svadu1p0" + +.attribute arch, "rv32i_svbare1p0" +# CHECK: attribute 5, "rv32i2p1_svbare1p0" + .attribute arch, "rv32i_zfbfmin1p0" # CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0" diff --git a/llvm/unittests/Support/RISCVISAInfoTest.cpp b/llvm/unittests/Support/RISCVISAInfoTest.cpp index 66e10bfcf1122..8f44c7ba69364 100644 --- a/llvm/unittests/Support/RISCVISAInfoTest.cpp +++ b/llvm/unittests/Support/RISCVISAInfoTest.cpp @@ -819,9 +819,26 @@ R"(All available -march extensions for RISC-V zvl8192b 1.0 zhinx 1.0 zhinxmin 1.0 + shcounterenw 1.0 + shgatpa 1.0 + shtvala 1.0 + shvsatpa 1.0 + shvstvala 1.0 + shvstvecd 1.0 smaia 1.0 smepmp 1.0 ssaia 1.0 + ssccptr 1.0 + sscounterenw 1.0 + ssstateen 1.0 + ssstrict 1.0 + sstc 1.0 + sstvala 1.0 + sstvecd 1.0 + ssu64xl 1.0 + svade 1.0 + svadu 1.0 + svbare 1.0 svinval 1.0 svnapot 1.0 svpbmt 1.0