diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 4ea4fc8c372956..a2fd45b48af718 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -22033,9 +22033,6 @@ static SDValue combineShuffleOfBitcast(ShuffleVectorSDNode *SVN,
                                        SelectionDAG &DAG,
                                        const TargetLowering &TLI,
                                        bool LegalOperations) {
-  // For now, we only support little endian
-  if (!DAG.getDataLayout().isLittleEndian())
-    return SDValue();
   SDValue Op0 = SVN->getOperand(0);
   SDValue Op1 = SVN->getOperand(1);
   EVT VT = SVN->getValueType(0);
diff --git a/llvm/test/CodeGen/PowerPC/aix-vsx-splatimm.ll b/llvm/test/CodeGen/PowerPC/aix-vsx-splatimm.ll
index c5714d14f54414..51d6ba429f60d1 100644
--- a/llvm/test/CodeGen/PowerPC/aix-vsx-splatimm.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-vsx-splatimm.ll
@@ -13,33 +13,23 @@ define void @test_aix_splatimm(i32 %arg, i32 %arg1, i32 %arg2) {
 ; CHECK-AIX-NEXT:  # %bb.1: # %bb3
 ; CHECK-AIX-NEXT:    srwi 4, 4, 16
 ; CHECK-AIX-NEXT:    srwi 5, 5, 16
-; CHECK-AIX-NEXT:    mullw 4, 5, 4
-; CHECK-AIX-NEXT:    lwz 5, 0(3)
 ; CHECK-AIX-NEXT:    slwi 3, 3, 8
+; CHECK-AIX-NEXT:    mullw 4, 5, 4
 ; CHECK-AIX-NEXT:    neg 3, 3
+; CHECK-AIX-NEXT:    lwz 5, 0(3)
+; CHECK-AIX-NEXT:    sth 3, -16(1)
+; CHECK-AIX-NEXT:    addi 3, 1, -16
+; CHECK-AIX-NEXT:    lxvw4x 34, 0, 3
 ; CHECK-AIX-NEXT:    srwi 5, 5, 1
+; CHECK-AIX-NEXT:    mullw 3, 4, 5
+; CHECK-AIX-NEXT:    li 4, 0
+; CHECK-AIX-NEXT:    vsplth 2, 2, 0
+; CHECK-AIX-NEXT:    neg 3, 3
+; CHECK-AIX-NEXT:    stxvw4x 34, 0, 4
 ; CHECK-AIX-NEXT:    sth 3, -32(1)
 ; CHECK-AIX-NEXT:    addi 3, 1, -32
-; CHECK-AIX-NEXT:    mullw 4, 4, 5
-; CHECK-AIX-NEXT:    li 5, 0
-; CHECK-AIX-NEXT:    sth 5, -48(1)
-; CHECK-AIX-NEXT:    neg 4, 4
-; CHECK-AIX-NEXT:    sth 4, -16(1)
-; CHECK-AIX-NEXT:    addi 4, 1, -48
-; CHECK-AIX-NEXT:    lxvw4x 34, 0, 4
-; CHECK-AIX-NEXT:    lxvw4x 35, 0, 3
-; CHECK-AIX-NEXT:    addi 3, 1, -16
-; CHECK-AIX-NEXT:    lxvw4x 36, 0, 3
-; CHECK-AIX-NEXT:    ld 3, L..C0(2) # %const.0
-; CHECK-AIX-NEXT:    vmrghh 3, 2, 3
-; CHECK-AIX-NEXT:    vmrghh 4, 4, 2
+; CHECK-AIX-NEXT:    lxvw4x 34, 0, 3
 ; CHECK-AIX-NEXT:    vsplth 2, 2, 0
-; CHECK-AIX-NEXT:    xxmrghw 34, 35, 34
-; CHECK-AIX-NEXT:    lxvw4x 35, 0, 3
-; CHECK-AIX-NEXT:    vperm 2, 2, 4, 3
-; CHECK-AIX-NEXT:    vsplth 3, 2, 1
-; CHECK-AIX-NEXT:    vsplth 2, 2, 4
-; CHECK-AIX-NEXT:    stxvw4x 35, 0, 5
 ; CHECK-AIX-NEXT:    stxvw4x 34, 0, 3
 ;
 ; CHECK-LABEL: test_aix_splatimm:
diff --git a/llvm/test/CodeGen/PowerPC/load-and-splat.ll b/llvm/test/CodeGen/PowerPC/load-and-splat.ll
index 91a19f58bb8ec0..469a56dfac1a8c 100644
--- a/llvm/test/CodeGen/PowerPC/load-and-splat.ll
+++ b/llvm/test/CodeGen/PowerPC/load-and-splat.ll
@@ -604,31 +604,22 @@ define <16 x i8> @adjusted_lxvwsx(i64* %s, i64* %t) {
 ;
 ; P9-AIX32-LABEL: adjusted_lxvwsx:
 ; P9-AIX32:       # %bb.0: # %entry
-; P9-AIX32-NEXT:    lwz r3, 4(r3)
-; P9-AIX32-NEXT:    stw r3, -16(r1)
-; P9-AIX32-NEXT:    lxv vs0, -16(r1)
-; P9-AIX32-NEXT:    xxmrghw v2, vs0, vs0
-; P9-AIX32-NEXT:    xxspltw v2, v2, 1
+; P9-AIX32-NEXT:    addi r3, r3, 4
+; P9-AIX32-NEXT:    lxvwsx v2, 0, r3
 ; P9-AIX32-NEXT:    blr
 ;
 ; P8-AIX32-LABEL: adjusted_lxvwsx:
 ; P8-AIX32:       # %bb.0: # %entry
-; P8-AIX32-NEXT:    lwz r3, 4(r3)
-; P8-AIX32-NEXT:    addi r4, r1, -16
-; P8-AIX32-NEXT:    stw r3, -16(r1)
-; P8-AIX32-NEXT:    lxvw4x vs0, 0, r4
-; P8-AIX32-NEXT:    xxmrghw v2, vs0, vs0
-; P8-AIX32-NEXT:    xxspltw v2, v2, 1
+; P8-AIX32-NEXT:    addi r3, r3, 4
+; P8-AIX32-NEXT:    lfiwzx f0, 0, r3
+; P8-AIX32-NEXT:    xxspltw v2, vs0, 1
 ; P8-AIX32-NEXT:    blr
 ;
 ; P7-AIX32-LABEL: adjusted_lxvwsx:
 ; P7-AIX32:       # %bb.0: # %entry
-; P7-AIX32-NEXT:    lwz r3, 4(r3)
-; P7-AIX32-NEXT:    addi r4, r1, -16
-; P7-AIX32-NEXT:    stw r3, -16(r1)
-; P7-AIX32-NEXT:    lxvw4x vs0, 0, r4
-; P7-AIX32-NEXT:    xxmrghw v2, vs0, vs0
-; P7-AIX32-NEXT:    xxspltw v2, v2, 1
+; P7-AIX32-NEXT:    addi r3, r3, 4
+; P7-AIX32-NEXT:    lfiwzx f0, 0, r3
+; P7-AIX32-NEXT:    xxspltw v2, vs0, 1
 ; P7-AIX32-NEXT:    blr
   entry:
     %0 = bitcast i64* %s to <8 x i8>*