From 5a6c622afdff2c18d82dbe4f463450feaa8b7e5e Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Tue, 18 Jan 2022 11:42:25 -0800 Subject: [PATCH] [RISCV] Remove special case for constant shift amount in FSHL/FSHR lowering to FSL/FSR. Remove fshl/fshr with constant shift amount isel patterns. Replace with fsr/fsl with constant isel patterns. This hack was trying to preserve as much optimization opportunity for fshl/fshr by constant as possible, but the conversion to RISCVISD::FSR/FSL happens so late it probably isn't worth much. The new isel patterns are needed by D117468 anyway. --- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 2 -- llvm/lib/Target/RISCV/RISCVInstrInfoZb.td | 11 +++-------- 2 files changed, 3 insertions(+), 10 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 078ce1b5ef5e6..9f720b674bfba 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -2792,8 +2792,6 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op, MVT VT = Op.getSimpleValueType(); assert(VT == Subtarget.getXLenVT() && "Unexpected custom legalization"); SDLoc DL(Op); - if (Op.getOperand(2).getOpcode() == ISD::Constant) - return Op; // FSL/FSR take a log2(XLen)+1 bit shift amount but XLenVT FSHL/FSHR only // use log(XLen) bits. Mask the shift amount accordingly to prevent // accidentally setting the extra bit. diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td index 74f617c8333a7..f23fd2adb665b 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td @@ -906,16 +906,11 @@ def : Pat<(riscv_fsl GPR:$rs1, GPR:$rs3, GPR:$rs2), (FSL GPR:$rs1, GPR:$rs2, GPR:$rs3)>; def : Pat<(riscv_fsr GPR:$rs1, GPR:$rs3, GPR:$rs2), (FSR GPR:$rs1, GPR:$rs2, GPR:$rs3)>; - -// fshl and fshr concatenate their operands in the same order. fsr and fsl -// instruction use different orders. fshl will return its first operand for -// shift of zero, fshr will return its second operand. fsl and fsr both return -// $rs1 so the patterns need to have different operand orders. -def : Pat<(fshr GPR:$rs3, GPR:$rs1, uimmlog2xlen:$shamt), +def : Pat<(riscv_fsr GPR:$rs1, GPR:$rs3, uimmlog2xlen:$shamt), (FSRI GPR:$rs1, GPR:$rs3, uimmlog2xlen:$shamt)>; -// We can use FSRI for fshl by immediate if we subtract the immediate from +// We can use FSRI for FSL by immediate if we subtract the immediate from // XLen and swap the operands. -def : Pat<(fshl GPR:$rs3, GPR:$rs1, uimmlog2xlen:$shamt), +def : Pat<(riscv_fsl GPR:$rs3, GPR:$rs1, uimmlog2xlen:$shamt), (FSRI GPR:$rs1, GPR:$rs3, (ImmSubFromXLen uimmlog2xlen:$shamt))>; } // Predicates = [HasStdExtZbt]