diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index 26ff1f2f49c290..02eb3287363be0 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -492,7 +492,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
       .unsupportedIf([&](const LegalityQuery &Query) {
         return Query.Types[0].getSizeInBits() != Query.Types[1].getSizeInBits();
       })
-      .legalFor({{p0, s64}});
+      .legalFor({{p0, s64}, {v2p0, v2s64}});
 
   // Casts for 32 and 64-bit width type are just copies.
   // Same for 128-bit width type, except they are on the FPR bank.
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-inttoptr.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-inttoptr.mir
new file mode 100644
index 00000000000000..cde5889a946b1b
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-inttoptr.mir
@@ -0,0 +1,44 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple aarch64 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
+
+...
+---
+name:            p0_s64_legal
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $q0, $x0
+    ; CHECK-LABEL: name: p0_s64_legal
+    ; CHECK: liveins: $q0, $x0
+    ; CHECK: %copy:_(s64) = COPY $x0
+    ; CHECK: %inttoptr:_(p0) = G_INTTOPTR %copy(s64)
+    ; CHECK: $x0 = COPY %inttoptr(p0)
+    ; CHECK: RET_ReallyLR implicit $x0
+    %copy:_(s64) = COPY $x0
+    %inttoptr:_(p0) = G_INTTOPTR %copy(s64)
+    $x0 = COPY %inttoptr(p0)
+    RET_ReallyLR implicit $x0
+...
+---
+name:            v2s64_to_v2p0_legal
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $q0, $x0
+
+    ; CHECK-LABEL: name: v2s64_to_v2p0_legal
+    ; CHECK: liveins: $q0, $x0
+    ; CHECK: %copy:_(<2 x s64>) = COPY $q0
+    ; CHECK: %idx:_(s64) = G_CONSTANT i64 0
+    ; CHECK: %inttoptr:_(<2 x p0>) = G_INTTOPTR %copy(<2 x s64>)
+    ; CHECK: %extract:_(p0) = G_EXTRACT_VECTOR_ELT %inttoptr(<2 x p0>), %idx(s64)
+    ; CHECK: $x0 = COPY %extract(p0)
+    ; CHECK: RET_ReallyLR implicit $x0
+    %copy:_(<2 x s64>) = COPY $q0
+    %idx:_(s64) = G_CONSTANT i64 0
+    %inttoptr:_(<2 x p0>) = G_INTTOPTR %copy(<2 x s64>)
+    %extract:_(p0) = G_EXTRACT_VECTOR_ELT %inttoptr(<2 x p0>), %idx(s64)
+    $x0 = COPY %extract(p0)
+    RET_ReallyLR implicit $x0
+
+...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir
index 31a44089f0c31f..07a2a9b78d8043 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir
@@ -10,6 +10,7 @@
   define void @ptrtoint_s16_p0() { ret void }
   define void @ptrtoint_s8_p0() { ret void }
   define void @ptrtoint_s1_p0() { ret void }
+  define void @inttoptr_v2p0_v2s64() { ret void }
 ...
 
 ---
@@ -135,3 +136,25 @@ body:             |
     %2:gpr(s32) = G_ANYEXT %1
     $w0 = COPY %2(s32)
 ...
+
+---
+name:            inttoptr_v2p0_v2s64
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $q0, $x0
+    ; CHECK-LABEL: name: inttoptr_v2p0_v2s64
+    ; CHECK: liveins: $q0, $x0
+    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY [[COPY]].dsub
+    ; CHECK: $x0 = COPY [[COPY1]]
+    ; CHECK: RET_ReallyLR implicit $x0
+    %1:fpr(<2 x s64>) = COPY $q0
+    %2:fpr(<2 x p0>) = G_INTTOPTR %1(<2 x s64>)
+    %4:gpr(s64) = G_CONSTANT i64 0
+    %3:fpr(p0) = G_EXTRACT_VECTOR_ELT %2(<2 x p0>), %4(s64)
+    $x0 = COPY %3(p0)
+    RET_ReallyLR implicit $x0
+...