diff --git a/llvm/lib/Target/X86/X86CompressEVEX.cpp b/llvm/lib/Target/X86/X86CompressEVEX.cpp index fc980c611dc67..07b59437fe2f8 100644 --- a/llvm/lib/Target/X86/X86CompressEVEX.cpp +++ b/llvm/lib/Target/X86/X86CompressEVEX.cpp @@ -11,7 +11,7 @@ // // Possible compression: // a. AVX512 instruction (EVEX) -> AVX instruction (VEX) -// b. Promoted instruction (EVEX) -> pre-promotion instruction (legacy) +// b. Promoted instruction (EVEX) -> pre-promotion instruction (legacy/VEX) // c. NDD (EVEX) -> non-NDD (legacy) // d. NF_ND (EVEX) -> NF (EVEX) // @@ -272,7 +272,7 @@ bool CompressEVEXPass::runOnMachineFunction(MachineFunction &MF) { } #endif const X86Subtarget &ST = MF.getSubtarget(); - if (!ST.hasAVX512()) + if (!ST.hasAVX512() && !ST.hasEGPR()) return false; bool Changed = false; diff --git a/llvm/utils/TableGen/X86CompressEVEXTablesEmitter.cpp b/llvm/utils/TableGen/X86CompressEVEXTablesEmitter.cpp index 82a9bfee0115b..b03bcb6bc26b3 100644 --- a/llvm/utils/TableGen/X86CompressEVEXTablesEmitter.cpp +++ b/llvm/utils/TableGen/X86CompressEVEXTablesEmitter.cpp @@ -136,7 +136,17 @@ void X86CompressEVEXTablesEmitter::run(raw_ostream &OS) { for (const CodeGenInstruction *Inst : NumberedInstructions) { const Record *Rec = Inst->TheDef; // _REV instruction should not appear before encoding optimization - if (!Rec->isSubClassOf("X86Inst") || Rec->getName().ends_with("_REV")) + if (!Rec->isSubClassOf("X86Inst") || + Rec->getValueAsBit("isAsmParserOnly") || + Rec->getName().ends_with("_REV")) + continue; + + // Promoted legacy instruction is in EVEX space, and has REX2-encoding + // alternative. It's added due to HW design and never emitted by compiler. + if (byteFromBitsInit(Rec->getValueAsBitsInit("OpMapBits")) == + X86Local::T_MAP4 && + byteFromBitsInit(Rec->getValueAsBitsInit("explicitOpPrefixBits")) == + X86Local::ExplicitEVEX) continue; if (NoCompressSet.find(Rec->getName()) != NoCompressSet.end())