diff --git a/llvm/lib/Target/VE/VEISelLowering.cpp b/llvm/lib/Target/VE/VEISelLowering.cpp
index e045899a1ec9db..bfe1e8d39e47a3 100644
--- a/llvm/lib/Target/VE/VEISelLowering.cpp
+++ b/llvm/lib/Target/VE/VEISelLowering.cpp
@@ -672,6 +672,14 @@ VETargetLowering::VETargetLowering(const TargetMachine &TM,
     setOperationAction(ISD::SDIVREM, IntVT, Expand);
     setOperationAction(ISD::UDIVREM, IntVT, Expand);
 
+    // VE has no MULHU/S or U/SMUL_LOHI operations.
+    // TODO: Use MPD instruction to implement SMUL_LOHI for i32 type.
+    setOperationAction(ISD::MULHU, IntVT, Expand);
+    setOperationAction(ISD::MULHS, IntVT, Expand);
+    setOperationAction(ISD::UMUL_LOHI, IntVT, Expand);
+    setOperationAction(ISD::SMUL_LOHI, IntVT, Expand);
+
+    // VE has no CTTZ, ROTL, ROTR operations.
     setOperationAction(ISD::CTTZ, IntVT, Expand);
     setOperationAction(ISD::ROTL, IntVT, Expand);
     setOperationAction(ISD::ROTR, IntVT, Expand);
diff --git a/llvm/test/CodeGen/VE/addition.ll b/llvm/test/CodeGen/VE/addition.ll
index 783bb275d5e114..a36ad44bd1c4cc 100644
--- a/llvm/test/CodeGen/VE/addition.ll
+++ b/llvm/test/CodeGen/VE/addition.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
 
-define signext i8 @func1(i8 signext %0, i8 signext %1) {
-; CHECK-LABEL: func1:
+define signext i8 @func8s(i8 signext %0, i8 signext %1) {
+; CHECK-LABEL: func8s:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    adds.w.sx %s0, %s1, %s0
 ; CHECK-NEXT:    sll %s0, %s0, 56
@@ -11,8 +11,8 @@ define signext i8 @func1(i8 signext %0, i8 signext %1) {
   ret i8 %3
 }
 
-define signext i16 @func2(i16 signext %0, i16 signext %1) {
-; CHECK-LABEL: func2:
+define signext i16 @func16s(i16 signext %0, i16 signext %1) {
+; CHECK-LABEL: func16s:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    adds.w.sx %s0, %s1, %s0
 ; CHECK-NEXT:    sll %s0, %s0, 48
@@ -22,17 +22,18 @@ define signext i16 @func2(i16 signext %0, i16 signext %1) {
   ret i16 %3
 }
 
-define i32 @func3(i32 %0, i32 %1) {
-; CHECK-LABEL: func3:
+define signext i32 @func32s(i32 signext %0, i32 signext %1) {
+; CHECK-LABEL: func32s:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    adds.w.sx %s0, %s1, %s0
+; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = add nsw i32 %1, %0
   ret i32 %3
 }
 
-define i64 @func4(i64 %0, i64 %1) {
-; CHECK-LABEL: func4:
+define i64 @func64s(i64 %0, i64 %1) {
+; CHECK-LABEL: func64s:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    adds.l %s0, %s1, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
@@ -40,8 +41,23 @@ define i64 @func4(i64 %0, i64 %1) {
   ret i64 %3
 }
 
-define zeroext i8 @func6(i8 zeroext %0, i8 zeroext %1) {
-; CHECK-LABEL: func6:
+define i128 @func128s(i128 %0, i128 %1) {
+; CHECK-LABEL: func128s:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    adds.l %s1, %s3, %s1
+; CHECK-NEXT:    adds.l %s0, %s2, %s0
+; CHECK-NEXT:    cmpu.l %s2, %s0, %s2
+; CHECK-NEXT:    or %s3, 0, (0)1
+; CHECK-NEXT:    cmov.l.lt %s3, (63)0, %s2
+; CHECK-NEXT:    adds.w.zx %s2, %s3, (0)1
+; CHECK-NEXT:    adds.l %s1, %s1, %s2
+; CHECK-NEXT:    or %s11, 0, %s9
+  %3 = add nsw i128 %1, %0
+  ret i128 %3
+}
+
+define zeroext i8 @func8z(i8 zeroext %0, i8 zeroext %1) {
+; CHECK-LABEL: func8z:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    adds.w.sx %s0, %s1, %s0
 ; CHECK-NEXT:    and %s0, %s0, (56)0
@@ -50,8 +66,8 @@ define zeroext i8 @func6(i8 zeroext %0, i8 zeroext %1) {
   ret i8 %3
 }
 
-define zeroext i16 @func7(i16 zeroext %0, i16 zeroext %1) {
-; CHECK-LABEL: func7:
+define zeroext i16 @func16z(i16 zeroext %0, i16 zeroext %1) {
+; CHECK-LABEL: func16z:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    adds.w.sx %s0, %s1, %s0
 ; CHECK-NEXT:    and %s0, %s0, (48)0
@@ -60,17 +76,18 @@ define zeroext i16 @func7(i16 zeroext %0, i16 zeroext %1) {
   ret i16 %3
 }
 
-define i32 @func8(i32 %0, i32 %1) {
-; CHECK-LABEL: func8:
+define zeroext i32 @func32z(i32 zeroext %0, i32 zeroext %1) {
+; CHECK-LABEL: func32z:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    adds.w.sx %s0, %s1, %s0
+; CHECK-NEXT:    adds.w.zx %s0, %s0, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = add i32 %1, %0
   ret i32 %3
 }
 
-define i64 @func9(i64 %0, i64 %1) {
-; CHECK-LABEL: func9:
+define i64 @func64z(i64 %0, i64 %1) {
+; CHECK-LABEL: func64z:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    adds.l %s0, %s1, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
@@ -78,8 +95,23 @@ define i64 @func9(i64 %0, i64 %1) {
   ret i64 %3
 }
 
-define signext i8 @func13(i8 signext %0) {
-; CHECK-LABEL: func13:
+define i128 @func128z(i128 %0, i128 %1) {
+; CHECK-LABEL: func128z:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    adds.l %s1, %s3, %s1
+; CHECK-NEXT:    adds.l %s0, %s2, %s0
+; CHECK-NEXT:    cmpu.l %s2, %s0, %s2
+; CHECK-NEXT:    or %s3, 0, (0)1
+; CHECK-NEXT:    cmov.l.lt %s3, (63)0, %s2
+; CHECK-NEXT:    adds.w.zx %s2, %s3, (0)1
+; CHECK-NEXT:    adds.l %s1, %s1, %s2
+; CHECK-NEXT:    or %s11, 0, %s9
+  %3 = add i128 %1, %0
+  ret i128 %3
+}
+
+define signext i8 @funci8s(i8 signext %0) {
+; CHECK-LABEL: funci8s:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    adds.w.sx %s0, 5, %s0
 ; CHECK-NEXT:    sll %s0, %s0, 56
@@ -89,8 +121,8 @@ define signext i8 @func13(i8 signext %0) {
   ret i8 %2
 }
 
-define signext i16 @func14(i16 signext %0) {
-; CHECK-LABEL: func14:
+define signext i16 @funci16s(i16 signext %0) {
+; CHECK-LABEL: funci16s:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    adds.w.sx %s0, 5, %s0
 ; CHECK-NEXT:    sll %s0, %s0, 48
@@ -100,17 +132,18 @@ define signext i16 @func14(i16 signext %0) {
   ret i16 %2
 }
 
-define i32 @func15(i32 %0) {
-; CHECK-LABEL: func15:
+define signext i32 @funci32s(i32 signext %0) {
+; CHECK-LABEL: funci32s:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    adds.w.sx %s0, 5, %s0
+; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = add nsw i32 %0, 5
   ret i32 %2
 }
 
-define i64 @func16(i64 %0) {
-; CHECK-LABEL: func16:
+define i64 @funci64s(i64 %0) {
+; CHECK-LABEL: funci64s:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s0, 5(, %s0)
 ; CHECK-NEXT:    or %s11, 0, %s9
@@ -118,8 +151,23 @@ define i64 @func16(i64 %0) {
   ret i64 %2
 }
 
-define zeroext i8 @func18(i8 zeroext %0) {
-; CHECK-LABEL: func18:
+define i128 @funci128s(i128 %0) {
+; CHECK-LABEL: funci128s:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    lea %s2, 5(, %s0)
+; CHECK-NEXT:    cmpu.l %s0, %s2, %s0
+; CHECK-NEXT:    or %s3, 0, (0)1
+; CHECK-NEXT:    cmov.l.lt %s3, (63)0, %s0
+; CHECK-NEXT:    adds.w.zx %s0, %s3, (0)1
+; CHECK-NEXT:    adds.l %s1, %s1, %s0
+; CHECK-NEXT:    or %s0, 0, %s2
+; CHECK-NEXT:    or %s11, 0, %s9
+  %2 = add nsw i128 %0, 5
+  ret i128 %2
+}
+
+define zeroext i8 @funci8z(i8 zeroext %0) {
+; CHECK-LABEL: funci8z:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    adds.w.sx %s0, 5, %s0
 ; CHECK-NEXT:    and %s0, %s0, (56)0
@@ -128,8 +176,8 @@ define zeroext i8 @func18(i8 zeroext %0) {
   ret i8 %2
 }
 
-define zeroext i16 @func19(i16 zeroext %0) {
-; CHECK-LABEL: func19:
+define zeroext i16 @funci16z(i16 zeroext %0) {
+; CHECK-LABEL: funci16z:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    adds.w.sx %s0, 5, %s0
 ; CHECK-NEXT:    and %s0, %s0, (48)0
@@ -138,17 +186,18 @@ define zeroext i16 @func19(i16 zeroext %0) {
   ret i16 %2
 }
 
-define i32 @func20(i32 %0) {
-; CHECK-LABEL: func20:
+define zeroext i32 @funci32z(i32 zeroext %0) {
+; CHECK-LABEL: funci32z:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    adds.w.sx %s0, 5, %s0
+; CHECK-NEXT:    adds.w.zx %s0, %s0, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = add i32 %0, 5
   ret i32 %2
 }
 
-define i64 @func21(i64 %0) {
-; CHECK-LABEL: func21:
+define i64 @funci64z(i64 %0) {
+; CHECK-LABEL: funci64z:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s0, 5(, %s0)
 ; CHECK-NEXT:    or %s11, 0, %s9
@@ -156,8 +205,23 @@ define i64 @func21(i64 %0) {
   ret i64 %2
 }
 
-define i64 @func26(i64 %0) {
-; CHECK-LABEL: func26:
+define i128 @funci128z(i128 %0) {
+; CHECK-LABEL: funci128z:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    lea %s2, 5(, %s0)
+; CHECK-NEXT:    cmpu.l %s0, %s2, %s0
+; CHECK-NEXT:    or %s3, 0, (0)1
+; CHECK-NEXT:    cmov.l.lt %s3, (63)0, %s0
+; CHECK-NEXT:    adds.w.zx %s0, %s3, (0)1
+; CHECK-NEXT:    adds.l %s1, %s1, %s0
+; CHECK-NEXT:    or %s0, 0, %s2
+; CHECK-NEXT:    or %s11, 0, %s9
+  %2 = add i128 %0, 5
+  ret i128 %2
+}
+
+define i64 @funci64_2(i64 %0) {
+; CHECK-LABEL: funci64_2:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s1, -2147483648
 ; CHECK-NEXT:    and %s1, %s1, (32)0
@@ -167,3 +231,19 @@ define i64 @func26(i64 %0) {
   ret i64 %2
 }
 
+define i128 @funci128_2(i128 %0) {
+; CHECK-LABEL: funci128_2:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    lea %s2, -2147483648
+; CHECK-NEXT:    and %s2, %s2, (32)0
+; CHECK-NEXT:    adds.l %s2, %s0, %s2
+; CHECK-NEXT:    cmpu.l %s0, %s2, %s0
+; CHECK-NEXT:    or %s3, 0, (0)1
+; CHECK-NEXT:    cmov.l.lt %s3, (63)0, %s0
+; CHECK-NEXT:    adds.w.zx %s0, %s3, (0)1
+; CHECK-NEXT:    adds.l %s1, %s1, %s0
+; CHECK-NEXT:    or %s0, 0, %s2
+; CHECK-NEXT:    or %s11, 0, %s9
+  %2 = add nsw i128 %0, 2147483648
+  ret i128 %2
+}
diff --git a/llvm/test/CodeGen/VE/div.ll b/llvm/test/CodeGen/VE/div.ll
index b1f5fdf5c5a9e8..b3808b5a8b23fe 100644
--- a/llvm/test/CodeGen/VE/div.ll
+++ b/llvm/test/CodeGen/VE/div.ll
@@ -1,5 +1,18 @@
 ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
 
+; Function Attrs: norecurse nounwind readnone
+define i128 @divi128(i128, i128) {
+; CHECK-LABEL: divi128:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    lea %s4, __divti3@lo
+; CHECK-NEXT:    and %s4, %s4, (32)0
+; CHECK-NEXT:    lea.sl %s12, __divti3@hi(, %s4)
+; CHECK-NEXT:    bsic %s10, (, %s12)
+; CHECK-NEXT:    or %s11, 0, %s9
+  %3 = sdiv i128 %0, %1
+  ret i128 %3
+}
+
 ; Function Attrs: norecurse nounwind readnone
 define i64 @divi64(i64 %a, i64 %b) {
 ; CHECK-LABEL: divi64:
@@ -11,15 +24,29 @@ define i64 @divi64(i64 %a, i64 %b) {
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define i32 @divi32(i32 %a, i32 %b) {
+define signext i32 @divi32(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: divi32:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    divs.w.sx %s0, %s0, %s1
+; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = sdiv i32 %a, %b
   ret i32 %r
 }
 
+; Function Attrs: norecurse nounwind readnone
+define i128 @divu128(i128, i128) {
+; CHECK-LABEL: divu128:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    lea %s4, __udivti3@lo
+; CHECK-NEXT:    and %s4, %s4, (32)0
+; CHECK-NEXT:    lea.sl %s12, __udivti3@hi(, %s4)
+; CHECK-NEXT:    bsic %s10, (, %s12)
+; CHECK-NEXT:    or %s11, 0, %s9
+  %3 = udiv i128 %0, %1
+  ret i128 %3
+}
+
 ; Function Attrs: norecurse nounwind readnone
 define i64 @divu64(i64 %a, i64 %b) {
 ; CHECK-LABEL: divu64:
@@ -31,10 +58,11 @@ define i64 @divu64(i64 %a, i64 %b) {
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define i32 @divu32(i32 %a, i32 %b) {
+define zeroext i32 @divu32(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: divu32:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    divu.w %s0, %s0, %s1
+; CHECK-NEXT:    adds.w.zx %s0, %s0, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = udiv i32 %a, %b
   ret i32 %r
@@ -92,6 +120,21 @@ define zeroext i8 @divu8(i8 zeroext %a, i8 zeroext %b) {
   ret i8 %r
 }
 
+; Function Attrs: norecurse nounwind readnone
+define i128 @divi128ri(i128) {
+; CHECK-LABEL: divi128ri:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    lea %s2, __divti3@lo
+; CHECK-NEXT:    and %s2, %s2, (32)0
+; CHECK-NEXT:    lea.sl %s12, __divti3@hi(, %s2)
+; CHECK-NEXT:    or %s2, 3, (0)1
+; CHECK-NEXT:    or %s3, 0, (0)1
+; CHECK-NEXT:    bsic %s10, (, %s12)
+; CHECK-NEXT:    or %s11, 0, %s9
+  %2 = sdiv i128 %0, 3
+  ret i128 %2
+}
+
 ; Function Attrs: norecurse nounwind readnone
 define i64 @divi64ri(i64 %a, i64 %b) {
 ; CHECK-LABEL: divi64ri:
@@ -103,15 +146,31 @@ define i64 @divi64ri(i64 %a, i64 %b) {
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define i32 @divi32ri(i32 %a, i32 %b) {
+define signext i32 @divi32ri(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: divi32ri:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    divs.w.sx %s0, %s0, (62)0
+; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = sdiv i32 %a, 3
   ret i32 %r
 }
 
+; Function Attrs: norecurse nounwind readnone
+define i128 @divu128ri(i128) {
+; CHECK-LABEL: divu128ri:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    lea %s2, __udivti3@lo
+; CHECK-NEXT:    and %s2, %s2, (32)0
+; CHECK-NEXT:    lea.sl %s12, __udivti3@hi(, %s2)
+; CHECK-NEXT:    or %s2, 3, (0)1
+; CHECK-NEXT:    or %s3, 0, (0)1
+; CHECK-NEXT:    bsic %s10, (, %s12)
+; CHECK-NEXT:    or %s11, 0, %s9
+  %2 = udiv i128 %0, 3
+  ret i128 %2
+}
+
 ; Function Attrs: norecurse nounwind readnone
 define i64 @divu64ri(i64 %a, i64 %b) {
 ; CHECK-LABEL: divu64ri:
@@ -123,15 +182,33 @@ define i64 @divu64ri(i64 %a, i64 %b) {
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define i32 @divu32ri(i32 %a, i32 %b) {
+define zeroext i32 @divu32ri(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: divu32ri:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    divu.w %s0, %s0, (62)0
+; CHECK-NEXT:    adds.w.zx %s0, %s0, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = udiv i32 %a, 3
   ret i32 %r
 }
 
+; Function Attrs: norecurse nounwind readnone
+define i128 @divi128li(i128) {
+; CHECK-LABEL: divi128li:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    or %s3, 0, %s1
+; CHECK-NEXT:    or %s2, 0, %s0
+; CHECK-NEXT:    lea %s0, __divti3@lo
+; CHECK-NEXT:    and %s0, %s0, (32)0
+; CHECK-NEXT:    lea.sl %s12, __divti3@hi(, %s0)
+; CHECK-NEXT:    or %s0, 3, (0)1
+; CHECK-NEXT:    or %s1, 0, (0)1
+; CHECK-NEXT:    bsic %s10, (, %s12)
+; CHECK-NEXT:    or %s11, 0, %s9
+  %2 = sdiv i128 3, %0
+  ret i128 %2
+}
+
 ; Function Attrs: norecurse nounwind readnone
 define i64 @divi64li(i64 %a, i64 %b) {
 ; CHECK-LABEL: divi64li:
@@ -143,15 +220,33 @@ define i64 @divi64li(i64 %a, i64 %b) {
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define i32 @divi32li(i32 %a, i32 %b) {
+define signext i32 @divi32li(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: divi32li:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    divs.w.sx %s0, 3, %s1
+; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = sdiv i32 3, %b
   ret i32 %r
 }
 
+; Function Attrs: norecurse nounwind readnone
+define i128 @divu128li(i128) {
+; CHECK-LABEL: divu128li:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    or %s3, 0, %s1
+; CHECK-NEXT:    or %s2, 0, %s0
+; CHECK-NEXT:    lea %s0, __udivti3@lo
+; CHECK-NEXT:    and %s0, %s0, (32)0
+; CHECK-NEXT:    lea.sl %s12, __udivti3@hi(, %s0)
+; CHECK-NEXT:    or %s0, 3, (0)1
+; CHECK-NEXT:    or %s1, 0, (0)1
+; CHECK-NEXT:    bsic %s10, (, %s12)
+; CHECK-NEXT:    or %s11, 0, %s9
+  %2 = udiv i128 3, %0
+  ret i128 %2
+}
+
 ; Function Attrs: norecurse nounwind readnone
 define i64 @divu64li(i64 %a, i64 %b) {
 ; CHECK-LABEL: divu64li:
@@ -163,10 +258,11 @@ define i64 @divu64li(i64 %a, i64 %b) {
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define i32 @divu32li(i32 %a, i32 %b) {
+define zeroext i32 @divu32li(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: divu32li:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    divu.w %s0, 3, %s1
+; CHECK-NEXT:    adds.w.zx %s0, %s0, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = udiv i32 3, %b
   ret i32 %r
diff --git a/llvm/test/CodeGen/VE/multiply.ll b/llvm/test/CodeGen/VE/multiply.ll
index cfff4c70cd3785..8b37a5b62c20de 100644
--- a/llvm/test/CodeGen/VE/multiply.ll
+++ b/llvm/test/CodeGen/VE/multiply.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
 
-define signext i8 @func1(i8 signext %a, i8 signext %b) {
-; CHECK-LABEL: func1:
+define signext i8 @func8s(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: func8s:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    muls.w.sx %s0, %s1, %s0
 ; CHECK-NEXT:    sll %s0, %s0, 56
@@ -11,8 +11,8 @@ define signext i8 @func1(i8 signext %a, i8 signext %b) {
   ret i8 %r
 }
 
-define signext i16 @func2(i16 signext %a, i16 signext %b) {
-; CHECK-LABEL: func2:
+define signext i16 @func16s(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: func16s:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    muls.w.sx %s0, %s1, %s0
 ; CHECK-NEXT:    sll %s0, %s0, 48
@@ -22,17 +22,18 @@ define signext i16 @func2(i16 signext %a, i16 signext %b) {
   ret i16 %r
 }
 
-define i32 @func3(i32 %a, i32 %b) {
-; CHECK-LABEL: func3:
+define signext i32 @func32s(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: func32s:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    muls.w.sx %s0, %s1, %s0
+; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = mul nsw i32 %b, %a
   ret i32 %r
 }
 
-define i64 @func4(i64 %a, i64 %b) {
-; CHECK-LABEL: func4:
+define i64 @func64(i64 %a, i64 %b) {
+; CHECK-LABEL: func64:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    muls.l %s0, %s1, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
@@ -40,8 +41,26 @@ define i64 @func4(i64 %a, i64 %b) {
   ret i64 %r
 }
 
-define zeroext i8 @func5(i8 zeroext %a, i8 zeroext %b) {
-; CHECK-LABEL: func5:
+define i128 @func128(i128 %a, i128 %b) {
+; CHECK-LABEL: func128:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    or %s4, 0, %s1
+; CHECK-NEXT:    or %s5, 0, %s0
+; CHECK-NEXT:    lea %s0, __multi3@lo
+; CHECK-NEXT:    and %s0, %s0, (32)0
+; CHECK-NEXT:    lea.sl %s12, __multi3@hi(, %s0)
+; CHECK-NEXT:    or %s0, 0, %s2
+; CHECK-NEXT:    or %s1, 0, %s3
+; CHECK-NEXT:    or %s2, 0, %s5
+; CHECK-NEXT:    or %s3, 0, %s4
+; CHECK-NEXT:    bsic %s10, (, %s12)
+; CHECK-NEXT:    or %s11, 0, %s9
+  %r = mul nsw i128 %b, %a
+  ret i128 %r
+}
+
+define zeroext i8 @func8z(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: func8z:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    muls.w.sx %s0, %s1, %s0
 ; CHECK-NEXT:    and %s0, %s0, (56)0
@@ -50,8 +69,8 @@ define zeroext i8 @func5(i8 zeroext %a, i8 zeroext %b) {
   ret i8 %r
 }
 
-define zeroext i16 @func6(i16 zeroext %a, i16 zeroext %b) {
-; CHECK-LABEL: func6:
+define zeroext i16 @func16z(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: func16z:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    muls.w.sx %s0, %s1, %s0
 ; CHECK-NEXT:    and %s0, %s0, (48)0
@@ -60,17 +79,18 @@ define zeroext i16 @func6(i16 zeroext %a, i16 zeroext %b) {
   ret i16 %r
 }
 
-define i32 @func7(i32 %a, i32 %b) {
-; CHECK-LABEL: func7:
+define zeroext i32 @func32z(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: func32z:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    muls.w.sx %s0, %s1, %s0
+; CHECK-NEXT:    adds.w.zx %s0, %s0, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = mul i32 %b, %a
   ret i32 %r
 }
 
-define i64 @func8(i64 %a, i64 %b) {
-; CHECK-LABEL: func8:
+define i64 @func64z(i64 %a, i64 %b) {
+; CHECK-LABEL: func64z:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    muls.l %s0, %s1, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
@@ -78,8 +98,26 @@ define i64 @func8(i64 %a, i64 %b) {
   ret i64 %r
 }
 
-define signext i8 @func9(i8 signext %a) {
-; CHECK-LABEL: func9:
+define i128 @func128z(i128 %a, i128 %b) {
+; CHECK-LABEL: func128z:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    or %s4, 0, %s1
+; CHECK-NEXT:    or %s5, 0, %s0
+; CHECK-NEXT:    lea %s0, __multi3@lo
+; CHECK-NEXT:    and %s0, %s0, (32)0
+; CHECK-NEXT:    lea.sl %s12, __multi3@hi(, %s0)
+; CHECK-NEXT:    or %s0, 0, %s2
+; CHECK-NEXT:    or %s1, 0, %s3
+; CHECK-NEXT:    or %s2, 0, %s5
+; CHECK-NEXT:    or %s3, 0, %s4
+; CHECK-NEXT:    bsic %s10, (, %s12)
+; CHECK-NEXT:    or %s11, 0, %s9
+  %r = mul i128 %b, %a
+  ret i128 %r
+}
+
+define signext i8 @funci8s(i8 signext %a) {
+; CHECK-LABEL: funci8s:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    muls.w.sx %s0, 5, %s0
 ; CHECK-NEXT:    sll %s0, %s0, 56
@@ -89,8 +127,8 @@ define signext i8 @func9(i8 signext %a) {
   ret i8 %r
 }
 
-define signext i16 @func10(i16 signext %a) {
-; CHECK-LABEL: func10:
+define signext i16 @funci16s(i16 signext %a) {
+; CHECK-LABEL: funci16s:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    muls.w.sx %s0, 5, %s0
 ; CHECK-NEXT:    sll %s0, %s0, 48
@@ -100,17 +138,18 @@ define signext i16 @func10(i16 signext %a) {
   ret i16 %r
 }
 
-define i32 @func11(i32 %a) {
-; CHECK-LABEL: func11:
+define signext i32 @funci32s(i32 signext %a) {
+; CHECK-LABEL: funci32s:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    muls.w.sx %s0, 5, %s0
+; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = mul nsw i32 %a, 5
   ret i32 %r
 }
 
-define i64 @func12(i64 %a) {
-; CHECK-LABEL: func12:
+define i64 @funci64(i64 %a) {
+; CHECK-LABEL: funci64:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    muls.l %s0, 5, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
@@ -118,8 +157,22 @@ define i64 @func12(i64 %a) {
   ret i64 %r
 }
 
-define zeroext i8 @func13(i8 zeroext %a) {
-; CHECK-LABEL: func13:
+define i128 @funci128(i128 %a) {
+; CHECK-LABEL: funci128:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    lea %s2, __multi3@lo
+; CHECK-NEXT:    and %s2, %s2, (32)0
+; CHECK-NEXT:    lea.sl %s12, __multi3@hi(, %s2)
+; CHECK-NEXT:    or %s2, 5, (0)1
+; CHECK-NEXT:    or %s3, 0, (0)1
+; CHECK-NEXT:    bsic %s10, (, %s12)
+; CHECK-NEXT:    or %s11, 0, %s9
+  %r = mul nsw i128 %a, 5
+  ret i128 %r
+}
+
+define zeroext i8 @funci8z(i8 zeroext %a) {
+; CHECK-LABEL: funci8z:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    muls.w.sx %s0, 5, %s0
 ; CHECK-NEXT:    and %s0, %s0, (56)0
@@ -128,8 +181,8 @@ define zeroext i8 @func13(i8 zeroext %a) {
   ret i8 %r
 }
 
-define zeroext i16 @func14(i16 zeroext %a) {
-; CHECK-LABEL: func14:
+define zeroext i16 @funci16z(i16 zeroext %a) {
+; CHECK-LABEL: funci16z:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    muls.w.sx %s0, 5, %s0
 ; CHECK-NEXT:    and %s0, %s0, (48)0
@@ -138,17 +191,18 @@ define zeroext i16 @func14(i16 zeroext %a) {
   ret i16 %r
 }
 
-define i32 @func15(i32 %a) {
-; CHECK-LABEL: func15:
+define zeroext i32 @funci32z(i32 zeroext %a) {
+; CHECK-LABEL: funci32z:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    muls.w.sx %s0, 5, %s0
+; CHECK-NEXT:    adds.w.zx %s0, %s0, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = mul i32 %a, 5
   ret i32 %r
 }
 
-define i64 @func16(i64 %a) {
-; CHECK-LABEL: func16:
+define i64 @funci64z(i64 %a) {
+; CHECK-LABEL: funci64z:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    muls.l %s0, 5, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
@@ -156,20 +210,47 @@ define i64 @func16(i64 %a) {
   ret i64 %r
 }
 
-define i32 @func17(i32 %a) {
-; CHECK-LABEL: func17:
+define i128 @funci128z(i128 %a) {
+; CHECK-LABEL: funci128z:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    lea %s2, __multi3@lo
+; CHECK-NEXT:    and %s2, %s2, (32)0
+; CHECK-NEXT:    lea.sl %s12, __multi3@hi(, %s2)
+; CHECK-NEXT:    or %s2, 5, (0)1
+; CHECK-NEXT:    or %s3, 0, (0)1
+; CHECK-NEXT:    bsic %s10, (, %s12)
+; CHECK-NEXT:    or %s11, 0, %s9
+  %r = mul i128 %a, 5
+  ret i128 %r
+}
+
+define zeroext i32 @funci32z_2(i32 zeroext %a) {
+; CHECK-LABEL: funci32z_2:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    sla.w.sx %s0, %s0, 31
+; CHECK-NEXT:    adds.w.zx %s0, %s0, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = shl i32 %a, 31
   ret i32 %r
 }
 
-define i64 @func18(i64 %a) {
-; CHECK-LABEL: func18:
+define i64 @funci64_2(i64 %a) {
+; CHECK-LABEL: funci64_2:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    sll %s0, %s0, 31
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = shl nsw i64 %a, 31
   ret i64 %r
 }
+
+define i128 @funci128_2(i128 %a) {
+; CHECK-LABEL: funci128_2:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    srl %s2, %s0, 33
+; CHECK-NEXT:    sll %s1, %s1, 31
+; CHECK-NEXT:    or %s1, %s1, %s2
+; CHECK-NEXT:    sll %s0, %s0, 31
+; CHECK-NEXT:    or %s11, 0, %s9
+  %r = shl nsw i128 %a, 31
+  ret i128 %r
+}
diff --git a/llvm/test/CodeGen/VE/rem.ll b/llvm/test/CodeGen/VE/rem.ll
index 57e07827ed9ef0..d4e72ca866967a 100644
--- a/llvm/test/CodeGen/VE/rem.ll
+++ b/llvm/test/CodeGen/VE/rem.ll
@@ -1,5 +1,18 @@
 ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
 
+; Function Attrs: norecurse nounwind readnone
+define i128 @remi128(i128 %a, i128 %b) {
+; CHECK-LABEL: remi128:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    lea %s4, __modti3@lo
+; CHECK-NEXT:    and %s4, %s4, (32)0
+; CHECK-NEXT:    lea.sl %s12, __modti3@hi(, %s4)
+; CHECK-NEXT:    bsic %s10, (, %s12)
+; CHECK-NEXT:    or %s11, 0, %s9
+  %r = srem i128 %a, %b
+  ret i128 %r
+}
+
 ; Function Attrs: norecurse nounwind readnone
 define i64 @remi64(i64 %a, i64 %b) {
 ; CHECK-LABEL: remi64:
@@ -13,17 +26,31 @@ define i64 @remi64(i64 %a, i64 %b) {
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define i32 @remi32(i32 %a, i32 %b) {
+define signext i32 @remi32(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: remi32:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    divs.w.sx %s2, %s0, %s1
 ; CHECK-NEXT:    muls.w.sx %s1, %s2, %s1
 ; CHECK-NEXT:    subs.w.sx %s0, %s0, %s1
+; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = srem i32 %a, %b
   ret i32 %r
 }
 
+; Function Attrs: norecurse nounwind readnone
+define i128 @remu128(i128 %a, i128 %b) {
+; CHECK-LABEL: remu128:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    lea %s4, __umodti3@lo
+; CHECK-NEXT:    and %s4, %s4, (32)0
+; CHECK-NEXT:    lea.sl %s12, __umodti3@hi(, %s4)
+; CHECK-NEXT:    bsic %s10, (, %s12)
+; CHECK-NEXT:    or %s11, 0, %s9
+  %r = urem i128 %a, %b
+  ret i128 %r
+}
+
 ; Function Attrs: norecurse nounwind readnone
 define i64 @remu64(i64 %a, i64 %b) {
 ; CHECK-LABEL: remu64:
@@ -37,12 +64,13 @@ define i64 @remu64(i64 %a, i64 %b) {
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define i32 @remu32(i32 %a, i32 %b) {
+define zeroext i32 @remu32(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: remu32:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    divu.w %s2, %s0, %s1
 ; CHECK-NEXT:    muls.w.sx %s1, %s2, %s1
 ; CHECK-NEXT:    subs.w.sx %s0, %s0, %s1
+; CHECK-NEXT:    adds.w.zx %s0, %s0, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = urem i32 %a, %b
   ret i32 %r
@@ -109,7 +137,22 @@ define zeroext i8 @remu8(i8 zeroext %a, i8 zeroext %b) {
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define i64 @remi64ri(i64 %a, i64 %b) {
+define i128 @remi128ri(i128 %a) {
+; CHECK-LABEL: remi128ri:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    lea %s2, __modti3@lo
+; CHECK-NEXT:    and %s2, %s2, (32)0
+; CHECK-NEXT:    lea.sl %s12, __modti3@hi(, %s2)
+; CHECK-NEXT:    or %s2, 3, (0)1
+; CHECK-NEXT:    or %s3, 0, (0)1
+; CHECK-NEXT:    bsic %s10, (, %s12)
+; CHECK-NEXT:    or %s11, 0, %s9
+  %r = srem i128 %a, 3
+  ret i128 %r
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @remi64ri(i64 %a) {
 ; CHECK-LABEL: remi64ri:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    divs.l %s1, %s0, (62)0
@@ -121,19 +164,35 @@ define i64 @remi64ri(i64 %a, i64 %b) {
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define i32 @remi32ri(i32 %a, i32 %b) {
+define signext i32 @remi32ri(i32 signext %a) {
 ; CHECK-LABEL: remi32ri:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    divs.w.sx %s1, %s0, (62)0
 ; CHECK-NEXT:    muls.w.sx %s1, 3, %s1
 ; CHECK-NEXT:    subs.w.sx %s0, %s0, %s1
+; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = srem i32 %a, 3
   ret i32 %r
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define i64 @remu64ri(i64 %a, i64 %b) {
+define i128 @remu128ri(i128 %a) {
+; CHECK-LABEL: remu128ri:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    lea %s2, __umodti3@lo
+; CHECK-NEXT:    and %s2, %s2, (32)0
+; CHECK-NEXT:    lea.sl %s12, __umodti3@hi(, %s2)
+; CHECK-NEXT:    or %s2, 3, (0)1
+; CHECK-NEXT:    or %s3, 0, (0)1
+; CHECK-NEXT:    bsic %s10, (, %s12)
+; CHECK-NEXT:    or %s11, 0, %s9
+  %r = urem i128 %a, 3
+  ret i128 %r
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @remu64ri(i64 %a) {
 ; CHECK-LABEL: remu64ri:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    divu.l %s1, %s0, (62)0
@@ -145,17 +204,35 @@ define i64 @remu64ri(i64 %a, i64 %b) {
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define i32 @remu32ri(i32 %a, i32 %b) {
+define zeroext i32 @remu32ri(i32 zeroext %a) {
 ; CHECK-LABEL: remu32ri:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    divu.w %s1, %s0, (62)0
 ; CHECK-NEXT:    muls.w.sx %s1, 3, %s1
 ; CHECK-NEXT:    subs.w.sx %s0, %s0, %s1
+; CHECK-NEXT:    adds.w.zx %s0, %s0, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = urem i32 %a, 3
   ret i32 %r
 }
 
+; Function Attrs: norecurse nounwind readnone
+define i128 @remi128li(i128 %a) {
+; CHECK-LABEL: remi128li:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    or %s3, 0, %s1
+; CHECK-NEXT:    or %s2, 0, %s0
+; CHECK-NEXT:    lea %s0, __modti3@lo
+; CHECK-NEXT:    and %s0, %s0, (32)0
+; CHECK-NEXT:    lea.sl %s12, __modti3@hi(, %s0)
+; CHECK-NEXT:    or %s0, 3, (0)1
+; CHECK-NEXT:    or %s1, 0, (0)1
+; CHECK-NEXT:    bsic %s10, (, %s12)
+; CHECK-NEXT:    or %s11, 0, %s9
+  %r = srem i128 3, %a
+  ret i128 %r
+}
+
 ; Function Attrs: norecurse nounwind readnone
 define i64 @remi64li(i64 %a, i64 %b) {
 ; CHECK-LABEL: remi64li:
@@ -169,17 +246,35 @@ define i64 @remi64li(i64 %a, i64 %b) {
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define i32 @remi32li(i32 %a, i32 %b) {
+define signext i32 @remi32li(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: remi32li:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    divs.w.sx %s0, 3, %s1
 ; CHECK-NEXT:    muls.w.sx %s0, %s0, %s1
 ; CHECK-NEXT:    subs.w.sx %s0, 3, %s0
+; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = srem i32 3, %b
   ret i32 %r
 }
 
+; Function Attrs: norecurse nounwind readnone
+define i128 @remu128li(i128) {
+; CHECK-LABEL: remu128li:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    or %s3, 0, %s1
+; CHECK-NEXT:    or %s2, 0, %s0
+; CHECK-NEXT:    lea %s0, __umodti3@lo
+; CHECK-NEXT:    and %s0, %s0, (32)0
+; CHECK-NEXT:    lea.sl %s12, __umodti3@hi(, %s0)
+; CHECK-NEXT:    or %s0, 3, (0)1
+; CHECK-NEXT:    or %s1, 0, (0)1
+; CHECK-NEXT:    bsic %s10, (, %s12)
+; CHECK-NEXT:    or %s11, 0, %s9
+  %2 = urem i128 3, %0
+  ret i128 %2
+}
+
 ; Function Attrs: norecurse nounwind readnone
 define i64 @remu64li(i64 %a, i64 %b) {
 ; CHECK-LABEL: remu64li:
@@ -193,12 +288,13 @@ define i64 @remu64li(i64 %a, i64 %b) {
 }
 
 ; Function Attrs: norecurse nounwind readnone
-define i32 @remu32li(i32 %a, i32 %b) {
+define zeroext i32 @remu32li(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: remu32li:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    divu.w %s0, 3, %s1
 ; CHECK-NEXT:    muls.w.sx %s0, %s0, %s1
 ; CHECK-NEXT:    subs.w.sx %s0, 3, %s0
+; CHECK-NEXT:    adds.w.zx %s0, %s0, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = urem i32 3, %b
   ret i32 %r
diff --git a/llvm/test/CodeGen/VE/subtraction.ll b/llvm/test/CodeGen/VE/subtraction.ll
index c3c6beeceda53e..991fea82d5e311 100644
--- a/llvm/test/CodeGen/VE/subtraction.ll
+++ b/llvm/test/CodeGen/VE/subtraction.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
 
-define signext i8 @func1(i8 signext %0, i8 signext %1) {
-; CHECK-LABEL: func1:
+define signext i8 @func8s(i8 signext %0, i8 signext %1) {
+; CHECK-LABEL: func8s:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    subs.w.sx %s0, %s0, %s1
 ; CHECK-NEXT:    sll %s0, %s0, 56
@@ -11,8 +11,8 @@ define signext i8 @func1(i8 signext %0, i8 signext %1) {
   ret i8 %3
 }
 
-define signext i16 @func2(i16 signext %0, i16 signext %1) {
-; CHECK-LABEL: func2:
+define signext i16 @func16s(i16 signext %0, i16 signext %1) {
+; CHECK-LABEL: func16s:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    subs.w.sx %s0, %s0, %s1
 ; CHECK-NEXT:    sll %s0, %s0, 48
@@ -22,17 +22,18 @@ define signext i16 @func2(i16 signext %0, i16 signext %1) {
   ret i16 %3
 }
 
-define i32 @func3(i32 %0, i32 %1) {
-; CHECK-LABEL: func3:
+define signext i32 @func32s(i32 signext %0, i32 signext %1) {
+; CHECK-LABEL: func32s:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    subs.w.sx %s0, %s0, %s1
+; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = sub nsw i32 %0, %1
   ret i32 %3
 }
 
-define i64 @func4(i64 %0, i64 %1) {
-; CHECK-LABEL: func4:
+define i64 @func64s(i64 %0, i64 %1) {
+; CHECK-LABEL: func64s:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    subs.l %s0, %s0, %s1
 ; CHECK-NEXT:    or %s11, 0, %s9
@@ -40,8 +41,23 @@ define i64 @func4(i64 %0, i64 %1) {
   ret i64 %3
 }
 
-define zeroext i8 @func6(i8 zeroext %0, i8 zeroext %1) {
-; CHECK-LABEL: func6:
+define i128 @func128s(i128 %0, i128 %1) {
+; CHECK-LABEL: func128s:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    subs.l %s1, %s1, %s3
+; CHECK-NEXT:    cmpu.l %s3, %s0, %s2
+; CHECK-NEXT:    or %s4, 0, (0)1
+; CHECK-NEXT:    cmov.l.lt %s4, (63)0, %s3
+; CHECK-NEXT:    adds.w.zx %s3, %s4, (0)1
+; CHECK-NEXT:    subs.l %s1, %s1, %s3
+; CHECK-NEXT:    subs.l %s0, %s0, %s2
+; CHECK-NEXT:    or %s11, 0, %s9
+  %3 = sub nsw i128 %0, %1
+  ret i128 %3
+}
+
+define zeroext i8 @func8z(i8 zeroext %0, i8 zeroext %1) {
+; CHECK-LABEL: func8z:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    subs.w.sx %s0, %s0, %s1
 ; CHECK-NEXT:    and %s0, %s0, (56)0
@@ -50,8 +66,8 @@ define zeroext i8 @func6(i8 zeroext %0, i8 zeroext %1) {
   ret i8 %3
 }
 
-define zeroext i16 @func7(i16 zeroext %0, i16 zeroext %1) {
-; CHECK-LABEL: func7:
+define zeroext i16 @func16z(i16 zeroext %0, i16 zeroext %1) {
+; CHECK-LABEL: func16z:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    subs.w.sx %s0, %s0, %s1
 ; CHECK-NEXT:    and %s0, %s0, (48)0
@@ -60,17 +76,18 @@ define zeroext i16 @func7(i16 zeroext %0, i16 zeroext %1) {
   ret i16 %3
 }
 
-define i32 @func8(i32 %0, i32 %1) {
-; CHECK-LABEL: func8:
+define zeroext i32 @func32z(i32 zeroext %0, i32 zeroext %1) {
+; CHECK-LABEL: func32z:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    subs.w.sx %s0, %s0, %s1
+; CHECK-NEXT:    adds.w.zx %s0, %s0, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = sub i32 %0, %1
   ret i32 %3
 }
 
-define i64 @func9(i64 %0, i64 %1) {
-; CHECK-LABEL: func9:
+define i64 @func64z(i64 %0, i64 %1) {
+; CHECK-LABEL: func64z:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    subs.l %s0, %s0, %s1
 ; CHECK-NEXT:    or %s11, 0, %s9
@@ -78,90 +95,151 @@ define i64 @func9(i64 %0, i64 %1) {
   ret i64 %3
 }
 
-define signext i8 @func13(i8 signext %0, i8 signext %1) {
-; CHECK-LABEL: func13:
+define i128 @func128z(i128 %0, i128 %1) {
+; CHECK-LABEL: func128z:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    subs.l %s1, %s1, %s3
+; CHECK-NEXT:    cmpu.l %s3, %s0, %s2
+; CHECK-NEXT:    or %s4, 0, (0)1
+; CHECK-NEXT:    cmov.l.lt %s4, (63)0, %s3
+; CHECK-NEXT:    adds.w.zx %s3, %s4, (0)1
+; CHECK-NEXT:    subs.l %s1, %s1, %s3
+; CHECK-NEXT:    subs.l %s0, %s0, %s2
+; CHECK-NEXT:    or %s11, 0, %s9
+  %3 = sub i128 %0, %1
+  ret i128 %3
+}
+
+define signext i8 @funci8s(i8 signext %a) {
+; CHECK-LABEL: funci8s:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    adds.w.sx %s0, -5, %s0
 ; CHECK-NEXT:    sll %s0, %s0, 56
 ; CHECK-NEXT:    sra.l %s0, %s0, 56
 ; CHECK-NEXT:    or %s11, 0, %s9
-  %3 = add i8 %0, -5
-  ret i8 %3
+  %ret = add i8 %a, -5
+  ret i8 %ret
 }
 
-define signext i16 @func14(i16 signext %0, i16 signext %1) {
-; CHECK-LABEL: func14:
+define signext i16 @funci16s(i16 signext %a) {
+; CHECK-LABEL: funci16s:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    adds.w.sx %s0, -5, %s0
 ; CHECK-NEXT:    sll %s0, %s0, 48
 ; CHECK-NEXT:    sra.l %s0, %s0, 48
 ; CHECK-NEXT:    or %s11, 0, %s9
-  %3 = add i16 %0, -5
-  ret i16 %3
+  %ret = add i16 %a, -5
+  ret i16 %ret
 }
 
-define i32 @func15(i32 %0, i32 %1) {
-; CHECK-LABEL: func15:
+define signext i32 @funci32s(i32 signext %a) {
+; CHECK-LABEL: funci32s:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    adds.w.sx %s0, -5, %s0
+; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
-  %3 = add nsw i32 %0, -5
-  ret i32 %3
+  %ret = add i32 %a, -5
+  ret i32 %ret
 }
 
-define i64 @func16(i64 %0, i64 %1) {
-; CHECK-LABEL: func16:
+define i64 @funci64s(i64 %a) {
+; CHECK-LABEL: funci64s:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s0, -5(, %s0)
 ; CHECK-NEXT:    or %s11, 0, %s9
-  %3 = add nsw i64 %0, -5
-  ret i64 %3
+  %ret = add nsw i64 %a, -5
+  ret i64 %ret
+}
+
+define i128 @funci128s(i128 %0) {
+; CHECK-LABEL: funci128s:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    lea %s2, -5(, %s0)
+; CHECK-NEXT:    cmpu.l %s0, %s2, %s0
+; CHECK-NEXT:    or %s3, 0, (0)1
+; CHECK-NEXT:    cmov.l.lt %s3, (63)0, %s0
+; CHECK-NEXT:    adds.w.zx %s0, %s3, (0)1
+; CHECK-NEXT:    lea %s1, -1(%s0, %s1)
+; CHECK-NEXT:    or %s0, 0, %s2
+; CHECK-NEXT:    or %s11, 0, %s9
+  %2 = add nsw i128 %0, -5
+  ret i128 %2
 }
 
-define zeroext i8 @func18(i8 zeroext %0, i8 zeroext %1) {
-; CHECK-LABEL: func18:
+define zeroext i8 @funci8z(i8 zeroext %a) {
+; CHECK-LABEL: funci8z:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    adds.w.sx %s0, -5, %s0
 ; CHECK-NEXT:    and %s0, %s0, (56)0
 ; CHECK-NEXT:    or %s11, 0, %s9
-  %3 = add i8 %0, -5
-  ret i8 %3
+  %ret = add i8 %a, -5
+  ret i8 %ret
 }
 
-define zeroext i16 @func19(i16 zeroext %0, i16 zeroext %1) {
-; CHECK-LABEL: func19:
+define zeroext i16 @funci16z(i16 zeroext %a) {
+; CHECK-LABEL: funci16z:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    adds.w.sx %s0, -5, %s0
 ; CHECK-NEXT:    and %s0, %s0, (48)0
 ; CHECK-NEXT:    or %s11, 0, %s9
-  %3 = add i16 %0, -5
-  ret i16 %3
+  %ret = add i16 %a, -5
+  ret i16 %ret
 }
 
-define i32 @func20(i32 %0, i32 %1) {
-; CHECK-LABEL: func20:
+define zeroext i32 @funci32z(i32 zeroext %a) {
+; CHECK-LABEL: funci32z:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    adds.w.sx %s0, -5, %s0
+; CHECK-NEXT:    adds.w.zx %s0, %s0, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
-  %3 = add i32 %0, -5
-  ret i32 %3
+  %ret = add i32 %a, -5
+  ret i32 %ret
 }
 
-define i64 @func21(i64 %0, i64 %1) {
-; CHECK-LABEL: func21:
+define i64 @funci64z(i64 %a) {
+; CHECK-LABEL: funci64z:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s0, -5(, %s0)
 ; CHECK-NEXT:    or %s11, 0, %s9
-  %3 = add i64 %0, -5
-  ret i64 %3
+  %ret = add i64 %a, -5
+  ret i64 %ret
+}
+
+define i128 @funci128z(i128 %0) {
+; CHECK-LABEL: funci128z:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    lea %s2, -5(, %s0)
+; CHECK-NEXT:    cmpu.l %s0, %s2, %s0
+; CHECK-NEXT:    or %s3, 0, (0)1
+; CHECK-NEXT:    cmov.l.lt %s3, (63)0, %s0
+; CHECK-NEXT:    adds.w.zx %s0, %s3, (0)1
+; CHECK-NEXT:    lea %s1, -1(%s0, %s1)
+; CHECK-NEXT:    or %s0, 0, %s2
+; CHECK-NEXT:    or %s11, 0, %s9
+  %2 = add i128 %0, -5
+  ret i128 %2
 }
 
-define i64 @func26(i64 %0, i64 %1) {
-; CHECK-LABEL: func26:
+define i64 @funci64_2(i64 %a) {
+; CHECK-LABEL: funci64_2:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s0, -2147483648(, %s0)
 ; CHECK-NEXT:    or %s11, 0, %s9
-  %3 = add nsw i64 %0, -2147483648
-  ret i64 %3
+  %ret = add nsw i64 %a, -2147483648
+  ret i64 %ret
 }
 
+define i128 @funci128_2(i128 %0) {
+; CHECK-LABEL: funci128_2:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    lea %s2, -2147483648(, %s0)
+; CHECK-NEXT:    cmpu.l %s0, %s2, %s0
+; CHECK-NEXT:    or %s3, 0, (0)1
+; CHECK-NEXT:    cmov.l.lt %s3, (63)0, %s0
+; CHECK-NEXT:    adds.w.zx %s0, %s3, (0)1
+; CHECK-NEXT:    lea %s1, -1(%s0, %s1)
+; CHECK-NEXT:    or %s0, 0, %s2
+; CHECK-NEXT:    or %s11, 0, %s9
+  %2 = add nsw i128 %0, -2147483648
+  ret i128 %2
+}