diff --git a/clang-tools-extra/clangd/Quality.cpp b/clang-tools-extra/clangd/Quality.cpp index 318488f269f8c..8840f805f0e87 100644 --- a/clang-tools-extra/clangd/Quality.cpp +++ b/clang-tools-extra/clangd/Quality.cpp @@ -538,7 +538,7 @@ static uint32_t encodeFloat(float F) { constexpr uint32_t TopBit = ~(~uint32_t{0} >> 1); // Get the bits of the float. Endianness is the same as for integers. - uint32_t U = llvm::FloatToBits(F); + uint32_t U = llvm::bit_cast(F); // IEEE 754 floats compare like sign-magnitude integers. if (U & TopBit) // Negative float. return 0 - U; // Map onto the low half of integers, order reversed. diff --git a/llvm/include/llvm/ADT/APInt.h b/llvm/include/llvm/ADT/APInt.h index 83734c4fc11cf..9eabccdbdb87c 100644 --- a/llvm/include/llvm/ADT/APInt.h +++ b/llvm/include/llvm/ADT/APInt.h @@ -1665,7 +1665,7 @@ class [[nodiscard]] APInt { /// The conversion does not do a translation from integer to double, it just /// re-interprets the bits as a double. Note that it is valid to do this on /// any bit width. Exactly 64 bits will be translated. - double bitsToDouble() const { return BitsToDouble(getWord(0)); } + double bitsToDouble() const { return llvm::bit_cast(getWord(0)); } /// Converts APInt bits to a float /// @@ -1673,7 +1673,7 @@ class [[nodiscard]] APInt { /// re-interprets the bits as a float. Note that it is valid to do this on /// any bit width. Exactly 32 bits will be translated. float bitsToFloat() const { - return BitsToFloat(static_cast(getWord(0))); + return llvm::bit_cast(static_cast(getWord(0))); } /// Converts a double to APInt bits. @@ -1681,7 +1681,7 @@ class [[nodiscard]] APInt { /// The conversion does not do a translation from double to integer, it just /// re-interprets the bits of the double. static APInt doubleToBits(double V) { - return APInt(sizeof(double) * CHAR_BIT, DoubleToBits(V)); + return APInt(sizeof(double) * CHAR_BIT, llvm::bit_cast(V)); } /// Converts a float to APInt bits. @@ -1689,7 +1689,7 @@ class [[nodiscard]] APInt { /// The conversion does not do a translation from float to integer, it just /// re-interprets the bits of the float. static APInt floatToBits(float V) { - return APInt(sizeof(float) * CHAR_BIT, FloatToBits(V)); + return APInt(sizeof(float) * CHAR_BIT, llvm::bit_cast(V)); } /// @} diff --git a/llvm/include/llvm/Support/EndianStream.h b/llvm/include/llvm/Support/EndianStream.h index ed941c61fbebc..d2289ccfa8932 100644 --- a/llvm/include/llvm/Support/EndianStream.h +++ b/llvm/include/llvm/Support/EndianStream.h @@ -32,13 +32,13 @@ inline void write(raw_ostream &os, value_type value, endianness endian) { template <> inline void write(raw_ostream &os, float value, endianness endian) { - write(os, FloatToBits(value), endian); + write(os, llvm::bit_cast(value), endian); } template <> inline void write(raw_ostream &os, double value, endianness endian) { - write(os, DoubleToBits(value), endian); + write(os, llvm::bit_cast(value), endian); } template diff --git a/llvm/lib/BinaryFormat/MsgPackReader.cpp b/llvm/lib/BinaryFormat/MsgPackReader.cpp index 146edaa95b81e..2599d75efa084 100644 --- a/llvm/lib/BinaryFormat/MsgPackReader.cpp +++ b/llvm/lib/BinaryFormat/MsgPackReader.cpp @@ -74,7 +74,8 @@ Expected Reader::read(Object &Obj) { return make_error( "Invalid Float32 with insufficient payload", std::make_error_code(std::errc::invalid_argument)); - Obj.Float = BitsToFloat(endian::read(Current)); + Obj.Float = + llvm::bit_cast(endian::read(Current)); Current += sizeof(float); return true; case FirstByte::Float64: @@ -83,7 +84,8 @@ Expected Reader::read(Object &Obj) { return make_error( "Invalid Float64 with insufficient payload", std::make_error_code(std::errc::invalid_argument)); - Obj.Float = BitsToDouble(endian::read(Current)); + Obj.Float = + llvm::bit_cast(endian::read(Current)); Current += sizeof(double); return true; case FirstByte::Str8: diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index c3106216a0609..754e95dc521e4 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -2365,10 +2365,10 @@ SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(SDNode *Node, SDValue Load = DAG.getLoad(MVT::f64, dl, MemChain, StackSlot, MachinePointerInfo()); // FP constant to bias correct the final result - SDValue Bias = DAG.getConstantFP(isSigned ? - BitsToDouble(0x4330000080000000ULL) : - BitsToDouble(0x4330000000000000ULL), - dl, MVT::f64); + SDValue Bias = DAG.getConstantFP( + isSigned ? llvm::bit_cast(0x4330000080000000ULL) + : llvm::bit_cast(0x4330000000000000ULL), + dl, MVT::f64); // Subtract the bias and get the final result. SDValue Sub; SDValue Result; diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp index 518970dfdf1fe..ebfaf06bd8787 100644 --- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -7912,7 +7912,7 @@ bool TargetLowering::expandUINT_TO_FP(SDNode *Node, SDValue &Result, // -0.0. This will be added to +0.0 and produce -0.0 which is incorrect. SDValue TwoP52 = DAG.getConstant(UINT64_C(0x4330000000000000), dl, SrcVT); SDValue TwoP84PlusTwoP52 = DAG.getConstantFP( - BitsToDouble(UINT64_C(0x4530000000100000)), dl, DstVT); + llvm::bit_cast(UINT64_C(0x4530000000100000)), dl, DstVT); SDValue TwoP84 = DAG.getConstant(UINT64_C(0x4530000000000000), dl, SrcVT); SDValue LoMask = DAG.getConstant(UINT64_C(0x00000000FFFFFFFF), dl, SrcVT); SDValue HiShift = DAG.getConstant(32, dl, ShiftVT); diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp index 08b29641d14a5..5f6ac8ce0dc4d 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp @@ -1147,7 +1147,7 @@ Value *AMDGPUCodeGenPrepare::expandDivRem32(IRBuilder<> &Builder, Value *FloatY = Builder.CreateUIToFP(Y, F32Ty); Function *Rcp = Intrinsic::getDeclaration(Mod, Intrinsic::amdgcn_rcp, F32Ty); Value *RcpY = Builder.CreateCall(Rcp, {FloatY}); - Constant *Scale = ConstantFP::get(F32Ty, BitsToFloat(0x4F7FFFFE)); + Constant *Scale = ConstantFP::get(F32Ty, llvm::bit_cast(0x4F7FFFFE)); Value *ScaledY = Builder.CreateFMul(RcpY, Scale); Value *Z = Builder.CreateFPToUI(ScaledY, I32Ty); diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp index aa5d2b951ff8c..35584681a6ba1 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp @@ -2721,15 +2721,17 @@ SDValue AMDGPUTargetLowering::LowerFP_TO_INT64(SDValue Op, SelectionDAG &DAG, SDValue K0, K1; if (SrcVT == MVT::f64) { - K0 = DAG.getConstantFP(BitsToDouble(UINT64_C(/*2^-32*/ 0x3df0000000000000)), - SL, SrcVT); - K1 = DAG.getConstantFP(BitsToDouble(UINT64_C(/*-2^32*/ 0xc1f0000000000000)), - SL, SrcVT); + K0 = DAG.getConstantFP( + llvm::bit_cast(UINT64_C(/*2^-32*/ 0x3df0000000000000)), SL, + SrcVT); + K1 = DAG.getConstantFP( + llvm::bit_cast(UINT64_C(/*-2^32*/ 0xc1f0000000000000)), SL, + SrcVT); } else { - K0 = DAG.getConstantFP(BitsToFloat(UINT32_C(/*2^-32*/ 0x2f800000)), SL, - SrcVT); - K1 = DAG.getConstantFP(BitsToFloat(UINT32_C(/*-2^32*/ 0xcf800000)), SL, - SrcVT); + K0 = DAG.getConstantFP( + llvm::bit_cast(UINT32_C(/*2^-32*/ 0x2f800000)), SL, SrcVT); + K1 = DAG.getConstantFP( + llvm::bit_cast(UINT32_C(/*-2^32*/ 0xcf800000)), SL, SrcVT); } // TODO: Should this propagate fast-math-flags? SDValue Mul = DAG.getNode(ISD::FMUL, SL, SrcVT, Trunc, K0); diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp index 5ae67e0f03ad9..a9459b20f8380 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp @@ -2279,13 +2279,15 @@ bool AMDGPULegalizerInfo::legalizeFPTOI(MachineInstr &MI, } MachineInstrBuilder K0, K1; if (SrcLT == S64) { - K0 = B.buildFConstant(S64, - BitsToDouble(UINT64_C(/*2^-32*/ 0x3df0000000000000))); - K1 = B.buildFConstant(S64, - BitsToDouble(UINT64_C(/*-2^32*/ 0xc1f0000000000000))); + K0 = B.buildFConstant( + S64, llvm::bit_cast(UINT64_C(/*2^-32*/ 0x3df0000000000000))); + K1 = B.buildFConstant( + S64, llvm::bit_cast(UINT64_C(/*-2^32*/ 0xc1f0000000000000))); } else { - K0 = B.buildFConstant(S32, BitsToFloat(UINT32_C(/*2^-32*/ 0x2f800000))); - K1 = B.buildFConstant(S32, BitsToFloat(UINT32_C(/*-2^32*/ 0xcf800000))); + K0 = B.buildFConstant( + S32, llvm::bit_cast(UINT32_C(/*2^-32*/ 0x2f800000))); + K1 = B.buildFConstant( + S32, llvm::bit_cast(UINT32_C(/*-2^32*/ 0xcf800000))); } auto Mul = B.buildFMul(SrcLT, Trunc, K0, Flags); @@ -2837,7 +2839,8 @@ bool AMDGPULegalizerInfo::legalizeFFloor(MachineInstr &MI, // shouldn't matter? Register ModSrc = stripAnySourceMods(OrigSrc, MRI); - auto Const = B.buildFConstant(S64, BitsToDouble(0x3fefffffffffffff)); + auto Const = + B.buildFConstant(S64, llvm::bit_cast(0x3fefffffffffffff)); Register Min = MRI.createGenericVirtualRegister(S64); @@ -3438,7 +3441,7 @@ void AMDGPULegalizerInfo::legalizeUnsignedDIV_REM32Impl(MachineIRBuilder &B, // Initial estimate of inv(y). auto FloatY = B.buildUITOFP(S32, Y); auto RcpIFlag = B.buildInstr(AMDGPU::G_AMDGPU_RCP_IFLAG, {S32}, {FloatY}); - auto Scale = B.buildFConstant(S32, BitsToFloat(0x4f7ffffe)); + auto Scale = B.buildFConstant(S32, llvm::bit_cast(0x4f7ffffe)); auto ScaledY = B.buildFMul(S32, RcpIFlag, Scale); auto Z = B.buildFPTOUI(S32, ScaledY); @@ -3488,21 +3491,23 @@ static std::pair emitReciprocalU64(MachineIRBuilder &B, auto CvtLo = B.buildUITOFP(S32, Unmerge.getReg(0)); auto CvtHi = B.buildUITOFP(S32, Unmerge.getReg(1)); - auto Mad = B.buildFMAD(S32, CvtHi, // 2**32 - B.buildFConstant(S32, BitsToFloat(0x4f800000)), CvtLo); + auto Mad = B.buildFMAD( + S32, CvtHi, // 2**32 + B.buildFConstant(S32, llvm::bit_cast(0x4f800000)), CvtLo); auto Rcp = B.buildInstr(AMDGPU::G_AMDGPU_RCP_IFLAG, {S32}, {Mad}); - auto Mul1 = - B.buildFMul(S32, Rcp, B.buildFConstant(S32, BitsToFloat(0x5f7ffffc))); + auto Mul1 = B.buildFMul( + S32, Rcp, B.buildFConstant(S32, llvm::bit_cast(0x5f7ffffc))); // 2**(-32) - auto Mul2 = - B.buildFMul(S32, Mul1, B.buildFConstant(S32, BitsToFloat(0x2f800000))); + auto Mul2 = B.buildFMul( + S32, Mul1, B.buildFConstant(S32, llvm::bit_cast(0x2f800000))); auto Trunc = B.buildIntrinsicTrunc(S32, Mul2); // -(2**32) - auto Mad2 = B.buildFMAD(S32, Trunc, - B.buildFConstant(S32, BitsToFloat(0xcf800000)), Mul1); + auto Mad2 = B.buildFMAD( + S32, Trunc, B.buildFConstant(S32, llvm::bit_cast(0xcf800000)), + Mul1); auto ResultLo = B.buildFPTOUI(S32, Mad2); auto ResultHi = B.buildFPTOUI(S32, Trunc); @@ -4047,7 +4052,7 @@ bool AMDGPULegalizerInfo::legalizeFDIVFastIntrin(MachineInstr &MI, auto C0 = B.buildConstant(S32, 0x6f800000); auto C1 = B.buildConstant(S32, 0x2f800000); - auto C2 = B.buildConstant(S32, FloatToBits(1.0f)); + auto C2 = B.buildConstant(S32, llvm::bit_cast(1.0f)); auto CmpRes = B.buildFCmp(CmpInst::FCMP_OGT, S1, Abs, C0, Flags); auto Sel = B.buildSelect(S32, CmpRes, C1, C2, Flags); diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp index 7e8c5d33159f4..342a8137f6505 100644 --- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp +++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp @@ -1179,21 +1179,21 @@ MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) { static int64_t getInlineImmVal32(unsigned Imm) { switch (Imm) { case 240: - return FloatToBits(0.5f); + return llvm::bit_cast(0.5f); case 241: - return FloatToBits(-0.5f); + return llvm::bit_cast(-0.5f); case 242: - return FloatToBits(1.0f); + return llvm::bit_cast(1.0f); case 243: - return FloatToBits(-1.0f); + return llvm::bit_cast(-1.0f); case 244: - return FloatToBits(2.0f); + return llvm::bit_cast(2.0f); case 245: - return FloatToBits(-2.0f); + return llvm::bit_cast(-2.0f); case 246: - return FloatToBits(4.0f); + return llvm::bit_cast(4.0f); case 247: - return FloatToBits(-4.0f); + return llvm::bit_cast(-4.0f); case 248: // 1 / (2 * PI) return 0x3e22f983; default: @@ -1204,21 +1204,21 @@ static int64_t getInlineImmVal32(unsigned Imm) { static int64_t getInlineImmVal64(unsigned Imm) { switch (Imm) { case 240: - return DoubleToBits(0.5); + return llvm::bit_cast(0.5); case 241: - return DoubleToBits(-0.5); + return llvm::bit_cast(-0.5); case 242: - return DoubleToBits(1.0); + return llvm::bit_cast(1.0); case 243: - return DoubleToBits(-1.0); + return llvm::bit_cast(-1.0); case 244: - return DoubleToBits(2.0); + return llvm::bit_cast(2.0); case 245: - return DoubleToBits(-2.0); + return llvm::bit_cast(-2.0); case 246: - return DoubleToBits(4.0); + return llvm::bit_cast(4.0); case 247: - return DoubleToBits(-4.0); + return llvm::bit_cast(-4.0); case 248: // 1 / (2 * PI) return 0x3fc45f306dc9c882; default: diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp index acd7f64f74f69..182f4a1d4dfcd 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp @@ -476,23 +476,23 @@ void AMDGPUInstPrinter::printImmediate32(uint32_t Imm, return; } - if (Imm == FloatToBits(0.0f)) + if (Imm == llvm::bit_cast(0.0f)) O << "0.0"; - else if (Imm == FloatToBits(1.0f)) + else if (Imm == llvm::bit_cast(1.0f)) O << "1.0"; - else if (Imm == FloatToBits(-1.0f)) + else if (Imm == llvm::bit_cast(-1.0f)) O << "-1.0"; - else if (Imm == FloatToBits(0.5f)) + else if (Imm == llvm::bit_cast(0.5f)) O << "0.5"; - else if (Imm == FloatToBits(-0.5f)) + else if (Imm == llvm::bit_cast(-0.5f)) O << "-0.5"; - else if (Imm == FloatToBits(2.0f)) + else if (Imm == llvm::bit_cast(2.0f)) O << "2.0"; - else if (Imm == FloatToBits(-2.0f)) + else if (Imm == llvm::bit_cast(-2.0f)) O << "-2.0"; - else if (Imm == FloatToBits(4.0f)) + else if (Imm == llvm::bit_cast(4.0f)) O << "4.0"; - else if (Imm == FloatToBits(-4.0f)) + else if (Imm == llvm::bit_cast(-4.0f)) O << "-4.0"; else if (Imm == 0x3e22f983 && STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm]) @@ -510,23 +510,23 @@ void AMDGPUInstPrinter::printImmediate64(uint64_t Imm, return; } - if (Imm == DoubleToBits(0.0)) + if (Imm == llvm::bit_cast(0.0)) O << "0.0"; - else if (Imm == DoubleToBits(1.0)) + else if (Imm == llvm::bit_cast(1.0)) O << "1.0"; - else if (Imm == DoubleToBits(-1.0)) + else if (Imm == llvm::bit_cast(-1.0)) O << "-1.0"; - else if (Imm == DoubleToBits(0.5)) + else if (Imm == llvm::bit_cast(0.5)) O << "0.5"; - else if (Imm == DoubleToBits(-0.5)) + else if (Imm == llvm::bit_cast(-0.5)) O << "-0.5"; - else if (Imm == DoubleToBits(2.0)) + else if (Imm == llvm::bit_cast(2.0)) O << "2.0"; - else if (Imm == DoubleToBits(-2.0)) + else if (Imm == llvm::bit_cast(-2.0)) O << "-2.0"; - else if (Imm == DoubleToBits(4.0)) + else if (Imm == llvm::bit_cast(4.0)) O << "4.0"; - else if (Imm == DoubleToBits(-4.0)) + else if (Imm == llvm::bit_cast(-4.0)) O << "-4.0"; else if (Imm == 0x3fc45f306dc9c882 && STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm]) @@ -752,9 +752,9 @@ void AMDGPUInstPrinter::printRegularOperand(const MCInst *MI, unsigned OpNo, int RCID = Desc.operands()[OpNo].RegClass; unsigned RCBits = AMDGPU::getRegBitWidth(MRI.getRegClass(RCID)); if (RCBits == 32) - printImmediate32(FloatToBits(Value), STI, O); + printImmediate32(llvm::bit_cast((float)Value), STI, O); else if (RCBits == 64) - printImmediate64(DoubleToBits(Value), STI, O); + printImmediate64(llvm::bit_cast(Value), STI, O); else llvm_unreachable("Invalid register class size"); } diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp index f659f08de0276..497ac60eaf085 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp @@ -151,28 +151,28 @@ static uint32_t getLit32Encoding(uint32_t Val, const MCSubtargetInfo &STI) { if (IntImm != 0) return IntImm; - if (Val == FloatToBits(0.5f)) + if (Val == llvm::bit_cast(0.5f)) return 240; - if (Val == FloatToBits(-0.5f)) + if (Val == llvm::bit_cast(-0.5f)) return 241; - if (Val == FloatToBits(1.0f)) + if (Val == llvm::bit_cast(1.0f)) return 242; - if (Val == FloatToBits(-1.0f)) + if (Val == llvm::bit_cast(-1.0f)) return 243; - if (Val == FloatToBits(2.0f)) + if (Val == llvm::bit_cast(2.0f)) return 244; - if (Val == FloatToBits(-2.0f)) + if (Val == llvm::bit_cast(-2.0f)) return 245; - if (Val == FloatToBits(4.0f)) + if (Val == llvm::bit_cast(4.0f)) return 246; - if (Val == FloatToBits(-4.0f)) + if (Val == llvm::bit_cast(-4.0f)) return 247; if (Val == 0x3e22f983 && // 1.0 / (2.0 * pi) @@ -187,28 +187,28 @@ static uint32_t getLit64Encoding(uint64_t Val, const MCSubtargetInfo &STI) { if (IntImm != 0) return IntImm; - if (Val == DoubleToBits(0.5)) + if (Val == llvm::bit_cast(0.5)) return 240; - if (Val == DoubleToBits(-0.5)) + if (Val == llvm::bit_cast(-0.5)) return 241; - if (Val == DoubleToBits(1.0)) + if (Val == llvm::bit_cast(1.0)) return 242; - if (Val == DoubleToBits(-1.0)) + if (Val == llvm::bit_cast(-1.0)) return 243; - if (Val == DoubleToBits(2.0)) + if (Val == llvm::bit_cast(2.0)) return 244; - if (Val == DoubleToBits(-2.0)) + if (Val == llvm::bit_cast(-2.0)) return 245; - if (Val == DoubleToBits(4.0)) + if (Val == llvm::bit_cast(4.0)) return 246; - if (Val == DoubleToBits(-4.0)) + if (Val == llvm::bit_cast(-4.0)) return 247; if (Val == 0x3fc45f306dc9c882 && // 1.0 / (2.0 * pi) diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 3e866213ec1d3..7c8e0c952ac74 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -9050,10 +9050,10 @@ SDValue SITargetLowering::lowerFDIV_FAST(SDValue Op, SelectionDAG &DAG) const { SDValue r1 = DAG.getNode(ISD::FABS, SL, MVT::f32, RHS); - const APFloat K0Val(BitsToFloat(0x6f800000)); + const APFloat K0Val(llvm::bit_cast(0x6f800000)); const SDValue K0 = DAG.getConstantFP(K0Val, SL, MVT::f32); - const APFloat K1Val(BitsToFloat(0x2f800000)); + const APFloat K1Val(llvm::bit_cast(0x2f800000)); const SDValue K1 = DAG.getConstantFP(K1Val, SL, MVT::f32); const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f32); diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp index f0667645c2bc8..bb52fd3b1e855 100644 --- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp +++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp @@ -2368,15 +2368,15 @@ bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi) { return true; uint64_t Val = static_cast(Literal); - return (Val == DoubleToBits(0.0)) || - (Val == DoubleToBits(1.0)) || - (Val == DoubleToBits(-1.0)) || - (Val == DoubleToBits(0.5)) || - (Val == DoubleToBits(-0.5)) || - (Val == DoubleToBits(2.0)) || - (Val == DoubleToBits(-2.0)) || - (Val == DoubleToBits(4.0)) || - (Val == DoubleToBits(-4.0)) || + return (Val == llvm::bit_cast(0.0)) || + (Val == llvm::bit_cast(1.0)) || + (Val == llvm::bit_cast(-1.0)) || + (Val == llvm::bit_cast(0.5)) || + (Val == llvm::bit_cast(-0.5)) || + (Val == llvm::bit_cast(2.0)) || + (Val == llvm::bit_cast(-2.0)) || + (Val == llvm::bit_cast(4.0)) || + (Val == llvm::bit_cast(-4.0)) || (Val == 0x3fc45f306dc9c882 && HasInv2Pi); } @@ -2394,15 +2394,15 @@ bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi) { // floating-point, so it is a legal inline immediate. uint32_t Val = static_cast(Literal); - return (Val == FloatToBits(0.0f)) || - (Val == FloatToBits(1.0f)) || - (Val == FloatToBits(-1.0f)) || - (Val == FloatToBits(0.5f)) || - (Val == FloatToBits(-0.5f)) || - (Val == FloatToBits(2.0f)) || - (Val == FloatToBits(-2.0f)) || - (Val == FloatToBits(4.0f)) || - (Val == FloatToBits(-4.0f)) || + return (Val == llvm::bit_cast(0.0f)) || + (Val == llvm::bit_cast(1.0f)) || + (Val == llvm::bit_cast(-1.0f)) || + (Val == llvm::bit_cast(0.5f)) || + (Val == llvm::bit_cast(-0.5f)) || + (Val == llvm::bit_cast(2.0f)) || + (Val == llvm::bit_cast(-2.0f)) || + (Val == llvm::bit_cast(4.0f)) || + (Val == llvm::bit_cast(-4.0f)) || (Val == 0x3e22f983 && HasInv2Pi); } diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp index 5be256b389857..c0f5116a6502e 100644 --- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -3342,9 +3342,9 @@ static uint64_t convertIntToDoubleImm(uint64_t ImmOp64) { static uint32_t covertDoubleImmToSingleImm(uint64_t ImmOp64) { // Conversion of a double in an uint64_t to a float in a uint32_t, // retaining the bit pattern of a float. - double DoubleImm = BitsToDouble(ImmOp64); + double DoubleImm = llvm::bit_cast(ImmOp64); float TmpFloat = static_cast(DoubleImm); - return FloatToBits(TmpFloat); + return llvm::bit_cast(TmpFloat); } bool MipsAsmParser::expandLoadSingleImmToGPR(MCInst &Inst, SMLoc IDLoc, diff --git a/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp b/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp index 7ed504325dbfa..2738a78e4a867 100644 --- a/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp +++ b/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp @@ -445,7 +445,7 @@ bool MipsLegalizerInfo::legalizeCustom(LegalizerHelper &Helper, MIRBuilder.buildMergeLikeInstr(s64, {Src, C_HiMask.getReg(0)}); MachineInstrBuilder TwoP52FP = MIRBuilder.buildFConstant( - s64, BitsToDouble(UINT64_C(0x4330000000000000))); + s64, llvm::bit_cast(UINT64_C(0x4330000000000000))); if (DstTy == s64) MIRBuilder.buildFSub(Dst, Bitcast, TwoP52FP); diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 38eb7427af38a..bd0cbd15bc267 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -2550,7 +2550,7 @@ SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) { Value = CN->getZExtValue(); } else if (ConstantFPSDNode *CN = dyn_cast(OpVal)) { assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!"); - Value = FloatToBits(CN->getValueAPF().convertToFloat()); + Value = llvm::bit_cast(CN->getValueAPF().convertToFloat()); } // If the splat value is larger than the element value, then we can never do diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 24bd18df57e12..62265f3bd63ed 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -21666,8 +21666,8 @@ static SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG, unsigned OpNo = Op.getNode()->isStrictFPOpcode() ? 1 : 0; SDLoc dl(Op); // FP constant to bias correct the final result. - SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl, - MVT::f64); + SDValue Bias = DAG.getConstantFP( + llvm::bit_cast(0x4330000000000000ULL), dl, MVT::f64); // Load the 32-bit value into an XMM register. SDValue Load = @@ -21752,8 +21752,8 @@ static SDValue lowerUINT_TO_FP_v2i32(SDValue Op, SelectionDAG &DAG, // since double has 52-bits of mantissa. Then subtract 2^52 in floating // point leaving just our i32 integers in double format. SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v2i64, N0); - SDValue VBias = - DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), DL, MVT::v2f64); + SDValue VBias = DAG.getConstantFP( + llvm::bit_cast(0x4330000000000000ULL), DL, MVT::v2f64); SDValue Or = DAG.getNode(ISD::OR, DL, MVT::v2i64, ZExtIn, DAG.getBitcast(MVT::v2i64, VBias)); Or = DAG.getBitcast(MVT::v2f64, Or); @@ -34127,8 +34127,8 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N, assert(Subtarget.hasSSE2() && "Requires at least SSE2!"); SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64, Src); - SDValue VBias = - DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl, MVT::v2f64); + SDValue VBias = DAG.getConstantFP( + llvm::bit_cast(0x4330000000000000ULL), dl, MVT::v2f64); SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn, DAG.getBitcast(MVT::v2i64, VBias)); Or = DAG.getBitcast(MVT::v2f64, Or);