diff --git a/llvm/lib/Target/VE/VEISelLowering.cpp b/llvm/lib/Target/VE/VEISelLowering.cpp
index cc7f5f6800ecd9..25a3910a48e48a 100644
--- a/llvm/lib/Target/VE/VEISelLowering.cpp
+++ b/llvm/lib/Target/VE/VEISelLowering.cpp
@@ -913,10 +913,6 @@ SDValue VETargetLowering::makeAddress(SDValue Op, SelectionDAG &DAG) const {
 
   // Handle PIC mode first. VE needs a got load for every variable!
   if (isPositionIndependent()) {
-    // GLOBAL_BASE_REG codegen'ed with call. Inform MFI that this
-    // function has calls.
-    MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
-    MFI.setHasCalls(true);
     auto GlobalN = dyn_cast<GlobalAddressSDNode>(Op);
 
     if (isa<ConstantPoolSDNode>(Op) || isa<JumpTableSDNode>(Op) ||
diff --git a/llvm/test/CodeGen/VE/Scalar/br_jt.ll b/llvm/test/CodeGen/VE/Scalar/br_jt.ll
index 88d5378830a1dd..3000ff27251add 100644
--- a/llvm/test/CodeGen/VE/Scalar/br_jt.ll
+++ b/llvm/test/CodeGen/VE/Scalar/br_jt.ll
@@ -92,7 +92,9 @@ define signext i32 @br_jt4(i32 signext %0) {
 ; CHECK-NEXT:    b.l.t (, %s10)
 ;
 ; PIC-LABEL: br_jt4:
-; PIC:       .LBB{{[0-9]+}}_5:
+; PIC:       # %bb.0:
+; PIC-NEXT:    st %s15, 24(, %s11)
+; PIC-NEXT:    st %s16, 32(, %s11)
 ; PIC-NEXT:    and %s0, %s0, (32)0
 ; PIC-NEXT:    adds.w.sx %s1, -1, %s0
 ; PIC-NEXT:    cmpu.w %s2, 3, %s1
@@ -112,7 +114,9 @@ define signext i32 @br_jt4(i32 signext %0) {
 ; PIC-NEXT:  .LBB1_2:
 ; PIC-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; PIC-NEXT:  .LBB1_3:
-; PIC-NEXT:    or %s11, 0, %s9
+; PIC-NEXT:    ld %s16, 32(, %s11)
+; PIC-NEXT:    ld %s15, 24(, %s11)
+; PIC-NEXT:    b.l.t (, %s10)
   %2 = add i32 %0, -1
   %3 = icmp ult i32 %2, 4
   br i1 %3, label %4, label %8
@@ -155,7 +159,9 @@ define signext i32 @br_jt7(i32 signext %0) {
 ; CHECK-NEXT:    b.l.t (, %s10)
 ;
 ; PIC-LABEL: br_jt7:
-; PIC:       .LBB{{[0-9]+}}_6:
+; PIC:       # %bb.0:
+; PIC-NEXT:    st %s15, 24(, %s11)
+; PIC-NEXT:    st %s16, 32(, %s11)
 ; PIC-NEXT:    and %s0, %s0, (32)0
 ; PIC-NEXT:    adds.w.sx %s1, -1, %s0
 ; PIC-NEXT:    cmpu.w %s2, 8, %s1
@@ -182,7 +188,9 @@ define signext i32 @br_jt7(i32 signext %0) {
 ; PIC-NEXT:    lea.sl %s1, .Lswitch.table.br_jt7@gotoff_hi(%s1, %s15)
 ; PIC-NEXT:    ldl.sx %s0, (%s0, %s1)
 ; PIC-NEXT:  .LBB2_4:
-; PIC-NEXT:    or %s11, 0, %s9
+; PIC-NEXT:    ld %s16, 32(, %s11)
+; PIC-NEXT:    ld %s15, 24(, %s11)
+; PIC-NEXT:    b.l.t (, %s10)
   %2 = add i32 %0, -1
   %3 = icmp ult i32 %2, 9
   br i1 %3, label %4, label %13
@@ -232,7 +240,9 @@ define signext i32 @br_jt8(i32 signext %0) {
 ; CHECK-NEXT:    b.l.t (, %s10)
 ;
 ; PIC-LABEL: br_jt8:
-; PIC:       .LBB{{[0-9]+}}_6:
+; PIC:       # %bb.0:
+; PIC-NEXT:    st %s15, 24(, %s11)
+; PIC-NEXT:    st %s16, 32(, %s11)
 ; PIC-NEXT:    and %s0, %s0, (32)0
 ; PIC-NEXT:    adds.w.sx %s1, -1, %s0
 ; PIC-NEXT:    cmpu.w %s2, 8, %s1
@@ -259,7 +269,9 @@ define signext i32 @br_jt8(i32 signext %0) {
 ; PIC-NEXT:    lea.sl %s1, .Lswitch.table.br_jt8@gotoff_hi(%s1, %s15)
 ; PIC-NEXT:    ldl.sx %s0, (%s0, %s1)
 ; PIC-NEXT:  .LBB3_4:
-; PIC-NEXT:    or %s11, 0, %s9
+; PIC-NEXT:    ld %s16, 32(, %s11)
+; PIC-NEXT:    ld %s15, 24(, %s11)
+; PIC-NEXT:    b.l.t (, %s10)
   %2 = add i32 %0, -1
   %3 = icmp ult i32 %2, 9
   br i1 %3, label %4, label %13
@@ -625,7 +637,9 @@ define signext i32 @br_jt8_m(i32 signext %0, i32 signext %1) {
 ; CHECK-NEXT:    b.l.t (, %s10)
 ;
 ; PIC-LABEL: br_jt8_m:
-; PIC:       .LBB{{[0-9]+}}_12:
+; PIC:       # %bb.0:
+; PIC-NEXT:    st %s15, 24(, %s11)
+; PIC-NEXT:    st %s16, 32(, %s11)
 ; PIC-NEXT:    and %s2, %s0, (32)0
 ; PIC-NEXT:    adds.w.sx %s0, -1, %s2
 ; PIC-NEXT:    cmpu.w %s3, 8, %s0
@@ -673,7 +687,9 @@ define signext i32 @br_jt8_m(i32 signext %0, i32 signext %1) {
 ; PIC-NEXT:    or %s0, 10, (0)1
 ; PIC-NEXT:  .LBB7_10:
 ; PIC-NEXT:    adds.w.sx %s0, %s0, (0)1
-; PIC-NEXT:    or %s11, 0, %s9
+; PIC-NEXT:    ld %s16, 32(, %s11)
+; PIC-NEXT:    ld %s15, 24(, %s11)
+; PIC-NEXT:    b.l.t (, %s10)
   switch i32 %0, label %13 [
     i32 1, label %14
     i32 2, label %3
diff --git a/llvm/test/CodeGen/VE/Scalar/function_prologue_epilogue.ll b/llvm/test/CodeGen/VE/Scalar/function_prologue_epilogue.ll
index 19c3dd2ce42cff..2332f72ef639df 100644
--- a/llvm/test/CodeGen/VE/Scalar/function_prologue_epilogue.ll
+++ b/llvm/test/CodeGen/VE/Scalar/function_prologue_epilogue.ll
@@ -28,23 +28,8 @@ define i8 @func_gv() {
 ;
 ; PIC-LABEL: func_gv:
 ; PIC:       # %bb.0:
-; PIC-NEXT:    st %s9, (, %s11)
-; PIC-NEXT:    st %s10, 8(, %s11)
 ; PIC-NEXT:    st %s15, 24(, %s11)
 ; PIC-NEXT:    st %s16, 32(, %s11)
-; PIC-NEXT:    or %s9, 0, %s11
-; PIC-NEXT:    lea %s11, -176(, %s11)
-; PIC-NEXT:    brge.l.t %s11, %s8, .LBB1_2
-; PIC-NEXT:  # %bb.1:
-; PIC-NEXT:    ld %s61, 24(, %s14)
-; PIC-NEXT:    or %s62, 0, %s0
-; PIC-NEXT:    lea %s63, 315
-; PIC-NEXT:    shm.l %s63, (%s61)
-; PIC-NEXT:    shm.l %s8, 8(%s61)
-; PIC-NEXT:    shm.l %s11, 16(%s61)
-; PIC-NEXT:    monc
-; PIC-NEXT:    or %s0, 0, %s62
-; PIC-NEXT:  .LBB1_2:
 ; PIC-NEXT:    lea %s15, _GLOBAL_OFFSET_TABLE_@pc_lo(-24)
 ; PIC-NEXT:    and %s15, %s15, (32)0
 ; PIC-NEXT:    sic %s16
@@ -54,11 +39,8 @@ define i8 @func_gv() {
 ; PIC-NEXT:    lea.sl %s0, vi8@got_hi(, %s0)
 ; PIC-NEXT:    ld %s0, (%s0, %s15)
 ; PIC-NEXT:    ld1b.zx %s0, (, %s0)
-; PIC-NEXT:    or %s11, 0, %s9
 ; PIC-NEXT:    ld %s16, 32(, %s11)
 ; PIC-NEXT:    ld %s15, 24(, %s11)
-; PIC-NEXT:    ld %s10, 8(, %s11)
-; PIC-NEXT:    ld %s9, (, %s11)
 ; PIC-NEXT:    b.l.t (, %s10)
 
   %v = load i8, i8* @vi8, align 1
diff --git a/llvm/test/CodeGen/VE/Scalar/pic_access_data.ll b/llvm/test/CodeGen/VE/Scalar/pic_access_data.ll
index 9b9bdadc2f9bf6..184b1aa8a55329 100644
--- a/llvm/test/CodeGen/VE/Scalar/pic_access_data.ll
+++ b/llvm/test/CodeGen/VE/Scalar/pic_access_data.ll
@@ -6,7 +6,9 @@
 
 define i32 @func() {
 ; CHECK-LABEL: func:
-; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    st %s15, 24(, %s11)
+; CHECK-NEXT:    st %s16, 32(, %s11)
 ; CHECK-NEXT:    lea %s15, _GLOBAL_OFFSET_TABLE_@pc_lo(-24)
 ; CHECK-NEXT:    and %s15, %s15, (32)0
 ; CHECK-NEXT:    sic %s16
@@ -27,7 +29,9 @@ define i32 @func() {
 ; CHECK-NEXT:    st %s1, (, %s0)
 ; CHECK-NEXT:    or %s0, 1, (0)1
 ; CHECK-NEXT:    stl %s2, (, %s1)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    ld %s16, 32(, %s11)
+; CHECK-NEXT:    ld %s15, 24(, %s11)
+; CHECK-NEXT:    b.l.t (, %s10)
 
   store i32* @dst, i32** @ptr, align 8
   %1 = load i32, i32* @src, align 4
diff --git a/llvm/test/CodeGen/VE/Scalar/pic_access_static_data.ll b/llvm/test/CodeGen/VE/Scalar/pic_access_static_data.ll
index 62afe5c7a6b5a6..790aaf8b20a531 100644
--- a/llvm/test/CodeGen/VE/Scalar/pic_access_static_data.ll
+++ b/llvm/test/CodeGen/VE/Scalar/pic_access_static_data.ll
@@ -6,7 +6,9 @@
 
 define void @func() {
 ; CHECK-LABEL: func:
-; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    st %s15, 24(, %s11)
+; CHECK-NEXT:    st %s16, 32(, %s11)
 ; CHECK-NEXT:    lea %s15, _GLOBAL_OFFSET_TABLE_@pc_lo(-24)
 ; CHECK-NEXT:    and %s15, %s15, (32)0
 ; CHECK-NEXT:    sic %s16
@@ -21,7 +23,9 @@ define void @func() {
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    lea.sl %s0, dst@gotoff_hi(, %s0)
 ; CHECK-NEXT:    stl %s1, (%s0, %s15)
-; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    ld %s16, 32(, %s11)
+; CHECK-NEXT:    ld %s15, 24(, %s11)
+; CHECK-NEXT:    b.l.t (, %s10)
 
   %1 = load i1, i1* @src, align 4
   %2 = select i1 %1, i32 100, i32 0
diff --git a/llvm/test/CodeGen/VE/Scalar/stackframe_nocall.ll b/llvm/test/CodeGen/VE/Scalar/stackframe_nocall.ll
index f157c54c36fc3f..47eb8732ed981d 100644
--- a/llvm/test/CodeGen/VE/Scalar/stackframe_nocall.ll
+++ b/llvm/test/CodeGen/VE/Scalar/stackframe_nocall.ll
@@ -195,23 +195,8 @@ define i8* @test_frame0_var(i8* returned %0, i8* nocapture readnone %1) {
 ;
 ; PIC-LABEL: test_frame0_var:
 ; PIC:       # %bb.0:
-; PIC-NEXT:    st %s9, (, %s11)
-; PIC-NEXT:    st %s10, 8(, %s11)
 ; PIC-NEXT:    st %s15, 24(, %s11)
 ; PIC-NEXT:    st %s16, 32(, %s11)
-; PIC-NEXT:    or %s9, 0, %s11
-; PIC-NEXT:    lea %s11, -176(, %s11)
-; PIC-NEXT:    brge.l.t %s11, %s8, .LBB3_2
-; PIC-NEXT:  # %bb.1:
-; PIC-NEXT:    ld %s61, 24(, %s14)
-; PIC-NEXT:    or %s62, 0, %s0
-; PIC-NEXT:    lea %s63, 315
-; PIC-NEXT:    shm.l %s63, (%s61)
-; PIC-NEXT:    shm.l %s8, 8(%s61)
-; PIC-NEXT:    shm.l %s11, 16(%s61)
-; PIC-NEXT:    monc
-; PIC-NEXT:    or %s0, 0, %s62
-; PIC-NEXT:  .LBB3_2:
 ; PIC-NEXT:    lea %s15, _GLOBAL_OFFSET_TABLE_@pc_lo(-24)
 ; PIC-NEXT:    and %s15, %s15, (32)0
 ; PIC-NEXT:    sic %s16
@@ -222,11 +207,8 @@ define i8* @test_frame0_var(i8* returned %0, i8* nocapture readnone %1) {
 ; PIC-NEXT:    ld %s1, (%s1, %s15)
 ; PIC-NEXT:    ld1b.zx %s1, (, %s1)
 ; PIC-NEXT:    st1b %s1, (, %s0)
-; PIC-NEXT:    or %s11, 0, %s9
 ; PIC-NEXT:    ld %s16, 32(, %s11)
 ; PIC-NEXT:    ld %s15, 24(, %s11)
-; PIC-NEXT:    ld %s10, 8(, %s11)
-; PIC-NEXT:    ld %s9, (, %s11)
 ; PIC-NEXT:    b.l.t (, %s10)
   %3 = load i8, i8* @data, align 1
   store i8 %3, i8* %0, align 1
@@ -260,12 +242,9 @@ define nonnull i8* @test_frame32_var(i8* nocapture readnone %0) {
 ;
 ; PIC-LABEL: test_frame32_var:
 ; PIC:       # %bb.0:
-; PIC-NEXT:    st %s9, (, %s11)
-; PIC-NEXT:    st %s10, 8(, %s11)
 ; PIC-NEXT:    st %s15, 24(, %s11)
 ; PIC-NEXT:    st %s16, 32(, %s11)
-; PIC-NEXT:    or %s9, 0, %s11
-; PIC-NEXT:    lea %s11, -208(, %s11)
+; PIC-NEXT:    adds.l %s11, -32, %s11
 ; PIC-NEXT:    brge.l.t %s11, %s8, .LBB4_2
 ; PIC-NEXT:  # %bb.1:
 ; PIC-NEXT:    ld %s61, 24(, %s14)
@@ -286,13 +265,11 @@ define nonnull i8* @test_frame32_var(i8* nocapture readnone %0) {
 ; PIC-NEXT:    lea.sl %s0, data@got_hi(, %s0)
 ; PIC-NEXT:    ld %s0, (%s0, %s15)
 ; PIC-NEXT:    ld1b.zx %s1, (, %s0)
-; PIC-NEXT:    lea %s0, 176(, %s11)
-; PIC-NEXT:    st1b %s1, 176(, %s11)
-; PIC-NEXT:    or %s11, 0, %s9
+; PIC-NEXT:    lea %s0, (, %s11)
+; PIC-NEXT:    st1b %s1, (, %s11)
+; PIC-NEXT:    adds.l %s11, 32, %s11
 ; PIC-NEXT:    ld %s16, 32(, %s11)
 ; PIC-NEXT:    ld %s15, 24(, %s11)
-; PIC-NEXT:    ld %s10, 8(, %s11)
-; PIC-NEXT:    ld %s9, (, %s11)
 ; PIC-NEXT:    b.l.t (, %s10)
   %2 = alloca [32 x i8], align 1
   %3 = getelementptr inbounds [32 x i8], [32 x i8]* %2, i64 0, i64 0