diff --git a/llvm/lib/Target/X86/X86InstructionSelector.cpp b/llvm/lib/Target/X86/X86InstructionSelector.cpp
index 4b8ca29b9f38f..2e79164e5bdae 100644
--- a/llvm/lib/Target/X86/X86InstructionSelector.cpp
+++ b/llvm/lib/Target/X86/X86InstructionSelector.cpp
@@ -808,12 +808,17 @@ bool X86InstructionSelector::selectZext(MachineInstr &I,
   else
     return false;
 
-  unsigned DefReg = SrcReg;
+  Register DefReg = SrcReg;
   if (DstTy != LLT::scalar(8)) {
+    Register ImpDefReg =
+        MRI.createVirtualRegister(getRegClass(DstTy, DstReg, MRI));
+    BuildMI(*I.getParent(), I, I.getDebugLoc(),
+            TII.get(TargetOpcode::IMPLICIT_DEF), ImpDefReg);
+
     DefReg = MRI.createVirtualRegister(getRegClass(DstTy, DstReg, MRI));
     BuildMI(*I.getParent(), I, I.getDebugLoc(),
-            TII.get(TargetOpcode::SUBREG_TO_REG), DefReg)
-        .addImm(0)
+            TII.get(TargetOpcode::INSERT_SUBREG), DefReg)
+        .addReg(ImpDefReg)
         .addReg(SrcReg)
         .addImm(X86::sub_8bit);
   }
diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-cmp.mir b/llvm/test/CodeGen/X86/GlobalISel/select-cmp.mir
index 2ff1fcba56156..6e89f5aaef1b7 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/select-cmp.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/select-cmp.mir
@@ -100,8 +100,9 @@ body:             |
     ; CHECK: [[COPY1:%[0-9]+]]:gr8 = COPY $sil
     ; CHECK: CMP8rr [[COPY]], [[COPY1]], implicit-def $eflags
     ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
-    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETCCr]], %subreg.sub_8bit
-    ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags
+    ; CHECK: [[DEF:%[0-9]+]]:gr32 = IMPLICIT_DEF
+    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr32 = INSERT_SUBREG [[DEF]], [[SETCCr]], %subreg.sub_8bit
+    ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[INSERT_SUBREG]], 1, implicit-def $eflags
     ; CHECK: $eax = COPY [[AND32ri8_]]
     ; CHECK: RET 0, implicit $eax
     %0(s8) = COPY $dil
@@ -131,8 +132,9 @@ body:             |
     ; CHECK: [[COPY1:%[0-9]+]]:gr16 = COPY $si
     ; CHECK: CMP16rr [[COPY]], [[COPY1]], implicit-def $eflags
     ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
-    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETCCr]], %subreg.sub_8bit
-    ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags
+    ; CHECK: [[DEF:%[0-9]+]]:gr32 = IMPLICIT_DEF
+    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr32 = INSERT_SUBREG [[DEF]], [[SETCCr]], %subreg.sub_8bit
+    ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[INSERT_SUBREG]], 1, implicit-def $eflags
     ; CHECK: $eax = COPY [[AND32ri8_]]
     ; CHECK: RET 0, implicit $eax
     %0(s16) = COPY $di
@@ -162,8 +164,9 @@ body:             |
     ; CHECK: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
     ; CHECK: CMP64rr [[COPY]], [[COPY1]], implicit-def $eflags
     ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
-    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETCCr]], %subreg.sub_8bit
-    ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags
+    ; CHECK: [[DEF:%[0-9]+]]:gr32 = IMPLICIT_DEF
+    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr32 = INSERT_SUBREG [[DEF]], [[SETCCr]], %subreg.sub_8bit
+    ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[INSERT_SUBREG]], 1, implicit-def $eflags
     ; CHECK: $eax = COPY [[AND32ri8_]]
     ; CHECK: RET 0, implicit $eax
     %0(s64) = COPY $rdi
@@ -193,8 +196,9 @@ body:             |
     ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
     ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
     ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
-    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETCCr]], %subreg.sub_8bit
-    ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags
+    ; CHECK: [[DEF:%[0-9]+]]:gr32 = IMPLICIT_DEF
+    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr32 = INSERT_SUBREG [[DEF]], [[SETCCr]], %subreg.sub_8bit
+    ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[INSERT_SUBREG]], 1, implicit-def $eflags
     ; CHECK: $eax = COPY [[AND32ri8_]]
     ; CHECK: RET 0, implicit $eax
     %0(s32) = COPY $edi
@@ -224,8 +228,9 @@ body:             |
     ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
     ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
     ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 5, implicit $eflags
-    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETCCr]], %subreg.sub_8bit
-    ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags
+    ; CHECK: [[DEF:%[0-9]+]]:gr32 = IMPLICIT_DEF
+    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr32 = INSERT_SUBREG [[DEF]], [[SETCCr]], %subreg.sub_8bit
+    ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[INSERT_SUBREG]], 1, implicit-def $eflags
     ; CHECK: $eax = COPY [[AND32ri8_]]
     ; CHECK: RET 0, implicit $eax
     %0(s32) = COPY $edi
@@ -255,8 +260,9 @@ body:             |
     ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
     ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
     ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags
-    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETCCr]], %subreg.sub_8bit
-    ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags
+    ; CHECK: [[DEF:%[0-9]+]]:gr32 = IMPLICIT_DEF
+    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr32 = INSERT_SUBREG [[DEF]], [[SETCCr]], %subreg.sub_8bit
+    ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[INSERT_SUBREG]], 1, implicit-def $eflags
     ; CHECK: $eax = COPY [[AND32ri8_]]
     ; CHECK: RET 0, implicit $eax
     %0(s32) = COPY $edi
@@ -286,8 +292,9 @@ body:             |
     ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
     ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
     ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 3, implicit $eflags
-    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETCCr]], %subreg.sub_8bit
-    ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags
+    ; CHECK: [[DEF:%[0-9]+]]:gr32 = IMPLICIT_DEF
+    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr32 = INSERT_SUBREG [[DEF]], [[SETCCr]], %subreg.sub_8bit
+    ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[INSERT_SUBREG]], 1, implicit-def $eflags
     ; CHECK: $eax = COPY [[AND32ri8_]]
     ; CHECK: RET 0, implicit $eax
     %0(s32) = COPY $edi
@@ -317,8 +324,9 @@ body:             |
     ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
     ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
     ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
-    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETCCr]], %subreg.sub_8bit
-    ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags
+    ; CHECK: [[DEF:%[0-9]+]]:gr32 = IMPLICIT_DEF
+    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr32 = INSERT_SUBREG [[DEF]], [[SETCCr]], %subreg.sub_8bit
+    ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[INSERT_SUBREG]], 1, implicit-def $eflags
     ; CHECK: $eax = COPY [[AND32ri8_]]
     ; CHECK: RET 0, implicit $eax
     %0(s32) = COPY $edi
@@ -348,8 +356,9 @@ body:             |
     ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
     ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
     ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 6, implicit $eflags
-    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETCCr]], %subreg.sub_8bit
-    ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags
+    ; CHECK: [[DEF:%[0-9]+]]:gr32 = IMPLICIT_DEF
+    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr32 = INSERT_SUBREG [[DEF]], [[SETCCr]], %subreg.sub_8bit
+    ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[INSERT_SUBREG]], 1, implicit-def $eflags
     ; CHECK: $eax = COPY [[AND32ri8_]]
     ; CHECK: RET 0, implicit $eax
     %0(s32) = COPY $edi
@@ -379,8 +388,9 @@ body:             |
     ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
     ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
     ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
-    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETCCr]], %subreg.sub_8bit
-    ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags
+    ; CHECK: [[DEF:%[0-9]+]]:gr32 = IMPLICIT_DEF
+    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr32 = INSERT_SUBREG [[DEF]], [[SETCCr]], %subreg.sub_8bit
+    ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[INSERT_SUBREG]], 1, implicit-def $eflags
     ; CHECK: $eax = COPY [[AND32ri8_]]
     ; CHECK: RET 0, implicit $eax
     %0(s32) = COPY $edi
@@ -410,8 +420,9 @@ body:             |
     ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
     ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
     ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 13, implicit $eflags
-    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETCCr]], %subreg.sub_8bit
-    ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags
+    ; CHECK: [[DEF:%[0-9]+]]:gr32 = IMPLICIT_DEF
+    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr32 = INSERT_SUBREG [[DEF]], [[SETCCr]], %subreg.sub_8bit
+    ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[INSERT_SUBREG]], 1, implicit-def $eflags
     ; CHECK: $eax = COPY [[AND32ri8_]]
     ; CHECK: RET 0, implicit $eax
     %0(s32) = COPY $edi
@@ -441,8 +452,9 @@ body:             |
     ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
     ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
     ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 12, implicit $eflags
-    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETCCr]], %subreg.sub_8bit
-    ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags
+    ; CHECK: [[DEF:%[0-9]+]]:gr32 = IMPLICIT_DEF
+    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr32 = INSERT_SUBREG [[DEF]], [[SETCCr]], %subreg.sub_8bit
+    ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[INSERT_SUBREG]], 1, implicit-def $eflags
     ; CHECK: $eax = COPY [[AND32ri8_]]
     ; CHECK: RET 0, implicit $eax
     %0(s32) = COPY $edi
@@ -472,8 +484,9 @@ body:             |
     ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
     ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
     ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 14, implicit $eflags
-    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETCCr]], %subreg.sub_8bit
-    ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags
+    ; CHECK: [[DEF:%[0-9]+]]:gr32 = IMPLICIT_DEF
+    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr32 = INSERT_SUBREG [[DEF]], [[SETCCr]], %subreg.sub_8bit
+    ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[INSERT_SUBREG]], 1, implicit-def $eflags
     ; CHECK: $eax = COPY [[AND32ri8_]]
     ; CHECK: RET 0, implicit $eax
     %0(s32) = COPY $edi
diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir b/llvm/test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir
index 4eb2d5b148a42..797c45c3efde3 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir
@@ -38,8 +38,9 @@ body:             |
 
     ; ALL-LABEL: name: test_zext_i1
     ; ALL: [[COPY:%[0-9]+]]:gr8 = COPY $dil
-    ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_8bit
-    ; ALL: [[AND64ri8_:%[0-9]+]]:gr64 = AND64ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags
+    ; ALL: [[DEF:%[0-9]+]]:gr64 = IMPLICIT_DEF
+    ; ALL: [[INSERT_SUBREG:%[0-9]+]]:gr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_8bit
+    ; ALL: [[AND64ri8_:%[0-9]+]]:gr64 = AND64ri8 [[INSERT_SUBREG]], 1, implicit-def $eflags
     ; ALL: $rax = COPY [[AND64ri8_]]
     ; ALL: RET 0, implicit $rax
     %0(s8) = COPY $dil