diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c index f32d511ec3d18..d181755bb5850 100644 --- a/clang/test/Driver/riscv-cpus.c +++ b/clang/test/Driver/riscv-cpus.c @@ -153,7 +153,6 @@ // MCPU-SIFIVE-S76: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" // MCPU-SIFIVE-S76: "-target-feature" "+c" // MCPU-SIFIVE-S76: "-target-feature" "+zicsr" "-target-feature" "+zifencei" "-target-feature" "+zihintpause" -// MCPU-SIFIVE-S76: "-target-feature" "+xsfcie" // MCPU-SIFIVE-S76: "-target-abi" "lp64d" // mcpu with default march diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c index 43fcb35aba039..b16a1b0c17300 100644 --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -33,7 +33,6 @@ // CHECK-NOT: __riscv_xcvmac {{.*$}} // CHECK-NOT: __riscv_xcvmem {{.*$}} // CHECK-NOT: __riscv_xcvsimd {{.*$}} -// CHECK-NOT: __riscv_xsfcie {{.*$}} // CHECK-NOT: __riscv_xsfvcp {{.*$}} // CHECK-NOT: __riscv_xsfvfnrclipxfqf {{.*$}} // CHECK-NOT: __riscv_xsfvfwmaccqqq {{.*$}} @@ -315,14 +314,6 @@ // RUN: -o - | FileCheck --check-prefix=CHECK-XCVSIMD-EXT %s // CHECK-XCVSIMD-EXT: __riscv_xcvsimd 1000000{{$}} -// RUN: %clang --target=riscv32-unknown-linux-gnu \ -// RUN: -march=rv32ixsfcie -x c -E -dM %s \ -// RUN: -o - | FileCheck --check-prefix=CHECK-XSFCIE-EXT %s -// RUN: %clang --target=riscv64-unknown-linux-gnu \ -// RUN: -march=rv64ixsfcie -x c -E -dM %s \ -// RUN: -o - | FileCheck --check-prefix=CHECK-XSFCIE-EXT %s -// CHECK-XSFCIE-EXT: __riscv_xsfcie 1000000{{$}} - // RUN: %clang --target=riscv32-unknown-linux-gnu \ // RUN: -march=rv32ixsfvcp -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-XSFVCP-EXT %s diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index 836a4e9ff08e5..4dc04bc8361e6 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -300,9 +300,6 @@ The current vendor extensions supported are: ``XCVbi`` LLVM implements `version 1.0.0 of the CORE-V immediate branching custom instructions specification `_ by OpenHW Group. All instructions are prefixed with `cv.` as described in the specification. These instructions are only available for riscv32 at this time. -``XSfcie`` - LLVM implements `version 1.0.0 of the SiFive Custom Instruction Extension (CIE) Software Specification `_ by SiFive. All custom instruction are added as described in the specification, and the riscv-toolchain-convention document linked above. These instructions are only available for S76 processor at this time. - Experimental C Intrinsics ========================= diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst index 9d5124680141e..52610e7de1875 100644 --- a/llvm/docs/ReleaseNotes.rst +++ b/llvm/docs/ReleaseNotes.rst @@ -146,6 +146,11 @@ Changes to the RISC-V Backend and is no longer experimental. However, the C intrinsics for these extensions are still experimental. To use the C intrinsics for these extensions, ``-menable-experimental-extensions`` needs to be passed to Clang. +* XSfcie extension and SiFive CSRs and instructions that were associated with + it have been removed. None of these CSRs and instructions were part of + "SiFive Custom Instruction Extension" as SiFive defines it. The LLVM project + needs to work with SiFive to define and document real extension names for + individual CSRs and instructions. Changes to the WebAssembly Backend ---------------------------------- diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp index 14079a0eb0760..467494da4db16 100644 --- a/llvm/lib/Support/RISCVISAInfo.cpp +++ b/llvm/lib/Support/RISCVISAInfo.cpp @@ -75,7 +75,6 @@ static const RISCVSupportedExtension SupportedExtensions[] = { {"xcvmac", RISCVExtensionVersion{1, 0}}, {"xcvmem", RISCVExtensionVersion{1, 0}}, {"xcvsimd", RISCVExtensionVersion{1, 0}}, - {"xsfcie", RISCVExtensionVersion{1, 0}}, {"xsfvcp", RISCVExtensionVersion{1, 0}}, {"xsfvfnrclipxfqf", RISCVExtensionVersion{1, 0}}, {"xsfvfwmaccqqq", RISCVExtensionVersion{1, 0}}, diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp index f3ea0f597eec4..4759aa951664c 100644 --- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp @@ -1832,57 +1832,18 @@ ParseStatus RISCVAsmParser::parseCSRSystemRegister(OperandVector &Operands) { if (getParser().parseIdentifier(Identifier)) return ParseStatus::Failure; - // Check for CSR names conflicts. - // Custom CSR names might conflict with CSR names in privileged spec. - // E.g. - SiFive mnscratch(0x350) and privileged spec mnscratch(0x740). - auto CheckCSRNameConflict = [&]() { - if (!(RISCVSysReg::lookupSysRegByName(Identifier))) { - Error(S, "system register use requires an option to be enabled"); - return true; - } - return false; - }; - - // First check for vendor specific CSRs. - auto SiFiveReg = RISCVSysReg::lookupSiFiveRegByName(Identifier); - if (SiFiveReg) { - if (SiFiveReg->haveVendorRequiredFeatures(getSTI().getFeatureBits())) { - Operands.push_back( - RISCVOperand::createSysReg(Identifier, S, SiFiveReg->Encoding)); - return ParseStatus::Success; - } - if (CheckCSRNameConflict()) - return ParseStatus::Failure; - } - auto SysReg = RISCVSysReg::lookupSysRegByName(Identifier); + if (!SysReg) + SysReg = RISCVSysReg::lookupSysRegByAltName(Identifier); if (!SysReg) if ((SysReg = RISCVSysReg::lookupSysRegByDeprecatedName(Identifier))) Warning(S, "'" + Identifier + "' is a deprecated alias for '" + SysReg->Name + "'"); - // Check for CSR encoding conflicts. - // Custom CSR encoding might conflict with CSR encoding in privileged spec. - // E.g. - SiFive mnscratch(0x350) and privileged spec miselect(0x350). - auto CheckCSREncodingConflict = [&]() { - auto Reg = RISCVSysReg::lookupSiFiveRegByEncoding(SysReg->Encoding); - if (Reg && Reg->haveVendorRequiredFeatures(getSTI().getFeatureBits())) { - Warning(S, "'" + Identifier + "' CSR is not available on the current " + - "subtarget. Instead '" + Reg->Name + - "' CSR will be used."); - Operands.push_back( - RISCVOperand::createSysReg(Reg->Name, S, Reg->Encoding)); - return true; - } - return false; - }; - - // Accept a named SysReg if the required features are present. + // Accept a named Sys Reg if the required features are present. if (SysReg) { if (!SysReg->haveRequiredFeatures(getSTI().getFeatureBits())) return Error(S, "system register use requires an option to be enabled"); - if (CheckCSREncodingConflict()) - return ParseStatus::Success; Operands.push_back( RISCVOperand::createSysReg(Identifier, S, SysReg->Encoding)); return ParseStatus::Success; diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index 184000b48987e..a639634d36a12 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -566,8 +566,6 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size, TRY_TO_DECODE_FEATURE( RISCV::FeatureVendorXSfvfnrclipxfqf, DecoderTableXSfvfnrclipxfqf32, "SiFive FP32-to-int8 Ranged Clip Instructions opcode table"); - TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfcie, DecoderTableXSfcie32, - "Sifive CIE custom opcode table"); TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbitmanip, DecoderTableXCVbitmanip32, "CORE-V Bit Manipulation custom opcode table"); diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp index 66a46a485f538..74d0db545e556 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp @@ -27,7 +27,6 @@ extern const SubtargetFeatureKV RISCVFeatureKV[RISCV::NumSubtargetFeatures]; namespace RISCVSysReg { #define GET_SysRegsList_IMPL -#define GET_SiFiveRegsList_IMPL #include "RISCVGenSearchableTables.inc" } // namespace RISCVSysReg diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h index 30ed36525e29f..c32210fc14192 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h @@ -401,6 +401,7 @@ int getLoadFPImm(APFloat FPImm); namespace RISCVSysReg { struct SysReg { const char *Name; + const char *AltName; const char *DeprecatedName; unsigned Encoding; // FIXME: add these additional fields when needed. @@ -424,22 +425,9 @@ struct SysReg { return true; return (FeaturesRequired & ActiveFeatures) == FeaturesRequired; } - - bool haveVendorRequiredFeatures(const FeatureBitset &ActiveFeatures) const { - // Not in 32-bit mode. - if (isRV32Only && ActiveFeatures[RISCV::Feature64Bit]) - return false; - // No required feature associated with the system register. - if (FeaturesRequired.none()) - return false; - return (FeaturesRequired & ActiveFeatures) == FeaturesRequired; - } }; -struct SiFiveReg : SysReg {}; - #define GET_SysRegsList_DECL -#define GET_SiFiveRegsList_DECL #include "RISCVGenSearchableTables.inc" } // end namespace RISCVSysReg diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp index 195dda0b8b140..bd899495812f4 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp @@ -121,11 +121,8 @@ void RISCVInstPrinter::printCSRSystemRegister(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) { unsigned Imm = MI->getOperand(OpNo).getImm(); - auto SiFiveReg = RISCVSysReg::lookupSiFiveRegByEncoding(Imm); auto SysReg = RISCVSysReg::lookupSysRegByEncoding(Imm); - if (SiFiveReg && SiFiveReg->haveVendorRequiredFeatures(STI.getFeatureBits())) - markup(O, Markup::Register) << SiFiveReg->Name; - else if (SysReg && SysReg->haveRequiredFeatures(STI.getFeatureBits())) + if (SysReg && SysReg->haveRequiredFeatures(STI.getFeatureBits())) markup(O, Markup::Register) << SysReg->Name; else markup(O, Markup::Register) << formatImm(Imm); diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index adf3c84b586a2..bdab052d67cdc 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -826,13 +826,6 @@ def HasVendorXSfvcp : Predicate<"Subtarget->hasVendorXSfvcp()">, AssemblerPredicate<(all_of FeatureVendorXSfvcp), "'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions)">; -def FeatureVendorXSfcie - : SubtargetFeature<"xsfcie", "HasVendorXSfcie", "true", - "'XSfcie' (SiFive Custom Instruction Extension SCIE.)">; -def HasVendorXSfcie : Predicate<"Subtarget->hasVendorXSfcie()">, - AssemblerPredicate<(all_of FeatureVendorXSfcie), - "'XSfcie' (SiFive Custom Instruction Extension SCIE.)">; - def FeatureVendorXSfvqmaccdod : SubtargetFeature<"xsfvqmaccdod", "HasVendorXSfvqmaccdod", "true", "'XSfvqmaccdod' (SiFive Int8 Matrix Multiplication Instructions (2-by-8 and 8-by-2))", diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td index 561ab8d7403d6..31f832dfd84ce 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td @@ -673,27 +673,3 @@ let Predicates = [HasVendorXSfvfnrclipxfqf] in { defm : VPatVFNRCLIP<"vfnrclip_xu_f_qf", "VFNRCLIP_XU_F_QF">; defm : VPatVFNRCLIP<"vfnrclip_x_f_qf", "VFNRCLIP_X_F_QF">; } - -let Predicates = [HasVendorXSfcie] in { -let hasSideEffects = 1, mayLoad = 0, mayStore = 0, DecoderNamespace = "XSfcie" in { -def SF_CFLUSH_D_L1 : RVInstI<0b000, OPC_SYSTEM, (outs), (ins GPR:$rs1), "cflush.d.l1","$rs1">, - Sched<[]> { - let rd = 0; - let imm12 = {0b1111,0b1100,0b0000}; -} - -def SF_CDISCARD_D_L1 : RVInstI<0b000, OPC_SYSTEM, (outs), (ins GPR:$rs1), "cdiscard.d.l1","$rs1">, - Sched<[]> { - let rd = 0; - let imm12 = {0b1111,0b1100,0b0010}; -} - -def SF_CEASE : RVInstI<0b000, OPC_SYSTEM, (outs), (ins), "cease","">, Sched<[]> { - let rs1 = 0; - let rd = 0; - let imm12 = {0b0011,0b0000,0b0101}; -} -} -def : InstAlias<"cflush.d.l1", (SF_CFLUSH_D_L1 X0)>; -def : InstAlias<"cdiscard.d.l1", (SF_CDISCARD_D_L1 X0)>; -} // Predicates = [HasVendorXScie] diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td index 6362a3bef6f28..ba8996e710edc 100644 --- a/llvm/lib/Target/RISCV/RISCVProcessors.td +++ b/llvm/lib/Target/RISCV/RISCVProcessors.td @@ -174,8 +174,7 @@ def SIFIVE_S76 : RISCVProcessorModel<"sifive-s76", FeatureStdExtF, FeatureStdExtD, FeatureStdExtC, - FeatureStdExtZihintpause, - FeatureVendorXSfcie], + FeatureStdExtZihintpause], [TuneSiFive7]>; def SIFIVE_U54 : RISCVProcessorModel<"sifive-u54", diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td b/llvm/lib/Target/RISCV/RISCVSystemOperands.td index 953df7b15e2f6..43475e825b46f 100644 --- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td +++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td @@ -19,9 +19,11 @@ include "llvm/TableGen/SearchableTable.td" class SysReg op> { string Name = name; - // A maximum of one deprecated name is supported right now. It generates a - // diagnostic when the name is used to encourage software to migrate away from - // the name. + // A maximum of one alias is supported right now. + string AltName = name; + // A maximum of one deprecated name is supported right now. Unlike the + // `AltName` alias, a `DeprecatedName` generates a diagnostic when the name is + // used to encourage software to migrate away from the name. string DeprecatedName = ""; bits<12> Encoding = op; // FIXME: add these additional fields when needed. @@ -41,7 +43,7 @@ def SysRegsList : GenericTable { let FilterClass = "SysReg"; // FIXME: add "ReadWrite", "Mode", "Extra", "Number" fields when needed. let Fields = [ - "Name", "DeprecatedName", "Encoding", "FeaturesRequired", + "Name", "AltName", "DeprecatedName", "Encoding", "FeaturesRequired", "isRV32Only", ]; @@ -54,32 +56,13 @@ def lookupSysRegByName : SearchIndex { let Key = [ "Name" ]; } -def lookupSysRegByDeprecatedName : SearchIndex { +def lookupSysRegByAltName : SearchIndex { let Table = SysRegsList; - let Key = [ "DeprecatedName" ]; -} - -class SiFiveReg op> : SysReg; - -def SiFiveRegsList : GenericTable { - let FilterClass = "SiFiveReg"; - // FIXME: add "ReadWrite", "Mode", "Extra", "Number" fields when needed. - let Fields = [ - "Name", "DeprecatedName", "Encoding", "FeaturesRequired", - "isRV32Only", - ]; - - let PrimaryKey = [ "Encoding" ]; - let PrimaryKeyName = "lookupSiFiveRegByEncoding"; + let Key = [ "AltName" ]; } -def lookupSiFiveRegByName : SearchIndex { - let Table = SiFiveRegsList; - let Key = [ "Name" ]; -} - -def lookupSiFiveRegByDeprecatedName : SearchIndex { - let Table = SiFiveRegsList; +def lookupSysRegByDeprecatedName : SearchIndex { + let Table = SysRegsList; let Key = [ "DeprecatedName" ]; } @@ -309,7 +292,7 @@ foreach i = 3...31 in //===----------------------------------------------------------------------===// // Machine Counter Setup //===----------------------------------------------------------------------===// -let DeprecatedName = "mucounteren" in // Privileged spec v1.9.1 Name +let AltName = "mucounteren" in // Privileged spec v1.9.1 Name def : SysReg<"mcountinhibit", 0x320>; // mhpmevent3-mhpmevent31 at 0x323-0x33F. @@ -322,20 +305,6 @@ foreach i = 3...31 in { def : SysReg<"mhpmevent"#i#"h", !add(0x723, !sub(i, 3))>; } -//===----------------------------------------------------------------------===// -// SiFive Custom Machine Mode Registers -//===----------------------------------------------------------------------===// - -let FeaturesRequired = [{ {RISCV::FeatureVendorXSfcie} }] in { -def : SiFiveReg<"mnscratch", 0x350>; -def : SiFiveReg<"mnepc", 0x351>; -def : SiFiveReg<"mncause", 0x352>; -def : SiFiveReg<"mnstatus", 0x353>; -def : SiFiveReg<"mbpm", 0x7C0>; -def : SiFiveReg<"mfd", 0x7C1>; -def : SiFiveReg<"mpd", 0x7C8>; -} - //===----------------------------------------------------------------------===// // Debug/ Trace Registers (shared with Debug Mode) //===----------------------------------------------------------------------===// @@ -353,7 +322,7 @@ def : SysReg<"dpc", 0x7B1>; // "dscratch" is an alternative name for "dscratch0" which appeared in earlier // drafts of the RISC-V debug spec -let DeprecatedName = "dscratch" in +let AltName = "dscratch" in def : SysReg<"dscratch0", 0x7B2>; def : SysReg<"dscratch1", 0x7B3>; diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s index f1c080580fe25..b0708ca2f81f3 100644 --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -282,9 +282,6 @@ .attribute arch, "rv32i_zvfbfwma0p8" # CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin0p8_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvfbfwma0p8_zvl32b1p0" -.attribute arch, "rv64i_xsfcie" -# CHECK: attribute 5, "rv64i2p1_xsfcie1p0" - .attribute arch, "rv32izacas1p0" # CHECK: attribute 5, "rv32i2p1_a2p1_zacas1p0" diff --git a/llvm/test/MC/RISCV/machine-csr-names.s b/llvm/test/MC/RISCV/machine-csr-names.s index 664cf0301eff9..3b6d73b5118be 100644 --- a/llvm/test/MC/RISCV/machine-csr-names.s +++ b/llvm/test/MC/RISCV/machine-csr-names.s @@ -9,9 +9,6 @@ # RUN: llvm-mc -filetype=obj -triple riscv64 < %s \ # RUN: | llvm-objdump -d - \ # RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s -# -# RUN: llvm-mc -triple riscv32 %s 2>&1 | FileCheck -check-prefix CHECK-WARN %s -# RUN: llvm-mc -triple riscv64 %s 2>&1 | FileCheck -check-prefix CHECK-WARN %s ################################## # Machine Information Registers @@ -1495,8 +1492,6 @@ csrrs t1, dscratch, zero # uimm12 csrrs t2, 0x7B2, zero -# CHECK-WARN: warning: 'dscratch' is a deprecated alias for 'dscratch0' - # dscratch1 # name # CHECK-INST: csrrs t1, dscratch1, zero @@ -1949,8 +1944,6 @@ csrrs t1, mucounteren, zero # uimm12 csrrs t2, 0x320, zero -# CHECK-WARN: warning: 'mucounteren' is a deprecated alias for 'mcountinhibit' - # mhpmevent3 # name # CHECK-INST: csrrs t1, mhpmevent3, zero diff --git a/llvm/test/MC/RISCV/xsfcie-invalid.s b/llvm/test/MC/RISCV/xsfcie-invalid.s deleted file mode 100644 index a84ffeeaa054e..0000000000000 --- a/llvm/test/MC/RISCV/xsfcie-invalid.s +++ /dev/null @@ -1,39 +0,0 @@ -# SCIE - SiFive Custom Instructions Extension. -# RUN: not llvm-mc -triple riscv32 -mattr=-xsfcie < %s 2>&1 | FileCheck %s -# RUN: not llvm-mc -triple riscv64 -mattr=-xsfcie < %s 2>&1 | FileCheck %s - -cflush.d.l1 0x10 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction - -cdiscard.d.l1 0x10 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction - -cflush.d.l1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SCIE.) - -cdiscard.d.l1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SCIE.) - -cflush.d.l1 x0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SCIE.) - -cflush.d.l1 x7 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SCIE.) - -cdiscard.d.l1 x0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SCIE.) - -cdiscard.d.l1 x7 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SCIE.) - -cease x1 # CHECK: :[[@LINE]]:7: error: invalid operand for instruction - -cease 0x10 # CHECK: :[[@LINE]]:7: error: invalid operand for instruction - -cease # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SCIE.) - -csrr t1, mbpm # CHECK: :[[@LINE]]:10: error: system register use requires an option to be enabled - -csrr t1, mfd # CHECK: :[[@LINE]]:10: error: system register use requires an option to be enabled - -csrr t1, mpd # CHECK: :[[@LINE]]:10: error: system register use requires an option to be enabled - -csrr t1, mnscratch # CHECK: :[[@LINE]]:10: error: system register use requires an option to be enabled - -csrr t1, mnepc # CHECK: :[[@LINE]]:10: error: system register use requires an option to be enabled - -csrr t1, mncause # CHECK: :[[@LINE]]:10: error: system register use requires an option to be enabled - -csrr t1, mnstatus # CHECK: :[[@LINE]]:10: error: system register use requires an option to be enabled diff --git a/llvm/test/MC/RISCV/xsfcie-valid.s b/llvm/test/MC/RISCV/xsfcie-valid.s deleted file mode 100644 index 25f743f5ed797..0000000000000 --- a/llvm/test/MC/RISCV/xsfcie-valid.s +++ /dev/null @@ -1,136 +0,0 @@ -# SCIE - SiFive Custom Instructions Extension. -# RUN: llvm-mc %s -triple=riscv32 -mattr=+xsfcie -riscv-no-aliases -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s -# RUN: llvm-mc %s -triple=riscv64 -mattr=+xsfcie -riscv-no-aliases -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s -# RUN: llvm-mc %s -triple=riscv32 -mattr=+xsfcie -riscv-no-aliases -show-encoding 2>&1 \ -# RUN: | FileCheck -check-prefixes=CHECK-WARN %s -# RUN: llvm-mc %s -triple=riscv64 -mattr=+xsfcie -riscv-no-aliases -show-encoding 2>&1 \ -# RUN: | FileCheck -check-prefixes=CHECK-WARN %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xsfcie < %s \ -# RUN: | llvm-objdump --mattr=+xsfcie -M no-aliases -d - \ -# RUN: | FileCheck -check-prefix=CHECK-INST %s -# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+xsfcie < %s \ -# RUN: | llvm-objdump --mattr=+xsfcie -M no-aliases -d - \ -# RUN: | FileCheck -check-prefix=CHECK-INST %s -# RUN: llvm-mc %s -triple=riscv64 -mcpu=sifive-s76 -riscv-no-aliases -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s -# RUN: llvm-mc %s -triple=riscv64 -mcpu=sifive-s76 -riscv-no-aliases -show-encoding 2>&1 \ -# RUN: | FileCheck -check-prefixes=CHECK-WARN %s -# RUN: llvm-mc -filetype=obj -triple riscv64 -mcpu=sifive-s76 < %s \ -# RUN: | llvm-objdump --mcpu=sifive-s76 -M no-aliases -d - \ -# RUN: | FileCheck -check-prefix=CHECK-INST %s - -# CHECK-INST: cflush.d.l1 zero -# CHECK-ENC: encoding: [0x73,0x00,0x00,0xfc] -# CHECK-INST: cflush.d.l1 zero -# CHECK-ENC: encoding: [0x73,0x00,0x00,0xfc] -cflush.d.l1 x0 -cflush.d.l1 - -# CHECK-INST: cflush.d.l1 t2 -# CHECK-ENC: encoding: [0x73,0x80,0x03,0xfc] -cflush.d.l1 x7 - -# CHECK-INST: cdiscard.d.l1 zero -# CHECK-ENC: encoding: [0x73,0x00,0x20,0xfc] -# CHECK-INST: cdiscard.d.l1 zero -# CHECK-ENC: encoding: [0x73,0x00,0x20,0xfc] -cdiscard.d.l1 x0 -cdiscard.d.l1 - -# CHECK-INST: cdiscard.d.l1 t2 -# CHECK-ENC: encoding: [0x73,0x80,0x23,0xfc] -cdiscard.d.l1 x7 - -# CHECK-INST: cease -# CHECK-ENC: encoding: [0x73,0x00,0x50,0x30] -cease - -# mbpm -# name -# CHECK-INST: csrrs t2, mbpm, zero -# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x7c] -# uimm12 -# CHECK-INST: csrrs t2, mbpm, zero -# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x7c] -# name -csrrs t2, mbpm, zero -# uimm12 -csrrs t2, 0x7C0, zero - -# mfd -# name -# CHECK-INST: csrrs t2, mfd, zero -# CHECK-ENC: encoding: [0xf3,0x23,0x10,0x7c] -# uimm12 -# CHECK-INST: csrrs t2, mfd, zero -# CHECK-ENC: encoding: [0xf3,0x23,0x10,0x7c] -# name -csrrs t2, mfd, zero -# uimm12 -csrrs t2, 0x7C1, zero - -# mpd -# name -# CHECK-INST: csrrs t2, mpd, zero -# CHECK-ENC: encoding: [0xf3,0x23,0x80,0x7c] -# uimm12 -# CHECK-INST: csrrs t2, mpd, zero -# CHECK-ENC: encoding: [0xf3,0x23,0x80,0x7c] -# name -csrrs t2, mpd, zero -# uimm12 -csrrs t2, 0x7C8, zero - -# mnscratch -# name -# CHECK-INST: csrrs t1, mnscratch, zero -# CHECK-ENC: encoding: [0x73,0x23,0x00,0x35] -# CHECK-WARN: warning: 'miselect' CSR is not available on the current subtarget. Instead 'mnscratch' CSR will be used. -# uimm12 -# CHECK-INST: csrrs t2, mnscratch, zero -# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x35] -# name -csrrs t1, mnscratch, zero -csrrs t1, miselect, zero -# uimm12 -csrrs t2, 0x350, zero - -# mnepc -# name -# CHECK-INST: csrrs t1, mnepc, zero -# CHECK-ENC: encoding: [0x73,0x23,0x10,0x35] -# CHECK-WARN: warning: 'mireg' CSR is not available on the current subtarget. Instead 'mnepc' CSR will be used. -# uimm12 -# CHECK-INST: csrrs t2, mnepc, zero -# CHECK-ENC: encoding: [0xf3,0x23,0x10,0x35] -# name -csrrs t1, mnepc, zero -csrrs t1, mireg, zero -# uimm12 -csrrs t2, 0x351, zero - -# mncause -# name -# CHECK-INST: csrrs t1, mncause, zero -# CHECK-ENC: encoding: [0x73,0x23,0x20,0x35] -# uimm12 -# CHECK-INST: csrrs t2, mncause, zero -# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x35] -# name -csrrs t1, mncause, zero -# uimm12 -csrrs t2, 0x352, zero - -# mnstatus -# name -# CHECK-INST: csrrs t1, mnstatus, zero -# CHECK-ENC: encoding: [0x73,0x23,0x30,0x35] -# uimm12 -# CHECK-INST: csrrs t2, mnstatus, zero -# CHECK-ENC: encoding: [0xf3,0x23,0x30,0x35] -# name -csrrs t1, mnstatus, zero -# uimm12 -csrrs t2, 0x353, zero diff --git a/llvm/unittests/Support/RISCVISAInfoTest.cpp b/llvm/unittests/Support/RISCVISAInfoTest.cpp index 5044177915dbd..97689538d7854 100644 --- a/llvm/unittests/Support/RISCVISAInfoTest.cpp +++ b/llvm/unittests/Support/RISCVISAInfoTest.cpp @@ -734,7 +734,6 @@ R"(All available -march extensions for RISC-V xcvmac 1.0 xcvmem 1.0 xcvsimd 1.0 - xsfcie 1.0 xsfvcp 1.0 xsfvfnrclipxfqf 1.0 xsfvfwmaccqqq 1.0