diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/add_reduce.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/add_reduce.mir index ecaf68d90a954..19147a2a2e92b 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/add_reduce.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/add_reduce.mir @@ -147,53 +147,59 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: max_min_add_reduce ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.1(0x40000000), %bb.3(0x40000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8 - ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $lr - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 24 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -12 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -16 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -20 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -24 - ; CHECK: renamable $r12 = t2LDRi12 $sp, 48, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.6, align 8) - ; CHECK: renamable $r5 = t2ADDri renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r7, dead $cpsr = tLSRri killed renamable $r5, 2, 14 /* CC::al */, $noreg - ; CHECK: dead $lr = t2WLS renamable $r7, %bb.3 - ; CHECK: bb.1.for.body.lr.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3, $r7, $r12 - ; CHECK: $r6, $r5 = t2LDRDi8 $sp, 40, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.4, align 8), (load (s32) from %fixed-stack.5) - ; CHECK: $r4 = tMOVr killed $r7, 14 /* CC::al */, $noreg - ; CHECK: $r7, $r8 = t2LDRDi8 $sp, 24, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8), (load (s32) from %fixed-stack.1) - ; CHECK: renamable $q0 = MVE_VDUP32 killed renamable $r5, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: renamable $q1 = MVE_VDUP32 killed renamable $r6, 0, $noreg, $noreg, undef renamable $q1 - ; CHECK: renamable $r5, dead $cpsr = tSUBi3 killed renamable $r7, 4, 14 /* CC::al */, $noreg - ; CHECK: bb.2.for.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $q0, $q1, $r0, $r1, $r2, $r3, $r4, $r5, $r8, $r12 - ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg, $noreg - ; CHECK: MVE_VPST 8, implicit $vpr - ; CHECK: renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 4, 1, renamable $vpr, $noreg :: (load (s128) from %ir.input_2_cast, align 4) - ; CHECK: MVE_VPST 8, implicit $vpr - ; CHECK: renamable $r0, renamable $q3 = MVE_VLDRWU32_post killed renamable $r0, 4, 1, renamable $vpr, $noreg :: (load (s128) from %ir.input_1_cast, align 4) - ; CHECK: renamable $q2 = MVE_VADD_qr_i32 killed renamable $q2, renamable $r3, 0, $noreg, $noreg, undef renamable $q2 - ; CHECK: renamable $q3 = MVE_VADD_qr_i32 killed renamable $q3, renamable $r2, 0, $noreg, $noreg, undef renamable $q3 - ; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg - ; CHECK: renamable $q2 = MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, $noreg, undef renamable $q2 - ; CHECK: renamable $r4, dead $cpsr = tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $q2 = MVE_VADD_qr_i32 killed renamable $q2, renamable $r8, 0, $noreg, $noreg, undef renamable $q2 - ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg - ; CHECK: MVE_VPST 4, implicit $vpr - ; CHECK: renamable $q2 = MVE_VMAXu32 killed renamable $q2, renamable $q1, 1, renamable $vpr, $noreg, undef renamable $q2 - ; CHECK: renamable $q2 = MVE_VMINu32 killed renamable $q2, renamable $q0, 1, killed renamable $vpr, $noreg, undef renamable $q2 - ; CHECK: renamable $r6 = MVE_VADDVu32no_acc killed renamable $q2, 0, $noreg, $noreg - ; CHECK: early-clobber renamable $r5 = t2STR_PRE killed renamable $r6, killed renamable $r5, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.scevgep2) - ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 - ; CHECK: bb.3.for.cond.cleanup: - ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg - ; CHECK: $sp = t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $pc, implicit killed $r0 + ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.3(0x40000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $lr + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 24 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r8, -8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -12 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r6, -16 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r5, -20 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -24 + ; CHECK-NEXT: renamable $r12 = t2LDRi12 $sp, 48, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.6, align 8) + ; CHECK-NEXT: renamable $r5 = t2ADDri renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r7, dead $cpsr = tLSRri killed renamable $r5, 2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: dead $lr = t2WLS renamable $r7, %bb.3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.for.body.lr.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3, $r7, $r12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $r6, $r5 = t2LDRDi8 $sp, 40, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.4, align 8), (load (s32) from %fixed-stack.5) + ; CHECK-NEXT: $r4 = tMOVr killed $r7, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $r7, $r8 = t2LDRDi8 $sp, 24, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8), (load (s32) from %fixed-stack.1) + ; CHECK-NEXT: renamable $q0 = MVE_VDUP32 killed renamable $r5, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: renamable $q1 = MVE_VDUP32 killed renamable $r6, 0, $noreg, $noreg, undef renamable $q1 + ; CHECK-NEXT: renamable $r5, dead $cpsr = tSUBi3 killed renamable $r7, 4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.for.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $q0, $q1, $r0, $r1, $r2, $r3, $r4, $r5, $r8, $r12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg, $noreg + ; CHECK-NEXT: MVE_VPST 8, implicit $vpr + ; CHECK-NEXT: renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 4, 1, renamable $vpr, $noreg :: (load (s128) from %ir.input_2_cast, align 4) + ; CHECK-NEXT: MVE_VPST 8, implicit $vpr + ; CHECK-NEXT: renamable $r0, renamable $q3 = MVE_VLDRWU32_post killed renamable $r0, 4, 1, renamable $vpr, $noreg :: (load (s128) from %ir.input_1_cast, align 4) + ; CHECK-NEXT: renamable $q2 = MVE_VADD_qr_i32 killed renamable $q2, renamable $r3, 0, $noreg, $noreg, undef renamable $q2 + ; CHECK-NEXT: renamable $q3 = MVE_VADD_qr_i32 killed renamable $q3, renamable $r2, 0, $noreg, $noreg, undef renamable $q3 + ; CHECK-NEXT: $lr = tMOVr $r4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $q2 = MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, $noreg, undef renamable $q2 + ; CHECK-NEXT: renamable $r4, dead $cpsr = tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $q2 = MVE_VADD_qr_i32 killed renamable $q2, renamable $r8, 0, $noreg, $noreg, undef renamable $q2 + ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: MVE_VPST 4, implicit $vpr + ; CHECK-NEXT: renamable $q2 = MVE_VMAXu32 killed renamable $q2, renamable $q1, 1, renamable $vpr, $noreg, undef renamable $q2 + ; CHECK-NEXT: renamable $q2 = MVE_VMINu32 killed renamable $q2, renamable $q0, 1, killed renamable $vpr, $noreg, undef renamable $q2 + ; CHECK-NEXT: renamable $r6 = MVE_VADDVu32no_acc killed renamable $q2, 0, $noreg, $noreg + ; CHECK-NEXT: early-clobber renamable $r5 = t2STR_PRE killed renamable $r6, killed renamable $r5, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.scevgep2) + ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.for.cond.cleanup: + ; CHECK-NEXT: $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $sp = t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $pc, implicit killed $r0 bb.0.entry: successors: %bb.1(0x40000000), %bb.3(0x40000000) liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $lr diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/ctlz-non-zeros.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/ctlz-non-zeros.mir index 588fe4cfcdb99..e04e6e8cdc3dc 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/ctlz-non-zeros.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/ctlz-non-zeros.mir @@ -158,38 +158,44 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: test_ctlz_i8 ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 - ; CHECK: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 11, 8, implicit-def $itstate - ; CHECK: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r4, def $pc, implicit killed $itstate - ; CHECK: bb.1.loop.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: renamable $lr = t2LDRi12 $sp, 8, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8) - ; CHECK: $r4 = tMOVr killed $lr, 14 /* CC::al */, $noreg - ; CHECK: bb.2.loop.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3, $r4 - ; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg - ; CHECK: renamable $vpr = MVE_VCTP16 renamable $r3, 0, $noreg, $noreg - ; CHECK: MVE_VPST 4, implicit $vpr - ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.b, align 2) - ; CHECK: renamable $q1 = MVE_VLDRHU16 killed renamable $r0, 0, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.a, align 2) - ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 8, 14 /* CC::al */, $noreg - ; CHECK: renamable $r4, dead $cpsr = tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $q1 = MVE_VCLZs8 killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1 - ; CHECK: $r0 = tMOVr $r1, 14 /* CC::al */, $noreg - ; CHECK: renamable $q1 = MVE_VQSHRUNs16th killed renamable $q1, killed renamable $q0, 1, 0, $noreg, $noreg - ; CHECK: MVE_VPST 8, implicit $vpr - ; CHECK: renamable $r2 = MVE_VSTRHU16_post killed renamable $q1, killed renamable $r2, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.addr.c, align 2) - ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 - ; CHECK: bb.3.exit: - ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -8 + ; CHECK-NEXT: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: t2IT 11, 8, implicit-def $itstate + ; CHECK-NEXT: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r4, def $pc, implicit killed $itstate + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.loop.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $lr = t2LDRi12 $sp, 8, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8) + ; CHECK-NEXT: $r4 = tMOVr killed $lr, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.loop.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3, $r4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $lr = tMOVr $r4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $vpr = MVE_VCTP16 renamable $r3, 0, $noreg, $noreg + ; CHECK-NEXT: MVE_VPST 4, implicit $vpr + ; CHECK-NEXT: renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.b, align 2) + ; CHECK-NEXT: renamable $q1 = MVE_VLDRHU16 killed renamable $r0, 0, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.a, align 2) + ; CHECK-NEXT: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 8, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r4, dead $cpsr = tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $q1 = MVE_VCLZs8 killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1 + ; CHECK-NEXT: $r0 = tMOVr $r1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $q1 = MVE_VQSHRUNs16th killed renamable $q1, killed renamable $q0, 1, 0, $noreg, $noreg + ; CHECK-NEXT: MVE_VPST 8, implicit $vpr + ; CHECK-NEXT: renamable $r2 = MVE_VSTRHU16_post killed renamable $q1, killed renamable $r2, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.addr.c, align 2) + ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.exit: + ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $r3, $r4, $lr @@ -265,38 +271,45 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: test_ctlz_i16 ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r7 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 11, 8, implicit-def $itstate - ; CHECK: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def dead $r7, def $pc, implicit killed $itstate - ; CHECK: bb.1.loop.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3, $r4 - ; CHECK: renamable $lr = t2LDRi12 $sp, 8, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8) - ; CHECK: $r12 = tMOVr killed $lr, 14 /* CC::al */, $noreg - ; CHECK: bb.2.loop.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3, $r4, $r12 - ; CHECK: $lr = tMOVr $r12, 14 /* CC::al */, $noreg - ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg - ; CHECK: MVE_VPST 4, implicit $vpr - ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.b, align 4) - ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.a, align 4) - ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg - ; CHECK: renamable $r12 = t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $q1 = MVE_VCLZs16 killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1 - ; CHECK: renamable $q1 = MVE_VQSHRUNs32th killed renamable $q1, killed renamable $q0, 3, 0, $noreg, $noreg - ; CHECK: MVE_VPST 8, implicit $vpr - ; CHECK: renamable $r2 = MVE_VSTRWU32_post killed renamable $q1, killed renamable $r2, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.addr.c, align 4) - ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 - ; CHECK: bb.3.exit: - ; CHECK: liveins: $r4 - ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def dead $r7, def $pc + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: t2IT 11, 8, implicit-def $itstate + ; CHECK-NEXT: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def dead $r7, def $pc, implicit killed $itstate + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.loop.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3, $r4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $lr = t2LDRi12 $sp, 8, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8) + ; CHECK-NEXT: $r12 = tMOVr killed $lr, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.loop.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3, $r4, $r12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $lr = tMOVr $r12, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg + ; CHECK-NEXT: MVE_VPST 4, implicit $vpr + ; CHECK-NEXT: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.b, align 4) + ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.a, align 4) + ; CHECK-NEXT: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r12 = t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $q1 = MVE_VCLZs16 killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1 + ; CHECK-NEXT: renamable $q1 = MVE_VQSHRUNs32th killed renamable $q1, killed renamable $q0, 3, 0, $noreg, $noreg + ; CHECK-NEXT: MVE_VPST 8, implicit $vpr + ; CHECK-NEXT: renamable $r2 = MVE_VSTRWU32_post killed renamable $q1, killed renamable $r2, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.addr.c, align 4) + ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.exit: + ; CHECK-NEXT: liveins: $r4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def dead $r7, def $pc bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $r3, $r7, $lr @@ -371,38 +384,45 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: test_ctlz_i32 ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r7 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 11, 8, implicit-def $itstate - ; CHECK: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def dead $r7, def $pc, implicit killed $itstate - ; CHECK: bb.1.loop.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3, $r4 - ; CHECK: renamable $lr = t2LDRi12 $sp, 8, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8) - ; CHECK: $r12 = tMOVr killed $lr, 14 /* CC::al */, $noreg - ; CHECK: bb.2.loop.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3, $r4, $r12 - ; CHECK: $lr = tMOVr $r12, 14 /* CC::al */, $noreg - ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg - ; CHECK: MVE_VPST 4, implicit $vpr - ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.a, align 4) - ; CHECK: renamable $r1, renamable $q1 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.b, align 4) - ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg - ; CHECK: renamable $r12 = t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $q1 = MVE_VCLZs32 killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1 - ; CHECK: renamable $q0 = MVE_VQSHRUNs32th killed renamable $q0, killed renamable $q1, 3, 0, $noreg, $noreg - ; CHECK: MVE_VPST 8, implicit $vpr - ; CHECK: renamable $r2 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r2, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.addr.c, align 4) - ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 - ; CHECK: bb.3.exit: - ; CHECK: liveins: $r4 - ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def dead $r7, def $pc + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: t2IT 11, 8, implicit-def $itstate + ; CHECK-NEXT: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def dead $r7, def $pc, implicit killed $itstate + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.loop.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3, $r4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $lr = t2LDRi12 $sp, 8, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8) + ; CHECK-NEXT: $r12 = tMOVr killed $lr, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.loop.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3, $r4, $r12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $lr = tMOVr $r12, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg + ; CHECK-NEXT: MVE_VPST 4, implicit $vpr + ; CHECK-NEXT: renamable $r0, renamable $q0 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.a, align 4) + ; CHECK-NEXT: renamable $r1, renamable $q1 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.b, align 4) + ; CHECK-NEXT: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r12 = t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $q1 = MVE_VCLZs32 killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1 + ; CHECK-NEXT: renamable $q0 = MVE_VQSHRUNs32th killed renamable $q0, killed renamable $q1, 3, 0, $noreg, $noreg + ; CHECK-NEXT: MVE_VPST 8, implicit $vpr + ; CHECK-NEXT: renamable $r2 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r2, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.addr.c, align 4) + ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.exit: + ; CHECK-NEXT: liveins: $r4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def dead $r7, def $pc bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $r3, $r7, $lr diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/disjoint-vcmp.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/disjoint-vcmp.mir index d71a8299db1a8..d8c9aeda0c9e5 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/disjoint-vcmp.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/disjoint-vcmp.mir @@ -120,51 +120,57 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: test ; CHECK: bb.0.bb: - ; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r7 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 16 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -12 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -16 - ; CHECK: $sp = frame-setup tSUBspi $sp, 1, 14 /* CC::al */, $noreg - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 20 - ; CHECK: tCBZ $r2, %bb.3 - ; CHECK: bb.1.bb3: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: $r12 = t2MOVi16 target-flags(arm-lo16) @mask, 14 /* CC::al */, $noreg - ; CHECK: renamable $r4, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg - ; CHECK: $r12 = t2MOVTi16 killed $r12, target-flags(arm-hi16) @mask, 14 /* CC::al */, $noreg - ; CHECK: renamable $r4 = t2BICri killed renamable $r4, 3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r5 = t2LDRHi12 killed renamable $r12, 0, 14 /* CC::al */, $noreg :: (dereferenceable load (s16) from %ir.mask.gep9) - ; CHECK: renamable $r12 = t2SUBri killed renamable $r4, 4, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg - ; CHECK: $vpr = VMSR_P0 $r5, 14 /* CC::al */, $noreg - ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r4, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 16, 14 /* CC::al */, $noreg, $noreg - ; CHECK: VSTR_P0_off killed renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0) - ; CHECK: renamable $q0 = MVE_VDUP32 killed renamable $r5, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: $r3 = tMOVr $r0, 14 /* CC::al */, $noreg - ; CHECK: bb.2.bb9: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r12 - ; CHECK: renamable $vpr = VLDR_P0_off $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0) - ; CHECK: MVE_VPST 2, implicit $vpr - ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr, $noreg - ; CHECK: renamable $r1, renamable $q1 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv24, align 4) - ; CHECK: renamable $r3, renamable $q2 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1, align 4) - ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg - ; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1 - ; CHECK: renamable $r12, renamable $q2 = MVE_VLDRWU32_pre killed renamable $r12, 16, 0, $noreg, $noreg :: (load (s128) from %ir.scevgep2, align 8) - ; CHECK: MVE_VPTv4u32 8, renamable $q0, killed renamable $q2, 2, implicit-def $vpr - ; CHECK: MVE_VSTRWU32 killed renamable $q1, killed renamable $r0, 0, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv1, align 4) - ; CHECK: $r0 = tMOVr $r3, 14 /* CC::al */, $noreg - ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 - ; CHECK: bb.3.bb27: - ; CHECK: $sp = tADDspi $sp, 1, 14 /* CC::al */, $noreg - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r7, def $pc + ; CHECK-NEXT: successors: %bb.3(0x30000000), %bb.1(0x50000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r5, -12 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -16 + ; CHECK-NEXT: $sp = frame-setup tSUBspi $sp, 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 20 + ; CHECK-NEXT: tCBZ $r2, %bb.3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.bb3: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $r12 = t2MOVi16 target-flags(arm-lo16) @mask, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r4, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $r12 = t2MOVTi16 killed $r12, target-flags(arm-hi16) @mask, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r4 = t2BICri killed renamable $r4, 3, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r5 = t2LDRHi12 killed renamable $r12, 0, 14 /* CC::al */, $noreg :: (dereferenceable load (s16) from %ir.mask.gep9) + ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r4, 4, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r4, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $vpr = VMSR_P0 $r5, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $lr = nuw nsw t2ADDrs killed renamable $r4, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r3, 16, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: VSTR_P0_off killed renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0) + ; CHECK-NEXT: renamable $q0 = MVE_VDUP32 killed renamable $r5, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: $r3 = tMOVr $r0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.bb9: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $vpr = VLDR_P0_off $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0) + ; CHECK-NEXT: MVE_VPST 2, implicit $vpr + ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr, $noreg + ; CHECK-NEXT: renamable $r1, renamable $q1 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv24, align 4) + ; CHECK-NEXT: renamable $r3, renamable $q2 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1, align 4) + ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1 + ; CHECK-NEXT: renamable $r12, renamable $q2 = MVE_VLDRWU32_pre killed renamable $r12, 16, 0, $noreg, $noreg :: (load (s128) from %ir.scevgep2, align 8) + ; CHECK-NEXT: MVE_VPTv4u32 8, renamable $q0, killed renamable $q2, 2, implicit-def $vpr + ; CHECK-NEXT: MVE_VSTRWU32 killed renamable $q1, killed renamable $r0, 0, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv1, align 4) + ; CHECK-NEXT: $r0 = tMOVr $r3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.bb27: + ; CHECK-NEXT: $sp = tADDspi $sp, 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r7, def $pc bb.0.bb: successors: %bb.3(0x30000000), %bb.1(0x50000000) liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r7, $lr diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update.mir index 56bb50a43ab29..7f046a376ddba 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update.mir @@ -104,40 +104,46 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: use_before_def ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r7 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7 - ; CHECK: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 11, 8, implicit-def $itstate - ; CHECK: tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate - ; CHECK: bb.1.vector.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: renamable $r12 = t2ADDri renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r12 = t2BICri killed renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg - ; CHECK: bb.2.vector.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 - ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg - ; CHECK: MVE_VPST 4, implicit $vpr - ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $lr :: (load (s128) from %ir.lsr.iv13, align 4) - ; CHECK: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 1, renamable $vpr, $lr :: (load (s128) from %ir.lsr.iv1416, align 4) - ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg - ; CHECK: renamable $q0 = nsw MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $lr, undef renamable $q0 - ; CHECK: MVE_VPST 8, implicit $vpr - ; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $lr :: (store (s128) into %ir.lsr.iv1719, align 4) - ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg - ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 - ; CHECK: bb.3.for.cond.cleanup: - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $r7 + ; CHECK-NEXT: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: t2IT 11, 8, implicit-def $itstate + ; CHECK-NEXT: tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.vector.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r12 = t2ADDri renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r12 = t2BICri killed renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.vector.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg + ; CHECK-NEXT: MVE_VPST 4, implicit $vpr + ; CHECK-NEXT: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $lr :: (load (s128) from %ir.lsr.iv13, align 4) + ; CHECK-NEXT: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 1, renamable $vpr, $lr :: (load (s128) from %ir.lsr.iv1416, align 4) + ; CHECK-NEXT: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $q0 = nsw MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $lr, undef renamable $q0 + ; CHECK-NEXT: MVE_VPST 8, implicit $vpr + ; CHECK-NEXT: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $lr :: (store (s128) into %ir.lsr.iv1719, align 4) + ; CHECK-NEXT: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.for.cond.cleanup: + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $r3, $r7, $lr diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir index 4f667a549f3f5..9ebb714bc4eea 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir @@ -39,13 +39,10 @@ br label %for.body } - ; Function Attrs: nounwind declare i32 @llvm.arm.space(i32 immarg, i32) #0 - ; Function Attrs: noduplicate nounwind declare i32 @llvm.start.loop.iterations.i32(i32) #1 - ; Function Attrs: noduplicate nounwind declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #1 attributes #0 = { nounwind } @@ -125,56 +122,62 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: size_limit ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.3(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r7 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: $sp = frame-setup tSUBspi $sp, 8, 14 /* CC::al */, $noreg - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 40 - ; CHECK: dead $lr = tMOVr renamable $r3, 14 /* CC::al */, $noreg - ; CHECK: renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 4, 14 /* CC::al */, $noreg - ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg - ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg - ; CHECK: tSTRspi killed $r1, $sp, 7, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0) - ; CHECK: tSTRspi killed $r2, $sp, 6, 14 /* CC::al */, $noreg :: (store (s32) into %stack.1) - ; CHECK: tSTRspi killed $r0, $sp, 5, 14 /* CC::al */, $noreg :: (store (s32) into %stack.2) - ; CHECK: tSTRspi killed $r3, $sp, 4, 14 /* CC::al */, $noreg :: (store (s32) into %stack.3) - ; CHECK: tB %bb.3, 14 /* CC::al */, $noreg - ; CHECK: bb.1.for.body: - ; CHECK: successors: %bb.3(0x40000000), %bb.2(0x40000000) - ; CHECK: $r0 = tLDRspi $sp, 3, 14 /* CC::al */, $noreg :: (load (s32) from %stack.4) - ; CHECK: renamable $r1, renamable $r0 = t2LDR_PRE killed renamable $r0, 4, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep11) - ; CHECK: $r2 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg :: (load (s32) from %stack.5) - ; CHECK: renamable $r3, renamable $r2 = t2LDR_PRE killed renamable $r2, 4, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep7) - ; CHECK: renamable $r1, dead $cpsr = nsw tMUL killed renamable $r3, killed renamable $r1, 14 /* CC::al */, $noreg - ; CHECK: $r3 = tLDRspi $sp, 1, 14 /* CC::al */, $noreg :: (load (s32) from %stack.6) - ; CHECK: early-clobber renamable $r3 = t2STR_PRE killed renamable $r1, killed renamable $r3, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.scevgep3) - ; CHECK: $r1 = tLDRspi $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.7) - ; CHECK: $lr = tMOVr killed $r1, 14 /* CC::al */, $noreg - ; CHECK: renamable $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, def $cpsr - ; CHECK: $r12 = tMOVr killed $lr, 14 /* CC::al */, $noreg - ; CHECK: tSTRspi killed $r0, $sp, 7, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0) - ; CHECK: tSTRspi killed $r2, $sp, 6, 14 /* CC::al */, $noreg :: (store (s32) into %stack.1) - ; CHECK: tSTRspi killed $r3, $sp, 5, 14 /* CC::al */, $noreg :: (store (s32) into %stack.2) - ; CHECK: t2STRi12 killed $r12, $sp, 16, 14 /* CC::al */, $noreg :: (store (s32) into %stack.3) - ; CHECK: tBcc %bb.3, 1 /* CC::ne */, killed $cpsr - ; CHECK: tB %bb.2, 14 /* CC::al */, $noreg - ; CHECK: bb.2.for.cond.cleanup: - ; CHECK: $sp = tADDspi $sp, 8, 14 /* CC::al */, $noreg - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc - ; CHECK: bb.3.for.header: - ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: $r0 = tLDRspi $sp, 4, 14 /* CC::al */, $noreg :: (load (s32) from %stack.3) - ; CHECK: $r1 = tLDRspi $sp, 5, 14 /* CC::al */, $noreg :: (load (s32) from %stack.2) - ; CHECK: $r2 = tLDRspi $sp, 6, 14 /* CC::al */, $noreg :: (load (s32) from %stack.1) - ; CHECK: $r3 = tLDRspi $sp, 7, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0) - ; CHECK: tSTRspi killed $r0, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.7) - ; CHECK: tSTRspi killed $r1, $sp, 1, 14 /* CC::al */, $noreg :: (store (s32) into %stack.6) - ; CHECK: tSTRspi killed $r2, $sp, 2, 14 /* CC::al */, $noreg :: (store (s32) into %stack.5) - ; CHECK: tSTRspi killed $r3, $sp, 3, 14 /* CC::al */, $noreg :: (store (s32) into %stack.4) - ; CHECK: tB %bb.1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: successors: %bb.3(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: $sp = frame-setup tSUBspi $sp, 8, 14 /* CC::al */, $noreg + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 40 + ; CHECK-NEXT: dead $lr = tMOVr renamable $r3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: tSTRspi killed $r1, $sp, 7, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0) + ; CHECK-NEXT: tSTRspi killed $r2, $sp, 6, 14 /* CC::al */, $noreg :: (store (s32) into %stack.1) + ; CHECK-NEXT: tSTRspi killed $r0, $sp, 5, 14 /* CC::al */, $noreg :: (store (s32) into %stack.2) + ; CHECK-NEXT: tSTRspi killed $r3, $sp, 4, 14 /* CC::al */, $noreg :: (store (s32) into %stack.3) + ; CHECK-NEXT: tB %bb.3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.for.body: + ; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $r0 = tLDRspi $sp, 3, 14 /* CC::al */, $noreg :: (load (s32) from %stack.4) + ; CHECK-NEXT: renamable $r1, renamable $r0 = t2LDR_PRE killed renamable $r0, 4, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep11) + ; CHECK-NEXT: $r2 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg :: (load (s32) from %stack.5) + ; CHECK-NEXT: renamable $r3, renamable $r2 = t2LDR_PRE killed renamable $r2, 4, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep7) + ; CHECK-NEXT: renamable $r1, dead $cpsr = nsw tMUL killed renamable $r3, killed renamable $r1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $r3 = tLDRspi $sp, 1, 14 /* CC::al */, $noreg :: (load (s32) from %stack.6) + ; CHECK-NEXT: early-clobber renamable $r3 = t2STR_PRE killed renamable $r1, killed renamable $r3, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.scevgep3) + ; CHECK-NEXT: $r1 = tLDRspi $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.7) + ; CHECK-NEXT: $lr = tMOVr killed $r1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, def $cpsr + ; CHECK-NEXT: $r12 = tMOVr killed $lr, 14 /* CC::al */, $noreg + ; CHECK-NEXT: tSTRspi killed $r0, $sp, 7, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0) + ; CHECK-NEXT: tSTRspi killed $r2, $sp, 6, 14 /* CC::al */, $noreg :: (store (s32) into %stack.1) + ; CHECK-NEXT: tSTRspi killed $r3, $sp, 5, 14 /* CC::al */, $noreg :: (store (s32) into %stack.2) + ; CHECK-NEXT: t2STRi12 killed $r12, $sp, 16, 14 /* CC::al */, $noreg :: (store (s32) into %stack.3) + ; CHECK-NEXT: tBcc %bb.3, 1 /* CC::ne */, killed $cpsr + ; CHECK-NEXT: tB %bb.2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.for.cond.cleanup: + ; CHECK-NEXT: $sp = tADDspi $sp, 8, 14 /* CC::al */, $noreg + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.for.header: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $r0 = tLDRspi $sp, 4, 14 /* CC::al */, $noreg :: (load (s32) from %stack.3) + ; CHECK-NEXT: $r1 = tLDRspi $sp, 5, 14 /* CC::al */, $noreg :: (load (s32) from %stack.2) + ; CHECK-NEXT: $r2 = tLDRspi $sp, 6, 14 /* CC::al */, $noreg :: (load (s32) from %stack.1) + ; CHECK-NEXT: $r3 = tLDRspi $sp, 7, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0) + ; CHECK-NEXT: tSTRspi killed $r0, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.7) + ; CHECK-NEXT: tSTRspi killed $r1, $sp, 1, 14 /* CC::al */, $noreg :: (store (s32) into %stack.6) + ; CHECK-NEXT: tSTRspi killed $r2, $sp, 2, 14 /* CC::al */, $noreg :: (store (s32) into %stack.5) + ; CHECK-NEXT: tSTRspi killed $r3, $sp, 3, 14 /* CC::al */, $noreg :: (store (s32) into %stack.4) + ; CHECK-NEXT: tB %bb.1, 14 /* CC::al */, $noreg bb.0.entry: successors: %bb.3(0x80000000) liveins: $r0, $r1, $r2, $r3, $r7, $lr diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/extract-element.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/extract-element.mir index 6955007957f4e..44bcaba4e3fd9 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/extract-element.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/extract-element.mir @@ -105,33 +105,40 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: no_vpsel_liveout ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 - ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 0, 4, implicit-def $itstate - ; CHECK: renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate - ; CHECK: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate - ; CHECK: bb.1.vector.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2 - ; CHECK: bb.2.vector.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $lr, $q0, $r0, $r1 - ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 0, $noreg, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) - ; CHECK: renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 0, killed $noreg, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2) - ; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1 - ; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 - ; CHECK: bb.3.middle.block: - ; CHECK: liveins: $q0 - ; CHECK: $r0 = VMOVRS killed $s3, 14 /* CC::al */, $noreg, implicit killed $q0 - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: t2IT 0, 4, implicit-def $itstate + ; CHECK-NEXT: renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate + ; CHECK-NEXT: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.vector.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.vector.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $lr, $q0, $r0, $r1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 0, $noreg, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) + ; CHECK-NEXT: renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 0, killed $noreg, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2) + ; CHECK-NEXT: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1 + ; CHECK-NEXT: renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.middle.block: + ; CHECK-NEXT: liveins: $q0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $r0 = VMOVRS killed $s3, 14 /* CC::al */, $noreg, implicit killed $q0 + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $lr, $r7 diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-16.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-16.mir index 4d3f0ac5f92d2..b7275f8b5ab6a 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-16.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-16.mir @@ -96,37 +96,43 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: incorrect_sub_16 ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r7 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 11, 8, implicit-def $itstate - ; CHECK: tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate - ; CHECK: bb.1.vector.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: renamable $r12 = t2ADDri renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r12 = t2BICri killed renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg - ; CHECK: bb.2.vector.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 - ; CHECK: renamable $vpr = MVE_VCTP16 renamable $r3, 0, $noreg, $noreg - ; CHECK: MVE_VPST 4, implicit $vpr - ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv13, align 4) - ; CHECK: renamable $r2, renamable $q1 = MVE_VLDRHU16_post killed renamable $r2, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1416, align 4) - ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 7, 14 /* CC::al */, $noreg - ; CHECK: renamable $q0 = nsw MVE_VADDi16 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: MVE_VPST 8, implicit $vpr - ; CHECK: renamable $r0 = MVE_VSTRHU16_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv1719, align 4) - ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 - ; CHECK: bb.3.for.cond.cleanup: - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: t2IT 11, 8, implicit-def $itstate + ; CHECK-NEXT: tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.vector.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r12 = t2ADDri renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r12 = t2BICri killed renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.vector.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $vpr = MVE_VCTP16 renamable $r3, 0, $noreg, $noreg + ; CHECK-NEXT: MVE_VPST 4, implicit $vpr + ; CHECK-NEXT: renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv13, align 4) + ; CHECK-NEXT: renamable $r2, renamable $q1 = MVE_VLDRHU16_post killed renamable $r2, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1416, align 4) + ; CHECK-NEXT: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 7, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $q0 = nsw MVE_VADDi16 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: MVE_VPST 8, implicit $vpr + ; CHECK-NEXT: renamable $r0 = MVE_VSTRHU16_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv1719, align 4) + ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.for.cond.cleanup: + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $r3, $r7, $lr diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-32.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-32.mir index 7ea07bd639560..a8cbeb13a01dd 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-32.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-32.mir @@ -104,37 +104,43 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: incorrect_sub_32 ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r7 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 11, 8, implicit-def $itstate - ; CHECK: tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate - ; CHECK: bb.1.vector.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: renamable $r12 = t2ADDri renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r12 = t2BICri killed renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg - ; CHECK: bb.2.vector.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 - ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg - ; CHECK: MVE_VPST 4, implicit $vpr - ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv13, align 4) - ; CHECK: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1416, align 4) - ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 5, 14 /* CC::al */, $noreg - ; CHECK: renamable $q0 = nsw MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: MVE_VPST 8, implicit $vpr - ; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv1719, align 4) - ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 - ; CHECK: bb.3.for.cond.cleanup: - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: t2IT 11, 8, implicit-def $itstate + ; CHECK-NEXT: tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.vector.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r12 = t2ADDri renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r12 = t2BICri killed renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.vector.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg + ; CHECK-NEXT: MVE_VPST 4, implicit $vpr + ; CHECK-NEXT: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv13, align 4) + ; CHECK-NEXT: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1416, align 4) + ; CHECK-NEXT: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 5, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $q0 = nsw MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: MVE_VPST 8, implicit $vpr + ; CHECK-NEXT: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv1719, align 4) + ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.for.cond.cleanup: + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $r3, $r7, $lr diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-8.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-8.mir index eb578318c3ac8..4d892751115de 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-8.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-8.mir @@ -97,37 +97,43 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: incorrect_sub_8 ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r7 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 11, 8, implicit-def $itstate - ; CHECK: tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate - ; CHECK: bb.1.vector.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: renamable $r12 = t2ADDri renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r12 = t2BICri killed renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg - ; CHECK: bb.2.vector.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 - ; CHECK: renamable $vpr = MVE_VCTP8 renamable $r3, 0, $noreg, $noreg - ; CHECK: MVE_VPST 4, implicit $vpr - ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRBU8_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv13, align 4) - ; CHECK: renamable $r2, renamable $q1 = MVE_VLDRBU8_post killed renamable $r2, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1416, align 4) - ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 15, 14 /* CC::al */, $noreg - ; CHECK: renamable $q0 = nsw MVE_VADDi8 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: MVE_VPST 8, implicit $vpr - ; CHECK: renamable $r0 = MVE_VSTRBU8_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv1719, align 4) - ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 - ; CHECK: bb.3.for.cond.cleanup: - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: t2IT 11, 8, implicit-def $itstate + ; CHECK-NEXT: tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.vector.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r12 = t2ADDri renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r12 = t2BICri killed renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.vector.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $vpr = MVE_VCTP8 renamable $r3, 0, $noreg, $noreg + ; CHECK-NEXT: MVE_VPST 4, implicit $vpr + ; CHECK-NEXT: renamable $r1, renamable $q0 = MVE_VLDRBU8_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv13, align 4) + ; CHECK-NEXT: renamable $r2, renamable $q1 = MVE_VLDRBU8_post killed renamable $r2, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1416, align 4) + ; CHECK-NEXT: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 15, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $q0 = nsw MVE_VADDi8 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: MVE_VPST 8, implicit $vpr + ; CHECK-NEXT: renamable $r0 = MVE_VSTRBU8_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv1719, align 4) + ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.for.cond.cleanup: + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $r3, $r7, $lr diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-1.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-1.mir index d9b8ca242ee63..d364b56749cb7 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-1.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-1.mir @@ -130,51 +130,57 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: inloop_vpnot ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r7 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 16 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -12 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -16 - ; CHECK: renamable $r12 = t2LDRi12 $sp, 20, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.1) - ; CHECK: t2CMPri renamable $r12, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: tBcc %bb.3, 0 /* CC::eq */, killed $cpsr - ; CHECK: bb.1.vector.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3, $r12 - ; CHECK: renamable $lr = t2ADDri renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $lr = t2BICri killed renamable $lr, 3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r5 = tLDRspi $sp, 4, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8) - ; CHECK: renamable $lr = t2SUBri killed renamable $lr, 4, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r4, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $r4 = tMOVr killed $lr, 14 /* CC::al */, $noreg - ; CHECK: bb.2.vector.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r12 - ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg, $noreg - ; CHECK: MVE_VPST 4, implicit $vpr - ; CHECK: renamable $r3, renamable $q1 = MVE_VLDRHS32_post killed renamable $r3, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17.d, align 2) - ; CHECK: renamable $r2, renamable $q2 = MVE_VLDRHS32_post killed renamable $r2, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820.c, align 2) - ; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1 - ; CHECK: MVE_VPST 4, implicit $vpr - ; CHECK: renamable $r0, renamable $q2 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) - ; CHECK: renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2) - ; CHECK: renamable $q2 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, $noreg, undef renamable $q2 - ; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg - ; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1 - ; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg, $noreg - ; CHECK: MVE_VPST 8, implicit $vpr - ; CHECK: renamable $r5 = MVE_VSTRWU32_post renamable $q0, killed renamable $r5, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.cast.e, align 4) - ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 - ; CHECK: bb.3.for.cond.cleanup: - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r7, def $pc + ; CHECK-NEXT: successors: %bb.3(0x30000000), %bb.1(0x50000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r5, -12 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -16 + ; CHECK-NEXT: renamable $r12 = t2LDRi12 $sp, 20, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.1) + ; CHECK-NEXT: t2CMPri renamable $r12, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: tBcc %bb.3, 0 /* CC::eq */, killed $cpsr + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.vector.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3, $r12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $lr = t2ADDri renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r4, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $lr = t2BICri killed renamable $lr, 3, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r5 = tLDRspi $sp, 4, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8) + ; CHECK-NEXT: renamable $lr = t2SUBri killed renamable $lr, 4, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: renamable $lr = nuw nsw t2ADDrs killed renamable $r4, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: $r4 = tMOVr killed $lr, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.vector.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg, $noreg + ; CHECK-NEXT: MVE_VPST 4, implicit $vpr + ; CHECK-NEXT: renamable $r3, renamable $q1 = MVE_VLDRHS32_post killed renamable $r3, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17.d, align 2) + ; CHECK-NEXT: renamable $r2, renamable $q2 = MVE_VLDRHS32_post killed renamable $r2, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820.c, align 2) + ; CHECK-NEXT: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1 + ; CHECK-NEXT: MVE_VPST 4, implicit $vpr + ; CHECK-NEXT: renamable $r0, renamable $q2 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) + ; CHECK-NEXT: renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2) + ; CHECK-NEXT: renamable $q2 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, $noreg, undef renamable $q2 + ; CHECK-NEXT: $lr = tMOVr $r4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1 + ; CHECK-NEXT: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg, $noreg + ; CHECK-NEXT: MVE_VPST 8, implicit $vpr + ; CHECK-NEXT: renamable $r5 = MVE_VSTRWU32_post renamable $q0, killed renamable $r5, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.cast.e, align 4) + ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.for.cond.cleanup: + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r7, def $pc bb.0.entry: successors: %bb.3(0x30000000), %bb.1(0x50000000) liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r7, $lr diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-2.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-2.mir index 92d59989d955d..466feba059dc0 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-2.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-2.mir @@ -130,51 +130,57 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: inloop_vpnot ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r7 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 16 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -12 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -16 - ; CHECK: renamable $r12 = t2LDRi12 $sp, 20, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.1) - ; CHECK: t2CMPri renamable $r12, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: tBcc %bb.3, 0 /* CC::eq */, killed $cpsr - ; CHECK: bb.1.vector.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3, $r12 - ; CHECK: renamable $lr = t2ADDri renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $lr = t2BICri killed renamable $lr, 3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r5 = tLDRspi $sp, 4, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8) - ; CHECK: renamable $lr = t2SUBri killed renamable $lr, 4, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r4, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $r4 = tMOVr killed $lr, 14 /* CC::al */, $noreg - ; CHECK: bb.2.vector.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r12 - ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg, $noreg - ; CHECK: MVE_VPST 4, implicit $vpr - ; CHECK: renamable $r3, renamable $q1 = MVE_VLDRHS32_post killed renamable $r3, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17.d, align 2) - ; CHECK: renamable $r2, renamable $q2 = MVE_VLDRHS32_post killed renamable $r2, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820.c, align 2) - ; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1 - ; CHECK: MVE_VPST 4, implicit $vpr - ; CHECK: renamable $r0, renamable $q2 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) - ; CHECK: renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2) - ; CHECK: renamable $q2 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, $noreg, undef renamable $q2 - ; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg - ; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1 - ; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: MVE_VPST 4, implicit $vpr - ; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, killed renamable $vpr, $noreg - ; CHECK: renamable $r5 = MVE_VSTRWU32_post renamable $q0, killed renamable $r5, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.cast.e, align 4) - ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 - ; CHECK: bb.3.for.cond.cleanup: - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r7, def $pc + ; CHECK-NEXT: successors: %bb.3(0x30000000), %bb.1(0x50000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r5, -12 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -16 + ; CHECK-NEXT: renamable $r12 = t2LDRi12 $sp, 20, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.1) + ; CHECK-NEXT: t2CMPri renamable $r12, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: tBcc %bb.3, 0 /* CC::eq */, killed $cpsr + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.vector.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3, $r12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $lr = t2ADDri renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r4, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $lr = t2BICri killed renamable $lr, 3, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r5 = tLDRspi $sp, 4, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8) + ; CHECK-NEXT: renamable $lr = t2SUBri killed renamable $lr, 4, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: renamable $lr = nuw nsw t2ADDrs killed renamable $r4, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: $r4 = tMOVr killed $lr, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.vector.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg, $noreg + ; CHECK-NEXT: MVE_VPST 4, implicit $vpr + ; CHECK-NEXT: renamable $r3, renamable $q1 = MVE_VLDRHS32_post killed renamable $r3, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17.d, align 2) + ; CHECK-NEXT: renamable $r2, renamable $q2 = MVE_VLDRHS32_post killed renamable $r2, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820.c, align 2) + ; CHECK-NEXT: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1 + ; CHECK-NEXT: MVE_VPST 4, implicit $vpr + ; CHECK-NEXT: renamable $r0, renamable $q2 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) + ; CHECK-NEXT: renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2) + ; CHECK-NEXT: renamable $q2 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, $noreg, undef renamable $q2 + ; CHECK-NEXT: $lr = tMOVr $r4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1 + ; CHECK-NEXT: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: MVE_VPST 4, implicit $vpr + ; CHECK-NEXT: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, killed renamable $vpr, $noreg + ; CHECK-NEXT: renamable $r5 = MVE_VSTRWU32_post renamable $q0, killed renamable $r5, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.cast.e, align 4) + ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.for.cond.cleanup: + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r7, def $pc bb.0.entry: successors: %bb.3(0x30000000), %bb.1(0x50000000) liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r7, $lr diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-3.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-3.mir index 2a8aa845a06b7..699629049a16e 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-3.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-3.mir @@ -130,51 +130,57 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: inloop_vpnot ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r7 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 16 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -12 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -16 - ; CHECK: renamable $r12 = t2LDRi12 $sp, 20, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.1) - ; CHECK: t2CMPri renamable $r12, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: tBcc %bb.3, 0 /* CC::eq */, killed $cpsr - ; CHECK: bb.1.vector.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3, $r12 - ; CHECK: renamable $lr = t2ADDri renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $lr = t2BICri killed renamable $lr, 3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r5 = tLDRspi $sp, 4, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8) - ; CHECK: renamable $lr = t2SUBri killed renamable $lr, 4, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r4, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $r4 = tMOVr killed $lr, 14 /* CC::al */, $noreg - ; CHECK: bb.2.vector.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r12 - ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg, $noreg - ; CHECK: MVE_VPST 4, implicit $vpr - ; CHECK: renamable $r3, renamable $q1 = MVE_VLDRHS32_post killed renamable $r3, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17.d, align 2) - ; CHECK: renamable $r2, renamable $q2 = MVE_VLDRHS32_post killed renamable $r2, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820.c, align 2) - ; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1 - ; CHECK: MVE_VPST 4, implicit $vpr - ; CHECK: renamable $r0, renamable $q2 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) - ; CHECK: renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2) - ; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg - ; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg - ; CHECK: MVE_VPST 2, implicit $vpr - ; CHECK: renamable $q2 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, $noreg, undef renamable $q2 - ; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, renamable $vpr, $noreg, undef renamable $q1 - ; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, renamable $vpr, $noreg, undef renamable $q0 - ; CHECK: renamable $r5 = MVE_VSTRWU32_post renamable $q0, killed renamable $r5, 16, 1, renamable $vpr, $noreg :: (store (s128) into %ir.lsr.cast.e, align 4) - ; CHECK: dead renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg, $noreg - ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 - ; CHECK: bb.3.for.cond.cleanup: - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r7, def $pc + ; CHECK-NEXT: successors: %bb.3(0x30000000), %bb.1(0x50000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r5, -12 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -16 + ; CHECK-NEXT: renamable $r12 = t2LDRi12 $sp, 20, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.1) + ; CHECK-NEXT: t2CMPri renamable $r12, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: tBcc %bb.3, 0 /* CC::eq */, killed $cpsr + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.vector.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3, $r12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $lr = t2ADDri renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r4, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $lr = t2BICri killed renamable $lr, 3, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r5 = tLDRspi $sp, 4, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8) + ; CHECK-NEXT: renamable $lr = t2SUBri killed renamable $lr, 4, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: renamable $lr = nuw nsw t2ADDrs killed renamable $r4, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: $r4 = tMOVr killed $lr, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.vector.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg, $noreg + ; CHECK-NEXT: MVE_VPST 4, implicit $vpr + ; CHECK-NEXT: renamable $r3, renamable $q1 = MVE_VLDRHS32_post killed renamable $r3, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17.d, align 2) + ; CHECK-NEXT: renamable $r2, renamable $q2 = MVE_VLDRHS32_post killed renamable $r2, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820.c, align 2) + ; CHECK-NEXT: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1 + ; CHECK-NEXT: MVE_VPST 4, implicit $vpr + ; CHECK-NEXT: renamable $r0, renamable $q2 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) + ; CHECK-NEXT: renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2) + ; CHECK-NEXT: $lr = tMOVr $r4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: MVE_VPST 2, implicit $vpr + ; CHECK-NEXT: renamable $q2 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, $noreg, undef renamable $q2 + ; CHECK-NEXT: renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, renamable $vpr, $noreg, undef renamable $q1 + ; CHECK-NEXT: renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, renamable $vpr, $noreg, undef renamable $q0 + ; CHECK-NEXT: renamable $r5 = MVE_VSTRWU32_post renamable $q0, killed renamable $r5, 16, 1, renamable $vpr, $noreg :: (store (s128) into %ir.lsr.cast.e, align 4) + ; CHECK-NEXT: dead renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg, $noreg + ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.for.cond.cleanup: + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r7, def $pc bb.0.entry: successors: %bb.3(0x30000000), %bb.1(0x50000000) liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r7, $lr diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpsel-1.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpsel-1.mir index 46a011d2e3003..195154c61083f 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpsel-1.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpsel-1.mir @@ -128,54 +128,62 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: vpsel_after_vpt ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.4(0x30000000), %bb.1(0x50000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r7 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 16 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -12 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -16 - ; CHECK: renamable $r12 = t2LDRi12 $sp, 16, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8) - ; CHECK: t2CMPri renamable $r12, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: tBcc %bb.4, 0 /* CC::eq */, killed $cpsr - ; CHECK: bb.1.vector.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3, $r12 - ; CHECK: renamable $lr = t2ADDri renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $lr = t2BICri killed renamable $lr, 3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: renamable $lr = t2SUBri killed renamable $lr, 4, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r5 = nuw nsw t2ADDrs killed renamable $r4, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg - ; CHECK: dead $lr = t2DLS renamable $r5 - ; CHECK: $r4 = tMOVr killed $r5, 14 /* CC::al */, $noreg - ; CHECK: bb.2.vector.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $q0, $r0, $r1, $r2, $r3, $r4, $r12 - ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg, $noreg - ; CHECK: MVE_VPST 4, implicit $vpr - ; CHECK: renamable $r3, renamable $q1 = MVE_VLDRHS32_post killed renamable $r3, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17.d, align 2) - ; CHECK: renamable $r2, renamable $q2 = MVE_VLDRHS32_post killed renamable $r2, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820.c, align 2) - ; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1 - ; CHECK: MVE_VPST 4, implicit $vpr - ; CHECK: renamable $r0, renamable $q2 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) - ; CHECK: renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2) - ; CHECK: renamable $q2 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, $noreg, undef renamable $q2 - ; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg - ; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1 - ; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1 - ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr, $noreg - ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 - ; CHECK: bb.3.middle.block: - ; CHECK: liveins: $q0 - ; CHECK: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0 - ; CHECK: bb.4: - ; CHECK: renamable $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0 + ; CHECK-NEXT: successors: %bb.4(0x30000000), %bb.1(0x50000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r5, -12 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -16 + ; CHECK-NEXT: renamable $r12 = t2LDRi12 $sp, 16, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8) + ; CHECK-NEXT: t2CMPri renamable $r12, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: tBcc %bb.4, 0 /* CC::eq */, killed $cpsr + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.vector.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3, $r12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $lr = t2ADDri renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r4, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $lr = t2BICri killed renamable $lr, 3, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: renamable $lr = t2SUBri killed renamable $lr, 4, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r5 = nuw nsw t2ADDrs killed renamable $r4, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: dead $lr = t2DLS renamable $r5 + ; CHECK-NEXT: $r4 = tMOVr killed $r5, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.vector.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $q0, $r0, $r1, $r2, $r3, $r4, $r12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg, $noreg + ; CHECK-NEXT: MVE_VPST 4, implicit $vpr + ; CHECK-NEXT: renamable $r3, renamable $q1 = MVE_VLDRHS32_post killed renamable $r3, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17.d, align 2) + ; CHECK-NEXT: renamable $r2, renamable $q2 = MVE_VLDRHS32_post killed renamable $r2, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820.c, align 2) + ; CHECK-NEXT: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1 + ; CHECK-NEXT: MVE_VPST 4, implicit $vpr + ; CHECK-NEXT: renamable $r0, renamable $q2 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) + ; CHECK-NEXT: renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2) + ; CHECK-NEXT: renamable $q2 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, $noreg, undef renamable $q2 + ; CHECK-NEXT: $lr = tMOVr $r4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1 + ; CHECK-NEXT: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1 + ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr, $noreg + ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.middle.block: + ; CHECK-NEXT: liveins: $q0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4: + ; CHECK-NEXT: renamable $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0 bb.0.entry: successors: %bb.4(0x30000000), %bb.1(0x50000000) liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r7, $lr diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpsel-2.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpsel-2.mir index dd9fc35b54e16..724567f86bdea 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpsel-2.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpsel-2.mir @@ -130,53 +130,61 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: vpsel_after_vpt ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.4(0x30000000), %bb.1(0x50000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r7 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 16 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -12 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -16 - ; CHECK: renamable $r12 = t2LDRi12 $sp, 16, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8) - ; CHECK: t2CMPri renamable $r12, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: tBcc %bb.4, 0 /* CC::eq */, killed $cpsr - ; CHECK: bb.1.vector.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3, $r12 - ; CHECK: renamable $lr = t2ADDri renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $lr = t2BICri killed renamable $lr, 3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: renamable $lr = t2SUBri killed renamable $lr, 4, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r5 = nuw nsw t2ADDrs killed renamable $r4, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg - ; CHECK: dead $lr = t2DLS renamable $r5 - ; CHECK: $r4 = tMOVr killed $r5, 14 /* CC::al */, $noreg - ; CHECK: bb.2.vector.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $q0, $r0, $r1, $r2, $r3, $r4, $r12 - ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg, $noreg - ; CHECK: MVE_VPST 2, implicit $vpr - ; CHECK: renamable $r3, renamable $q1 = MVE_VLDRHS32_post killed renamable $r3, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17.d, align 2) - ; CHECK: renamable $r2, renamable $q2 = MVE_VLDRHS32_post killed renamable $r2, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820.c, align 2) - ; CHECK: renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2) - ; CHECK: renamable $r0, renamable $q4 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) - ; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1 - ; CHECK: renamable $q2 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q4, 0, $noreg, $noreg, undef renamable $q2 - ; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg - ; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1 - ; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1 - ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr, $noreg - ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 - ; CHECK: bb.3.middle.block: - ; CHECK: liveins: $q0 - ; CHECK: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0 - ; CHECK: bb.4: - ; CHECK: renamable $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0 + ; CHECK-NEXT: successors: %bb.4(0x30000000), %bb.1(0x50000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r5, -12 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -16 + ; CHECK-NEXT: renamable $r12 = t2LDRi12 $sp, 16, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8) + ; CHECK-NEXT: t2CMPri renamable $r12, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: tBcc %bb.4, 0 /* CC::eq */, killed $cpsr + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.vector.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3, $r12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $lr = t2ADDri renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r4, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $lr = t2BICri killed renamable $lr, 3, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: renamable $lr = t2SUBri killed renamable $lr, 4, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r5 = nuw nsw t2ADDrs killed renamable $r4, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: dead $lr = t2DLS renamable $r5 + ; CHECK-NEXT: $r4 = tMOVr killed $r5, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.vector.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $q0, $r0, $r1, $r2, $r3, $r4, $r12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg, $noreg + ; CHECK-NEXT: MVE_VPST 2, implicit $vpr + ; CHECK-NEXT: renamable $r3, renamable $q1 = MVE_VLDRHS32_post killed renamable $r3, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17.d, align 2) + ; CHECK-NEXT: renamable $r2, renamable $q2 = MVE_VLDRHS32_post killed renamable $r2, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820.c, align 2) + ; CHECK-NEXT: renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2) + ; CHECK-NEXT: renamable $r0, renamable $q4 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) + ; CHECK-NEXT: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1 + ; CHECK-NEXT: renamable $q2 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q4, 0, $noreg, $noreg, undef renamable $q2 + ; CHECK-NEXT: $lr = tMOVr $r4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1 + ; CHECK-NEXT: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1 + ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr, $noreg + ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.middle.block: + ; CHECK-NEXT: liveins: $q0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4: + ; CHECK-NEXT: renamable $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0 bb.0.entry: successors: %bb.4(0x30000000), %bb.1(0x50000000) liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r7, $lr diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/invariant-qreg.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/invariant-qreg.mir index 2890b722b6b23..7b19827a3c31f 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/invariant-qreg.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/invariant-qreg.mir @@ -155,33 +155,40 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: invariant_use_store ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: renamable $r3 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg - ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from %fixed-stack.0, align 8) - ; CHECK: tCBZ $r2, %bb.3 - ; CHECK: bb.1.vector.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $q0, $r0, $r1, $r2 - ; CHECK: renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q1 - ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2 - ; CHECK: bb.2.vector.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $lr, $q0, $q1, $r0, $r1 - ; CHECK: renamable $r0, renamable $q2 = MVE_VLDRHS32_post killed renamable $r0, 8, 0, $noreg, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) - ; CHECK: renamable $q2 = nsw MVE_VMULi32 renamable $q0, killed renamable $q2, 0, $noreg, $noreg, undef renamable $q2 - ; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1 - ; CHECK: renamable $r1 = MVE_VSTRWU32_post renamable $q1, killed renamable $r1, 16, 0, killed $noreg, $noreg :: (store (s128) into %ir.lsr.store, align 4) - ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 - ; CHECK: bb.3.exit: - ; CHECK: liveins: $q0 - ; CHECK: renamable $r0, renamable $r1 = VMOVRRD renamable $d0, 14 /* CC::al */, $noreg - ; CHECK: renamable $r2, renamable $r3 = VMOVRRD killed renamable $d1, 14 /* CC::al */, $noreg, implicit killed $q0 - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0, implicit killed $r1, implicit killed $r2, implicit killed $r3 + ; CHECK-NEXT: successors: %bb.3(0x30000000), %bb.1(0x50000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: renamable $r3 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from %fixed-stack.0, align 8) + ; CHECK-NEXT: tCBZ $r2, %bb.3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.vector.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $q0, $r0, $r1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q1 + ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.vector.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $lr, $q0, $q1, $r0, $r1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r0, renamable $q2 = MVE_VLDRHS32_post killed renamable $r0, 8, 0, $noreg, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) + ; CHECK-NEXT: renamable $q2 = nsw MVE_VMULi32 renamable $q0, killed renamable $q2, 0, $noreg, $noreg, undef renamable $q2 + ; CHECK-NEXT: renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1 + ; CHECK-NEXT: renamable $r1 = MVE_VSTRWU32_post renamable $q1, killed renamable $r1, 16, 0, killed $noreg, $noreg :: (store (s128) into %ir.lsr.store, align 4) + ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.exit: + ; CHECK-NEXT: liveins: $q0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r0, renamable $r1 = VMOVRRD renamable $d0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r2, renamable $r3 = VMOVRRD killed renamable $d1, 14 /* CC::al */, $noreg, implicit killed $q0 + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0, implicit killed $r1, implicit killed $r2, implicit killed $r3 bb.0.entry: successors: %bb.3(0x30000000), %bb.1(0x50000000) liveins: $r0, $r1, $r2, $r7, $lr @@ -262,44 +269,52 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: invariant_mul_use_reduce ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.4(0x30000000), %bb.1(0x50000000) - ; CHECK: liveins: $lr, $r0, $r2, $r7 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: tCBZ $r2, %bb.4 - ; CHECK: bb.1.vector.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r2 - ; CHECK: renamable $r1, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg - ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $r1 = t2BICri killed renamable $r1, 3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg - ; CHECK: renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r1, 19, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r1 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg - ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r1, 0, 0, $noreg, $noreg :: (load (s128) from %fixed-stack.0, align 8) - ; CHECK: dead $lr = t2DLS renamable $r3 - ; CHECK: $r1 = tMOVr killed $r3, 14 /* CC::al */, $noreg - ; CHECK: bb.2.vector.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $q0, $r0, $r1, $r2 - ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg - ; CHECK: $lr = tMOVr $r1, 14 /* CC::al */, $noreg - ; CHECK: renamable $r1, dead $cpsr = nsw tSUBi8 killed $r1, 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg - ; CHECK: MVE_VPST 8, implicit $vpr - ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) - ; CHECK: renamable $r12 = MVE_VMLADAVu32 renamable $q0, killed renamable $q1, 0, $noreg, $noreg - ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 - ; CHECK: bb.3.exit: - ; CHECK: liveins: $r12 - ; CHECK: $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 - ; CHECK: bb.4: - ; CHECK: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 + ; CHECK-NEXT: successors: %bb.4(0x30000000), %bb.1(0x50000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r2, $r7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: tCBZ $r2, %bb.4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.vector.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r1, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r1 = t2BICri killed renamable $r1, 3, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r1, 19, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r1 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $q0 = MVE_VLDRWU32 killed renamable $r1, 0, 0, $noreg, $noreg :: (load (s128) from %fixed-stack.0, align 8) + ; CHECK-NEXT: dead $lr = t2DLS renamable $r3 + ; CHECK-NEXT: $r1 = tMOVr killed $r3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.vector.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $q0, $r0, $r1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg + ; CHECK-NEXT: $lr = tMOVr $r1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r1, dead $cpsr = nsw tSUBi8 killed $r1, 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: MVE_VPST 8, implicit $vpr + ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) + ; CHECK-NEXT: renamable $r12 = MVE_VMLADAVu32 renamable $q0, killed renamable $q1, 0, $noreg, $noreg + ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.exit: + ; CHECK-NEXT: liveins: $r12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4: + ; CHECK-NEXT: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 bb.0.entry: successors: %bb.4(0x30000000), %bb.1(0x50000000) liveins: $r0, $r2, $r7, $lr @@ -380,45 +395,53 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: invariant_add_use_reduce ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.4(0x30000000), %bb.1(0x50000000) - ; CHECK: liveins: $lr, $r0, $r2, $r7 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: tCBZ $r2, %bb.4 - ; CHECK: bb.1.vector.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r2 - ; CHECK: renamable $r1, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg - ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $r1 = t2BICri killed renamable $r1, 3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg - ; CHECK: renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r1, 19, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r1 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg - ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r1, 0, 0, $noreg, $noreg :: (load (s128) from %fixed-stack.0, align 8) - ; CHECK: dead $lr = t2DLS renamable $r3 - ; CHECK: $r1 = tMOVr killed $r3, 14 /* CC::al */, $noreg - ; CHECK: bb.2.vector.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $q0, $r0, $r1, $r2 - ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg - ; CHECK: MVE_VPST 8, implicit $vpr - ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) - ; CHECK: $lr = tMOVr $r1, 14 /* CC::al */, $noreg - ; CHECK: renamable $q1 = nsw MVE_VADDi32 renamable $q0, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1 - ; CHECK: renamable $r1, dead $cpsr = nsw tSUBi8 killed $r1, 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg - ; CHECK: renamable $r12 = MVE_VADDVu32no_acc killed renamable $q1, 0, $noreg, $noreg - ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 - ; CHECK: bb.3.exit: - ; CHECK: liveins: $r12 - ; CHECK: $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 - ; CHECK: bb.4: - ; CHECK: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 + ; CHECK-NEXT: successors: %bb.4(0x30000000), %bb.1(0x50000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r2, $r7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: tCBZ $r2, %bb.4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.vector.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r1, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r1 = t2BICri killed renamable $r1, 3, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r1, 19, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r1 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $q0 = MVE_VLDRWU32 killed renamable $r1, 0, 0, $noreg, $noreg :: (load (s128) from %fixed-stack.0, align 8) + ; CHECK-NEXT: dead $lr = t2DLS renamable $r3 + ; CHECK-NEXT: $r1 = tMOVr killed $r3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.vector.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $q0, $r0, $r1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg + ; CHECK-NEXT: MVE_VPST 8, implicit $vpr + ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) + ; CHECK-NEXT: $lr = tMOVr $r1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $q1 = nsw MVE_VADDi32 renamable $q0, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1 + ; CHECK-NEXT: renamable $r1, dead $cpsr = nsw tSUBi8 killed $r1, 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r12 = MVE_VADDVu32no_acc killed renamable $q1, 0, $noreg, $noreg + ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.exit: + ; CHECK-NEXT: liveins: $r12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4: + ; CHECK-NEXT: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 bb.0.entry: successors: %bb.4(0x30000000), %bb.1(0x50000000) liveins: $r0, $r2, $r7, $lr diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-chain-store.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-chain-store.mir index ae13493c4af83..f8414329ad58c 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-chain-store.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-chain-store.mir @@ -74,19 +74,14 @@ ret void } - ; Function Attrs: nounwind readnone declare <4 x i1> @llvm.arm.mve.vctp32(i32) #1 - ; Function Attrs: argmemonly nounwind readonly willreturn declare <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>*, i32 immarg, <4 x i1>, <4 x float>) #2 - ; Function Attrs: argmemonly nounwind willreturn writeonly declare void @llvm.masked.store.v4f32.p0v4f32(<4 x float>, <4 x float>*, i32 immarg, <4 x i1>) #3 - ; Function Attrs: noduplicate nounwind declare i32 @llvm.start.loop.iterations.i32(i32) #4 - ; Function Attrs: noduplicate nounwind declare i32 @llvm.loop.decrement.reg.i32(i32, i32) #4 attributes #0 = { "target-features"="+mve.fp" } @@ -127,35 +122,39 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: it_block_store_count_before_start ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r7 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: renamable $lr = t2MOVi 4, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r12 = t2LSLri renamable $r2, 1, 14 /* CC::al */, $noreg, $noreg - ; CHECK: t2CMPri renamable $r12, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 11, 8, implicit-def $itstate - ; CHECK: $lr = t2LSLri renamable $r2, 1, 11 /* CC::lt */, killed $cpsr, $noreg, implicit killed renamable $lr, implicit killed $itstate - ; CHECK: renamable $r2 = t2RSBrs killed renamable $lr, killed renamable $r2, 10, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $lr = t2ADDri killed renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r2, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg - ; CHECK: t2STRi12 killed renamable $lr, killed renamable $r3, 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.iter.addr) - ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r12 - ; CHECK: $r2 = tMOVr killed $lr, 14 /* CC::al */, $noreg - ; CHECK: bb.1.do.body: - ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) - ; CHECK: liveins: $r0, $r1, $r2 - ; CHECK: $lr = tMOVr $r2, 14 /* CC::al */, $noreg - ; CHECK: renamable $r2, dead $cpsr = nsw tSUBi8 killed $r2, 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRWU32_post killed renamable $r0, 16, 0, $noreg, $noreg :: (load (s128) from %ir.pSrc.addr.02, align 4) - ; CHECK: renamable $q0 = MVE_VMULf32 killed renamable $q0, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: renamable $r1 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r1, 16, 0, killed $noreg, $noreg :: (store (s128) into %ir.pDst.addr.01, align 4) - ; CHECK: dead $lr = MVE_LETP killed renamable $lr, %bb.1 - ; CHECK: bb.2.do.end: - ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: renamable $lr = t2MOVi 4, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r12 = t2LSLri renamable $r2, 1, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: t2CMPri renamable $r12, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: t2IT 11, 8, implicit-def $itstate + ; CHECK-NEXT: $lr = t2LSLri renamable $r2, 1, 11 /* CC::lt */, killed $cpsr, $noreg, implicit killed renamable $lr, implicit killed $itstate + ; CHECK-NEXT: renamable $r2 = t2RSBrs killed renamable $lr, killed renamable $r2, 10, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $lr = t2ADDri killed renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r2, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: t2STRi12 killed renamable $lr, killed renamable $r3, 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.iter.addr) + ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r12 + ; CHECK-NEXT: $r2 = tMOVr killed $lr, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.do.body: + ; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $lr = tMOVr $r2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r2, dead $cpsr = nsw tSUBi8 killed $r2, 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r0, renamable $q0 = MVE_VLDRWU32_post killed renamable $r0, 16, 0, $noreg, $noreg :: (load (s128) from %ir.pSrc.addr.02, align 4) + ; CHECK-NEXT: renamable $q0 = MVE_VMULf32 killed renamable $q0, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: renamable $r1 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r1, 16, 0, killed $noreg, $noreg :: (store (s128) into %ir.pDst.addr.01, align 4) + ; CHECK-NEXT: dead $lr = MVE_LETP killed renamable $lr, %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.do.end: + ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $r3, $r7, $lr @@ -228,35 +227,39 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: it_block_store_count_after_start ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r7 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: renamable $lr = t2MOVi 4, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r12 = t2LSLri renamable $r2, 1, 14 /* CC::al */, $noreg, $noreg - ; CHECK: t2CMPri renamable $r12, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 11, 8, implicit-def $itstate - ; CHECK: $lr = t2LSLri renamable $r2, 1, 11 /* CC::lt */, killed $cpsr, $noreg, implicit killed renamable $lr, implicit killed $itstate - ; CHECK: renamable $r2 = t2RSBrs killed renamable $lr, killed renamable $r2, 10, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $lr = t2ADDri killed renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r2, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg - ; CHECK: t2STRi12 killed renamable $lr, killed renamable $r3, 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.iter.addr) - ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r12 - ; CHECK: $r2 = tMOVr killed $lr, 14 /* CC::al */, $noreg - ; CHECK: bb.1.do.body: - ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) - ; CHECK: liveins: $r0, $r1, $r2 - ; CHECK: $lr = tMOVr $r2, 14 /* CC::al */, $noreg - ; CHECK: renamable $r2, dead $cpsr = nsw tSUBi8 killed $r2, 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRWU32_post killed renamable $r0, 16, 0, $noreg, $noreg :: (load (s128) from %ir.pSrc.addr.02, align 4) - ; CHECK: renamable $q0 = MVE_VMULf32 killed renamable $q0, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: renamable $r1 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r1, 16, 0, killed $noreg, $noreg :: (store (s128) into %ir.pDst.addr.01, align 4) - ; CHECK: dead $lr = MVE_LETP killed renamable $lr, %bb.1 - ; CHECK: bb.2.do.end: - ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: renamable $lr = t2MOVi 4, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r12 = t2LSLri renamable $r2, 1, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: t2CMPri renamable $r12, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: t2IT 11, 8, implicit-def $itstate + ; CHECK-NEXT: $lr = t2LSLri renamable $r2, 1, 11 /* CC::lt */, killed $cpsr, $noreg, implicit killed renamable $lr, implicit killed $itstate + ; CHECK-NEXT: renamable $r2 = t2RSBrs killed renamable $lr, killed renamable $r2, 10, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $lr = t2ADDri killed renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r2, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: t2STRi12 killed renamable $lr, killed renamable $r3, 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.iter.addr) + ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r12 + ; CHECK-NEXT: $r2 = tMOVr killed $lr, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.do.body: + ; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $lr = tMOVr $r2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r2, dead $cpsr = nsw tSUBi8 killed $r2, 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r0, renamable $q0 = MVE_VLDRWU32_post killed renamable $r0, 16, 0, $noreg, $noreg :: (load (s128) from %ir.pSrc.addr.02, align 4) + ; CHECK-NEXT: renamable $q0 = MVE_VMULf32 killed renamable $q0, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: renamable $r1 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r1, 16, 0, killed $noreg, $noreg :: (store (s128) into %ir.pDst.addr.01, align 4) + ; CHECK-NEXT: dead $lr = MVE_LETP killed renamable $lr, %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.do.end: + ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $r3, $r7, $lr diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-mov.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-mov.mir index 938ae829db4eb..31e88ea49a1a0 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-mov.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-mov.mir @@ -2,7 +2,6 @@ # RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -run-pass=arm-low-overhead-loops %s -o - --verify-machineinstrs | FileCheck %s --- | - ; Function Attrs: nounwind define hidden arm_aapcs_vfpcc void @cond_trip_count(ptr %0, i32 %1, ptr nocapture %2) local_unnamed_addr #1 { ret void } @@ -39,79 +38,93 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: cond_trip_count ; CHECK: bb.0: - ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r4 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 - ; CHECK: tCMPi8 renamable $r1, 2, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: renamable $r12 = t2MOVi 4, 14 /* CC::al */, $noreg, $noreg - ; CHECK: tBcc %bb.2, 2 /* CC::hs */, killed $cpsr - ; CHECK: bb.1: - ; CHECK: liveins: $r2 - ; CHECK: renamable $s0 = VLDRS %const.0, 0, 14 /* CC::al */, $noreg - ; CHECK: VSTRS killed renamable $s0, killed renamable $r2, 0, 14 /* CC::al */, $noreg - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc - ; CHECK: bb.2: - ; CHECK: successors: %bb.3(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2, $r12 - ; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg - ; CHECK: tCMPi8 renamable $r1, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 11, 8, implicit-def $itstate - ; CHECK: $r12 = tMOVr renamable $r1, 11 /* CC::lt */, killed $cpsr, implicit killed renamable $r12, implicit killed $itstate - ; CHECK: renamable $r3 = t2SUBrr renamable $r1, killed renamable $r12, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 3, 14 /* CC::al */, $noreg - ; CHECK: $r12 = tMOVr $r1, 14 /* CC::al */, $noreg - ; CHECK: renamable $r4 = nuw nsw t2ADDrs killed renamable $r4, killed renamable $r3, 19, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: $r3 = tMOVr $r0, 14 /* CC::al */, $noreg - ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r12 - ; CHECK: bb.3: - ; CHECK: successors: %bb.3(0x7c000000), %bb.4(0x04000000) - ; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4 - ; CHECK: renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r3, 0, 0, $noreg, $noreg - ; CHECK: renamable $q0 = nnan ninf nsz MVE_VADDf32 killed renamable $q0, killed renamable $q1, 0, killed $noreg, $noreg, killed renamable $q0 - ; CHECK: renamable $r3, dead $cpsr = nuw tADDi8 killed renamable $r3, 16, 14 /* CC::al */, $noreg - ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.3 - ; CHECK: bb.4: - ; CHECK: successors: %bb.5(0x80000000) - ; CHECK: liveins: $q0, $r0, $r1, $r2, $r4 - ; CHECK: renamable $s4 = nnan ninf nsz VADDS renamable $s0, renamable $s1, 14 /* CC::al */, $noreg - ; CHECK: dead $lr = tMOVr $r4, 14 /* CC::al */, $noreg - ; CHECK: $r3 = tMOVr $r1, 14 /* CC::al */, $noreg - ; CHECK: renamable $s4 = nnan ninf nsz VADDS renamable $s2, killed renamable $s4, 14 /* CC::al */, $noreg - ; CHECK: renamable $s0 = nnan ninf nsz VADDS killed renamable $s3, killed renamable $s4, 14 /* CC::al */, $noreg, implicit killed $q0 - ; CHECK: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg - ; CHECK: renamable $s2 = VUITOS killed renamable $s2, 14 /* CC::al */, $noreg - ; CHECK: $lr = t2DLS killed $r4 - ; CHECK: renamable $s4 = nnan ninf nsz VDIVS killed renamable $s0, killed renamable $s2, 14 /* CC::al */, $noreg - ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: bb.5: - ; CHECK: successors: %bb.5(0x7c000000), %bb.6(0x04000000) - ; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3, $s4 - ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg - ; CHECK: $r4 = VMOVRS $s4, 14 /* CC::al */, $noreg - ; CHECK: MVE_VPST 2, implicit $vpr - ; CHECK: renamable $q2 = nnan ninf nsz MVE_VLDRWU32 renamable $r0, 0, 1, renamable $vpr, $noreg - ; CHECK: renamable $q2 = nnan ninf nsz MVE_VSUB_qr_f32 killed renamable $q2, killed renamable $r4, 1, renamable $vpr, $noreg, undef renamable $q2 - ; CHECK: renamable $q0 = nnan ninf nsz MVE_VFMAf32 killed renamable $q0, killed renamable $q2, killed renamable $q2, 1, killed renamable $vpr, $noreg - ; CHECK: renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg - ; CHECK: renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14 /* CC::al */, $noreg - ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.5 - ; CHECK: bb.6: - ; CHECK: liveins: $q0, $r1, $r2 - ; CHECK: renamable $s4 = nnan ninf nsz VADDS renamable $s0, renamable $s1, 14 /* CC::al */, $noreg - ; CHECK: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $s4 = nnan ninf nsz VADDS renamable $s2, killed renamable $s4, 14 /* CC::al */, $noreg - ; CHECK: renamable $s0 = nnan ninf nsz VADDS killed renamable $s3, killed renamable $s4, 14 /* CC::al */, $noreg, implicit killed $q0 - ; CHECK: $s2 = VMOVSR killed $r0, 14 /* CC::al */, $noreg - ; CHECK: renamable $s2 = VUITOS killed renamable $s2, 14 /* CC::al */, $noreg - ; CHECK: renamable $s0 = nnan ninf nsz VDIVS killed renamable $s0, killed renamable $s2, 14 /* CC::al */, $noreg - ; CHECK: VSTRS killed renamable $s0, killed renamable $r2, 0, 14 /* CC::al */, $noreg - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc - ; CHECK: bb.7 (align 4): - ; CHECK: CONSTPOOL_ENTRY 0, %const.0, 4 + ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -8 + ; CHECK-NEXT: tCMPi8 renamable $r1, 2, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: renamable $r12 = t2MOVi 4, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: tBcc %bb.2, 2 /* CC::hs */, killed $cpsr + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: liveins: $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $s0 = VLDRS %const.0, 0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: VSTRS killed renamable $s0, killed renamable $r2, 0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: successors: %bb.3(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r4, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: tCMPi8 renamable $r1, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: t2IT 11, 8, implicit-def $itstate + ; CHECK-NEXT: $r12 = tMOVr renamable $r1, 11 /* CC::lt */, killed $cpsr, implicit killed renamable $r12, implicit killed $itstate + ; CHECK-NEXT: renamable $r3 = t2SUBrr renamable $r1, killed renamable $r12, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $r12 = tMOVr $r1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r4 = nuw nsw t2ADDrs killed renamable $r4, killed renamable $r3, 19, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: $r3 = tMOVr $r0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3: + ; CHECK-NEXT: successors: %bb.3(0x7c000000), %bb.4(0x04000000) + ; CHECK-NEXT: liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r3, 0, 0, $noreg, $noreg + ; CHECK-NEXT: renamable $q0 = nnan ninf nsz MVE_VADDf32 killed renamable $q0, killed renamable $q1, 0, killed $noreg, $noreg, killed renamable $q0 + ; CHECK-NEXT: renamable $r3, dead $cpsr = nuw tADDi8 killed renamable $r3, 16, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4: + ; CHECK-NEXT: successors: %bb.5(0x80000000) + ; CHECK-NEXT: liveins: $q0, $r0, $r1, $r2, $r4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $s4 = nnan ninf nsz VADDS renamable $s0, renamable $s1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: dead $lr = tMOVr $r4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $r3 = tMOVr $r1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $s4 = nnan ninf nsz VADDS renamable $s2, killed renamable $s4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $s0 = nnan ninf nsz VADDS killed renamable $s3, killed renamable $s4, 14 /* CC::al */, $noreg, implicit killed $q0 + ; CHECK-NEXT: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $s2 = VUITOS killed renamable $s2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $lr = t2DLS killed $r4 + ; CHECK-NEXT: renamable $s4 = nnan ninf nsz VDIVS killed renamable $s0, killed renamable $s2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.5: + ; CHECK-NEXT: successors: %bb.5(0x7c000000), %bb.6(0x04000000) + ; CHECK-NEXT: liveins: $lr, $q0, $r0, $r1, $r2, $r3, $s4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg + ; CHECK-NEXT: $r4 = VMOVRS $s4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: MVE_VPST 2, implicit $vpr + ; CHECK-NEXT: renamable $q2 = nnan ninf nsz MVE_VLDRWU32 renamable $r0, 0, 1, renamable $vpr, $noreg + ; CHECK-NEXT: renamable $q2 = nnan ninf nsz MVE_VSUB_qr_f32 killed renamable $q2, killed renamable $r4, 1, renamable $vpr, $noreg, undef renamable $q2 + ; CHECK-NEXT: renamable $q0 = nnan ninf nsz MVE_VFMAf32 killed renamable $q0, killed renamable $q2, killed renamable $q2, 1, killed renamable $vpr, $noreg + ; CHECK-NEXT: renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.5 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.6: + ; CHECK-NEXT: liveins: $q0, $r1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $s4 = nnan ninf nsz VADDS renamable $s0, renamable $s1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $s4 = nnan ninf nsz VADDS renamable $s2, killed renamable $s4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $s0 = nnan ninf nsz VADDS killed renamable $s3, killed renamable $s4, 14 /* CC::al */, $noreg, implicit killed $q0 + ; CHECK-NEXT: $s2 = VMOVSR killed $r0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $s2 = VUITOS killed renamable $s2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $s0 = nnan ninf nsz VDIVS killed renamable $s0, killed renamable $s2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: VSTRS killed renamable $s0, killed renamable $r2, 0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.7 (align 4): + ; CHECK-NEXT: CONSTPOOL_ENTRY 0, %const.0, 4 bb.0: successors: %bb.1(0x40000000), %bb.2(0x40000000) liveins: $r0, $r1, $r2, $r4, $lr diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/iv-two-vcmp-reordered.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/iv-two-vcmp-reordered.mir index dbe0ac4a7ab78..d088bfaaa7d5c 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/iv-two-vcmp-reordered.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/iv-two-vcmp-reordered.mir @@ -97,52 +97,59 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: test ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000) - ; CHECK: liveins: $lr, $d8, $d9, $r0, $r1, $r2, $r4 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 - ; CHECK: $sp = frame-setup VSTMDDB_UPD $sp, 14 /* CC::al */, $noreg, killed $d8, killed $d9 - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 24 - ; CHECK: frame-setup CFI_INSTRUCTION offset $d9, -16 - ; CHECK: frame-setup CFI_INSTRUCTION offset $d8, -24 - ; CHECK: tCBZ $r2, %bb.3 - ; CHECK: bb.1.vector.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2 - ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg - ; CHECK: renamable $q2 = MVE_VMOVimmi32 1, 0, $noreg, $noreg, undef renamable $q2 - ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $q3 = MVE_VMOVimmi32 4, 0, $noreg, $noreg, undef renamable $q3 - ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg - ; CHECK: dead $lr = t2DLS renamable $r3 - ; CHECK: $r4 = tMOVr killed $r3, 14 /* CC::al */, $noreg - ; CHECK: renamable $r3 = tLEApcrel %const.0, 14 /* CC::al */, $noreg - ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool) - ; CHECK: renamable $r3, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, $noreg, undef renamable $q1 - ; CHECK: bb.2.vector.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $q0, $q1, $q2, $q3, $r0, $r1, $r2, $r4 - ; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg - ; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg - ; CHECK: renamable $vpr = MVE_VCMPu32 renamable $q1, renamable $q0, 8, 0, $noreg, $noreg - ; CHECK: MVE_VPST 1, implicit $vpr - ; CHECK: renamable $vpr = MVE_VCMPu32 renamable $q0, renamable $q2, 2, 1, killed renamable $vpr, $noreg - ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr, $noreg - ; CHECK: renamable $r1, renamable $q4 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv35, align 4) - ; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q4, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv12, align 4) - ; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q0, renamable $q3, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 - ; CHECK: bb.3.for.cond.cleanup: - ; CHECK: $sp = frame-destroy VLDMDIA_UPD $sp, 14 /* CC::al */, $noreg, def $d8, def $d9 - ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc - ; CHECK: bb.4 (align 16): - ; CHECK: CONSTPOOL_ENTRY 0, %const.0, 16 + ; CHECK-NEXT: successors: %bb.3(0x30000000), %bb.1(0x50000000) + ; CHECK-NEXT: liveins: $lr, $d8, $d9, $r0, $r1, $r2, $r4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -8 + ; CHECK-NEXT: $sp = frame-setup VSTMDDB_UPD $sp, 14 /* CC::al */, $noreg, killed $d8, killed $d9 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 24 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $d9, -16 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $d8, -24 + ; CHECK-NEXT: tCBZ $r2, %bb.3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.vector.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $q2 = MVE_VMOVimmi32 1, 0, $noreg, $noreg, undef renamable $q2 + ; CHECK-NEXT: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $q3 = MVE_VMOVimmi32 4, 0, $noreg, $noreg, undef renamable $q3 + ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: dead $lr = t2DLS renamable $r3 + ; CHECK-NEXT: $r4 = tMOVr killed $r3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r3 = tLEApcrel %const.0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool) + ; CHECK-NEXT: renamable $r3, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, $noreg, undef renamable $q1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.vector.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $q0, $q1, $q2, $q3, $r0, $r1, $r2, $r4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $lr = tMOVr $r4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $vpr = MVE_VCMPu32 renamable $q1, renamable $q0, 8, 0, $noreg, $noreg + ; CHECK-NEXT: MVE_VPST 1, implicit $vpr + ; CHECK-NEXT: renamable $vpr = MVE_VCMPu32 renamable $q0, renamable $q2, 2, 1, killed renamable $vpr, $noreg + ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr, $noreg + ; CHECK-NEXT: renamable $r1, renamable $q4 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv35, align 4) + ; CHECK-NEXT: renamable $r0 = MVE_VSTRWU32_post killed renamable $q4, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv12, align 4) + ; CHECK-NEXT: renamable $q0 = MVE_VADDi32 killed renamable $q0, renamable $q3, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.for.cond.cleanup: + ; CHECK-NEXT: $sp = frame-destroy VLDMDIA_UPD $sp, 14 /* CC::al */, $noreg, def $d8, def $d9 + ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4 (align 16): + ; CHECK-NEXT: CONSTPOOL_ENTRY 0, %const.0, 16 bb.0.entry: successors: %bb.3(0x30000000), %bb.1(0x50000000) liveins: $r0, $r1, $r2, $r4, $lr, $d8, $d9 diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/iv-two-vcmp.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/iv-two-vcmp.mir index be8fd89e6cc8f..f341d128b50ca 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/iv-two-vcmp.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/iv-two-vcmp.mir @@ -94,52 +94,59 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: test ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000) - ; CHECK: liveins: $lr, $d8, $d9, $r0, $r1, $r2, $r4 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 - ; CHECK: $sp = frame-setup VSTMDDB_UPD $sp, 14 /* CC::al */, $noreg, killed $d8, killed $d9 - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 24 - ; CHECK: frame-setup CFI_INSTRUCTION offset $d9, -16 - ; CHECK: frame-setup CFI_INSTRUCTION offset $d8, -24 - ; CHECK: tCBZ $r2, %bb.3 - ; CHECK: bb.1.vector.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2 - ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg - ; CHECK: renamable $q2 = MVE_VMOVimmi32 1, 0, $noreg, $noreg, undef renamable $q2 - ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $q3 = MVE_VMOVimmi32 4, 0, $noreg, $noreg, undef renamable $q3 - ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg - ; CHECK: dead $lr = t2DLS renamable $r3 - ; CHECK: $r4 = tMOVr killed $r3, 14 /* CC::al */, $noreg - ; CHECK: renamable $r3 = tLEApcrel %const.0, 14 /* CC::al */, $noreg - ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool) - ; CHECK: renamable $r3, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, $noreg, undef renamable $q1 - ; CHECK: bb.2.vector.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $q0, $q1, $q2, $q3, $r0, $r1, $r2, $r4 - ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg - ; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg - ; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg - ; CHECK: MVE_VPST 1, implicit $vpr - ; CHECK: renamable $vpr = MVE_VCMPu32 renamable $q1, renamable $q0, 8, 1, killed renamable $vpr, $noreg - ; CHECK: renamable $vpr = MVE_VCMPu32 renamable $q0, renamable $q2, 2, 1, killed renamable $vpr, $noreg - ; CHECK: renamable $r1, renamable $q4 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv35, align 4) - ; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q4, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv12, align 4) - ; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q0, renamable $q3, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 - ; CHECK: bb.3.for.cond.cleanup: - ; CHECK: $sp = frame-destroy VLDMDIA_UPD $sp, 14 /* CC::al */, $noreg, def $d8, def $d9 - ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc - ; CHECK: bb.4 (align 16): - ; CHECK: CONSTPOOL_ENTRY 0, %const.0, 16 + ; CHECK-NEXT: successors: %bb.3(0x30000000), %bb.1(0x50000000) + ; CHECK-NEXT: liveins: $lr, $d8, $d9, $r0, $r1, $r2, $r4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -8 + ; CHECK-NEXT: $sp = frame-setup VSTMDDB_UPD $sp, 14 /* CC::al */, $noreg, killed $d8, killed $d9 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 24 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $d9, -16 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $d8, -24 + ; CHECK-NEXT: tCBZ $r2, %bb.3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.vector.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $q2 = MVE_VMOVimmi32 1, 0, $noreg, $noreg, undef renamable $q2 + ; CHECK-NEXT: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $q3 = MVE_VMOVimmi32 4, 0, $noreg, $noreg, undef renamable $q3 + ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: dead $lr = t2DLS renamable $r3 + ; CHECK-NEXT: $r4 = tMOVr killed $r3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r3 = tLEApcrel %const.0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool) + ; CHECK-NEXT: renamable $r3, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, $noreg, undef renamable $q1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.vector.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $q0, $q1, $q2, $q3, $r0, $r1, $r2, $r4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg + ; CHECK-NEXT: $lr = tMOVr $r4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: MVE_VPST 1, implicit $vpr + ; CHECK-NEXT: renamable $vpr = MVE_VCMPu32 renamable $q1, renamable $q0, 8, 1, killed renamable $vpr, $noreg + ; CHECK-NEXT: renamable $vpr = MVE_VCMPu32 renamable $q0, renamable $q2, 2, 1, killed renamable $vpr, $noreg + ; CHECK-NEXT: renamable $r1, renamable $q4 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv35, align 4) + ; CHECK-NEXT: renamable $r0 = MVE_VSTRWU32_post killed renamable $q4, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv12, align 4) + ; CHECK-NEXT: renamable $q0 = MVE_VADDi32 killed renamable $q0, renamable $q3, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.for.cond.cleanup: + ; CHECK-NEXT: $sp = frame-destroy VLDMDIA_UPD $sp, 14 /* CC::al */, $noreg, def $d8, def $d9 + ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4 (align 16): + ; CHECK-NEXT: CONSTPOOL_ENTRY 0, %const.0, 16 bb.0.entry: successors: %bb.3(0x30000000), %bb.1(0x50000000) liveins: $r0, $r1, $r2, $r4, $lr, $d8, $d9 diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/iv-vcmp.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/iv-vcmp.mir index ec396187b92c9..541c518e0c3bb 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/iv-vcmp.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/iv-vcmp.mir @@ -2,7 +2,6 @@ # RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -verify-machineinstrs -o - | FileCheck %s --- | - ; Function Attrs: nofree norecurse nounwind define dso_local arm_aapcs_vfpcc void @test(i32* noalias nocapture %a, i32* nocapture readonly %b, i32 %N) local_unnamed_addr #0 { entry: %cmp9 = icmp eq i32 %N, 0 @@ -87,38 +86,45 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: test ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7 - ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 0, 8, implicit-def $itstate - ; CHECK: frame-destroy tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate - ; CHECK: bb.1.vector.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2 - ; CHECK: renamable $q2 = MVE_VMOVimmi32 4, 0, $noreg, $noreg, undef renamable $q2 - ; CHECK: renamable $r3 = tLEApcrel %const.0, 14 /* CC::al */, $noreg - ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool) - ; CHECK: renamable $r3, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, $noreg, undef renamable $q1 - ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2 - ; CHECK: bb.2.vector.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $lr, $q0, $q1, $q2, $r0, $r1 - ; CHECK: MVE_VPTv4u32 4, renamable $q1, renamable $q0, 8, implicit-def $vpr - ; CHECK: renamable $r1, renamable $q3 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv35, align 4) - ; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q3, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv12, align 4) - ; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q0, renamable $q2, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 - ; CHECK: bb.3.for.cond.cleanup: - ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc - ; CHECK: bb.4 (align 16): - ; CHECK: CONSTPOOL_ENTRY 0, %const.0, 16 + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $r7 + ; CHECK-NEXT: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: t2IT 0, 8, implicit-def $itstate + ; CHECK-NEXT: frame-destroy tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.vector.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $q2 = MVE_VMOVimmi32 4, 0, $noreg, $noreg, undef renamable $q2 + ; CHECK-NEXT: renamable $r3 = tLEApcrel %const.0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool) + ; CHECK-NEXT: renamable $r3, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, $noreg, undef renamable $q1 + ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.vector.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $lr, $q0, $q1, $q2, $r0, $r1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: MVE_VPTv4u32 4, renamable $q1, renamable $q0, 8, implicit-def $vpr + ; CHECK-NEXT: renamable $r1, renamable $q3 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv35, align 4) + ; CHECK-NEXT: renamable $r0 = MVE_VSTRWU32_post killed renamable $q3, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv12, align 4) + ; CHECK-NEXT: renamable $q0 = MVE_VADDi32 killed renamable $q0, renamable $q2, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.for.cond.cleanup: + ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4 (align 16): + ; CHECK-NEXT: CONSTPOOL_ENTRY 0, %const.0, 16 bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $lr diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/livereg-no-loop-def.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/livereg-no-loop-def.mir index 6322ddf615b35..40cb3a00d61b8 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/livereg-no-loop-def.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/livereg-no-loop-def.mir @@ -86,34 +86,41 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: exit_liveout ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 - ; CHECK: renamable $r12 = t2ADDri $sp, 8, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r12, 0, 0, $noreg, $noreg :: (load (s128) from %fixed-stack.0, align 8) - ; CHECK: tCBZ $r3, %bb.3 - ; CHECK: bb.1.vector.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $q0, $r0, $r1, $r2, $r3 - ; CHECK: renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q1 - ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3 - ; CHECK: bb.2.vector.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $lr, $q0, $q1, $r0, $r1, $r2 - ; CHECK: renamable $r0, renamable $q2 = MVE_VLDRHS32_post killed renamable $r0, 8, 0, $noreg, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) - ; CHECK: renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 0, $noreg, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2) - ; CHECK: renamable $q2 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, $noreg, undef renamable $q2 - ; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1 - ; CHECK: renamable $r2 = MVE_VSTRWU32_post renamable $q1, killed renamable $r2, 16, 0, killed $noreg, $noreg :: (store (s128) into %ir.lsr.store, align 4) - ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 - ; CHECK: bb.3.exit: - ; CHECK: liveins: $q0 - ; CHECK: renamable $r0, renamable $r1 = VMOVRRD renamable $d0, 14 /* CC::al */, $noreg - ; CHECK: renamable $r2, renamable $r3 = VMOVRRD killed renamable $d1, 14 /* CC::al */, $noreg, implicit killed $q0 - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0, implicit killed $r1, implicit killed $r2, implicit killed $r3 + ; CHECK-NEXT: successors: %bb.3(0x30000000), %bb.1(0x50000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -8 + ; CHECK-NEXT: renamable $r12 = t2ADDri $sp, 8, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $q0 = MVE_VLDRWU32 killed renamable $r12, 0, 0, $noreg, $noreg :: (load (s128) from %fixed-stack.0, align 8) + ; CHECK-NEXT: tCBZ $r3, %bb.3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.vector.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $q0, $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q1 + ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.vector.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $lr, $q0, $q1, $r0, $r1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r0, renamable $q2 = MVE_VLDRHS32_post killed renamable $r0, 8, 0, $noreg, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) + ; CHECK-NEXT: renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 0, $noreg, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2) + ; CHECK-NEXT: renamable $q2 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, $noreg, undef renamable $q2 + ; CHECK-NEXT: renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1 + ; CHECK-NEXT: renamable $r2 = MVE_VSTRWU32_post renamable $q1, killed renamable $r2, 16, 0, killed $noreg, $noreg :: (store (s128) into %ir.lsr.store, align 4) + ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.exit: + ; CHECK-NEXT: liveins: $q0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r0, renamable $r1 = VMOVRRD renamable $d0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r2, renamable $r3 = VMOVRRD killed renamable $d1, 14 /* CC::al */, $noreg, implicit killed $q0 + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0, implicit killed $r1, implicit killed $r2, implicit killed $r3 bb.0.entry: successors: %bb.3(0x30000000), %bb.1(0x50000000) liveins: $r0, $r1, $r2, $r3, $r4, $lr diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/massive.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/massive.mir index 2fb744e8e7621..9448a1ab00d3e 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/massive.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/massive.mir @@ -2,7 +2,6 @@ # RUN: llc -mtriple=armv8.1m.main -mattr=+lob -run-pass=arm-low-overhead-loops --verify-machineinstrs %s -o - | FileCheck %s --- | - ; ModuleID = 'massive.ll' source_filename = "massive.ll" target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" target triple = "thumbv8.1m.main" @@ -43,16 +42,12 @@ br i1 %4, label %for.body, label %for.cond.cleanup } - ; Function Attrs: nounwind declare i32 @llvm.arm.space(i32 immarg, i32) #0 - ; Function Attrs: noduplicate nounwind declare i32 @llvm.start.loop.iterations.i32(i32) #1 - ; Function Attrs: noduplicate nounwind declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #1 - ; Function Attrs: nounwind declare void @llvm.stackprotector(ptr, ptr) #0 attributes #0 = { nounwind } @@ -108,36 +103,42 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: massive ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r7 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: tCMPi8 $r3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 0, 8, implicit-def $itstate - ; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate - ; CHECK: bb.1.for.body.preheader: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg - ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg - ; CHECK: renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 4, 14 /* CC::al */, $noreg - ; CHECK: dead $lr = tMOVr $r3, 14 /* CC::al */, $noreg - ; CHECK: $lr = tMOVr killed $r3, 14 /* CC::al */, $noreg - ; CHECK: bb.2.for.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2 - ; CHECK: dead renamable $r3 = SPACE 4096, undef renamable $r0 - ; CHECK: renamable $r12, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep3) - ; CHECK: renamable $r3, renamable $r2 = t2LDR_PRE killed renamable $r2, 4, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep7) - ; CHECK: renamable $r3 = nsw t2MUL killed renamable $r3, killed renamable $r12, 14 /* CC::al */, $noreg - ; CHECK: early-clobber renamable $r0 = t2STR_PRE killed renamable $r3, killed renamable $r0, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.scevgep11) - ; CHECK: renamable $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, def $cpsr - ; CHECK: t2Bcc %bb.2, 1 /* CC::ne */, killed $cpsr - ; CHECK: tB %bb.3, 14 /* CC::al */, $noreg - ; CHECK: bb.3.for.cond.cleanup: - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: tCMPi8 $r3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: t2IT 0, 8, implicit-def $itstate + ; CHECK-NEXT: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.for.body.preheader: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: dead $lr = tMOVr $r3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $lr = tMOVr killed $r3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.for.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: dead renamable $r3 = SPACE 4096, undef renamable $r0 + ; CHECK-NEXT: renamable $r12, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep3) + ; CHECK-NEXT: renamable $r3, renamable $r2 = t2LDR_PRE killed renamable $r2, 4, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep7) + ; CHECK-NEXT: renamable $r3 = nsw t2MUL killed renamable $r3, killed renamable $r12, 14 /* CC::al */, $noreg + ; CHECK-NEXT: early-clobber renamable $r0 = t2STR_PRE killed renamable $r3, killed renamable $r0, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.scevgep11) + ; CHECK-NEXT: renamable $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, def $cpsr + ; CHECK-NEXT: t2Bcc %bb.2, 1 /* CC::ne */, killed $cpsr + ; CHECK-NEXT: tB %bb.3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.for.cond.cleanup: + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $r3, $r7, $lr diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-after-dlstp.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-after-dlstp.mir index af76970f18da8..57101b15243fb 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-after-dlstp.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-after-dlstp.mir @@ -73,25 +73,18 @@ ret void } - ; Function Attrs: nounwind readnone declare <4 x float> @llvm.arm.mve.sub.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>, <4 x float>) #1 - ; Function Attrs: nounwind readnone declare <4 x float> @llvm.arm.mve.fma.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x float>, <4 x i1>) #1 - ; Function Attrs: nounwind readnone declare <4 x i1> @llvm.arm.mve.vctp32(i32) #1 - ; Function Attrs: argmemonly nounwind readonly willreturn declare <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>*, i32 immarg, <4 x i1>, <4 x float>) #2 - ; Function Attrs: nounwind readnone declare <4 x float> @llvm.arm.mve.add.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>, <4 x float>) #1 - ; Function Attrs: noduplicate nounwind declare i32 @llvm.start.loop.iterations.i32(i32) #3 - ; Function Attrs: noduplicate nounwind declare i32 @llvm.loop.decrement.reg.i32(i32, i32) #3 attributes #0 = { "target-features"="+mve.fp" } @@ -148,55 +141,64 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: arm_var_f32_mve ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r4 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 - ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: $r3 = tMOVr $r1, 14 /* CC::al */, $noreg - ; CHECK: $r12 = tMOVr $r0, 14 /* CC::al */, $noreg - ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3 - ; CHECK: $r4 = tMOVr $lr, 14 /* CC::al */, $noreg - ; CHECK: bb.1.do.body.i: - ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) - ; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r4, $r12 - ; CHECK: renamable $r12, renamable $q1 = MVE_VLDRWU32_post killed renamable $r12, 16, 0, $noreg, $noreg :: (load (s128) from %ir.pSrc.addr.0.i2, align 4) - ; CHECK: renamable $q0 = nnan ninf nsz arcp contract afn reassoc MVE_VADDf32 killed renamable $q0, killed renamable $q1, 0, killed $noreg, $noreg, killed renamable $q0 - ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1 - ; CHECK: bb.2.arm_mean_f32_mve.exit: - ; CHECK: successors: %bb.3(0x80000000) - ; CHECK: liveins: $q0, $r0, $r1, $r2, $r4 - ; CHECK: $s4 = VMOVSR $r1, 14 /* CC::al */, $noreg - ; CHECK: dead $lr = tMOVr $r4, 14 /* CC::al */, $noreg - ; CHECK: renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s3, killed renamable $s3, 14 /* CC::al */, $noreg, implicit killed $q0 - ; CHECK: $lr = t2DLS killed $r4 - ; CHECK: renamable $s4 = VUITOS killed renamable $s4, 14 /* CC::al */, $noreg - ; CHECK: renamable $s0 = nnan ninf nsz arcp contract afn reassoc VDIVS killed renamable $s0, killed renamable $s4, 14 /* CC::al */, $noreg - ; CHECK: renamable $r3 = VMOVRS killed renamable $s0, 14 /* CC::al */, $noreg - ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, $noreg, undef renamable $q1 - ; CHECK: $r3 = tMOVr $r1, 14 /* CC::al */, $noreg - ; CHECK: bb.3.do.body: - ; CHECK: successors: %bb.3(0x7c000000), %bb.4(0x04000000) - ; CHECK: liveins: $lr, $q0, $q1, $r0, $r1, $r2, $r3 - ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg - ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg - ; CHECK: MVE_VPST 2, implicit $vpr - ; CHECK: renamable $r0, renamable $q2 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.pSrc.addr.01, align 4) - ; CHECK: renamable $q2 = nnan ninf nsz arcp contract afn reassoc MVE_VSUBf32 killed renamable $q2, renamable $q1, 1, renamable $vpr, $noreg, undef renamable $q2 - ; CHECK: renamable $q0 = nnan ninf nsz arcp contract afn reassoc MVE_VFMAf32 killed renamable $q0, killed renamable $q2, killed renamable $q2, 1, killed renamable $vpr, $noreg - ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.3 - ; CHECK: bb.4.do.end: - ; CHECK: liveins: $q0, $r1, $r2 - ; CHECK: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s3, killed renamable $s3, 14 /* CC::al */, $noreg, implicit killed $q0 - ; CHECK: $s2 = VMOVSR killed $r0, 14 /* CC::al */, $noreg - ; CHECK: renamable $s2 = VUITOS killed renamable $s2, 14 /* CC::al */, $noreg - ; CHECK: renamable $s0 = nnan ninf nsz arcp contract afn reassoc VDIVS killed renamable $s0, killed renamable $s2, 14 /* CC::al */, $noreg - ; CHECK: VSTRS killed renamable $s0, killed renamable $r2, 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.pResult) - ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -8 + ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: $r3 = tMOVr $r1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $r12 = tMOVr $r0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r3 + ; CHECK-NEXT: $r4 = tMOVr $lr, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.do.body.i: + ; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000) + ; CHECK-NEXT: liveins: $lr, $q0, $r0, $r1, $r2, $r4, $r12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r12, renamable $q1 = MVE_VLDRWU32_post killed renamable $r12, 16, 0, $noreg, $noreg :: (load (s128) from %ir.pSrc.addr.0.i2, align 4) + ; CHECK-NEXT: renamable $q0 = nnan ninf nsz arcp contract afn reassoc MVE_VADDf32 killed renamable $q0, killed renamable $q1, 0, killed $noreg, $noreg, killed renamable $q0 + ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.arm_mean_f32_mve.exit: + ; CHECK-NEXT: successors: %bb.3(0x80000000) + ; CHECK-NEXT: liveins: $q0, $r0, $r1, $r2, $r4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $s4 = VMOVSR $r1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: dead $lr = tMOVr $r4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s3, killed renamable $s3, 14 /* CC::al */, $noreg, implicit killed $q0 + ; CHECK-NEXT: $lr = t2DLS killed $r4 + ; CHECK-NEXT: renamable $s4 = VUITOS killed renamable $s4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $s0 = nnan ninf nsz arcp contract afn reassoc VDIVS killed renamable $s0, killed renamable $s4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r3 = VMOVRS killed renamable $s0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, $noreg, undef renamable $q1 + ; CHECK-NEXT: $r3 = tMOVr $r1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.do.body: + ; CHECK-NEXT: successors: %bb.3(0x7c000000), %bb.4(0x04000000) + ; CHECK-NEXT: liveins: $lr, $q0, $q1, $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg + ; CHECK-NEXT: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: MVE_VPST 2, implicit $vpr + ; CHECK-NEXT: renamable $r0, renamable $q2 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.pSrc.addr.01, align 4) + ; CHECK-NEXT: renamable $q2 = nnan ninf nsz arcp contract afn reassoc MVE_VSUBf32 killed renamable $q2, renamable $q1, 1, renamable $vpr, $noreg, undef renamable $q2 + ; CHECK-NEXT: renamable $q0 = nnan ninf nsz arcp contract afn reassoc MVE_VFMAf32 killed renamable $q0, killed renamable $q2, killed renamable $q2, 1, killed renamable $vpr, $noreg + ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4.do.end: + ; CHECK-NEXT: liveins: $q0, $r1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s3, killed renamable $s3, 14 /* CC::al */, $noreg, implicit killed $q0 + ; CHECK-NEXT: $s2 = VMOVSR killed $r0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $s2 = VUITOS killed renamable $s2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $s0 = nnan ninf nsz arcp contract afn reassoc VDIVS killed renamable $s0, killed renamable $s2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: VSTRS killed renamable $s0, killed renamable $r2, 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.pResult) + ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $r4, $lr diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-lr-terminator.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-lr-terminator.mir index 6f7a8cde23928..e0c79c6401439 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-lr-terminator.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-lr-terminator.mir @@ -99,35 +99,41 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: start_before_elems ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 - ; CHECK: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg - ; CHECK: t2CMPrs killed renamable $r12, renamable $r3, 11, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 0, 8, implicit-def $itstate - ; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $pc, implicit killed $itstate - ; CHECK: bb.1.vector.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: renamable $r12 = t2LSRri killed renamable $r3, 1, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg - ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r12 - ; CHECK: bb.2.vector.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 - ; CHECK: renamable $r4, dead $cpsr = tADDrr renamable $r1, renamable $r3, 14 /* CC::al */, $noreg - ; CHECK: renamable $q0 = MVE_VLDRBU32 killed renamable $r4, 0, 0, $noreg, $noreg :: (load (s32) from %ir.scevgep45, align 1) - ; CHECK: renamable $r4, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14 /* CC::al */, $noreg - ; CHECK: renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg - ; CHECK: renamable $q1 = MVE_VLDRBU32 killed renamable $r4, 0, 0, $noreg, $noreg :: (load (s32) from %ir.scevgep23, align 1) - ; CHECK: renamable $q0 = nuw nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 0, killed $noreg, $noreg :: (store (s128) into %ir.lsr.iv1, align 4) - ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 - ; CHECK: bb.3.for.cond.cleanup: - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -8 + ; CHECK-NEXT: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: t2CMPrs killed renamable $r12, renamable $r3, 11, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: t2IT 0, 8, implicit-def $itstate + ; CHECK-NEXT: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $pc, implicit killed $itstate + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.vector.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r12 = t2LSRri killed renamable $r3, 1, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.vector.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r4, dead $cpsr = tADDrr renamable $r1, renamable $r3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $q0 = MVE_VLDRBU32 killed renamable $r4, 0, 0, $noreg, $noreg :: (load (s32) from %ir.scevgep45, align 1) + ; CHECK-NEXT: renamable $r4, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $q1 = MVE_VLDRBU32 killed renamable $r4, 0, 0, $noreg, $noreg :: (load (s32) from %ir.scevgep23, align 1) + ; CHECK-NEXT: renamable $q0 = nuw nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 0, killed $noreg, $noreg :: (store (s128) into %ir.lsr.iv1, align 4) + ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.for.cond.cleanup: + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $r3, $r4, $lr diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-def-before-start.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-def-before-start.mir index 08353c8f92f18..c22660273158c 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-def-before-start.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-def-before-start.mir @@ -104,46 +104,52 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: start_before_elems ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 - ; CHECK: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg - ; CHECK: t2CMPrs killed renamable $r12, renamable $r3, 11, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 0, 8, implicit-def $itstate - ; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $pc, implicit killed $itstate - ; CHECK: bb.1.vector.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: renamable $r12 = t2MOVi 3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r12 = nuw t2ADDrs killed renamable $r12, renamable $r3, 11, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r12 = t2BICri killed renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $r12 = t2MOVr killed $r3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg - ; CHECK: renamable $r12 = t2LSRri killed renamable $r12, 1, 14 /* CC::al */, $noreg, $noreg - ; CHECK: bb.2.vector.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r12 - ; CHECK: renamable $r4, dead $cpsr = tADDrr renamable $r1, renamable $r3, 14 /* CC::al */, $noreg - ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg, $noreg - ; CHECK: MVE_VPST 8, implicit $vpr - ; CHECK: renamable $q0 = MVE_VLDRBU32 killed renamable $r4, 0, 1, renamable $vpr, $noreg :: (load (s32) from %ir.scevgep45, align 1) - ; CHECK: renamable $r4, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14 /* CC::al */, $noreg - ; CHECK: renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg - ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg - ; CHECK: MVE_VPST 8, implicit $vpr - ; CHECK: renamable $q1 = MVE_VLDRBU32 killed renamable $r4, 0, 1, renamable $vpr, $noreg :: (load (s32) from %ir.scevgep23, align 1) - ; CHECK: renamable $q0 = nuw nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: MVE_VPST 8, implicit $vpr - ; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv1, align 4) - ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 - ; CHECK: bb.3.for.cond.cleanup: - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -8 + ; CHECK-NEXT: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: t2CMPrs killed renamable $r12, renamable $r3, 11, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: t2IT 0, 8, implicit-def $itstate + ; CHECK-NEXT: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $pc, implicit killed $itstate + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.vector.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r12 = t2MOVi 3, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r12 = nuw t2ADDrs killed renamable $r12, renamable $r3, 11, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r12 = t2BICri killed renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: $r12 = t2MOVr killed $r3, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r12 = t2LSRri killed renamable $r12, 1, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.vector.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r4, dead $cpsr = tADDrr renamable $r1, renamable $r3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg, $noreg + ; CHECK-NEXT: MVE_VPST 8, implicit $vpr + ; CHECK-NEXT: renamable $q0 = MVE_VLDRBU32 killed renamable $r4, 0, 1, renamable $vpr, $noreg :: (load (s32) from %ir.scevgep45, align 1) + ; CHECK-NEXT: renamable $r4, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: MVE_VPST 8, implicit $vpr + ; CHECK-NEXT: renamable $q1 = MVE_VLDRBU32 killed renamable $r4, 0, 1, renamable $vpr, $noreg :: (load (s32) from %ir.scevgep23, align 1) + ; CHECK-NEXT: renamable $q0 = nuw nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: MVE_VPST 8, implicit $vpr + ; CHECK-NEXT: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv1, align 4) + ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.for.cond.cleanup: + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $r3, $r4, $lr diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-start-after-def.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-start-after-def.mir index 26b887906ea3e..255d4756abd95 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-start-after-def.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-start-after-def.mir @@ -104,46 +104,52 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: start_before_elems ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 - ; CHECK: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg - ; CHECK: t2CMPrs killed renamable $r12, renamable $r3, 11, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 0, 8, implicit-def $itstate - ; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $pc, implicit killed $itstate - ; CHECK: bb.1.vector.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: renamable $r12 = t2MOVi 3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r12 = nuw t2ADDrs killed renamable $r12, renamable $r3, 11, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r12 = t2BICri killed renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $r12 = t2MOVr killed $r3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg - ; CHECK: renamable $r12 = t2LSRri killed renamable $r12, 1, 14 /* CC::al */, $noreg, $noreg - ; CHECK: bb.2.vector.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r12 - ; CHECK: renamable $r4, dead $cpsr = tADDrr renamable $r1, renamable $r3, 14 /* CC::al */, $noreg - ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg, $noreg - ; CHECK: MVE_VPST 8, implicit $vpr - ; CHECK: renamable $q0 = MVE_VLDRBU32 killed renamable $r4, 0, 1, renamable $vpr, $noreg :: (load (s32) from %ir.scevgep45, align 1) - ; CHECK: renamable $r4, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14 /* CC::al */, $noreg - ; CHECK: renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg - ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg - ; CHECK: MVE_VPST 8, implicit $vpr - ; CHECK: renamable $q1 = MVE_VLDRBU32 killed renamable $r4, 0, 1, renamable $vpr, $noreg :: (load (s32) from %ir.scevgep23, align 1) - ; CHECK: renamable $q0 = nuw nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: MVE_VPST 8, implicit $vpr - ; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv1, align 4) - ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 - ; CHECK: bb.3.for.cond.cleanup: - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -8 + ; CHECK-NEXT: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: t2CMPrs killed renamable $r12, renamable $r3, 11, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: t2IT 0, 8, implicit-def $itstate + ; CHECK-NEXT: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $pc, implicit killed $itstate + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.vector.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r12 = t2MOVi 3, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r12 = nuw t2ADDrs killed renamable $r12, renamable $r3, 11, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r12 = t2BICri killed renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: $r12 = t2MOVr killed $r3, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r12 = t2LSRri killed renamable $r12, 1, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.vector.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r4, dead $cpsr = tADDrr renamable $r1, renamable $r3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg, $noreg + ; CHECK-NEXT: MVE_VPST 8, implicit $vpr + ; CHECK-NEXT: renamable $q0 = MVE_VLDRBU32 killed renamable $r4, 0, 1, renamable $vpr, $noreg :: (load (s32) from %ir.scevgep45, align 1) + ; CHECK-NEXT: renamable $r4, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: MVE_VPST 8, implicit $vpr + ; CHECK-NEXT: renamable $q1 = MVE_VLDRBU32 killed renamable $r4, 0, 1, renamable $vpr, $noreg :: (load (s32) from %ir.scevgep23, align 1) + ; CHECK-NEXT: renamable $q0 = nuw nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: MVE_VPST 8, implicit $vpr + ; CHECK-NEXT: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv1, align 4) + ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.for.cond.cleanup: + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $r3, $r4, $lr diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/multi-block-cond-iter-count.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/multi-block-cond-iter-count.mir index f17496c3d1653..199e222ccf6aa 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/multi-block-cond-iter-count.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/multi-block-cond-iter-count.mir @@ -192,118 +192,138 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: multi_cond_iter_count ; CHECK: bb.0 (%ir-block.4): - ; CHECK: successors: %bb.4(0x30000000), %bb.1(0x50000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r8, $r9, $r10 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 20 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -12 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -16 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -20 - ; CHECK: dead $r7 = frame-setup tADDrSPi $sp, 3, 14 /* CC::al */, $noreg - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa $r7, 8 - ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r8, killed $r9, killed $r10 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r10, -24 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r9, -28 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -32 - ; CHECK: tCMPi8 renamable $r3, 2, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: $r12 = tMOVr $r3, 14 /* CC::al */, $noreg - ; CHECK: t2IT 1, 8, implicit-def $itstate - ; CHECK: $r12 = t2MOVi 4, 1 /* CC::ne */, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate - ; CHECK: tCMPi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 0, 8, implicit-def $itstate - ; CHECK: $r12 = t2MOVi 1, 0 /* CC::eq */, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate - ; CHECK: renamable $r3 = t2LSLrr killed renamable $r2, killed renamable $r12, 14 /* CC::al */, $noreg, def $cpsr - ; CHECK: tBcc %bb.4, 0 /* CC::eq */, killed $cpsr - ; CHECK: bb.1 (%ir-block.11): - ; CHECK: successors: %bb.2(0x55555555), %bb.5(0x2aaaaaab) - ; CHECK: liveins: $r0, $r1, $r3 - ; CHECK: renamable $r2 = t2ADDrs renamable $r1, renamable $r3, 18, 14 /* CC::al */, $noreg, $noreg - ; CHECK: tCMPr killed renamable $r2, renamable $r0, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 8, 4, implicit-def $itstate - ; CHECK: renamable $r2 = t2ADDrs renamable $r0, renamable $r3, 18, 8 /* CC::hi */, $cpsr, $noreg, implicit $itstate - ; CHECK: tCMPr killed renamable $r2, renamable $r1, 8 /* CC::hi */, killed $cpsr, implicit-def $cpsr, implicit killed $itstate - ; CHECK: tBcc %bb.5, 8 /* CC::hi */, killed $cpsr - ; CHECK: bb.2 (%ir-block.32): - ; CHECK: successors: %bb.3(0x80000000) - ; CHECK: liveins: $r0, $r1, $r3 - ; CHECK: $r2 = tMOVr $r0, 14 /* CC::al */, $noreg - ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3 - ; CHECK: bb.3 (%ir-block.33): - ; CHECK: successors: %bb.3(0x7c000000), %bb.4(0x04000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2 - ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg, $noreg - ; CHECK: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 0, $noreg, $noreg - ; CHECK: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 0, killed $noreg, $noreg - ; CHECK: $r0 = tMOVr $r2, 14 /* CC::al */, $noreg - ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.3 - ; CHECK: bb.4 (%ir-block.64): - ; CHECK: $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r8, def $r9, def $r10 - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc - ; CHECK: bb.5 (%ir-block.23): - ; CHECK: successors: %bb.6(0x40000000), %bb.7(0x40000000) - ; CHECK: liveins: $r0, $r1, $r3 - ; CHECK: renamable $r2, dead $cpsr = tSUBi3 renamable $r3, 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $r12 = t2ANDri renamable $r3, 2, 14 /* CC::al */, $noreg, $noreg - ; CHECK: tCMPi8 killed renamable $r2, 3, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: tBcc %bb.7, 2 /* CC::hs */, killed $cpsr - ; CHECK: bb.6: - ; CHECK: successors: %bb.9(0x80000000) - ; CHECK: liveins: $r0, $r1, $r12 - ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg - ; CHECK: tB %bb.9, 14 /* CC::al */, $noreg - ; CHECK: bb.7 (%ir-block.31): - ; CHECK: successors: %bb.8(0x80000000) - ; CHECK: liveins: $r0, $r1, $r3, $r12 - ; CHECK: renamable $r2 = t2BICri killed renamable $r3, 2, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg - ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg - ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg - ; CHECK: bb.8 (%ir-block.65): - ; CHECK: successors: %bb.8(0x7c000000), %bb.9(0x04000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r12 - ; CHECK: renamable $r4 = tLDRr renamable $r1, $r2, 14 /* CC::al */, $noreg - ; CHECK: renamable $r3, dead $cpsr = nuw tADDi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg - ; CHECK: renamable $r5 = tLDRr renamable $r0, $r2, 14 /* CC::al */, $noreg - ; CHECK: renamable $r4, dead $cpsr = nsw tMUL killed renamable $r5, killed renamable $r4, 14 /* CC::al */, $noreg - ; CHECK: renamable $r5, dead $cpsr = tADDrr renamable $r0, renamable $r2, 14 /* CC::al */, $noreg - ; CHECK: $r10, $r8 = t2LDRDi8 $r5, 4, 14 /* CC::al */, $noreg - ; CHECK: renamable $r9 = t2LDRi12 renamable $r5, 12, 14 /* CC::al */, $noreg - ; CHECK: tSTRr killed renamable $r4, renamable $r0, $r2, 14 /* CC::al */, $noreg - ; CHECK: renamable $r4, dead $cpsr = tADDrr renamable $r1, renamable $r2, 14 /* CC::al */, $noreg - ; CHECK: renamable $r2, dead $cpsr = tADDi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg - ; CHECK: renamable $r6 = tLDRi renamable $r4, 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $r6 = nsw t2MUL killed renamable $r10, killed renamable $r6, 14 /* CC::al */, $noreg - ; CHECK: tSTRi killed renamable $r6, renamable $r5, 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $r6 = tLDRi renamable $r4, 2, 14 /* CC::al */, $noreg - ; CHECK: renamable $r6 = nsw t2MUL killed renamable $r8, killed renamable $r6, 14 /* CC::al */, $noreg - ; CHECK: tSTRi killed renamable $r6, renamable $r5, 2, 14 /* CC::al */, $noreg - ; CHECK: renamable $r4 = tLDRi killed renamable $r4, 3, 14 /* CC::al */, $noreg - ; CHECK: renamable $r4 = nsw t2MUL killed renamable $r9, killed renamable $r4, 14 /* CC::al */, $noreg - ; CHECK: tSTRi killed renamable $r4, killed renamable $r5, 3, 14 /* CC::al */, $noreg - ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.8 - ; CHECK: bb.9 (%ir-block.49): - ; CHECK: successors: %bb.4(0x40000000), %bb.10(0x40000000) - ; CHECK: liveins: $r0, $r1, $r3, $r12 - ; CHECK: t2CMPri killed renamable $r12, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: tBcc %bb.4, 0 /* CC::eq */, killed $cpsr - ; CHECK: bb.10 (%ir-block.52): - ; CHECK: liveins: $r0, $r1, $r3 - ; CHECK: renamable $r12 = t2LDRs renamable $r1, renamable $r3, 2, 14 /* CC::al */, $noreg - ; CHECK: renamable $r2 = t2LDRs renamable $r0, renamable $r3, 2, 14 /* CC::al */, $noreg - ; CHECK: renamable $r12 = nsw t2MUL killed renamable $r2, killed renamable $r12, 14 /* CC::al */, $noreg - ; CHECK: renamable $r2, dead $cpsr = tADDi3 renamable $r3, 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $lr = t2LDRs renamable $r0, renamable $r2, 2, 14 /* CC::al */, $noreg - ; CHECK: t2STRs killed renamable $r12, renamable $r0, killed renamable $r3, 2, 14 /* CC::al */, $noreg - ; CHECK: renamable $r1 = t2LDRs killed renamable $r1, renamable $r2, 2, 14 /* CC::al */, $noreg - ; CHECK: renamable $r1 = nsw t2MUL killed renamable $lr, killed renamable $r1, 14 /* CC::al */, $noreg - ; CHECK: t2STRs killed renamable $r1, killed renamable $r0, killed renamable $r2, 2, 14 /* CC::al */, $noreg - ; CHECK: $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r8, def $r9, def $r10 - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc + ; CHECK-NEXT: successors: %bb.4(0x30000000), %bb.1(0x50000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r8, $r9, $r10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 20 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r6, -12 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r5, -16 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -20 + ; CHECK-NEXT: dead $r7 = frame-setup tADDrSPi $sp, 3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa $r7, 8 + ; CHECK-NEXT: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r8, killed $r9, killed $r10 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r10, -24 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r9, -28 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r8, -32 + ; CHECK-NEXT: tCMPi8 renamable $r3, 2, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: $r12 = tMOVr $r3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: t2IT 1, 8, implicit-def $itstate + ; CHECK-NEXT: $r12 = t2MOVi 4, 1 /* CC::ne */, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate + ; CHECK-NEXT: tCMPi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: t2IT 0, 8, implicit-def $itstate + ; CHECK-NEXT: $r12 = t2MOVi 1, 0 /* CC::eq */, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate + ; CHECK-NEXT: renamable $r3 = t2LSLrr killed renamable $r2, killed renamable $r12, 14 /* CC::al */, $noreg, def $cpsr + ; CHECK-NEXT: tBcc %bb.4, 0 /* CC::eq */, killed $cpsr + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1 (%ir-block.11): + ; CHECK-NEXT: successors: %bb.2(0x55555555), %bb.5(0x2aaaaaab) + ; CHECK-NEXT: liveins: $r0, $r1, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r2 = t2ADDrs renamable $r1, renamable $r3, 18, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: tCMPr killed renamable $r2, renamable $r0, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: t2IT 8, 4, implicit-def $itstate + ; CHECK-NEXT: renamable $r2 = t2ADDrs renamable $r0, renamable $r3, 18, 8 /* CC::hi */, $cpsr, $noreg, implicit $itstate + ; CHECK-NEXT: tCMPr killed renamable $r2, renamable $r1, 8 /* CC::hi */, killed $cpsr, implicit-def $cpsr, implicit killed $itstate + ; CHECK-NEXT: tBcc %bb.5, 8 /* CC::hi */, killed $cpsr + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2 (%ir-block.32): + ; CHECK-NEXT: successors: %bb.3(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $r2 = tMOVr $r0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3 (%ir-block.33): + ; CHECK-NEXT: successors: %bb.3(0x7c000000), %bb.4(0x04000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg, $noreg + ; CHECK-NEXT: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 0, $noreg, $noreg + ; CHECK-NEXT: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 0, killed $noreg, $noreg + ; CHECK-NEXT: $r0 = tMOVr $r2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4 (%ir-block.64): + ; CHECK-NEXT: $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r8, def $r9, def $r10 + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.5 (%ir-block.23): + ; CHECK-NEXT: successors: %bb.6(0x40000000), %bb.7(0x40000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi3 renamable $r3, 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r12 = t2ANDri renamable $r3, 2, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: tCMPi8 killed renamable $r2, 3, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: tBcc %bb.7, 2 /* CC::hs */, killed $cpsr + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.6: + ; CHECK-NEXT: successors: %bb.9(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: tB %bb.9, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.7 (%ir-block.31): + ; CHECK-NEXT: successors: %bb.8(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r3, $r12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r2 = t2BICri killed renamable $r3, 2, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.8 (%ir-block.65): + ; CHECK-NEXT: successors: %bb.8(0x7c000000), %bb.9(0x04000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r4 = tLDRr renamable $r1, $r2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r3, dead $cpsr = nuw tADDi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r5 = tLDRr renamable $r0, $r2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r4, dead $cpsr = nsw tMUL killed renamable $r5, killed renamable $r4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r5, dead $cpsr = tADDrr renamable $r0, renamable $r2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $r10, $r8 = t2LDRDi8 $r5, 4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r9 = t2LDRi12 renamable $r5, 12, 14 /* CC::al */, $noreg + ; CHECK-NEXT: tSTRr killed renamable $r4, renamable $r0, $r2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r4, dead $cpsr = tADDrr renamable $r1, renamable $r2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r2, dead $cpsr = tADDi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r6 = tLDRi renamable $r4, 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r6 = nsw t2MUL killed renamable $r10, killed renamable $r6, 14 /* CC::al */, $noreg + ; CHECK-NEXT: tSTRi killed renamable $r6, renamable $r5, 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r6 = tLDRi renamable $r4, 2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r6 = nsw t2MUL killed renamable $r8, killed renamable $r6, 14 /* CC::al */, $noreg + ; CHECK-NEXT: tSTRi killed renamable $r6, renamable $r5, 2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r4 = tLDRi killed renamable $r4, 3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r4 = nsw t2MUL killed renamable $r9, killed renamable $r4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: tSTRi killed renamable $r4, killed renamable $r5, 3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.9 (%ir-block.49): + ; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.10(0x40000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r3, $r12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: t2CMPri killed renamable $r12, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: tBcc %bb.4, 0 /* CC::eq */, killed $cpsr + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.10 (%ir-block.52): + ; CHECK-NEXT: liveins: $r0, $r1, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r12 = t2LDRs renamable $r1, renamable $r3, 2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r2 = t2LDRs renamable $r0, renamable $r3, 2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r12 = nsw t2MUL killed renamable $r2, killed renamable $r12, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r2, dead $cpsr = tADDi3 renamable $r3, 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $lr = t2LDRs renamable $r0, renamable $r2, 2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: t2STRs killed renamable $r12, renamable $r0, killed renamable $r3, 2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r1 = t2LDRs killed renamable $r1, renamable $r2, 2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r1 = nsw t2MUL killed renamable $lr, killed renamable $r1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: t2STRs killed renamable $r1, killed renamable $r0, killed renamable $r2, 2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r8, def $r9, def $r10 + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc bb.0 (%ir-block.4): successors: %bb.4(0x30000000), %bb.1(0x50000000) liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $lr, $r8, $r9, $r10 diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/multi-cond-iter-count.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/multi-cond-iter-count.mir index 5ce9a63025d04..be255a0ee10de 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/multi-cond-iter-count.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/multi-cond-iter-count.mir @@ -78,40 +78,46 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: multi_cond_iter_count ; CHECK: bb.0 (%ir-block.4): - ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7 - ; CHECK: tCMPi8 renamable $r3, 2, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: $r12 = tMOVr $r3, 14 /* CC::al */, $noreg - ; CHECK: t2IT 1, 8, implicit-def $itstate - ; CHECK: $r12 = t2MOVi 4, 1 /* CC::ne */, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate - ; CHECK: tCMPi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 0, 8, implicit-def $itstate - ; CHECK: $r12 = t2MOVi 1, 0 /* CC::eq */, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate - ; CHECK: renamable $r2 = t2LSLrr killed renamable $r2, killed renamable $r12, 14 /* CC::al */, $noreg, def $cpsr - ; CHECK: t2IT 0, 8, implicit-def $itstate - ; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate - ; CHECK: bb.1 (%ir-block.17): - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2 - ; CHECK: $r3 = tMOVr $r0, 14 /* CC::al */, $noreg - ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2 - ; CHECK: bb.2 (%ir-block.18): - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $lr, $r0, $r1, $r3 - ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg, $noreg - ; CHECK: renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 0, $noreg, $noreg - ; CHECK: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 0, killed $noreg, $noreg - ; CHECK: $r0 = tMOVr $r3, 14 /* CC::al */, $noreg - ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 - ; CHECK: bb.3 (%ir-block.34): - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $r7 + ; CHECK-NEXT: tCMPi8 renamable $r3, 2, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: $r12 = tMOVr $r3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: t2IT 1, 8, implicit-def $itstate + ; CHECK-NEXT: $r12 = t2MOVi 4, 1 /* CC::ne */, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate + ; CHECK-NEXT: tCMPi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: t2IT 0, 8, implicit-def $itstate + ; CHECK-NEXT: $r12 = t2MOVi 1, 0 /* CC::eq */, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate + ; CHECK-NEXT: renamable $r2 = t2LSLrr killed renamable $r2, killed renamable $r12, 14 /* CC::al */, $noreg, def $cpsr + ; CHECK-NEXT: t2IT 0, 8, implicit-def $itstate + ; CHECK-NEXT: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1 (%ir-block.17): + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $r3 = tMOVr $r0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2 (%ir-block.18): + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg, $noreg + ; CHECK-NEXT: renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 0, $noreg, $noreg + ; CHECK-NEXT: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 0, killed $noreg, $noreg + ; CHECK-NEXT: $r0 = tMOVr $r3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3 (%ir-block.34): + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc bb.0 (%ir-block.4): successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $r3, $lr diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/multiblock-massive.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/multiblock-massive.mir index f4377a3996125..06dae765c8e33 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/multiblock-massive.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/multiblock-massive.mir @@ -42,16 +42,12 @@ br i1 %exitcond, label %for.cond.cleanup, label %for.body } - ; Function Attrs: nounwind declare i32 @llvm.arm.space(i32 immarg, i32) #0 - ; Function Attrs: noduplicate nounwind declare i32 @llvm.start.loop.iterations.i32(i32) #1 - ; Function Attrs: noduplicate nounwind declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #1 - ; Function Attrs: nounwind declare void @llvm.stackprotector(ptr, ptr) #0 attributes #0 = { nounwind } @@ -107,49 +103,59 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: size_limit ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 - ; CHECK: tCMPi8 $r3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 0, 8, implicit-def $itstate - ; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $pc, implicit killed $itstate - ; CHECK: bb.1.for.body.preheader: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: dead $lr = tMOVr $r3, 14 /* CC::al */, $noreg - ; CHECK: $lr = tMOVr killed $r3, 14 /* CC::al */, $noreg - ; CHECK: tB %bb.2, 14 /* CC::al */, $noreg - ; CHECK: bb.2.for.end: - ; CHECK: successors: %bb.5(0x04000000), %bb.3(0x7c000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2 - ; CHECK: renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg - ; CHECK: renamable $r2, dead $cpsr = tADDi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg - ; CHECK: renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 4, 14 /* CC::al */, $noreg - ; CHECK: renamable $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, def $cpsr - ; CHECK: tBcc %bb.3, 1 /* CC::ne */, killed $cpsr - ; CHECK: t2B %bb.5, 14 /* CC::al */, $noreg - ; CHECK: bb.3.for.body: - ; CHECK: successors: %bb.4(0x50000000), %bb.2(0x30000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2 - ; CHECK: dead renamable $r3 = SPACE 3072, undef renamable $r0 - ; CHECK: renamable $r3 = tLDRi renamable $r1, 0, 14 /* CC::al */, $noreg :: (load (s32) from %ir.lsr.iv4) - ; CHECK: renamable $r12 = t2LDRi12 renamable $r2, 0, 14 /* CC::al */, $noreg :: (load (s32) from %ir.lsr.iv2) - ; CHECK: tCMPi8 renamable $r3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: renamable $r4 = nsw t2MUL renamable $r12, renamable $r3, 14 /* CC::al */, $noreg - ; CHECK: tSTRi killed renamable $r4, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.lsr.iv1) - ; CHECK: t2Bcc %bb.2, 0 /* CC::eq */, killed $cpsr - ; CHECK: bb.4.middle.block: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r12 - ; CHECK: renamable $r3 = t2UDIV killed renamable $r12, killed renamable $r3, 14 /* CC::al */, $noreg - ; CHECK: tSTRi killed renamable $r3, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.lsr.iv1) - ; CHECK: dead renamable $r3 = SPACE 1024, undef renamable $r0 - ; CHECK: t2B %bb.2, 14 /* CC::al */, $noreg - ; CHECK: bb.5.for.cond.cleanup: - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -8 + ; CHECK-NEXT: tCMPi8 $r3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: t2IT 0, 8, implicit-def $itstate + ; CHECK-NEXT: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $pc, implicit killed $itstate + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.for.body.preheader: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: dead $lr = tMOVr $r3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $lr = tMOVr killed $r3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: tB %bb.2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.for.end: + ; CHECK-NEXT: successors: %bb.5(0x04000000), %bb.3(0x7c000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r2, dead $cpsr = tADDi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, def $cpsr + ; CHECK-NEXT: tBcc %bb.3, 1 /* CC::ne */, killed $cpsr + ; CHECK-NEXT: t2B %bb.5, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.for.body: + ; CHECK-NEXT: successors: %bb.4(0x50000000), %bb.2(0x30000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: dead renamable $r3 = SPACE 3072, undef renamable $r0 + ; CHECK-NEXT: renamable $r3 = tLDRi renamable $r1, 0, 14 /* CC::al */, $noreg :: (load (s32) from %ir.lsr.iv4) + ; CHECK-NEXT: renamable $r12 = t2LDRi12 renamable $r2, 0, 14 /* CC::al */, $noreg :: (load (s32) from %ir.lsr.iv2) + ; CHECK-NEXT: tCMPi8 renamable $r3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: renamable $r4 = nsw t2MUL renamable $r12, renamable $r3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: tSTRi killed renamable $r4, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.lsr.iv1) + ; CHECK-NEXT: t2Bcc %bb.2, 0 /* CC::eq */, killed $cpsr + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4.middle.block: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r3 = t2UDIV killed renamable $r12, killed renamable $r3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: tSTRi killed renamable $r3, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.lsr.iv1) + ; CHECK-NEXT: dead renamable $r3 = SPACE 1024, undef renamable $r0 + ; CHECK-NEXT: t2B %bb.2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.5.for.cond.cleanup: + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $r3, $r4, $lr diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/multiple-do-loops.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/multiple-do-loops.mir index 6e8ad0877f1c2..a86eec780b7f4 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/multiple-do-loops.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/multiple-do-loops.mir @@ -80,7 +80,6 @@ for.cond.cleanup6: ; preds = %vector.body38, %entry, %for.cond4.preheader ret void } - ; Function Attrs: nofree norecurse nounwind define dso_local arm_aapcs_vfpcc void @test2(i32* noalias nocapture %a, i32* nocapture readonly %b, i32* nocapture readonly %c, i32 %N) local_unnamed_addr { entry: %div = lshr i32 %N, 1 @@ -160,7 +159,6 @@ for.cond.cleanup6: ; preds = %vector.body38, %for.cond4.preheader ret void } - ; Function Attrs: nofree norecurse nounwind define dso_local arm_aapcs_vfpcc void @test3(i32* noalias nocapture %a, i32* nocapture readonly %b, i32* nocapture readonly %c, i32 %N) local_unnamed_addr { entry: %cmp54 = icmp eq i32 %N, 0 @@ -346,60 +344,72 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: test1 ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.6(0x30000000), %bb.1(0x50000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r8 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 20 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -12 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -16 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -20 - ; CHECK: dead $r7 = frame-setup tADDrSPi $sp, 3, 14 /* CC::al */, $noreg - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa $r7, 8 - ; CHECK: early-clobber $sp = frame-setup t2STR_PRE killed $r8, $sp, -4, 14 /* CC::al */, $noreg - ; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -24 - ; CHECK: tCMPi8 renamable $r3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: tBcc %bb.6, 0 /* CC::eq */, killed $cpsr - ; CHECK: bb.1.vector.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: $r8 = tMOVr $r0, 14 /* CC::al */, $noreg - ; CHECK: $r5 = tMOVr $r2, 14 /* CC::al */, $noreg - ; CHECK: $r4 = tMOVr $r3, 14 /* CC::al */, $noreg - ; CHECK: $r6 = tMOVr $r1, 14 /* CC::al */, $noreg - ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r4 - ; CHECK: bb.2.vector.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r5, $r6, $r8 - ; CHECK: renamable $r6, renamable $q0 = MVE_VLDRWU32_post killed renamable $r6, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv6264, align 4) - ; CHECK: renamable $r5, renamable $q1 = MVE_VLDRWU32_post killed renamable $r5, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv6567, align 4) - ; CHECK: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: renamable $r8 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r8, 16, 0, killed $noreg, $noreg :: (store (s128) into %ir.lsr.iv6870, align 4) - ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 - ; CHECK: bb.3.for.cond4.preheader: - ; CHECK: successors: %bb.6(0x30000000), %bb.4(0x50000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: tCBZ $r3, %bb.6 - ; CHECK: bb.4.vector.ph39: - ; CHECK: successors: %bb.5(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: $r12 = tMOVr $r0, 14 /* CC::al */, $noreg - ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3 - ; CHECK: bb.5.vector.body38: - ; CHECK: successors: %bb.5(0x7c000000), %bb.6(0x04000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r12 - ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv55, align 4) - ; CHECK: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv5658, align 4) - ; CHECK: renamable $r12, renamable $q2 = MVE_VLDRWU32_post killed renamable $r12, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv5961, align 4) - ; CHECK: renamable $q0 = MVE_VEOR killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: renamable $q0 = nsw MVE_VADDi32 killed renamable $q2, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 0, killed $noreg, $noreg :: (store (s128) into %ir.lsr.iv5961, align 4) - ; CHECK: $r0 = tMOVr $r12, 14 /* CC::al */, $noreg - ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.5 - ; CHECK: bb.6.for.cond.cleanup6: - ; CHECK: $r8, $sp = t2LDR_POST $sp, 4, 14 /* CC::al */, $noreg - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc + ; CHECK-NEXT: successors: %bb.6(0x30000000), %bb.1(0x50000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 20 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r6, -12 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r5, -16 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -20 + ; CHECK-NEXT: dead $r7 = frame-setup tADDrSPi $sp, 3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa $r7, 8 + ; CHECK-NEXT: early-clobber $sp = frame-setup t2STR_PRE killed $r8, $sp, -4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r8, -24 + ; CHECK-NEXT: tCMPi8 renamable $r3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: tBcc %bb.6, 0 /* CC::eq */, killed $cpsr + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.vector.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $r8 = tMOVr $r0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $r5 = tMOVr $r2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $r4 = tMOVr $r3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $r6 = tMOVr $r1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.vector.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r5, $r6, $r8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r6, renamable $q0 = MVE_VLDRWU32_post killed renamable $r6, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv6264, align 4) + ; CHECK-NEXT: renamable $r5, renamable $q1 = MVE_VLDRWU32_post killed renamable $r5, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv6567, align 4) + ; CHECK-NEXT: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: renamable $r8 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r8, 16, 0, killed $noreg, $noreg :: (store (s128) into %ir.lsr.iv6870, align 4) + ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.for.cond4.preheader: + ; CHECK-NEXT: successors: %bb.6(0x30000000), %bb.4(0x50000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: tCBZ $r3, %bb.6 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4.vector.ph39: + ; CHECK-NEXT: successors: %bb.5(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $r12 = tMOVr $r0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.5.vector.body38: + ; CHECK-NEXT: successors: %bb.5(0x7c000000), %bb.6(0x04000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv55, align 4) + ; CHECK-NEXT: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv5658, align 4) + ; CHECK-NEXT: renamable $r12, renamable $q2 = MVE_VLDRWU32_post killed renamable $r12, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv5961, align 4) + ; CHECK-NEXT: renamable $q0 = MVE_VEOR killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: renamable $q0 = nsw MVE_VADDi32 killed renamable $q2, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 0, killed $noreg, $noreg :: (store (s128) into %ir.lsr.iv5961, align 4) + ; CHECK-NEXT: $r0 = tMOVr $r12, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.5 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.6.for.cond.cleanup6: + ; CHECK-NEXT: $r8, $sp = t2LDR_POST $sp, 4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc bb.0.entry: successors: %bb.6(0x30000000), %bb.1(0x50000000) liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $lr, $r8 @@ -549,61 +559,73 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: test2 ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r8 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 20 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -12 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -16 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -20 - ; CHECK: dead $r7 = frame-setup tADDrSPi $sp, 3, 14 /* CC::al */, $noreg - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa $r7, 8 - ; CHECK: early-clobber $sp = frame-setup t2STR_PRE killed $r8, $sp, -4, 14 /* CC::al */, $noreg - ; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -24 - ; CHECK: renamable $r6, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg - ; CHECK: t2CMPrs killed renamable $r6, renamable $r3, 11, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: tBcc %bb.3, 0 /* CC::eq */, killed $cpsr - ; CHECK: bb.1.vector.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: renamable $r4, dead $cpsr = tLSRri renamable $r3, 1, 14 /* CC::al */, $noreg - ; CHECK: $r8 = tMOVr $r0, 14 /* CC::al */, $noreg - ; CHECK: $r5 = tMOVr $r1, 14 /* CC::al */, $noreg - ; CHECK: $r6 = tMOVr $r2, 14 /* CC::al */, $noreg - ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r4 - ; CHECK: bb.2.vector.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r5, $r6, $r8 - ; CHECK: renamable $r5, renamable $q0 = MVE_VLDRWU32_post killed renamable $r5, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv6264, align 4) - ; CHECK: renamable $r6, renamable $q1 = MVE_VLDRWU32_post killed renamable $r6, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv6567, align 4) - ; CHECK: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: renamable $r8 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r8, 16, 0, killed $noreg, $noreg :: (store (s128) into %ir.lsr.iv6870, align 4) - ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 - ; CHECK: bb.3.for.cond4.preheader: - ; CHECK: successors: %bb.6(0x30000000), %bb.4(0x50000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: tCBZ $r3, %bb.6 - ; CHECK: bb.4.vector.ph39: - ; CHECK: successors: %bb.5(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: $r4 = tMOVr $r0, 14 /* CC::al */, $noreg - ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3 - ; CHECK: bb.5.vector.body38: - ; CHECK: successors: %bb.5(0x7c000000), %bb.6(0x04000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r4 - ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv55, align 4) - ; CHECK: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv5658, align 4) - ; CHECK: renamable $r4, renamable $q2 = MVE_VLDRWU32_post killed renamable $r4, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv5961, align 4) - ; CHECK: renamable $q0 = MVE_VEOR killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: renamable $q0 = nsw MVE_VADDi32 killed renamable $q2, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 0, killed $noreg, $noreg :: (store (s128) into %ir.lsr.iv5961, align 4) - ; CHECK: $r0 = tMOVr $r4, 14 /* CC::al */, $noreg - ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.5 - ; CHECK: bb.6.for.cond.cleanup6: - ; CHECK: $r8, $sp = t2LDR_POST $sp, 4, 14 /* CC::al */, $noreg - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc + ; CHECK-NEXT: successors: %bb.3(0x30000000), %bb.1(0x50000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 20 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r6, -12 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r5, -16 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -20 + ; CHECK-NEXT: dead $r7 = frame-setup tADDrSPi $sp, 3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa $r7, 8 + ; CHECK-NEXT: early-clobber $sp = frame-setup t2STR_PRE killed $r8, $sp, -4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r8, -24 + ; CHECK-NEXT: renamable $r6, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: t2CMPrs killed renamable $r6, renamable $r3, 11, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: tBcc %bb.3, 0 /* CC::eq */, killed $cpsr + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.vector.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r4, dead $cpsr = tLSRri renamable $r3, 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $r8 = tMOVr $r0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $r5 = tMOVr $r1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $r6 = tMOVr $r2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.vector.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r5, $r6, $r8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r5, renamable $q0 = MVE_VLDRWU32_post killed renamable $r5, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv6264, align 4) + ; CHECK-NEXT: renamable $r6, renamable $q1 = MVE_VLDRWU32_post killed renamable $r6, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv6567, align 4) + ; CHECK-NEXT: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: renamable $r8 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r8, 16, 0, killed $noreg, $noreg :: (store (s128) into %ir.lsr.iv6870, align 4) + ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.for.cond4.preheader: + ; CHECK-NEXT: successors: %bb.6(0x30000000), %bb.4(0x50000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: tCBZ $r3, %bb.6 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4.vector.ph39: + ; CHECK-NEXT: successors: %bb.5(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $r4 = tMOVr $r0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.5.vector.body38: + ; CHECK-NEXT: successors: %bb.5(0x7c000000), %bb.6(0x04000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv55, align 4) + ; CHECK-NEXT: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv5658, align 4) + ; CHECK-NEXT: renamable $r4, renamable $q2 = MVE_VLDRWU32_post killed renamable $r4, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv5961, align 4) + ; CHECK-NEXT: renamable $q0 = MVE_VEOR killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: renamable $q0 = nsw MVE_VADDi32 killed renamable $q2, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 0, killed $noreg, $noreg :: (store (s128) into %ir.lsr.iv5961, align 4) + ; CHECK-NEXT: $r0 = tMOVr $r4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.5 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.6.for.cond.cleanup6: + ; CHECK-NEXT: $r8, $sp = t2LDR_POST $sp, 4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc bb.0.entry: successors: %bb.3(0x30000000), %bb.1(0x50000000) liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $lr, $r8 @@ -763,88 +785,106 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: test3 ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.9(0x30000000), %bb.1(0x50000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r8, $r9, $r10 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 20 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -12 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -16 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -20 - ; CHECK: dead $r7 = frame-setup tADDrSPi $sp, 3, 14 /* CC::al */, $noreg - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa $r7, 8 - ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r8, killed $r9, killed $r10 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r10, -24 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r9, -28 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -32 - ; CHECK: tCMPi8 renamable $r3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: tBcc %bb.9, 0 /* CC::eq */, killed $cpsr - ; CHECK: bb.1.vector.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: $r8 = tMOVr $r0, 14 /* CC::al */, $noreg - ; CHECK: $r5 = tMOVr $r2, 14 /* CC::al */, $noreg - ; CHECK: $r4 = tMOVr $r3, 14 /* CC::al */, $noreg - ; CHECK: $r6 = tMOVr $r1, 14 /* CC::al */, $noreg - ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r4 - ; CHECK: bb.2.vector.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r5, $r6, $r8 - ; CHECK: renamable $r6, renamable $q0 = MVE_VLDRWU32_post killed renamable $r6, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv117119, align 4) - ; CHECK: renamable $r5, renamable $q1 = MVE_VLDRWU32_post killed renamable $r5, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv120122, align 4) - ; CHECK: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: renamable $r8 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r8, 16, 0, killed $noreg, $noreg :: (store (s128) into %ir.lsr.iv123125, align 4) - ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 - ; CHECK: bb.3.for.cond4.preheader: - ; CHECK: successors: %bb.6(0x30000000), %bb.4(0x50000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: renamable $r6, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg - ; CHECK: t2CMPrs killed renamable $r6, renamable $r3, 11, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: tBcc %bb.6, 0 /* CC::eq */, killed $cpsr - ; CHECK: bb.4.vector.ph66: - ; CHECK: successors: %bb.5(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: renamable $r5, dead $cpsr = tLSRri renamable $r3, 1, 14 /* CC::al */, $noreg - ; CHECK: $r10 = tMOVr $r0, 14 /* CC::al */, $noreg - ; CHECK: $r9 = tMOVr $r2, 14 /* CC::al */, $noreg - ; CHECK: $r4 = tMOVr $r1, 14 /* CC::al */, $noreg - ; CHECK: $r6 = tMOVr $r0, 14 /* CC::al */, $noreg - ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r5 - ; CHECK: bb.5.vector.body65: - ; CHECK: successors: %bb.5(0x7c000000), %bb.6(0x04000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r6, $r9, $r10 - ; CHECK: renamable $r4, renamable $q0 = MVE_VLDRWU32_post killed renamable $r4, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv108110, align 4) - ; CHECK: renamable $r9, renamable $q1 = MVE_VLDRWU32_post killed renamable $r9, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv111113, align 4) - ; CHECK: renamable $r6, renamable $q2 = MVE_VLDRWU32_post killed renamable $r6, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv114116, align 4) - ; CHECK: renamable $q0 = MVE_VEOR killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: renamable $q0 = nsw MVE_VADDi32 killed renamable $q2, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r10, 0, 0, killed $noreg, $noreg :: (store (s128) into %ir.lsr.iv114116, align 4) - ; CHECK: $r10 = tMOVr $r6, 14 /* CC::al */, $noreg - ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.5 - ; CHECK: bb.6.for.cond15.preheader: - ; CHECK: successors: %bb.9(0x30000000), %bb.7(0x50000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: tCBZ $r3, %bb.9 - ; CHECK: bb.7.vector.ph85: - ; CHECK: successors: %bb.8(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: $r5 = tMOVr $r0, 14 /* CC::al */, $noreg - ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3 - ; CHECK: bb.8.vector.body84: - ; CHECK: successors: %bb.8(0x7c000000), %bb.9(0x04000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r5 - ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv101, align 4) - ; CHECK: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv102104, align 4) - ; CHECK: renamable $r5, renamable $q2 = MVE_VLDRWU32_post killed renamable $r5, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv105107, align 4) - ; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: renamable $q0 = MVE_VSUBi32 killed renamable $q2, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 0, killed $noreg, $noreg :: (store (s128) into %ir.lsr.iv105107, align 4) - ; CHECK: $r0 = tMOVr $r5, 14 /* CC::al */, $noreg - ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.8 - ; CHECK: bb.9.for.cond.cleanup17: - ; CHECK: $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r8, def $r9, def $r10 - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc + ; CHECK-NEXT: successors: %bb.9(0x30000000), %bb.1(0x50000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r8, $r9, $r10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 20 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r6, -12 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r5, -16 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -20 + ; CHECK-NEXT: dead $r7 = frame-setup tADDrSPi $sp, 3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa $r7, 8 + ; CHECK-NEXT: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r8, killed $r9, killed $r10 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r10, -24 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r9, -28 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r8, -32 + ; CHECK-NEXT: tCMPi8 renamable $r3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: tBcc %bb.9, 0 /* CC::eq */, killed $cpsr + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.vector.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $r8 = tMOVr $r0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $r5 = tMOVr $r2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $r4 = tMOVr $r3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $r6 = tMOVr $r1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.vector.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r5, $r6, $r8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r6, renamable $q0 = MVE_VLDRWU32_post killed renamable $r6, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv117119, align 4) + ; CHECK-NEXT: renamable $r5, renamable $q1 = MVE_VLDRWU32_post killed renamable $r5, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv120122, align 4) + ; CHECK-NEXT: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: renamable $r8 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r8, 16, 0, killed $noreg, $noreg :: (store (s128) into %ir.lsr.iv123125, align 4) + ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.for.cond4.preheader: + ; CHECK-NEXT: successors: %bb.6(0x30000000), %bb.4(0x50000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r6, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: t2CMPrs killed renamable $r6, renamable $r3, 11, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: tBcc %bb.6, 0 /* CC::eq */, killed $cpsr + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4.vector.ph66: + ; CHECK-NEXT: successors: %bb.5(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r5, dead $cpsr = tLSRri renamable $r3, 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $r10 = tMOVr $r0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $r9 = tMOVr $r2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $r4 = tMOVr $r1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $r6 = tMOVr $r0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r5 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.5.vector.body65: + ; CHECK-NEXT: successors: %bb.5(0x7c000000), %bb.6(0x04000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r6, $r9, $r10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r4, renamable $q0 = MVE_VLDRWU32_post killed renamable $r4, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv108110, align 4) + ; CHECK-NEXT: renamable $r9, renamable $q1 = MVE_VLDRWU32_post killed renamable $r9, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv111113, align 4) + ; CHECK-NEXT: renamable $r6, renamable $q2 = MVE_VLDRWU32_post killed renamable $r6, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv114116, align 4) + ; CHECK-NEXT: renamable $q0 = MVE_VEOR killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: renamable $q0 = nsw MVE_VADDi32 killed renamable $q2, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: MVE_VSTRWU32 killed renamable $q0, killed renamable $r10, 0, 0, killed $noreg, $noreg :: (store (s128) into %ir.lsr.iv114116, align 4) + ; CHECK-NEXT: $r10 = tMOVr $r6, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.5 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.6.for.cond15.preheader: + ; CHECK-NEXT: successors: %bb.9(0x30000000), %bb.7(0x50000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: tCBZ $r3, %bb.9 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.7.vector.ph85: + ; CHECK-NEXT: successors: %bb.8(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $r5 = tMOVr $r0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.8.vector.body84: + ; CHECK-NEXT: successors: %bb.8(0x7c000000), %bb.9(0x04000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r5 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv101, align 4) + ; CHECK-NEXT: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv102104, align 4) + ; CHECK-NEXT: renamable $r5, renamable $q2 = MVE_VLDRWU32_post killed renamable $r5, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv105107, align 4) + ; CHECK-NEXT: renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: renamable $q0 = MVE_VSUBi32 killed renamable $q2, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 0, killed $noreg, $noreg :: (store (s128) into %ir.lsr.iv105107, align 4) + ; CHECK-NEXT: $r0 = tMOVr $r5, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.9.for.cond.cleanup17: + ; CHECK-NEXT: $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r8, def $r9, def $r10 + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc bb.0.entry: successors: %bb.9(0x30000000), %bb.1(0x50000000) liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $lr, $r8, $r9, $r10 diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/no-vpsel-liveout.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/no-vpsel-liveout.mir index 7d898653caab0..2be11258eb258 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/no-vpsel-liveout.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/no-vpsel-liveout.mir @@ -102,33 +102,40 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: no_vpsel_liveout ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 - ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 0, 4, implicit-def $itstate - ; CHECK: renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate - ; CHECK: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate - ; CHECK: bb.1.vector.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2 - ; CHECK: bb.2.vector.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $lr, $q0, $r0, $r1 - ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 0, $noreg, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) - ; CHECK: renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 0, killed $noreg, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2) - ; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1 - ; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 - ; CHECK: bb.3.middle.block: - ; CHECK: liveins: $q0 - ; CHECK: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: t2IT 0, 4, implicit-def $itstate + ; CHECK-NEXT: renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate + ; CHECK-NEXT: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.vector.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.vector.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $lr, $q0, $r0, $r1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 0, $noreg, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) + ; CHECK-NEXT: renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 0, killed $noreg, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2) + ; CHECK-NEXT: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1 + ; CHECK-NEXT: renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.middle.block: + ; CHECK-NEXT: liveins: $q0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $lr, $r7 diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/non-masked-store.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/non-masked-store.mir index 3ee066a9ffe2e..af80a1f6e80cf 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/non-masked-store.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/non-masked-store.mir @@ -99,38 +99,44 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: non_masked_store ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7 - ; CHECK: tCMPi8 renamable $r3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 0, 8, implicit-def $itstate - ; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate - ; CHECK: bb.1.vector.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: renamable $r12 = t2ADDri renamable $r3, 15, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r12 = t2BICri killed renamable $r12, 15, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 16, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 35, 14 /* CC::al */, $noreg, $noreg - ; CHECK: bb.2.vector.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 - ; CHECK: renamable $vpr = MVE_VCTP8 renamable $r3, 0, $noreg, $noreg - ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 16, 14 /* CC::al */, $noreg - ; CHECK: MVE_VPST 4, implicit $vpr - ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRBU8_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv15, align 1) - ; CHECK: renamable $r2, renamable $q1 = MVE_VLDRBU8_post killed renamable $r2, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1618, align 1) - ; CHECK: renamable $q0 = MVE_VADDi8 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: renamable $r0 = MVE_VSTRBU8_post killed renamable $q0, killed renamable $r0, 16, 1, $noreg, $noreg :: (store (s128) into %ir.lsr.iv1921, align 1) - ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 - ; CHECK: bb.3.for.cond.cleanup: - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $r7 + ; CHECK-NEXT: tCMPi8 renamable $r3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: t2IT 0, 8, implicit-def $itstate + ; CHECK-NEXT: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.vector.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r12 = t2ADDri renamable $r3, 15, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r12 = t2BICri killed renamable $r12, 15, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r12, 16, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 35, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.vector.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $vpr = MVE_VCTP8 renamable $r3, 0, $noreg, $noreg + ; CHECK-NEXT: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 16, 14 /* CC::al */, $noreg + ; CHECK-NEXT: MVE_VPST 4, implicit $vpr + ; CHECK-NEXT: renamable $r1, renamable $q0 = MVE_VLDRBU8_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv15, align 1) + ; CHECK-NEXT: renamable $r2, renamable $q1 = MVE_VLDRBU8_post killed renamable $r2, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1618, align 1) + ; CHECK-NEXT: renamable $q0 = MVE_VADDi8 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: renamable $r0 = MVE_VSTRBU8_post killed renamable $q0, killed renamable $r0, 16, 1, $noreg, $noreg :: (store (s128) into %ir.lsr.iv1921, align 1) + ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.for.cond.cleanup: + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $r3, $lr diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/predicated-invariant.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/predicated-invariant.mir index 31b7ee2c4dad1..550602c1a9671 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/predicated-invariant.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/predicated-invariant.mir @@ -74,34 +74,43 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: invariant_predicated_add_use ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000) - ; CHECK: liveins: $lr, $r0, $r2, $r7 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: tCBZ $r2, %bb.3 - ; CHECK: bb.1.vector.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r2 - ; CHECK: renamable $r1 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg - ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r1, 0, 0, $noreg, $noreg :: (load (s128) from %fixed-stack.0, align 8) - ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2 - ; CHECK: bb.2.vector.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.4(0x04000000) - ; CHECK: liveins: $lr, $q0, $r0 - ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 0, $noreg, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) - ; CHECK: renamable $q1 = MVE_VADDi32 renamable $q0, killed renamable $q1, 0, killed $noreg, $noreg, undef renamable $q1 - ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 - ; CHECK: tB %bb.4, 14 /* CC::al */, $noreg - ; CHECK: bb.3: - ; CHECK: successors: %bb.4(0x80000000) - ; CHECK: renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q1 - ; CHECK: bb.4.exit: - ; CHECK: liveins: $q1 - ; CHECK: renamable $r0, renamable $r1 = VMOVRRD renamable $d2, 14 /* CC::al */, $noreg - ; CHECK: renamable $r2, renamable $r3 = VMOVRRD killed renamable $d3, 14 /* CC::al */, $noreg, implicit killed $q1 - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0, implicit killed $r1, implicit killed $r2, implicit killed $r3 + ; CHECK-NEXT: successors: %bb.3(0x30000000), %bb.1(0x50000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r2, $r7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: tCBZ $r2, %bb.3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.vector.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r1 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $q0 = MVE_VLDRWU32 killed renamable $r1, 0, 0, $noreg, $noreg :: (load (s128) from %fixed-stack.0, align 8) + ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.vector.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.4(0x04000000) + ; CHECK-NEXT: liveins: $lr, $q0, $r0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 0, $noreg, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) + ; CHECK-NEXT: renamable $q1 = MVE_VADDi32 renamable $q0, killed renamable $q1, 0, killed $noreg, $noreg, undef renamable $q1 + ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2 + ; CHECK-NEXT: tB %bb.4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3: + ; CHECK-NEXT: successors: %bb.4(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4.exit: + ; CHECK-NEXT: liveins: $q1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r0, renamable $r1 = VMOVRRD renamable $d2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r2, renamable $r3 = VMOVRRD killed renamable $d3, 14 /* CC::al */, $noreg, implicit killed $q1 + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0, implicit killed $r1, implicit killed $r2, implicit killed $r3 bb.0.entry: successors: %bb.3(0x30000000), %bb.1(0x50000000) liveins: $r0, $r2, $r7, $lr diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/predicated-liveout.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/predicated-liveout.mir index 13ba3594a22bf..d540ea6f38732 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/predicated-liveout.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/predicated-liveout.mir @@ -78,35 +78,44 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: predicated_livout ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.1(0x40000000), %bb.4(0x40000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: $lr = MVE_WLSTP_16 killed renamable $r2, %bb.4 - ; CHECK: bb.1.for.body.preheader: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1 - ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg - ; CHECK: bb.2.for.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $lr, $q0, $r0, $r1, $r3 - ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $r1, renamable $q1 = MVE_VLDRBU16_post killed renamable $r1, 8, 0, $noreg, $noreg :: (load (s64) from %ir.input_2_cast, align 1) - ; CHECK: renamable $r0, renamable $q2 = MVE_VLDRBU16_post killed renamable $r0, 8, 0, $noreg, $noreg :: (load (s64) from %ir.input_1_cast, align 1) - ; CHECK: renamable $q1 = MVE_VADDi16 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1 - ; CHECK: renamable $q0 = MVE_VADDi16 killed renamable $q1, killed renamable $q0, 0, killed $noreg, $noreg, undef renamable $q0 - ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 - ; CHECK: bb.3.middle.block: - ; CHECK: liveins: $q0 - ; CHECK: renamable $r0 = MVE_VADDVu16no_acc killed renamable $q0, 0, $noreg, $noreg - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 - ; CHECK: bb.4.for.cond.cleanup: - ; CHECK: liveins: $lr - ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg - ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit killed $r0 + ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.4(0x40000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: $lr = MVE_WLSTP_16 killed renamable $r2, %bb.4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.for.body.preheader: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.for.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $lr, $q0, $r0, $r1, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r3, dead $cpsr = tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r1, renamable $q1 = MVE_VLDRBU16_post killed renamable $r1, 8, 0, $noreg, $noreg :: (load (s64) from %ir.input_2_cast, align 1) + ; CHECK-NEXT: renamable $r0, renamable $q2 = MVE_VLDRBU16_post killed renamable $r0, 8, 0, $noreg, $noreg :: (load (s64) from %ir.input_1_cast, align 1) + ; CHECK-NEXT: renamable $q1 = MVE_VADDi16 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1 + ; CHECK-NEXT: renamable $q0 = MVE_VADDi16 killed renamable $q1, killed renamable $q0, 0, killed $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.middle.block: + ; CHECK-NEXT: liveins: $q0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r0 = MVE_VADDVu16no_acc killed renamable $q0, 0, $noreg, $noreg + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4.for.cond.cleanup: + ; CHECK-NEXT: liveins: $lr + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit killed $r0 bb.0.entry: successors: %bb.1(0x40000000), %bb.4(0x40000000) liveins: $r0, $r1, $r2, $lr, $r7 diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/reductions-vpt-liveout.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/reductions-vpt-liveout.mir index 4ac6c60764e12..b2979018a4c11 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/reductions-vpt-liveout.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/reductions-vpt-liveout.mir @@ -190,7 +190,6 @@ ret i32 %res.0.lcssa } - ; Function Attrs: norecurse nounwind readonly define dso_local arm_aapcs_vfpcc i32 @mul_var_i32(i32* nocapture readonly %a, i32* nocapture readonly %b, i32 %N) local_unnamed_addr #0 { entry: %cmp8.not = icmp eq i32 %N, 0 @@ -236,7 +235,6 @@ ret i32 %res.0.lcssa } - ; Function Attrs: norecurse nounwind readonly define dso_local arm_aapcs_vfpcc i32 @add_var_i32(i32* nocapture readonly %a, i32* nocapture readonly %b, i32 %N) local_unnamed_addr #0 { entry: %cmp9.not = icmp eq i32 %N, 0 @@ -318,35 +316,42 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: mul_var_i8 ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 - ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 0, 4, implicit-def $itstate - ; CHECK: renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate - ; CHECK: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate - ; CHECK: bb.1.vector.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7 - ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2 - ; CHECK: bb.2.vector.body (align 4): - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $lr, $q0, $r0, $r1 - ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRBU32_post killed renamable $r0, 4, 0, $noreg, $noreg :: (load (s32) from %ir.lsr.iv13, align 1) - ; CHECK: renamable $r1, renamable $q2 = MVE_VLDRBU32_post killed renamable $r1, 4, 0, $noreg, $noreg :: (load (s32) from %ir.lsr.iv1416, align 1) - ; CHECK: renamable $q1 = nuw nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1 - ; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q0, killed renamable $q1, 0, killed $noreg, $noreg, killed renamable $q0 - ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 - ; CHECK: bb.3.middle.block: - ; CHECK: liveins: $q0 - ; CHECK: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg - ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: t2IT 0, 4, implicit-def $itstate + ; CHECK-NEXT: renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate + ; CHECK-NEXT: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.vector.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $r7 + ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.vector.body (align 4): + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $lr, $q0, $r0, $r1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRBU32_post killed renamable $r0, 4, 0, $noreg, $noreg :: (load (s32) from %ir.lsr.iv13, align 1) + ; CHECK-NEXT: renamable $r1, renamable $q2 = MVE_VLDRBU32_post killed renamable $r1, 4, 0, $noreg, $noreg :: (load (s32) from %ir.lsr.iv1416, align 1) + ; CHECK-NEXT: renamable $q1 = nuw nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1 + ; CHECK-NEXT: renamable $q0 = MVE_VADDi32 killed renamable $q0, killed renamable $q1, 0, killed $noreg, $noreg, killed renamable $q0 + ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.middle.block: + ; CHECK-NEXT: liveins: $q0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg + ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 bb.0.entry: successors: %bb.1(0x50000000) liveins: $r0, $r1, $r2, $lr @@ -424,35 +429,42 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: add_var_i8 ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 - ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 0, 4, implicit-def $itstate - ; CHECK: renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate - ; CHECK: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate - ; CHECK: bb.1.vector.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7 - ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2 - ; CHECK: bb.2.vector.body (align 4): - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $lr, $q0, $r0, $r1 - ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRBU32_post killed renamable $r0, 4, 0, $noreg, $noreg :: (load (s32) from %ir.lsr.iv14, align 1) - ; CHECK: renamable $r1, renamable $q2 = MVE_VLDRBU32_post killed renamable $r1, 4, 0, $noreg, $noreg :: (load (s32) from %ir.lsr.iv1517, align 1) - ; CHECK: renamable $q1 = MVE_VADDi32 renamable $q0, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1 - ; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q2, 0, killed $noreg, $noreg, killed renamable $q0 - ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 - ; CHECK: bb.3.middle.block: - ; CHECK: liveins: $q0 - ; CHECK: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg - ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: t2IT 0, 4, implicit-def $itstate + ; CHECK-NEXT: renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate + ; CHECK-NEXT: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.vector.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $r7 + ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.vector.body (align 4): + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $lr, $q0, $r0, $r1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRBU32_post killed renamable $r0, 4, 0, $noreg, $noreg :: (load (s32) from %ir.lsr.iv14, align 1) + ; CHECK-NEXT: renamable $r1, renamable $q2 = MVE_VLDRBU32_post killed renamable $r1, 4, 0, $noreg, $noreg :: (load (s32) from %ir.lsr.iv1517, align 1) + ; CHECK-NEXT: renamable $q1 = MVE_VADDi32 renamable $q0, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1 + ; CHECK-NEXT: renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q2, 0, killed $noreg, $noreg, killed renamable $q0 + ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.middle.block: + ; CHECK-NEXT: liveins: $q0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg + ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 bb.0.entry: successors: %bb.1(0x50000000) liveins: $r0, $r1, $r2, $lr @@ -531,35 +543,42 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: mul_var_i16 ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 - ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 0, 4, implicit-def $itstate - ; CHECK: renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate - ; CHECK: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate - ; CHECK: bb.1.vector.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7 - ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2 - ; CHECK: bb.2.vector.body (align 4): - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $lr, $q0, $r0, $r1 - ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 0, $noreg, $noreg :: (load (s64) from %ir.lsr.iv13, align 2) - ; CHECK: renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 0, $noreg, $noreg :: (load (s64) from %ir.lsr.iv1416, align 2) - ; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1 - ; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q0, killed renamable $q1, 0, killed $noreg, $noreg, killed renamable $q0 - ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 - ; CHECK: bb.3.middle.block: - ; CHECK: liveins: $q0 - ; CHECK: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg - ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: t2IT 0, 4, implicit-def $itstate + ; CHECK-NEXT: renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate + ; CHECK-NEXT: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.vector.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $r7 + ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.vector.body (align 4): + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $lr, $q0, $r0, $r1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 0, $noreg, $noreg :: (load (s64) from %ir.lsr.iv13, align 2) + ; CHECK-NEXT: renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 0, $noreg, $noreg :: (load (s64) from %ir.lsr.iv1416, align 2) + ; CHECK-NEXT: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1 + ; CHECK-NEXT: renamable $q0 = MVE_VADDi32 killed renamable $q0, killed renamable $q1, 0, killed $noreg, $noreg, killed renamable $q0 + ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.middle.block: + ; CHECK-NEXT: liveins: $q0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg + ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 bb.0.entry: successors: %bb.1(0x50000000) liveins: $r0, $r1, $r2, $lr @@ -637,35 +656,42 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: add_var_i16 ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 - ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 0, 4, implicit-def $itstate - ; CHECK: renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate - ; CHECK: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate - ; CHECK: bb.1.vector.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7 - ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2 - ; CHECK: bb.2.vector.body (align 4): - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $lr, $q0, $r0, $r1 - ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 0, $noreg, $noreg :: (load (s64) from %ir.lsr.iv14, align 2) - ; CHECK: renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 0, $noreg, $noreg :: (load (s64) from %ir.lsr.iv1517, align 2) - ; CHECK: renamable $q1 = MVE_VADDi32 renamable $q0, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1 - ; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q2, 0, killed $noreg, $noreg, killed renamable $q0 - ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 - ; CHECK: bb.3.middle.block: - ; CHECK: liveins: $q0 - ; CHECK: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg - ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: t2IT 0, 4, implicit-def $itstate + ; CHECK-NEXT: renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate + ; CHECK-NEXT: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.vector.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $r7 + ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.vector.body (align 4): + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $lr, $q0, $r0, $r1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 0, $noreg, $noreg :: (load (s64) from %ir.lsr.iv14, align 2) + ; CHECK-NEXT: renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 0, $noreg, $noreg :: (load (s64) from %ir.lsr.iv1517, align 2) + ; CHECK-NEXT: renamable $q1 = MVE_VADDi32 renamable $q0, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1 + ; CHECK-NEXT: renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q2, 0, killed $noreg, $noreg, killed renamable $q0 + ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.middle.block: + ; CHECK-NEXT: liveins: $q0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg + ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 bb.0.entry: successors: %bb.1(0x50000000) liveins: $r0, $r1, $r2, $lr @@ -743,35 +769,42 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: mul_var_i32 ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 - ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 0, 4, implicit-def $itstate - ; CHECK: renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate - ; CHECK: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate - ; CHECK: bb.1.vector.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7 - ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2 - ; CHECK: bb.2.vector.body (align 4): - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $lr, $q0, $r0, $r1 - ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv12, align 4) - ; CHECK: renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv1315, align 4) - ; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1 - ; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q0, killed renamable $q1, 0, killed $noreg, $noreg, killed renamable $q0 - ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 - ; CHECK: bb.3.middle.block: - ; CHECK: liveins: $q0 - ; CHECK: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg - ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: t2IT 0, 4, implicit-def $itstate + ; CHECK-NEXT: renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate + ; CHECK-NEXT: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.vector.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $r7 + ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.vector.body (align 4): + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $lr, $q0, $r0, $r1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv12, align 4) + ; CHECK-NEXT: renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv1315, align 4) + ; CHECK-NEXT: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1 + ; CHECK-NEXT: renamable $q0 = MVE_VADDi32 killed renamable $q0, killed renamable $q1, 0, killed $noreg, $noreg, killed renamable $q0 + ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.middle.block: + ; CHECK-NEXT: liveins: $q0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg + ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 bb.0.entry: successors: %bb.1(0x50000000) liveins: $r0, $r1, $r2, $lr @@ -849,35 +882,42 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: add_var_i32 ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 - ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 0, 4, implicit-def $itstate - ; CHECK: renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate - ; CHECK: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate - ; CHECK: bb.1.vector.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7 - ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2 - ; CHECK: bb.2.vector.body (align 4): - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $lr, $q0, $r0, $r1 - ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv13, align 4) - ; CHECK: renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv1416, align 4) - ; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1 - ; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q2, 0, killed $noreg, $noreg, killed renamable $q0 - ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 - ; CHECK: bb.3.middle.block: - ; CHECK: liveins: $q0 - ; CHECK: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg - ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: t2IT 0, 4, implicit-def $itstate + ; CHECK-NEXT: renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate + ; CHECK-NEXT: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.vector.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $r7 + ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.vector.body (align 4): + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $lr, $q0, $r0, $r1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv13, align 4) + ; CHECK-NEXT: renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv1416, align 4) + ; CHECK-NEXT: renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1 + ; CHECK-NEXT: renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q2, 0, killed $noreg, $noreg, killed renamable $q0 + ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.middle.block: + ; CHECK-NEXT: liveins: $q0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg + ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 bb.0.entry: successors: %bb.1(0x50000000) liveins: $r0, $r1, $r2, $lr diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/remove-elem-moves.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/remove-elem-moves.mir index 26336836c370e..345fec361c69c 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/remove-elem-moves.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/remove-elem-moves.mir @@ -140,85 +140,103 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: remove_mov_lr_chain ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.9(0x30000000), %bb.1(0x50000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r4, $r5, $r7 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 16 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -12 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -16 - ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: tBcc %bb.9, 0 /* CC::eq */, killed $cpsr - ; CHECK: bb.1.while.body.preheader: - ; CHECK: successors: %bb.6(0x40000000), %bb.2(0x40000000) - ; CHECK: liveins: $r0, $r1, $r2 - ; CHECK: tCMPi8 renamable $r2, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: tBcc %bb.6, 3 /* CC::lo */, killed $cpsr - ; CHECK: bb.2.vector.memcheck: - ; CHECK: successors: %bb.3(0x40000000), %bb.6(0x40000000) - ; CHECK: liveins: $r0, $r1, $r2 - ; CHECK: renamable $r3 = t2ADDrs renamable $r0, renamable $r2, 18, 14 /* CC::al */, $noreg, $noreg - ; CHECK: tCMPr killed renamable $r3, renamable $r1, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 8, 4, implicit-def $itstate - ; CHECK: renamable $r3 = t2ADDrs renamable $r1, renamable $r2, 18, 8 /* CC::hi */, $cpsr, $noreg, implicit $itstate - ; CHECK: tCMPr killed renamable $r3, renamable $r0, 8 /* CC::hi */, killed $cpsr, implicit-def $cpsr, implicit killed $itstate - ; CHECK: tBcc %bb.6, 8 /* CC::hi */, killed $cpsr - ; CHECK: bb.3.vector.ph: - ; CHECK: successors: %bb.4(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2 - ; CHECK: renamable $r4 = t2BICri renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $r12 = t2SUBri renamable $r4, 4, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r7, dead $cpsr = tSUBrr renamable $r2, renamable $r4, 14 /* CC::al */, $noreg - ; CHECK: renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r12 = t2ADDrs renamable $r0, renamable $r4, 18, 14 /* CC::al */, $noreg, $noreg - ; CHECK: dead $lr = tMOVr renamable $r3, 14 /* CC::al */, $noreg - ; CHECK: renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 16, 14 /* CC::al */, $noreg - ; CHECK: $r5 = tMOVr killed $r3, 14 /* CC::al */, $noreg - ; CHECK: renamable $r3 = t2ADDrs renamable $r1, renamable $r4, 18, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg - ; CHECK: bb.4.vector.body: - ; CHECK: successors: %bb.4(0x7c000000), %bb.5(0x04000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r7, $r12 - ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRWU32_pre killed renamable $r0, 16, 0, $noreg, $noreg :: (load (s128) from %ir.scevgep18, align 4) - ; CHECK: $lr = tMOVr killed $r5, 14 /* CC::al */, $noreg - ; CHECK: renamable $q0 = nnan ninf nsz arcp contract afn reassoc MVE_VABSf32 killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: renamable $r1 = MVE_VSTRBU8_pre killed renamable $q0, killed renamable $r1, 16, 0, $noreg, $noreg :: (store (s128) into %ir.scevgep13, align 4) - ; CHECK: renamable $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, def $cpsr - ; CHECK: $r5 = tMOVr killed $lr, 14 /* CC::al */, $noreg - ; CHECK: tBcc %bb.4, 1 /* CC::ne */, killed $cpsr - ; CHECK: tB %bb.5, 14 /* CC::al */, $noreg - ; CHECK: bb.5.middle.block: - ; CHECK: successors: %bb.7(0x80000000) - ; CHECK: liveins: $r2, $r3, $r4, $r7, $r12 - ; CHECK: tCMPr killed renamable $r4, killed renamable $r2, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: $lr = tMOVr killed $r7, 14 /* CC::al */, $noreg - ; CHECK: t2IT 0, 8, implicit-def $itstate - ; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $r5, def $r7, def $pc, implicit killed $itstate - ; CHECK: tB %bb.7, 14 /* CC::al */, $noreg - ; CHECK: bb.6: - ; CHECK: successors: %bb.7(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2 - ; CHECK: $lr = tMOVr killed $r2, 14 /* CC::al */, $noreg - ; CHECK: $r12 = tMOVr killed $r0, 14 /* CC::al */, $noreg - ; CHECK: $r3 = tMOVr killed $r1, 14 /* CC::al */, $noreg - ; CHECK: bb.7.while.body.preheader19: - ; CHECK: successors: %bb.8(0x80000000) - ; CHECK: liveins: $lr, $r3, $r12 - ; CHECK: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r3, 4, 14 /* CC::al */, $noreg - ; CHECK: renamable $r1 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg - ; CHECK: bb.8.while.body: - ; CHECK: successors: %bb.8(0x7c000000), %bb.9(0x04000000) - ; CHECK: liveins: $lr, $r0, $r1 - ; CHECK: renamable $s0 = VLDRS renamable $r1, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep3) - ; CHECK: renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg - ; CHECK: renamable $s0 = nnan ninf nsz arcp contract afn reassoc VABSS killed renamable $s0, 14 /* CC::al */, $noreg - ; CHECK: VSTRS killed renamable $s0, renamable $r0, 1, 14 /* CC::al */, $noreg :: (store (s32) into %ir.scevgep7) - ; CHECK: renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 4, 14 /* CC::al */, $noreg - ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.8 - ; CHECK: bb.9.while.end: - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r7, def $pc + ; CHECK-NEXT: successors: %bb.9(0x30000000), %bb.1(0x50000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r4, $r5, $r7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r5, -12 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -16 + ; CHECK-NEXT: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: tBcc %bb.9, 0 /* CC::eq */, killed $cpsr + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.while.body.preheader: + ; CHECK-NEXT: successors: %bb.6(0x40000000), %bb.2(0x40000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: tCMPi8 renamable $r2, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: tBcc %bb.6, 3 /* CC::lo */, killed $cpsr + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.vector.memcheck: + ; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.6(0x40000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r3 = t2ADDrs renamable $r0, renamable $r2, 18, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: tCMPr killed renamable $r3, renamable $r1, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: t2IT 8, 4, implicit-def $itstate + ; CHECK-NEXT: renamable $r3 = t2ADDrs renamable $r1, renamable $r2, 18, 8 /* CC::hi */, $cpsr, $noreg, implicit $itstate + ; CHECK-NEXT: tCMPr killed renamable $r3, renamable $r0, 8 /* CC::hi */, killed $cpsr, implicit-def $cpsr, implicit killed $itstate + ; CHECK-NEXT: tBcc %bb.6, 8 /* CC::hi */, killed $cpsr + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.vector.ph: + ; CHECK-NEXT: successors: %bb.4(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r4 = t2BICri renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r12 = t2SUBri renamable $r4, 4, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r7, dead $cpsr = tSUBrr renamable $r2, renamable $r4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r12 = t2ADDrs renamable $r0, renamable $r4, 18, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: dead $lr = tMOVr renamable $r3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 16, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $r5 = tMOVr killed $r3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r3 = t2ADDrs renamable $r1, renamable $r4, 18, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4.vector.body: + ; CHECK-NEXT: successors: %bb.4(0x7c000000), %bb.5(0x04000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r7, $r12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r0, renamable $q0 = MVE_VLDRWU32_pre killed renamable $r0, 16, 0, $noreg, $noreg :: (load (s128) from %ir.scevgep18, align 4) + ; CHECK-NEXT: $lr = tMOVr killed $r5, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $q0 = nnan ninf nsz arcp contract afn reassoc MVE_VABSf32 killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: renamable $r1 = MVE_VSTRBU8_pre killed renamable $q0, killed renamable $r1, 16, 0, $noreg, $noreg :: (store (s128) into %ir.scevgep13, align 4) + ; CHECK-NEXT: renamable $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, def $cpsr + ; CHECK-NEXT: $r5 = tMOVr killed $lr, 14 /* CC::al */, $noreg + ; CHECK-NEXT: tBcc %bb.4, 1 /* CC::ne */, killed $cpsr + ; CHECK-NEXT: tB %bb.5, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.5.middle.block: + ; CHECK-NEXT: successors: %bb.7(0x80000000) + ; CHECK-NEXT: liveins: $r2, $r3, $r4, $r7, $r12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: tCMPr killed renamable $r4, killed renamable $r2, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: $lr = tMOVr killed $r7, 14 /* CC::al */, $noreg + ; CHECK-NEXT: t2IT 0, 8, implicit-def $itstate + ; CHECK-NEXT: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $r5, def $r7, def $pc, implicit killed $itstate + ; CHECK-NEXT: tB %bb.7, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.6: + ; CHECK-NEXT: successors: %bb.7(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $lr = tMOVr killed $r2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $r12 = tMOVr killed $r0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $r3 = tMOVr killed $r1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.7.while.body.preheader19: + ; CHECK-NEXT: successors: %bb.8(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r3, $r12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r3, 4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r1 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.8.while.body: + ; CHECK-NEXT: successors: %bb.8(0x7c000000), %bb.9(0x04000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $s0 = VLDRS renamable $r1, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep3) + ; CHECK-NEXT: renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $s0 = nnan ninf nsz arcp contract afn reassoc VABSS killed renamable $s0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: VSTRS killed renamable $s0, renamable $r0, 1, 14 /* CC::al */, $noreg :: (store (s32) into %ir.scevgep7) + ; CHECK-NEXT: renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.9.while.end: + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r7, def $pc bb.0.entry: successors: %bb.9(0x30000000), %bb.1(0x50000000) liveins: $r0, $r1, $r2, $r4, $r5, $r7, $lr diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-while.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-while.mir index 5dd75d94d319b..3a55b4905ec56 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-while.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-while.mir @@ -34,13 +34,10 @@ ret void } - ; Function Attrs: nounwind declare i32 @llvm.arm.space(i32 immarg, i32) #1 - ; Function Attrs: noduplicate nounwind declare i1 @llvm.test.set.loop.iterations.i32(i32) #2 - ; Function Attrs: noduplicate nounwind declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #2 attributes #0 = { "target-features"="+lob" } @@ -96,32 +93,38 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: ne_trip_count ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.1(0x40000000), %bb.3(0x40000000) - ; CHECK: liveins: $lr, $r1, $r2, $r3, $r7 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: dead $lr = t2SUBri $r3, 0, 14 /* CC::al */, $noreg, def $cpsr - ; CHECK: t2Bcc %bb.3, 0 /* CC::eq */, killed $cpsr - ; CHECK: tB %bb.1, 14 /* CC::al */, $noreg - ; CHECK: bb.1.do.body.preheader: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r1, $r2, $r3 - ; CHECK: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14 /* CC::al */, $noreg - ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg - ; CHECK: $lr = tMOVr killed $r3, 14 /* CC::al */, $noreg - ; CHECK: bb.2.do.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $lr, $r0, $r1 - ; CHECK: dead renamable $r2 = SPACE 4096, undef renamable $r0 - ; CHECK: renamable $r2, renamable $r0 = t2LDR_PRE killed renamable $r0, 4, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep) - ; CHECK: early-clobber renamable $r1 = t2STR_PRE killed renamable $r2, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.scevgep1) - ; CHECK: renamable $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, def $cpsr - ; CHECK: t2Bcc %bb.2, 1 /* CC::ne */, killed $cpsr - ; CHECK: tB %bb.3, 14 /* CC::al */, $noreg - ; CHECK: bb.3.if.end: - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc + ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.3(0x40000000) + ; CHECK-NEXT: liveins: $lr, $r1, $r2, $r3, $r7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: dead $lr = t2SUBri $r3, 0, 14 /* CC::al */, $noreg, def $cpsr + ; CHECK-NEXT: t2Bcc %bb.3, 0 /* CC::eq */, killed $cpsr + ; CHECK-NEXT: tB %bb.1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.do.body.preheader: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $lr = tMOVr killed $r3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.do.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: dead renamable $r2 = SPACE 4096, undef renamable $r0 + ; CHECK-NEXT: renamable $r2, renamable $r0 = t2LDR_PRE killed renamable $r0, 4, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep) + ; CHECK-NEXT: early-clobber renamable $r1 = t2STR_PRE killed renamable $r2, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.scevgep1) + ; CHECK-NEXT: renamable $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, def $cpsr + ; CHECK-NEXT: t2Bcc %bb.2, 1 /* CC::ne */, killed $cpsr + ; CHECK-NEXT: tB %bb.3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.if.end: + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc bb.0.entry: successors: %bb.1(0x40000000), %bb.3(0x40000000) liveins: $r1, $r2, $r3, $r7, $lr diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/safe-retaining.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/safe-retaining.mir index 4e4923a3ceadf..8e172f1553fc8 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/safe-retaining.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/safe-retaining.mir @@ -116,33 +116,39 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: test_vqrshruntq_n_s32 ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 - ; CHECK: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 11, 8, implicit-def $itstate - ; CHECK: tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r4, def $pc, implicit killed $itstate - ; CHECK: bb.1.loop.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: renamable $r4 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8) - ; CHECK: dead $lr = MVE_DLSTP_32 killed renamable $r3 - ; CHECK: $r12 = tMOVr killed $r4, 14 /* CC::al */, $noreg - ; CHECK: bb.2.loop.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $r0, $r1, $r2, $r12 - ; CHECK: $lr = tMOVr $r12, 14 /* CC::al */, $noreg - ; CHECK: renamable $r12 = t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg, $noreg :: (load (s128) from %ir.addr.b, align 4) - ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 0, $noreg, $noreg :: (load (s128) from %ir.addr.a, align 4) - ; CHECK: renamable $q1 = MVE_VQSHRUNs32th killed renamable $q1, killed renamable $q0, 3, 0, $noreg, $noreg - ; CHECK: renamable $r2 = MVE_VSTRWU32_post killed renamable $q1, killed renamable $r2, 16, 0, killed $noreg, $noreg :: (store (s128) into %ir.addr.c, align 4) - ; CHECK: dead $lr = MVE_LETP killed renamable $lr, %bb.2 - ; CHECK: bb.3.exit: - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -8 + ; CHECK-NEXT: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: t2IT 11, 8, implicit-def $itstate + ; CHECK-NEXT: tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r4, def $pc, implicit killed $itstate + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.loop.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r4 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8) + ; CHECK-NEXT: dead $lr = MVE_DLSTP_32 killed renamable $r3 + ; CHECK-NEXT: $r12 = tMOVr killed $r4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.loop.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $lr = tMOVr $r12, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r12 = t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg, $noreg :: (load (s128) from %ir.addr.b, align 4) + ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 0, $noreg, $noreg :: (load (s128) from %ir.addr.a, align 4) + ; CHECK-NEXT: renamable $q1 = MVE_VQSHRUNs32th killed renamable $q1, killed renamable $q0, 3, 0, $noreg, $noreg + ; CHECK-NEXT: renamable $r2 = MVE_VSTRWU32_post killed renamable $q1, killed renamable $r2, 16, 0, killed $noreg, $noreg :: (store (s128) into %ir.addr.c, align 4) + ; CHECK-NEXT: dead $lr = MVE_LETP killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.exit: + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $r3, $r4, $lr @@ -216,34 +222,40 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: test_vqrshruntq_n_s16 ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 - ; CHECK: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 11, 8, implicit-def $itstate - ; CHECK: tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r4, def $pc, implicit killed $itstate - ; CHECK: bb.1.loop.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: renamable $r12 = t2LDRi12 $sp, 8, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8) - ; CHECK: dead $lr = MVE_DLSTP_16 killed renamable $r3 - ; CHECK: $r4 = tMOVr killed $r12, 14 /* CC::al */, $noreg - ; CHECK: bb.2.loop.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $r0, $r1, $r2, $r4 - ; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg - ; CHECK: renamable $r4, dead $cpsr = tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 0, $noreg, $noreg :: (load (s128) from %ir.addr.b, align 2) - ; CHECK: renamable $q1 = MVE_VLDRHU16 killed renamable $r0, 0, 0, $noreg, $noreg :: (load (s128) from %ir.addr.a, align 2) - ; CHECK: $r0 = tMOVr $r1, 14 /* CC::al */, $noreg - ; CHECK: renamable $q1 = MVE_VQSHRUNs16th killed renamable $q1, killed renamable $q0, 1, 0, $noreg, $noreg - ; CHECK: renamable $r2 = MVE_VSTRHU16_post killed renamable $q1, killed renamable $r2, 16, 0, killed $noreg, $noreg :: (store (s128) into %ir.addr.c, align 2) - ; CHECK: dead $lr = MVE_LETP killed renamable $lr, %bb.2 - ; CHECK: bb.3.exit: - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -8 + ; CHECK-NEXT: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: t2IT 11, 8, implicit-def $itstate + ; CHECK-NEXT: tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r4, def $pc, implicit killed $itstate + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.loop.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r12 = t2LDRi12 $sp, 8, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8) + ; CHECK-NEXT: dead $lr = MVE_DLSTP_16 killed renamable $r3 + ; CHECK-NEXT: $r4 = tMOVr killed $r12, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.loop.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $lr = tMOVr $r4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r4, dead $cpsr = tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 0, $noreg, $noreg :: (load (s128) from %ir.addr.b, align 2) + ; CHECK-NEXT: renamable $q1 = MVE_VLDRHU16 killed renamable $r0, 0, 0, $noreg, $noreg :: (load (s128) from %ir.addr.a, align 2) + ; CHECK-NEXT: $r0 = tMOVr $r1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $q1 = MVE_VQSHRUNs16th killed renamable $q1, killed renamable $q0, 1, 0, $noreg, $noreg + ; CHECK-NEXT: renamable $r2 = MVE_VSTRHU16_post killed renamable $q1, killed renamable $r2, 16, 0, killed $noreg, $noreg :: (store (s128) into %ir.addr.c, align 2) + ; CHECK-NEXT: dead $lr = MVE_LETP killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.exit: + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $r3, $r4, $lr diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/size-limit.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/size-limit.mir index c87c0bb1e2fdd..8406720f02928 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/size-limit.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/size-limit.mir @@ -2,7 +2,6 @@ # RUN: llc -mtriple=armv8.1m.main -run-pass=arm-low-overhead-loops --verify-machineinstrs %s -o - | FileCheck %s --- | - ; ModuleID = 'size-limit.ll' source_filename = "size-limit.ll" target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" target triple = "thumbv8.1m.main" @@ -43,16 +42,12 @@ br i1 %4, label %for.body, label %for.cond.cleanup } - ; Function Attrs: nounwind declare i32 @llvm.arm.space(i32 immarg, i32) #0 - ; Function Attrs: noduplicate nounwind declare i32 @llvm.start.loop.iterations.i32(i32) #1 - ; Function Attrs: noduplicate nounwind declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #1 - ; Function Attrs: nounwind declare void @llvm.stackprotector(ptr, ptr) #0 attributes #0 = { nounwind } @@ -108,34 +103,40 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: size_limit ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r7 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: tCMPi8 $r3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 0, 8, implicit-def $itstate - ; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate - ; CHECK: bb.1.for.body.preheader: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg - ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg - ; CHECK: renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 4, 14 /* CC::al */, $noreg - ; CHECK: dead $lr = tMOVr $r3, 14 /* CC::al */, $noreg - ; CHECK: $lr = t2DLS killed $r3 - ; CHECK: bb.2.for.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2 - ; CHECK: dead renamable $r3 = SPACE 4070, undef renamable $r0 - ; CHECK: renamable $r12, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep3) - ; CHECK: renamable $r3, renamable $r2 = t2LDR_PRE killed renamable $r2, 4, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep7) - ; CHECK: renamable $r3 = nsw t2MUL killed renamable $r3, killed renamable $r12, 14 /* CC::al */, $noreg - ; CHECK: early-clobber renamable $r0 = t2STR_PRE killed renamable $r3, killed renamable $r0, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.scevgep11) - ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 - ; CHECK: bb.3.for.cond.cleanup: - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: tCMPi8 $r3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: t2IT 0, 8, implicit-def $itstate + ; CHECK-NEXT: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.for.body.preheader: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: dead $lr = tMOVr $r3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $lr = t2DLS killed $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.for.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: dead renamable $r3 = SPACE 4070, undef renamable $r0 + ; CHECK-NEXT: renamable $r12, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep3) + ; CHECK-NEXT: renamable $r3, renamable $r2 = t2LDR_PRE killed renamable $r2, 4, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep7) + ; CHECK-NEXT: renamable $r3 = nsw t2MUL killed renamable $r3, killed renamable $r12, 14 /* CC::al */, $noreg + ; CHECK-NEXT: early-clobber renamable $r0 = t2STR_PRE killed renamable $r3, killed renamable $r0, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.scevgep11) + ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.for.cond.cleanup: + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $r3, $r7, $lr diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/subreg-liveness.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/subreg-liveness.mir index 3b142e7ba2d41..cacadab5e4361 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/subreg-liveness.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/subreg-liveness.mir @@ -69,45 +69,54 @@ stack: body: | ; CHECK-LABEL: name: test ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.1(0x50000000), %bb.3(0x30000000) - ; CHECK: liveins: $lr, $r1, $r2, $r7 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: tCMPi8 renamable $r2, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: tBcc %bb.3, 11 /* CC::lt */, killed $cpsr - ; CHECK: bb.1.while.body.preheader: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r1, $r2 - ; CHECK: $r0 = tMOVr $r2, 14 /* CC::al */, $noreg - ; CHECK: tCMPi8 renamable $r2, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 10, 8, implicit-def $itstate - ; CHECK: renamable $r0 = tMOVi8 $noreg, 4, 10 /* CC::ge */, killed $cpsr, implicit killed renamable $r0, implicit killed $itstate - ; CHECK: renamable $r0, dead $cpsr = tSUBrr renamable $r2, killed renamable $r0, 14 /* CC::al */, $noreg - ; CHECK: renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 3, 14 /* CC::al */, $noreg - ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $r0 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r0, 19, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $q0 = MVE_VMOVimmi32 1, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: $lr = t2DLS killed renamable $r0 - ; CHECK: bb.2.while.body (align 4): - ; CHECK: successors: %bb.2(0x7c000000), %bb.4(0x04000000) - ; CHECK: liveins: $lr, $q0, $r1, $r2 - ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg - ; CHECK: MVE_VPST 8, implicit $vpr - ; CHECK: renamable $r1, renamable $q1 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, killed renamable $vpr, $lr :: (load (s128) from %ir.y.addr.0161, align 4) - ; CHECK: renamable $q0 = MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $lr, undef renamable $q0 - ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg - ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 - ; CHECK: tB %bb.4, 14 /* CC::al */, $noreg - ; CHECK: bb.3: - ; CHECK: successors: %bb.4(0x80000000) - ; CHECK: renamable $q0 = MVE_VMOVimmi32 1, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: bb.4.while.end: - ; CHECK: liveins: $d0 - ; CHECK: renamable $r0, renamable $r1 = VMOVRRD killed renamable $d0, 14 /* CC::al */, $noreg - ; CHECK: renamable $r0 = nsw tADDhirr killed renamable $r0, killed renamable $r1, 14 /* CC::al */, $noreg - ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 + ; CHECK-NEXT: successors: %bb.1(0x50000000), %bb.3(0x30000000) + ; CHECK-NEXT: liveins: $lr, $r1, $r2, $r7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: tCMPi8 renamable $r2, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: tBcc %bb.3, 11 /* CC::lt */, killed $cpsr + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.while.body.preheader: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $r0 = tMOVr $r2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: tCMPi8 renamable $r2, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: t2IT 10, 8, implicit-def $itstate + ; CHECK-NEXT: renamable $r0 = tMOVi8 $noreg, 4, 10 /* CC::ge */, killed $cpsr, implicit killed renamable $r0, implicit killed $itstate + ; CHECK-NEXT: renamable $r0, dead $cpsr = tSUBrr renamable $r2, killed renamable $r0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r0 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r0, 19, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 1, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: $lr = t2DLS killed renamable $r0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.while.body (align 4): + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.4(0x04000000) + ; CHECK-NEXT: liveins: $lr, $q0, $r1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg + ; CHECK-NEXT: MVE_VPST 8, implicit $vpr + ; CHECK-NEXT: renamable $r1, renamable $q1 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, killed renamable $vpr, $lr :: (load (s128) from %ir.y.addr.0161, align 4) + ; CHECK-NEXT: renamable $q0 = MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $lr, undef renamable $q0 + ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.2 + ; CHECK-NEXT: tB %bb.4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3: + ; CHECK-NEXT: successors: %bb.4(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 1, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4.while.end: + ; CHECK-NEXT: liveins: $d0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r0, renamable $r1 = VMOVRRD killed renamable $d0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r0 = nsw tADDhirr killed renamable $r0, killed renamable $r1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 bb.0.entry: successors: %bb.1(0x50000000), %bb.3(0x30000000) liveins: $r1, $r2, $r7, $lr diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/unpredicated-max.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/unpredicated-max.mir index 57cfaa8813734..5610bbc67b8fa 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/unpredicated-max.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/unpredicated-max.mir @@ -73,42 +73,48 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: variant_max_use ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r5 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r5, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -8 - ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 0, 8, implicit-def $itstate - ; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r5, def $pc, implicit killed $itstate - ; CHECK: bb.1.vector.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2 - ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg - ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $r12 = t2MOVi16 32768, 14 /* CC::al */, $noreg - ; CHECK: $r12 = t2MOVTi16 killed $r12, 65535, 14 /* CC::al */, $noreg - ; CHECK: dead $lr = t2DLS renamable $r3 - ; CHECK: $r5 = tMOVr killed $r3, 14 /* CC::al */, $noreg - ; CHECK: bb.2.vector.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $r0, $r1, $r2, $r5, $r12 - ; CHECK: $r3 = tMOVr $r12, 14 /* CC::al */, $noreg - ; CHECK: renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg, $noreg - ; CHECK: MVE_VPST 8, implicit $vpr - ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv17, align 2) - ; CHECK: renamable $r3 = MVE_VMAXVs16 killed renamable $r3, killed renamable $q0, 0, $noreg, $noreg - ; CHECK: $lr = tMOVr $r5, 14 /* CC::al */, $noreg - ; CHECK: early-clobber renamable $r1 = t2STRH_POST killed renamable $r3, killed renamable $r1, 2, 14 /* CC::al */, $noreg :: (store (s16) into %ir.lsr.iv.2) - ; CHECK: renamable $r5, dead $cpsr = nsw tSUBi8 killed $r5, 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 8, 14 /* CC::al */, $noreg - ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 - ; CHECK: bb.3.exit: - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r5, def $pc + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r5 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r5, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r5, -8 + ; CHECK-NEXT: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: t2IT 0, 8, implicit-def $itstate + ; CHECK-NEXT: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r5, def $pc, implicit killed $itstate + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.vector.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: $r12 = t2MOVi16 32768, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $r12 = t2MOVTi16 killed $r12, 65535, 14 /* CC::al */, $noreg + ; CHECK-NEXT: dead $lr = t2DLS renamable $r3 + ; CHECK-NEXT: $r5 = tMOVr killed $r3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.vector.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r5, $r12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $r3 = tMOVr $r12, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg, $noreg + ; CHECK-NEXT: MVE_VPST 8, implicit $vpr + ; CHECK-NEXT: renamable $r0, renamable $q0 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv17, align 2) + ; CHECK-NEXT: renamable $r3 = MVE_VMAXVs16 killed renamable $r3, killed renamable $q0, 0, $noreg, $noreg + ; CHECK-NEXT: $lr = tMOVr $r5, 14 /* CC::al */, $noreg + ; CHECK-NEXT: early-clobber renamable $r1 = t2STRH_POST killed renamable $r3, killed renamable $r1, 2, 14 /* CC::al */, $noreg :: (store (s16) into %ir.lsr.iv.2) + ; CHECK-NEXT: renamable $r5, dead $cpsr = nsw tSUBi8 killed $r5, 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 8, 14 /* CC::al */, $noreg + ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.exit: + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r5, def $pc bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $r5, $lr diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/unrolled-and-vector.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/unrolled-and-vector.mir index 7e2eda863d5da..7abe42b652266 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/unrolled-and-vector.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/unrolled-and-vector.mir @@ -231,136 +231,160 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: unrolled_and_vector ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.11(0x30000000), %bb.1(0x50000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r8, $r9, $r11 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 20 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -12 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -16 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -20 - ; CHECK: dead $r7 = frame-setup tADDrSPi $sp, 3, 14 /* CC::al */, $noreg - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa $r7, 8 - ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r8, killed $r9, killed $r11 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r11, -24 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r9, -28 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -32 - ; CHECK: tCMPi8 renamable $r3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: tBcc %bb.11, 0 /* CC::eq */, killed $cpsr - ; CHECK: bb.1.vector.memcheck: - ; CHECK: successors: %bb.2(0x40000000), %bb.4(0x40000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: renamable $r4, dead $cpsr = tADDrr renamable $r0, renamable $r3, 14 /* CC::al */, $noreg - ; CHECK: renamable $r5, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14 /* CC::al */, $noreg - ; CHECK: tCMPr renamable $r4, renamable $r2, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r12 = t2CSINC $zr, $zr, 9, implicit killed $cpsr - ; CHECK: tCMPr killed renamable $r5, renamable $r0, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: renamable $r6 = t2CSINC $zr, $zr, 9, implicit killed $cpsr - ; CHECK: tCMPr killed renamable $r4, renamable $r1, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: renamable $r5 = t2ADDrr renamable $r1, renamable $r3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r4 = t2CSINC $zr, $zr, 9, implicit killed $cpsr - ; CHECK: tCMPr killed renamable $r5, renamable $r0, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: renamable $r5 = t2CSINC $zr, $zr, 9, implicit killed $cpsr - ; CHECK: renamable $r5, dead $cpsr = tAND killed renamable $r5, killed renamable $r4, 14 /* CC::al */, $noreg - ; CHECK: dead renamable $r5, $cpsr = tLSLri killed renamable $r5, 31, 14 /* CC::al */, $noreg - ; CHECK: t2IT 0, 4, implicit-def $itstate - ; CHECK: renamable $r6 = t2ANDrr killed renamable $r6, killed renamable $r12, 0 /* CC::eq */, $cpsr, $noreg, implicit killed $r6, implicit $itstate - ; CHECK: dead renamable $r6 = t2LSLri killed renamable $r6, 31, 0 /* CC::eq */, killed $cpsr, def $cpsr, implicit killed $r6, implicit killed $itstate - ; CHECK: tBcc %bb.4, 0 /* CC::eq */, killed $cpsr - ; CHECK: bb.2.for.body.preheader: - ; CHECK: successors: %bb.3(0x40000000), %bb.6(0x40000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 - ; CHECK: renamable $r4, dead $cpsr = tSUBi3 renamable $r3, 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $r12 = t2ANDri renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: tCMPi8 killed renamable $r4, 3, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: tBcc %bb.6, 2 /* CC::hs */, killed $cpsr - ; CHECK: bb.3: - ; CHECK: successors: %bb.8(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2, $r12 - ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg - ; CHECK: tB %bb.8, 14 /* CC::al */, $noreg - ; CHECK: bb.4.vector.ph: - ; CHECK: successors: %bb.5(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: $lr = MVE_DLSTP_8 killed renamable $r3 - ; CHECK: bb.5.vector.body: - ; CHECK: successors: %bb.5(0x7c000000), %bb.11(0x04000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2 - ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRBU8_post killed renamable $r1, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv46, align 1) - ; CHECK: renamable $r2, renamable $q1 = MVE_VLDRBU8_post killed renamable $r2, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv4749, align 1) - ; CHECK: renamable $q0 = MVE_VADDi8 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: renamable $r0 = MVE_VSTRBU8_post killed renamable $q0, killed renamable $r0, 16, 0, killed $noreg, $noreg :: (store (s128) into %ir.lsr.iv5052, align 1) - ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.5 - ; CHECK: tB %bb.11, 14 /* CC::al */, $noreg - ; CHECK: bb.6.for.body.preheader.new: - ; CHECK: successors: %bb.7(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r12 - ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg - ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r3, 19, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg - ; CHECK: bb.7.for.body: - ; CHECK: successors: %bb.7(0x7c000000), %bb.8(0x04000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r12 - ; CHECK: renamable $r4 = tLDRBr renamable $r1, $r3, 14 /* CC::al */, $noreg :: (load (s8) from %ir.scevgep2453) - ; CHECK: renamable $r9 = t2ADDrr renamable $r1, renamable $r3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r5 = tLDRBr renamable $r2, $r3, 14 /* CC::al */, $noreg :: (load (s8) from %ir.scevgep2854) - ; CHECK: renamable $r6, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14 /* CC::al */, $noreg - ; CHECK: renamable $r4 = tADDhirr killed renamable $r4, killed renamable $r5, 14 /* CC::al */, $noreg - ; CHECK: tSTRBr killed renamable $r4, renamable $r0, $r3, 14 /* CC::al */, $noreg :: (store (s8) into %ir.scevgep3255) - ; CHECK: renamable $r8 = t2LDRBi12 renamable $r9, 1, 14 /* CC::al */, $noreg :: (load (s8) from %ir.scevgep40) - ; CHECK: renamable $r5 = tLDRBi renamable $r6, 1, 14 /* CC::al */, $noreg :: (load (s8) from %ir.scevgep42) - ; CHECK: renamable $r8 = tADDhirr killed renamable $r8, killed renamable $r5, 14 /* CC::al */, $noreg - ; CHECK: renamable $r5, dead $cpsr = tADDrr renamable $r0, renamable $r3, 14 /* CC::al */, $noreg - ; CHECK: renamable $r3, dead $cpsr = nuw tADDi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg - ; CHECK: t2STRBi12 killed renamable $r8, renamable $r5, 1, 14 /* CC::al */, $noreg :: (store (s8) into %ir.scevgep44) - ; CHECK: renamable $r8 = t2LDRBi12 renamable $r9, 2, 14 /* CC::al */, $noreg :: (load (s8) from %ir.scevgep34) - ; CHECK: renamable $r4 = tLDRBi renamable $r6, 2, 14 /* CC::al */, $noreg :: (load (s8) from %ir.scevgep36) - ; CHECK: renamable $r4 = tADDhirr killed renamable $r4, killed renamable $r8, 14 /* CC::al */, $noreg - ; CHECK: tSTRBi killed renamable $r4, renamable $r5, 2, 14 /* CC::al */, $noreg :: (store (s8) into %ir.scevgep38) - ; CHECK: renamable $r4 = t2LDRBi12 killed renamable $r9, 3, 14 /* CC::al */, $noreg :: (load (s8) from %ir.scevgep22) - ; CHECK: renamable $r6 = tLDRBi killed renamable $r6, 3, 14 /* CC::al */, $noreg :: (load (s8) from %ir.scevgep26) - ; CHECK: renamable $r4 = tADDhirr killed renamable $r4, killed renamable $r6, 14 /* CC::al */, $noreg - ; CHECK: tSTRBi killed renamable $r4, killed renamable $r5, 3, 14 /* CC::al */, $noreg :: (store (s8) into %ir.scevgep30) - ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.7 - ; CHECK: bb.8.for.cond.cleanup.loopexit.unr-lcssa: - ; CHECK: successors: %bb.11(0x30000000), %bb.9(0x50000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3, $r12 - ; CHECK: t2CMPri renamable $r12, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: tBcc %bb.11, 0 /* CC::eq */, killed $cpsr - ; CHECK: bb.9.for.body.epil: - ; CHECK: successors: %bb.11(0x40000000), %bb.10(0x40000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3, $r12 - ; CHECK: renamable $r6 = tLDRBr renamable $r1, $r3, 14 /* CC::al */, $noreg :: (load (s8) from %ir.arrayidx.epil) - ; CHECK: t2CMPri renamable $r12, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: renamable $r5 = tLDRBr renamable $r2, $r3, 14 /* CC::al */, $noreg :: (load (s8) from %ir.arrayidx1.epil) - ; CHECK: renamable $r6 = tADDhirr killed renamable $r6, killed renamable $r5, 14 /* CC::al */, $noreg - ; CHECK: tSTRBr killed renamable $r6, renamable $r0, $r3, 14 /* CC::al */, $noreg :: (store (s8) into %ir.arrayidx4.epil) - ; CHECK: tBcc %bb.11, 0 /* CC::eq */, killed $cpsr - ; CHECK: bb.10.for.body.epil.1: - ; CHECK: successors: %bb.11(0x40000000), %bb.12(0x40000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3, $r12 - ; CHECK: renamable $r6, dead $cpsr = nuw tADDi3 renamable $r3, 1, 14 /* CC::al */, $noreg - ; CHECK: t2CMPri killed renamable $r12, 2, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: renamable $r5 = tLDRBr renamable $r1, $r6, 14 /* CC::al */, $noreg :: (load (s8) from %ir.arrayidx.epil.1) - ; CHECK: renamable $r4 = tLDRBr renamable $r2, $r6, 14 /* CC::al */, $noreg :: (load (s8) from %ir.arrayidx1.epil.1) - ; CHECK: renamable $r5 = tADDhirr killed renamable $r5, killed renamable $r4, 14 /* CC::al */, $noreg - ; CHECK: tSTRBr killed renamable $r5, renamable $r0, killed $r6, 14 /* CC::al */, $noreg :: (store (s8) into %ir.arrayidx4.epil.1) - ; CHECK: tBcc %bb.12, 1 /* CC::ne */, killed $cpsr - ; CHECK: bb.11.for.cond.cleanup: - ; CHECK: $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r8, def $r9, def $r11 - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc - ; CHECK: bb.12.for.body.epil.2: - ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: renamable $r3, dead $cpsr = nuw tADDi8 killed renamable $r3, 2, 14 /* CC::al */, $noreg - ; CHECK: renamable $r1 = tLDRBr killed renamable $r1, $r3, 14 /* CC::al */, $noreg :: (load (s8) from %ir.arrayidx.epil.2) - ; CHECK: renamable $r2 = tLDRBr killed renamable $r2, $r3, 14 /* CC::al */, $noreg :: (load (s8) from %ir.arrayidx1.epil.2) - ; CHECK: renamable $r1 = tADDhirr killed renamable $r1, killed renamable $r2, 14 /* CC::al */, $noreg - ; CHECK: tSTRBr killed renamable $r1, killed renamable $r0, killed $r3, 14 /* CC::al */, $noreg :: (store (s8) into %ir.arrayidx4.epil.2) - ; CHECK: $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r8, def $r9, def $r11 - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc + ; CHECK-NEXT: successors: %bb.11(0x30000000), %bb.1(0x50000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r8, $r9, $r11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 20 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r6, -12 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r5, -16 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -20 + ; CHECK-NEXT: dead $r7 = frame-setup tADDrSPi $sp, 3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa $r7, 8 + ; CHECK-NEXT: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r8, killed $r9, killed $r11 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r11, -24 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r9, -28 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r8, -32 + ; CHECK-NEXT: tCMPi8 renamable $r3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: tBcc %bb.11, 0 /* CC::eq */, killed $cpsr + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.vector.memcheck: + ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.4(0x40000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r4, dead $cpsr = tADDrr renamable $r0, renamable $r3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r5, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: tCMPr renamable $r4, renamable $r2, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r12 = t2CSINC $zr, $zr, 9, implicit killed $cpsr + ; CHECK-NEXT: tCMPr killed renamable $r5, renamable $r0, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: renamable $r6 = t2CSINC $zr, $zr, 9, implicit killed $cpsr + ; CHECK-NEXT: tCMPr killed renamable $r4, renamable $r1, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: renamable $r5 = t2ADDrr renamable $r1, renamable $r3, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r4 = t2CSINC $zr, $zr, 9, implicit killed $cpsr + ; CHECK-NEXT: tCMPr killed renamable $r5, renamable $r0, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: renamable $r5 = t2CSINC $zr, $zr, 9, implicit killed $cpsr + ; CHECK-NEXT: renamable $r5, dead $cpsr = tAND killed renamable $r5, killed renamable $r4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: dead renamable $r5, $cpsr = tLSLri killed renamable $r5, 31, 14 /* CC::al */, $noreg + ; CHECK-NEXT: t2IT 0, 4, implicit-def $itstate + ; CHECK-NEXT: renamable $r6 = t2ANDrr killed renamable $r6, killed renamable $r12, 0 /* CC::eq */, $cpsr, $noreg, implicit killed $r6, implicit $itstate + ; CHECK-NEXT: dead renamable $r6 = t2LSLri killed renamable $r6, 31, 0 /* CC::eq */, killed $cpsr, def $cpsr, implicit killed $r6, implicit killed $itstate + ; CHECK-NEXT: tBcc %bb.4, 0 /* CC::eq */, killed $cpsr + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.for.body.preheader: + ; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.6(0x40000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r4, dead $cpsr = tSUBi3 renamable $r3, 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r12 = t2ANDri renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: tCMPi8 killed renamable $r4, 3, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: tBcc %bb.6, 2 /* CC::hs */, killed $cpsr + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3: + ; CHECK-NEXT: successors: %bb.8(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: tB %bb.8, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4.vector.ph: + ; CHECK-NEXT: successors: %bb.5(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $lr = MVE_DLSTP_8 killed renamable $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.5.vector.body: + ; CHECK-NEXT: successors: %bb.5(0x7c000000), %bb.11(0x04000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r1, renamable $q0 = MVE_VLDRBU8_post killed renamable $r1, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv46, align 1) + ; CHECK-NEXT: renamable $r2, renamable $q1 = MVE_VLDRBU8_post killed renamable $r2, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv4749, align 1) + ; CHECK-NEXT: renamable $q0 = MVE_VADDi8 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: renamable $r0 = MVE_VSTRBU8_post killed renamable $q0, killed renamable $r0, 16, 0, killed $noreg, $noreg :: (store (s128) into %ir.lsr.iv5052, align 1) + ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.5 + ; CHECK-NEXT: tB %bb.11, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.6.for.body.preheader.new: + ; CHECK-NEXT: successors: %bb.7(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r3, 19, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.7.for.body: + ; CHECK-NEXT: successors: %bb.7(0x7c000000), %bb.8(0x04000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r4 = tLDRBr renamable $r1, $r3, 14 /* CC::al */, $noreg :: (load (s8) from %ir.scevgep2453) + ; CHECK-NEXT: renamable $r9 = t2ADDrr renamable $r1, renamable $r3, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r5 = tLDRBr renamable $r2, $r3, 14 /* CC::al */, $noreg :: (load (s8) from %ir.scevgep2854) + ; CHECK-NEXT: renamable $r6, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r4 = tADDhirr killed renamable $r4, killed renamable $r5, 14 /* CC::al */, $noreg + ; CHECK-NEXT: tSTRBr killed renamable $r4, renamable $r0, $r3, 14 /* CC::al */, $noreg :: (store (s8) into %ir.scevgep3255) + ; CHECK-NEXT: renamable $r8 = t2LDRBi12 renamable $r9, 1, 14 /* CC::al */, $noreg :: (load (s8) from %ir.scevgep40) + ; CHECK-NEXT: renamable $r5 = tLDRBi renamable $r6, 1, 14 /* CC::al */, $noreg :: (load (s8) from %ir.scevgep42) + ; CHECK-NEXT: renamable $r8 = tADDhirr killed renamable $r8, killed renamable $r5, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r5, dead $cpsr = tADDrr renamable $r0, renamable $r3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r3, dead $cpsr = nuw tADDi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: t2STRBi12 killed renamable $r8, renamable $r5, 1, 14 /* CC::al */, $noreg :: (store (s8) into %ir.scevgep44) + ; CHECK-NEXT: renamable $r8 = t2LDRBi12 renamable $r9, 2, 14 /* CC::al */, $noreg :: (load (s8) from %ir.scevgep34) + ; CHECK-NEXT: renamable $r4 = tLDRBi renamable $r6, 2, 14 /* CC::al */, $noreg :: (load (s8) from %ir.scevgep36) + ; CHECK-NEXT: renamable $r4 = tADDhirr killed renamable $r4, killed renamable $r8, 14 /* CC::al */, $noreg + ; CHECK-NEXT: tSTRBi killed renamable $r4, renamable $r5, 2, 14 /* CC::al */, $noreg :: (store (s8) into %ir.scevgep38) + ; CHECK-NEXT: renamable $r4 = t2LDRBi12 killed renamable $r9, 3, 14 /* CC::al */, $noreg :: (load (s8) from %ir.scevgep22) + ; CHECK-NEXT: renamable $r6 = tLDRBi killed renamable $r6, 3, 14 /* CC::al */, $noreg :: (load (s8) from %ir.scevgep26) + ; CHECK-NEXT: renamable $r4 = tADDhirr killed renamable $r4, killed renamable $r6, 14 /* CC::al */, $noreg + ; CHECK-NEXT: tSTRBi killed renamable $r4, killed renamable $r5, 3, 14 /* CC::al */, $noreg :: (store (s8) into %ir.scevgep30) + ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.8.for.cond.cleanup.loopexit.unr-lcssa: + ; CHECK-NEXT: successors: %bb.11(0x30000000), %bb.9(0x50000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3, $r12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: t2CMPri renamable $r12, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: tBcc %bb.11, 0 /* CC::eq */, killed $cpsr + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.9.for.body.epil: + ; CHECK-NEXT: successors: %bb.11(0x40000000), %bb.10(0x40000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3, $r12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r6 = tLDRBr renamable $r1, $r3, 14 /* CC::al */, $noreg :: (load (s8) from %ir.arrayidx.epil) + ; CHECK-NEXT: t2CMPri renamable $r12, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: renamable $r5 = tLDRBr renamable $r2, $r3, 14 /* CC::al */, $noreg :: (load (s8) from %ir.arrayidx1.epil) + ; CHECK-NEXT: renamable $r6 = tADDhirr killed renamable $r6, killed renamable $r5, 14 /* CC::al */, $noreg + ; CHECK-NEXT: tSTRBr killed renamable $r6, renamable $r0, $r3, 14 /* CC::al */, $noreg :: (store (s8) into %ir.arrayidx4.epil) + ; CHECK-NEXT: tBcc %bb.11, 0 /* CC::eq */, killed $cpsr + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.10.for.body.epil.1: + ; CHECK-NEXT: successors: %bb.11(0x40000000), %bb.12(0x40000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3, $r12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r6, dead $cpsr = nuw tADDi3 renamable $r3, 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: t2CMPri killed renamable $r12, 2, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: renamable $r5 = tLDRBr renamable $r1, $r6, 14 /* CC::al */, $noreg :: (load (s8) from %ir.arrayidx.epil.1) + ; CHECK-NEXT: renamable $r4 = tLDRBr renamable $r2, $r6, 14 /* CC::al */, $noreg :: (load (s8) from %ir.arrayidx1.epil.1) + ; CHECK-NEXT: renamable $r5 = tADDhirr killed renamable $r5, killed renamable $r4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: tSTRBr killed renamable $r5, renamable $r0, killed $r6, 14 /* CC::al */, $noreg :: (store (s8) into %ir.arrayidx4.epil.1) + ; CHECK-NEXT: tBcc %bb.12, 1 /* CC::ne */, killed $cpsr + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.11.for.cond.cleanup: + ; CHECK-NEXT: $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r8, def $r9, def $r11 + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.12.for.body.epil.2: + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r3, dead $cpsr = nuw tADDi8 killed renamable $r3, 2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r1 = tLDRBr killed renamable $r1, $r3, 14 /* CC::al */, $noreg :: (load (s8) from %ir.arrayidx.epil.2) + ; CHECK-NEXT: renamable $r2 = tLDRBr killed renamable $r2, $r3, 14 /* CC::al */, $noreg :: (load (s8) from %ir.arrayidx1.epil.2) + ; CHECK-NEXT: renamable $r1 = tADDhirr killed renamable $r1, killed renamable $r2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: tSTRBr killed renamable $r1, killed renamable $r0, killed $r3, 14 /* CC::al */, $noreg :: (store (s8) into %ir.arrayidx4.epil.2) + ; CHECK-NEXT: $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r8, def $r9, def $r11 + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc bb.0.entry: successors: %bb.11(0x30000000), %bb.1(0x50000000) liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $lr, $r8, $r9, $r11 diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-retaining.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-retaining.mir index 6642c1ad97797..8d6125e3459d7 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-retaining.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-retaining.mir @@ -114,38 +114,44 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: test_vmvn ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 - ; CHECK: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 11, 8, implicit-def $itstate - ; CHECK: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r4, def $pc, implicit killed $itstate - ; CHECK: bb.1.loop.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: renamable $r4 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8) - ; CHECK: dead $lr = t2DLS renamable $r4 - ; CHECK: $r12 = tMOVr killed $r4, 14 /* CC::al */, $noreg - ; CHECK: bb.2.loop.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3, $r12 - ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg - ; CHECK: $lr = tMOVr $r12, 14 /* CC::al */, $noreg - ; CHECK: MVE_VPST 4, implicit $vpr - ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.a, align 4) - ; CHECK: renamable $r1, renamable $q1 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.b, align 4) - ; CHECK: renamable $r12 = t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg - ; CHECK: renamable $q1 = MVE_VMVN killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1 - ; CHECK: renamable $q0 = MVE_VQSHRNbhs32 killed renamable $q0, killed renamable $q1, 15, 0, $noreg, $noreg - ; CHECK: MVE_VPST 8, implicit $vpr - ; CHECK: renamable $r2 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r2, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.addr.c, align 4) - ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 - ; CHECK: bb.3.exit: - ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -8 + ; CHECK-NEXT: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: t2IT 11, 8, implicit-def $itstate + ; CHECK-NEXT: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r4, def $pc, implicit killed $itstate + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.loop.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r4 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8) + ; CHECK-NEXT: dead $lr = t2DLS renamable $r4 + ; CHECK-NEXT: $r12 = tMOVr killed $r4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.loop.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3, $r12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg + ; CHECK-NEXT: $lr = tMOVr $r12, 14 /* CC::al */, $noreg + ; CHECK-NEXT: MVE_VPST 4, implicit $vpr + ; CHECK-NEXT: renamable $r0, renamable $q0 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.a, align 4) + ; CHECK-NEXT: renamable $r1, renamable $q1 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.b, align 4) + ; CHECK-NEXT: renamable $r12 = t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $q1 = MVE_VMVN killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1 + ; CHECK-NEXT: renamable $q0 = MVE_VQSHRNbhs32 killed renamable $q0, killed renamable $q1, 15, 0, $noreg, $noreg + ; CHECK-NEXT: MVE_VPST 8, implicit $vpr + ; CHECK-NEXT: renamable $r2 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r2, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.addr.c, align 4) + ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.exit: + ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $r3, $r4, $lr @@ -220,38 +226,44 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: test_vorn ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 - ; CHECK: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 11, 8, implicit-def $itstate - ; CHECK: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r4, def $pc, implicit killed $itstate - ; CHECK: bb.1.loop.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: renamable $r4 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8) - ; CHECK: dead $lr = t2DLS renamable $r4 - ; CHECK: $r12 = tMOVr killed $r4, 14 /* CC::al */, $noreg - ; CHECK: bb.2.loop.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3, $r12 - ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg - ; CHECK: MVE_VPST 4, implicit $vpr - ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.b, align 4) - ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.a, align 4) - ; CHECK: $lr = tMOVr $r12, 14 /* CC::al */, $noreg - ; CHECK: renamable $r12 = t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg - ; CHECK: renamable $q0 = MVE_VORN renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: renamable $q1 = MVE_VQSHRUNs32th killed renamable $q1, killed renamable $q0, 3, 0, $noreg, $noreg - ; CHECK: MVE_VPST 8, implicit $vpr - ; CHECK: renamable $r2 = MVE_VSTRWU32_post killed renamable $q1, killed renamable $r2, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.addr.c, align 4) - ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 - ; CHECK: bb.3.exit: - ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -8 + ; CHECK-NEXT: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: t2IT 11, 8, implicit-def $itstate + ; CHECK-NEXT: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r4, def $pc, implicit killed $itstate + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.loop.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r4 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8) + ; CHECK-NEXT: dead $lr = t2DLS renamable $r4 + ; CHECK-NEXT: $r12 = tMOVr killed $r4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.loop.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3, $r12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg + ; CHECK-NEXT: MVE_VPST 4, implicit $vpr + ; CHECK-NEXT: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.b, align 4) + ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.a, align 4) + ; CHECK-NEXT: $lr = tMOVr $r12, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r12 = t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $q0 = MVE_VORN renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: renamable $q1 = MVE_VQSHRUNs32th killed renamable $q1, killed renamable $q0, 3, 0, $noreg, $noreg + ; CHECK-NEXT: MVE_VPST 8, implicit $vpr + ; CHECK-NEXT: renamable $r2 = MVE_VSTRWU32_post killed renamable $q1, killed renamable $r2, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.addr.c, align 4) + ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.exit: + ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $r3, $r4, $lr diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vaddv.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vaddv.mir index 2d1c743d1025c..8f50632a3c6f2 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vaddv.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vaddv.mir @@ -844,28 +844,34 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: legal_vaddv_s32 ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 0, 8, implicit-def $itstate - ; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate - ; CHECK: bb.1.vector.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2 - ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2 - ; CHECK: bb.2.vector.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $lr, $r0, $r1 - ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRHS32_post killed renamable $r0, 8, 0, killed $noreg, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) - ; CHECK: renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg - ; CHECK: early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr) - ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 - ; CHECK: bb.3.exit: - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: t2IT 0, 8, implicit-def $itstate + ; CHECK-NEXT: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.vector.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.vector.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r0, renamable $q0 = MVE_VLDRHS32_post killed renamable $r0, 8, 0, killed $noreg, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) + ; CHECK-NEXT: renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg + ; CHECK-NEXT: early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr) + ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.exit: + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $r7, $lr @@ -943,28 +949,34 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: legal_vaddv_s16 ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 0, 8, implicit-def $itstate - ; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate - ; CHECK: bb.1.vector.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2 - ; CHECK: $lr = MVE_DLSTP_16 killed renamable $r2 - ; CHECK: bb.2.vector.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $lr, $r0, $r1 - ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRHU16_post killed renamable $r0, 16, 0, killed $noreg, $noreg :: (load (s128) from %ir.lsr.iv17, align 2) - ; CHECK: renamable $r12 = MVE_VADDVs16no_acc killed renamable $q0, 0, $noreg, $noreg - ; CHECK: early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr) - ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 - ; CHECK: bb.3.exit: - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: t2IT 0, 8, implicit-def $itstate + ; CHECK-NEXT: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.vector.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $lr = MVE_DLSTP_16 killed renamable $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.vector.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r0, renamable $q0 = MVE_VLDRHU16_post killed renamable $r0, 16, 0, killed $noreg, $noreg :: (load (s128) from %ir.lsr.iv17, align 2) + ; CHECK-NEXT: renamable $r12 = MVE_VADDVs16no_acc killed renamable $q0, 0, $noreg, $noreg + ; CHECK-NEXT: early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr) + ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.exit: + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $r7, $lr @@ -1042,28 +1054,34 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: legal_vaddv_s8 ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 0, 8, implicit-def $itstate - ; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate - ; CHECK: bb.1.vector.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2 - ; CHECK: $lr = MVE_DLSTP_8 killed renamable $r2 - ; CHECK: bb.2.vector.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $lr, $r0, $r1 - ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRBU8_post killed renamable $r0, 16, 0, killed $noreg, $noreg :: (load (s128) from %ir.lsr.iv17, align 1) - ; CHECK: renamable $r12 = MVE_VADDVs8no_acc killed renamable $q0, 0, $noreg, $noreg - ; CHECK: early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr) - ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 - ; CHECK: bb.3.exit: - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: t2IT 0, 8, implicit-def $itstate + ; CHECK-NEXT: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.vector.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $lr = MVE_DLSTP_8 killed renamable $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.vector.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r0, renamable $q0 = MVE_VLDRBU8_post killed renamable $r0, 16, 0, killed $noreg, $noreg :: (load (s128) from %ir.lsr.iv17, align 1) + ; CHECK-NEXT: renamable $r12 = MVE_VADDVs8no_acc killed renamable $q0, 0, $noreg, $noreg + ; CHECK-NEXT: early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr) + ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.exit: + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $r7, $lr @@ -1140,32 +1158,40 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: legal_vaddva_s32 ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.4(0x30000000), %bb.1(0x50000000) - ; CHECK: liveins: $lr, $r0, $r1, $r7 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: tCBZ $r1, %bb.4 - ; CHECK: bb.1.vector.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1 - ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r1 - ; CHECK: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg - ; CHECK: bb.2.vector.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $lr, $r0, $r2 - ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRHS32_post killed renamable $r0, 8, 0, killed $noreg, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) - ; CHECK: renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg, $noreg - ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 - ; CHECK: bb.3.exit: - ; CHECK: liveins: $r2 - ; CHECK: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 - ; CHECK: bb.4: - ; CHECK: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg - ; CHECK: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 + ; CHECK-NEXT: successors: %bb.4(0x30000000), %bb.1(0x50000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: tCBZ $r1, %bb.4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.vector.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r1 + ; CHECK-NEXT: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.vector.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r0, renamable $q0 = MVE_VLDRHS32_post killed renamable $r0, 8, 0, killed $noreg, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) + ; CHECK-NEXT: renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg, $noreg + ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.exit: + ; CHECK-NEXT: liveins: $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4: + ; CHECK-NEXT: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 bb.0.entry: successors: %bb.4(0x30000000), %bb.1(0x50000000) liveins: $r0, $r1, $r7, $lr @@ -1249,40 +1275,46 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: illegal_vaddv_s32 ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 0, 8, implicit-def $itstate - ; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate - ; CHECK: bb.1.vector.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2 - ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg - ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg - ; CHECK: dead $lr = t2DLS renamable $r12 - ; CHECK: $r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg - ; CHECK: bb.2.vector.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg - ; CHECK: MVE_VPST 8, implicit $vpr - ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) - ; CHECK: renamable $q0 = MVE_VMVN killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: $lr = tMOVr $r3, 14 /* CC::al */, $noreg - ; CHECK: renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg - ; CHECK: renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg - ; CHECK: early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr) - ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg - ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 - ; CHECK: bb.3.exit: - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: t2IT 0, 8, implicit-def $itstate + ; CHECK-NEXT: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.vector.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: dead $lr = t2DLS renamable $r12 + ; CHECK-NEXT: $r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.vector.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg + ; CHECK-NEXT: MVE_VPST 8, implicit $vpr + ; CHECK-NEXT: renamable $r0, renamable $q0 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) + ; CHECK-NEXT: renamable $q0 = MVE_VMVN killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: $lr = tMOVr $r3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg + ; CHECK-NEXT: renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr) + ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.exit: + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $r7, $lr @@ -1360,44 +1392,52 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: illegal_vaddva_s32 ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.4(0x30000000), %bb.1(0x50000000) - ; CHECK: liveins: $lr, $r0, $r1, $r7 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: tCBZ $r1, %bb.4 - ; CHECK: bb.1.vector.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1 - ; CHECK: renamable $r2, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg - ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $r2 = t2BICri killed renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg - ; CHECK: renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg - ; CHECK: dead $lr = t2DLS renamable $r2 - ; CHECK: $r3 = tMOVr killed $r2, 14 /* CC::al */, $noreg - ; CHECK: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg - ; CHECK: bb.2.vector.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg, $noreg - ; CHECK: MVE_VPST 8, implicit $vpr - ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) - ; CHECK: $lr = tMOVr $r3, 14 /* CC::al */, $noreg - ; CHECK: renamable $q0 = MVE_VMVN killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg - ; CHECK: renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg, $noreg - ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 - ; CHECK: bb.3.exit: - ; CHECK: liveins: $r2 - ; CHECK: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 - ; CHECK: bb.4: - ; CHECK: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg - ; CHECK: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 + ; CHECK-NEXT: successors: %bb.4(0x30000000), %bb.1(0x50000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: tCBZ $r1, %bb.4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.vector.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r2, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r2 = t2BICri killed renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: dead $lr = t2DLS renamable $r2 + ; CHECK-NEXT: $r3 = tMOVr killed $r2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.vector.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg, $noreg + ; CHECK-NEXT: MVE_VPST 8, implicit $vpr + ; CHECK-NEXT: renamable $r0, renamable $q0 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) + ; CHECK-NEXT: $lr = tMOVr $r3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $q0 = MVE_VMVN killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg, $noreg + ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.exit: + ; CHECK-NEXT: liveins: $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4: + ; CHECK-NEXT: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 bb.0.entry: successors: %bb.4(0x30000000), %bb.1(0x50000000) liveins: $r0, $r1, $r7, $lr @@ -1482,40 +1522,46 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: illegal_vaddv_u32 ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 0, 8, implicit-def $itstate - ; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate - ; CHECK: bb.1.vector.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2 - ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg - ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg - ; CHECK: dead $lr = t2DLS renamable $r12 - ; CHECK: $r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg - ; CHECK: bb.2.vector.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg - ; CHECK: MVE_VPST 8, implicit $vpr - ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRHU32_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) - ; CHECK: renamable $q0 = MVE_VMVN killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: $lr = tMOVr $r3, 14 /* CC::al */, $noreg - ; CHECK: renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg - ; CHECK: renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg - ; CHECK: early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr) - ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg - ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 - ; CHECK: bb.3.exit: - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: t2IT 0, 8, implicit-def $itstate + ; CHECK-NEXT: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.vector.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: dead $lr = t2DLS renamable $r12 + ; CHECK-NEXT: $r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.vector.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg + ; CHECK-NEXT: MVE_VPST 8, implicit $vpr + ; CHECK-NEXT: renamable $r0, renamable $q0 = MVE_VLDRHU32_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) + ; CHECK-NEXT: renamable $q0 = MVE_VMVN killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: $lr = tMOVr $r3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg + ; CHECK-NEXT: renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr) + ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.exit: + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $r7, $lr @@ -1593,44 +1639,52 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: illegal_vaddva_u32 ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.4(0x30000000), %bb.1(0x50000000) - ; CHECK: liveins: $lr, $r0, $r1, $r7 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: tCBZ $r1, %bb.4 - ; CHECK: bb.1.vector.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1 - ; CHECK: renamable $r2, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg - ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $r2 = t2BICri killed renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg - ; CHECK: renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg - ; CHECK: dead $lr = t2DLS renamable $r2 - ; CHECK: $r3 = tMOVr killed $r2, 14 /* CC::al */, $noreg - ; CHECK: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg - ; CHECK: bb.2.vector.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg, $noreg - ; CHECK: MVE_VPST 8, implicit $vpr - ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRHU32_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) - ; CHECK: $lr = tMOVr $r3, 14 /* CC::al */, $noreg - ; CHECK: renamable $q0 = MVE_VMVN killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg - ; CHECK: renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg, $noreg - ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 - ; CHECK: bb.3.exit: - ; CHECK: liveins: $r2 - ; CHECK: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 - ; CHECK: bb.4: - ; CHECK: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg - ; CHECK: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 + ; CHECK-NEXT: successors: %bb.4(0x30000000), %bb.1(0x50000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: tCBZ $r1, %bb.4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.vector.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r2, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r2 = t2BICri killed renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: dead $lr = t2DLS renamable $r2 + ; CHECK-NEXT: $r3 = tMOVr killed $r2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.vector.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg, $noreg + ; CHECK-NEXT: MVE_VPST 8, implicit $vpr + ; CHECK-NEXT: renamable $r0, renamable $q0 = MVE_VLDRHU32_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) + ; CHECK-NEXT: $lr = tMOVr $r3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $q0 = MVE_VMVN killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg, $noreg + ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.exit: + ; CHECK-NEXT: liveins: $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4: + ; CHECK-NEXT: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 bb.0.entry: successors: %bb.4(0x30000000), %bb.1(0x50000000) liveins: $r0, $r1, $r7, $lr @@ -1718,43 +1772,49 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: illegal_vaddv_s16 ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r4 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 - ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 0, 8, implicit-def $itstate - ; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $pc, implicit killed $itstate - ; CHECK: bb.1.vector.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2 - ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg - ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r3 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg - ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from %fixed-stack.0, align 8) - ; CHECK: dead $lr = t2DLS renamable $r12 - ; CHECK: $r4 = tMOVr killed $r12, 14 /* CC::al */, $noreg - ; CHECK: bb.2.vector.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $q0, $r0, $r1, $r2, $r4 - ; CHECK: renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg, $noreg - ; CHECK: MVE_VPST 8, implicit $vpr - ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRBS16_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 1) - ; CHECK: renamable $q1 = MVE_VSUBi16 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1 - ; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg - ; CHECK: renamable $r12 = MVE_VADDVu16no_acc killed renamable $q1, 0, $noreg, $noreg - ; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $r3 = t2SXTH killed renamable $r12, 0, 14 /* CC::al */, $noreg - ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 8, 14 /* CC::al */, $noreg - ; CHECK: early-clobber renamable $r1 = t2STR_POST killed renamable $r3, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr) - ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 - ; CHECK: bb.3.exit: - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -8 + ; CHECK-NEXT: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: t2IT 0, 8, implicit-def $itstate + ; CHECK-NEXT: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $pc, implicit killed $itstate + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.vector.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r3 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from %fixed-stack.0, align 8) + ; CHECK-NEXT: dead $lr = t2DLS renamable $r12 + ; CHECK-NEXT: $r4 = tMOVr killed $r12, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.vector.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $q0, $r0, $r1, $r2, $r4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg, $noreg + ; CHECK-NEXT: MVE_VPST 8, implicit $vpr + ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRBS16_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 1) + ; CHECK-NEXT: renamable $q1 = MVE_VSUBi16 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1 + ; CHECK-NEXT: $lr = tMOVr $r4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r12 = MVE_VADDVu16no_acc killed renamable $q1, 0, $noreg, $noreg + ; CHECK-NEXT: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r3 = t2SXTH killed renamable $r12, 0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 8, 14 /* CC::al */, $noreg + ; CHECK-NEXT: early-clobber renamable $r1 = t2STR_POST killed renamable $r3, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr) + ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.exit: + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc bb.0.entry: successors: %bb.1(0x80000000) @@ -1841,47 +1901,55 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: illegal_vaddva_s16 ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.4(0x30000000), %bb.1(0x50000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 - ; CHECK: tCBZ $r1, %bb.4 - ; CHECK: bb.1.vector.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: renamable $d0 = VMOVDRR killed renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg, implicit-def $q0 - ; CHECK: renamable $r2, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg - ; CHECK: renamable $r2 = t2BICri killed renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg - ; CHECK: renamable $d1 = VLDRD $sp, 2, 14 /* CC::al */, $noreg, implicit killed $q0, implicit-def $q0 :: (load (s64) from %fixed-stack.0) - ; CHECK: renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg - ; CHECK: dead $lr = t2DLS renamable $r2 - ; CHECK: $r4 = tMOVr killed $r2, 14 /* CC::al */, $noreg - ; CHECK: bb.2.vector.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $q0, $r0, $r1, $r3, $r4 - ; CHECK: renamable $vpr = MVE_VCTP16 renamable $r1, 0, $noreg, $noreg - ; CHECK: MVE_VPST 8, implicit $vpr - ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRBS16_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 1) - ; CHECK: renamable $q1 = MVE_VSUBi16 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1 - ; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg - ; CHECK: renamable $r2 = MVE_VADDVu16no_acc killed renamable $q1, 0, $noreg, $noreg - ; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $r3 = t2SXTAH killed renamable $r3, killed renamable $r2, 0, 14 /* CC::al */, $noreg - ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 8, 14 /* CC::al */, $noreg - ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 - ; CHECK: bb.3.exit: - ; CHECK: liveins: $r3 - ; CHECK: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0 - ; CHECK: bb.4: - ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg - ; CHECK: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0 + ; CHECK-NEXT: successors: %bb.4(0x30000000), %bb.1(0x50000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -8 + ; CHECK-NEXT: tCBZ $r1, %bb.4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.vector.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $d0 = VMOVDRR killed renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg, implicit-def $q0 + ; CHECK-NEXT: renamable $r2, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r2 = t2BICri killed renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $d1 = VLDRD $sp, 2, 14 /* CC::al */, $noreg, implicit killed $q0, implicit-def $q0 :: (load (s64) from %fixed-stack.0) + ; CHECK-NEXT: renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: dead $lr = t2DLS renamable $r2 + ; CHECK-NEXT: $r4 = tMOVr killed $r2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.vector.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $q0, $r0, $r1, $r3, $r4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $vpr = MVE_VCTP16 renamable $r1, 0, $noreg, $noreg + ; CHECK-NEXT: MVE_VPST 8, implicit $vpr + ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRBS16_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 1) + ; CHECK-NEXT: renamable $q1 = MVE_VSUBi16 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1 + ; CHECK-NEXT: $lr = tMOVr $r4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r2 = MVE_VADDVu16no_acc killed renamable $q1, 0, $noreg, $noreg + ; CHECK-NEXT: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r3 = t2SXTAH killed renamable $r3, killed renamable $r2, 0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 8, 14 /* CC::al */, $noreg + ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.exit: + ; CHECK-NEXT: liveins: $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4: + ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0 bb.0.entry: successors: %bb.4(0x30000000), %bb.1(0x50000000) liveins: $r0, $r1, $r2, $r3, $r4, $lr @@ -1972,43 +2040,49 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: illegal_vaddv_u16 ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r4 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 - ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 0, 8, implicit-def $itstate - ; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $pc, implicit killed $itstate - ; CHECK: bb.1.vector.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2 - ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg - ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r3 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg - ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from %fixed-stack.0, align 8) - ; CHECK: dead $lr = t2DLS renamable $r12 - ; CHECK: $r4 = tMOVr killed $r12, 14 /* CC::al */, $noreg - ; CHECK: bb.2.vector.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $q0, $r0, $r1, $r2, $r4 - ; CHECK: renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg, $noreg - ; CHECK: MVE_VPST 8, implicit $vpr - ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv17, align 2) - ; CHECK: renamable $q1 = MVE_VSUBi16 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1 - ; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg - ; CHECK: renamable $r12 = MVE_VADDVu16no_acc killed renamable $q1, 0, $noreg, $noreg - ; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $r3 = t2UXTH killed renamable $r12, 0, 14 /* CC::al */, $noreg - ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 8, 14 /* CC::al */, $noreg - ; CHECK: early-clobber renamable $r1 = t2STR_POST killed renamable $r3, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr) - ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 - ; CHECK: bb.3.exit: - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -8 + ; CHECK-NEXT: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: t2IT 0, 8, implicit-def $itstate + ; CHECK-NEXT: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $pc, implicit killed $itstate + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.vector.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r3 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from %fixed-stack.0, align 8) + ; CHECK-NEXT: dead $lr = t2DLS renamable $r12 + ; CHECK-NEXT: $r4 = tMOVr killed $r12, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.vector.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $q0, $r0, $r1, $r2, $r4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg, $noreg + ; CHECK-NEXT: MVE_VPST 8, implicit $vpr + ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv17, align 2) + ; CHECK-NEXT: renamable $q1 = MVE_VSUBi16 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1 + ; CHECK-NEXT: $lr = tMOVr $r4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r12 = MVE_VADDVu16no_acc killed renamable $q1, 0, $noreg, $noreg + ; CHECK-NEXT: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r3 = t2UXTH killed renamable $r12, 0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 8, 14 /* CC::al */, $noreg + ; CHECK-NEXT: early-clobber renamable $r1 = t2STR_POST killed renamable $r3, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr) + ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.exit: + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $r4, $lr @@ -2094,47 +2168,55 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: illegal_vaddva_u16 ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.4(0x30000000), %bb.1(0x50000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 - ; CHECK: tCBZ $r1, %bb.4 - ; CHECK: bb.1.vector.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: renamable $d0 = VMOVDRR killed renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg, implicit-def $q0 - ; CHECK: renamable $r2, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg - ; CHECK: renamable $r2 = t2BICri killed renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg - ; CHECK: renamable $d1 = VLDRD $sp, 2, 14 /* CC::al */, $noreg, implicit killed $q0, implicit-def $q0 :: (load (s64) from %fixed-stack.0) - ; CHECK: renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg - ; CHECK: dead $lr = t2DLS renamable $r2 - ; CHECK: $r4 = tMOVr killed $r2, 14 /* CC::al */, $noreg - ; CHECK: bb.2.vector.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $q0, $r0, $r1, $r3, $r4 - ; CHECK: renamable $vpr = MVE_VCTP16 renamable $r1, 0, $noreg, $noreg - ; CHECK: MVE_VPST 8, implicit $vpr - ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv17, align 2) - ; CHECK: renamable $q1 = MVE_VSUBi16 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1 - ; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg - ; CHECK: renamable $r2 = MVE_VADDVu16no_acc killed renamable $q1, 0, $noreg, $noreg - ; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $r3 = t2UXTAH killed renamable $r3, killed renamable $r2, 0, 14 /* CC::al */, $noreg - ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 8, 14 /* CC::al */, $noreg - ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 - ; CHECK: bb.3.exit: - ; CHECK: liveins: $r3 - ; CHECK: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0 - ; CHECK: bb.4: - ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg - ; CHECK: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0 + ; CHECK-NEXT: successors: %bb.4(0x30000000), %bb.1(0x50000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -8 + ; CHECK-NEXT: tCBZ $r1, %bb.4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.vector.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $d0 = VMOVDRR killed renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg, implicit-def $q0 + ; CHECK-NEXT: renamable $r2, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r2 = t2BICri killed renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $d1 = VLDRD $sp, 2, 14 /* CC::al */, $noreg, implicit killed $q0, implicit-def $q0 :: (load (s64) from %fixed-stack.0) + ; CHECK-NEXT: renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: dead $lr = t2DLS renamable $r2 + ; CHECK-NEXT: $r4 = tMOVr killed $r2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.vector.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $q0, $r0, $r1, $r3, $r4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $vpr = MVE_VCTP16 renamable $r1, 0, $noreg, $noreg + ; CHECK-NEXT: MVE_VPST 8, implicit $vpr + ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv17, align 2) + ; CHECK-NEXT: renamable $q1 = MVE_VSUBi16 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1 + ; CHECK-NEXT: $lr = tMOVr $r4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r2 = MVE_VADDVu16no_acc killed renamable $q1, 0, $noreg, $noreg + ; CHECK-NEXT: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r3 = t2UXTAH killed renamable $r3, killed renamable $r2, 0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 8, 14 /* CC::al */, $noreg + ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.exit: + ; CHECK-NEXT: liveins: $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4: + ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0 bb.0.entry: successors: %bb.4(0x30000000), %bb.1(0x50000000) liveins: $r0, $r1, $r2, $r3, $r4, $lr @@ -2225,43 +2307,49 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: illegal_vaddv_s8 ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r4 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 - ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 0, 8, implicit-def $itstate - ; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $pc, implicit killed $itstate - ; CHECK: bb.1.vector.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2 - ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 7, 14 /* CC::al */, $noreg - ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r3 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg - ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from %fixed-stack.0, align 8) - ; CHECK: dead $lr = t2DLS renamable $r12 - ; CHECK: $r4 = tMOVr killed $r12, 14 /* CC::al */, $noreg - ; CHECK: bb.2.vector.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $q0, $r0, $r1, $r2, $r4 - ; CHECK: renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg, $noreg - ; CHECK: MVE_VPST 8, implicit $vpr - ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv17, align 1) - ; CHECK: renamable $q1 = MVE_VEOR killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1 - ; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg - ; CHECK: renamable $r12 = MVE_VADDVu8no_acc killed renamable $q1, 0, $noreg, $noreg - ; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $r3 = t2SXTB killed renamable $r12, 0, 14 /* CC::al */, $noreg - ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg - ; CHECK: early-clobber renamable $r1 = t2STR_POST killed renamable $r3, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr) - ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 - ; CHECK: bb.3.exit: - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -8 + ; CHECK-NEXT: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: t2IT 0, 8, implicit-def $itstate + ; CHECK-NEXT: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $pc, implicit killed $itstate + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.vector.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 7, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r3 = t2BICri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r3 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from %fixed-stack.0, align 8) + ; CHECK-NEXT: dead $lr = t2DLS renamable $r12 + ; CHECK-NEXT: $r4 = tMOVr killed $r12, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.vector.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $q0, $r0, $r1, $r2, $r4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg, $noreg + ; CHECK-NEXT: MVE_VPST 8, implicit $vpr + ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv17, align 1) + ; CHECK-NEXT: renamable $q1 = MVE_VEOR killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1 + ; CHECK-NEXT: $lr = tMOVr $r4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r12 = MVE_VADDVu8no_acc killed renamable $q1, 0, $noreg, $noreg + ; CHECK-NEXT: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r3 = t2SXTB killed renamable $r12, 0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg + ; CHECK-NEXT: early-clobber renamable $r1 = t2STR_POST killed renamable $r3, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr) + ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.exit: + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $r4, $lr @@ -2347,47 +2435,55 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: illegal_vaddva_s8 ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.4(0x30000000), %bb.1(0x50000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 - ; CHECK: tCBZ $r1, %bb.4 - ; CHECK: bb.1.vector.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: renamable $d0 = VMOVDRR killed renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg, implicit-def $q0 - ; CHECK: renamable $r2, dead $cpsr = tADDi3 renamable $r1, 7, 14 /* CC::al */, $noreg - ; CHECK: renamable $r2 = t2BICri killed renamable $r2, 7, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 7, 14 /* CC::al */, $noreg - ; CHECK: renamable $d1 = VLDRD $sp, 2, 14 /* CC::al */, $noreg, implicit killed $q0, implicit-def $q0 :: (load (s64) from %fixed-stack.0) - ; CHECK: renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 27, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg - ; CHECK: dead $lr = t2DLS renamable $r2 - ; CHECK: $r4 = tMOVr killed $r2, 14 /* CC::al */, $noreg - ; CHECK: bb.2.vector.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $q0, $r0, $r1, $r3, $r4 - ; CHECK: renamable $vpr = MVE_VCTP8 renamable $r1, 0, $noreg, $noreg - ; CHECK: MVE_VPST 8, implicit $vpr - ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv17, align 1) - ; CHECK: renamable $q1 = MVE_VEOR killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1 - ; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg - ; CHECK: renamable $r2 = MVE_VADDVu8no_acc killed renamable $q1, 0, $noreg, $noreg - ; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $r3 = t2SXTAB killed renamable $r3, killed renamable $r2, 0, 14 /* CC::al */, $noreg - ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg - ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 - ; CHECK: bb.3.exit: - ; CHECK: liveins: $r3 - ; CHECK: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0 - ; CHECK: bb.4: - ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg - ; CHECK: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0 + ; CHECK-NEXT: successors: %bb.4(0x30000000), %bb.1(0x50000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -8 + ; CHECK-NEXT: tCBZ $r1, %bb.4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.vector.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $d0 = VMOVDRR killed renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg, implicit-def $q0 + ; CHECK-NEXT: renamable $r2, dead $cpsr = tADDi3 renamable $r1, 7, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r2 = t2BICri killed renamable $r2, 7, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 7, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $d1 = VLDRD $sp, 2, 14 /* CC::al */, $noreg, implicit killed $q0, implicit-def $q0 :: (load (s64) from %fixed-stack.0) + ; CHECK-NEXT: renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 27, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: dead $lr = t2DLS renamable $r2 + ; CHECK-NEXT: $r4 = tMOVr killed $r2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.vector.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $q0, $r0, $r1, $r3, $r4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $vpr = MVE_VCTP8 renamable $r1, 0, $noreg, $noreg + ; CHECK-NEXT: MVE_VPST 8, implicit $vpr + ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv17, align 1) + ; CHECK-NEXT: renamable $q1 = MVE_VEOR killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1 + ; CHECK-NEXT: $lr = tMOVr $r4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r2 = MVE_VADDVu8no_acc killed renamable $q1, 0, $noreg, $noreg + ; CHECK-NEXT: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r3 = t2SXTAB killed renamable $r3, killed renamable $r2, 0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg + ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.exit: + ; CHECK-NEXT: liveins: $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4: + ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0 bb.0.entry: successors: %bb.4(0x30000000), %bb.1(0x50000000) liveins: $r0, $r1, $r2, $r3, $r4, $lr @@ -2478,43 +2574,49 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: illegal_vaddv_u8 ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r4 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 - ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 0, 8, implicit-def $itstate - ; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $pc, implicit killed $itstate - ; CHECK: bb.1.vector.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2 - ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 7, 14 /* CC::al */, $noreg - ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r3 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg - ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from %fixed-stack.0, align 8) - ; CHECK: dead $lr = t2DLS renamable $r12 - ; CHECK: $r4 = tMOVr killed $r12, 14 /* CC::al */, $noreg - ; CHECK: bb.2.vector.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $q0, $r0, $r1, $r2, $r4 - ; CHECK: renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg, $noreg - ; CHECK: MVE_VPST 8, implicit $vpr - ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv17, align 1) - ; CHECK: renamable $q1 = MVE_VEOR killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1 - ; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg - ; CHECK: renamable $r12 = MVE_VADDVu8no_acc killed renamable $q1, 0, $noreg, $noreg - ; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $r3 = t2UXTB killed renamable $r12, 0, 14 /* CC::al */, $noreg - ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg - ; CHECK: early-clobber renamable $r1 = t2STR_POST killed renamable $r3, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr) - ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 - ; CHECK: bb.3.exit: - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -8 + ; CHECK-NEXT: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: t2IT 0, 8, implicit-def $itstate + ; CHECK-NEXT: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $pc, implicit killed $itstate + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.vector.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 7, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r3 = t2BICri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r3 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from %fixed-stack.0, align 8) + ; CHECK-NEXT: dead $lr = t2DLS renamable $r12 + ; CHECK-NEXT: $r4 = tMOVr killed $r12, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.vector.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $q0, $r0, $r1, $r2, $r4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg, $noreg + ; CHECK-NEXT: MVE_VPST 8, implicit $vpr + ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv17, align 1) + ; CHECK-NEXT: renamable $q1 = MVE_VEOR killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1 + ; CHECK-NEXT: $lr = tMOVr $r4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r12 = MVE_VADDVu8no_acc killed renamable $q1, 0, $noreg, $noreg + ; CHECK-NEXT: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r3 = t2UXTB killed renamable $r12, 0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg + ; CHECK-NEXT: early-clobber renamable $r1 = t2STR_POST killed renamable $r3, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr) + ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.exit: + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $r4, $lr @@ -2600,47 +2702,55 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: illegal_vaddva_u8 ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.4(0x30000000), %bb.1(0x50000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 - ; CHECK: tCBZ $r1, %bb.4 - ; CHECK: bb.1.vector.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: renamable $d0 = VMOVDRR killed renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg, implicit-def $q0 - ; CHECK: renamable $r2, dead $cpsr = tADDi3 renamable $r1, 7, 14 /* CC::al */, $noreg - ; CHECK: renamable $r2 = t2BICri killed renamable $r2, 7, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 7, 14 /* CC::al */, $noreg - ; CHECK: renamable $d1 = VLDRD $sp, 2, 14 /* CC::al */, $noreg, implicit killed $q0, implicit-def $q0 :: (load (s64) from %fixed-stack.0) - ; CHECK: renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 27, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg - ; CHECK: dead $lr = t2DLS renamable $r2 - ; CHECK: $r4 = tMOVr killed $r2, 14 /* CC::al */, $noreg - ; CHECK: bb.2.vector.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $q0, $r0, $r1, $r3, $r4 - ; CHECK: renamable $vpr = MVE_VCTP8 renamable $r1, 0, $noreg, $noreg - ; CHECK: MVE_VPST 8, implicit $vpr - ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv17, align 1) - ; CHECK: renamable $q1 = MVE_VEOR killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1 - ; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg - ; CHECK: renamable $r2 = MVE_VADDVu8no_acc killed renamable $q1, 0, $noreg, $noreg - ; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $r3 = t2UXTAB killed renamable $r3, killed renamable $r2, 0, 14 /* CC::al */, $noreg - ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg - ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 - ; CHECK: bb.3.exit: - ; CHECK: liveins: $r3 - ; CHECK: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0 - ; CHECK: bb.4: - ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg - ; CHECK: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0 + ; CHECK-NEXT: successors: %bb.4(0x30000000), %bb.1(0x50000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -8 + ; CHECK-NEXT: tCBZ $r1, %bb.4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.vector.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $d0 = VMOVDRR killed renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg, implicit-def $q0 + ; CHECK-NEXT: renamable $r2, dead $cpsr = tADDi3 renamable $r1, 7, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r2 = t2BICri killed renamable $r2, 7, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 7, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $d1 = VLDRD $sp, 2, 14 /* CC::al */, $noreg, implicit killed $q0, implicit-def $q0 :: (load (s64) from %fixed-stack.0) + ; CHECK-NEXT: renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 27, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: dead $lr = t2DLS renamable $r2 + ; CHECK-NEXT: $r4 = tMOVr killed $r2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.vector.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $q0, $r0, $r1, $r3, $r4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $vpr = MVE_VCTP8 renamable $r1, 0, $noreg, $noreg + ; CHECK-NEXT: MVE_VPST 8, implicit $vpr + ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv17, align 1) + ; CHECK-NEXT: renamable $q1 = MVE_VEOR killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1 + ; CHECK-NEXT: $lr = tMOVr $r4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r2 = MVE_VADDVu8no_acc killed renamable $q1, 0, $noreg, $noreg + ; CHECK-NEXT: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r3 = t2UXTAB killed renamable $r3, killed renamable $r2, 0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg + ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.exit: + ; CHECK-NEXT: liveins: $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4: + ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0 bb.0.entry: successors: %bb.4(0x30000000), %bb.1(0x50000000) liveins: $r0, $r1, $r2, $r3, $r4, $lr @@ -2728,35 +2838,43 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: regalloc_legality_vaddva_u32 ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.1(0x50000000), %bb.4(0x30000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: tCMPi8 renamable $r2, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: tBcc %bb.4, 11 /* CC::lt */, killed $cpsr - ; CHECK: bb.1.while.body.preheader: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2 - ; CHECK: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2 - ; CHECK: bb.2.while.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $lr, $r0, $r1, $r12 - ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRHU32_post killed renamable $r1, 8, 0, $noreg, $noreg :: (load (s64) from %ir.tmp3, align 2) - ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHU32_post killed renamable $r0, 8, 0, killed $noreg, $noreg :: (load (s64) from %ir.tmp1, align 2) - ; CHECK: renamable $q0 = MVE_VORR killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: renamable $r12 = MVE_VADDVu32acc killed renamable $r12, killed renamable $q0, 0, $noreg, $noreg - ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 - ; CHECK: bb.3.while.end: - ; CHECK: liveins: $r12 - ; CHECK: $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 - ; CHECK: bb.4: - ; CHECK: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 + ; CHECK-NEXT: successors: %bb.1(0x50000000), %bb.4(0x30000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: tCMPi8 renamable $r2, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: tBcc %bb.4, 11 /* CC::lt */, killed $cpsr + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.while.body.preheader: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.while.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r1, renamable $q0 = MVE_VLDRHU32_post killed renamable $r1, 8, 0, $noreg, $noreg :: (load (s64) from %ir.tmp3, align 2) + ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRHU32_post killed renamable $r0, 8, 0, killed $noreg, $noreg :: (load (s64) from %ir.tmp1, align 2) + ; CHECK-NEXT: renamable $q0 = MVE_VORR killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: renamable $r12 = MVE_VADDVu32acc killed renamable $r12, killed renamable $q0, 0, $noreg, $noreg + ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.while.end: + ; CHECK-NEXT: liveins: $r12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4: + ; CHECK-NEXT: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 bb.0.entry: successors: %bb.1(0x50000000), %bb.4(0x30000000) liveins: $r0, $r1, $r2, $r7, $lr @@ -2843,36 +2961,44 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: regalloc_legality_vaddv_u16 ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.1(0x50000000), %bb.4(0x30000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: tCMPi8 renamable $r2, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: tBcc %bb.4, 11 /* CC::lt */, killed $cpsr - ; CHECK: bb.1.while.body.preheader: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2 - ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg - ; CHECK: $lr = MVE_DLSTP_16 killed renamable $r2 - ; CHECK: bb.2.while.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $lr, $r0, $r1, $r3 - ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 0, $noreg, $noreg :: (load (s128) from %ir.tmp3, align 2) - ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 0, killed $noreg, $noreg :: (load (s128) from %ir.tmp1, align 2) - ; CHECK: renamable $q0 = MVE_VORR killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: renamable $r12 = MVE_VADDVu16no_acc killed renamable $q0, 0, $noreg, $noreg - ; CHECK: renamable $r3 = t2UXTAH killed renamable $r3, killed renamable $r12, 0, 14 /* CC::al */, $noreg - ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 - ; CHECK: bb.3.while.end: - ; CHECK: liveins: $r3 - ; CHECK: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 - ; CHECK: bb.4: - ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg - ; CHECK: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 + ; CHECK-NEXT: successors: %bb.1(0x50000000), %bb.4(0x30000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: tCMPi8 renamable $r2, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: tBcc %bb.4, 11 /* CC::lt */, killed $cpsr + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.while.body.preheader: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $lr = MVE_DLSTP_16 killed renamable $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.while.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 0, $noreg, $noreg :: (load (s128) from %ir.tmp3, align 2) + ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 0, killed $noreg, $noreg :: (load (s128) from %ir.tmp1, align 2) + ; CHECK-NEXT: renamable $q0 = MVE_VORR killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: renamable $r12 = MVE_VADDVu16no_acc killed renamable $q0, 0, $noreg, $noreg + ; CHECK-NEXT: renamable $r3 = t2UXTAH killed renamable $r3, killed renamable $r12, 0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.while.end: + ; CHECK-NEXT: liveins: $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4: + ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 bb.0.entry: successors: %bb.1(0x50000000), %bb.4(0x30000000) liveins: $r0, $r1, $r2, $r7, $lr @@ -2960,47 +3086,55 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: regalloc_illegality_vaddva_s32 ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.1(0x50000000), %bb.4(0x30000000) - ; CHECK: liveins: $lr, $r0, $r1, $r3, $r7 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: tCMPi8 renamable $r3, 8, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: $r2 = tMOVr $r3, 14 /* CC::al */, $noreg - ; CHECK: t2IT 10, 8, implicit-def $itstate - ; CHECK: renamable $r2 = tMOVi8 $noreg, 8, 10 /* CC::ge */, killed $cpsr, implicit killed renamable $r2, implicit killed $itstate - ; CHECK: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: tBcc %bb.4, 11 /* CC::lt */, killed $cpsr - ; CHECK: bb.1.while.body.preheader: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: renamable $r2, dead $cpsr = tSUBrr renamable $r3, killed renamable $r2, 14 /* CC::al */, $noreg - ; CHECK: renamable $r12 = t2ADDri killed renamable $r2, 7, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r2, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg - ; CHECK: bb.2.while.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 - ; CHECK: renamable $vpr = MVE_VCTP16 renamable $r3, 0, $noreg, $noreg - ; CHECK: MVE_VPST 4, implicit $vpr - ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.tmp3, align 2) - ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.tmp1, align 2) - ; CHECK: renamable $q2 = MVE_VMULLBs16 renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q2 - ; CHECK: renamable $q0 = MVE_VMULLTs16 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q0, killed renamable $q2, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 8, 14 /* CC::al */, $noreg - ; CHECK: renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg, $noreg - ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 - ; CHECK: bb.3.while.end: - ; CHECK: liveins: $r2 - ; CHECK: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 - ; CHECK: bb.4: - ; CHECK: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg - ; CHECK: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 + ; CHECK-NEXT: successors: %bb.1(0x50000000), %bb.4(0x30000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r3, $r7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: tCMPi8 renamable $r3, 8, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: $r2 = tMOVr $r3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: t2IT 10, 8, implicit-def $itstate + ; CHECK-NEXT: renamable $r2 = tMOVi8 $noreg, 8, 10 /* CC::ge */, killed $cpsr, implicit killed renamable $r2, implicit killed $itstate + ; CHECK-NEXT: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: tBcc %bb.4, 11 /* CC::lt */, killed $cpsr + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.while.body.preheader: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBrr renamable $r3, killed renamable $r2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r12 = t2ADDri killed renamable $r2, 7, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r2, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.while.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $vpr = MVE_VCTP16 renamable $r3, 0, $noreg, $noreg + ; CHECK-NEXT: MVE_VPST 4, implicit $vpr + ; CHECK-NEXT: renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.tmp3, align 2) + ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.tmp1, align 2) + ; CHECK-NEXT: renamable $q2 = MVE_VMULLBs16 renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q2 + ; CHECK-NEXT: renamable $q0 = MVE_VMULLTs16 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: renamable $q0 = MVE_VADDi32 killed renamable $q0, killed renamable $q2, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 8, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg, $noreg + ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.while.end: + ; CHECK-NEXT: liveins: $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4: + ; CHECK-NEXT: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 bb.0.entry: successors: %bb.1(0x50000000), %bb.4(0x30000000) liveins: $r0, $r1, $r3, $r7, $lr @@ -3083,49 +3217,57 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: illegal_vmull_non_zero ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.1(0x50000000), %bb.4(0x30000000) - ; CHECK: liveins: $lr, $r0, $r1, $r3, $r7 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: tCMPi8 renamable $r3, 8, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: $r2 = tMOVr $r3, 14 /* CC::al */, $noreg - ; CHECK: t2IT 10, 8, implicit-def $itstate - ; CHECK: renamable $r2 = tMOVi8 $noreg, 8, 10 /* CC::ge */, killed $cpsr, implicit killed renamable $r2, implicit killed $itstate - ; CHECK: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: tBcc %bb.4, 11 /* CC::lt */, killed $cpsr - ; CHECK: bb.1.while.body.preheader: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: renamable $r2, dead $cpsr = tSUBrr renamable $r3, killed renamable $r2, 14 /* CC::al */, $noreg - ; CHECK: renamable $r12 = t2ADDri killed renamable $r2, 7, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r2, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $r2 = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg - ; CHECK: dead $lr = t2DLS renamable $r2 - ; CHECK: $r12 = tMOVr killed $r2, 14 /* CC::al */, $noreg - ; CHECK: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg - ; CHECK: bb.2.while.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3, $r12 - ; CHECK: renamable $vpr = MVE_VCTP16 renamable $r3, 0, $noreg, $noreg - ; CHECK: MVE_VPST 4, implicit $vpr - ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.tmp3, align 2) - ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.tmp1, align 2) - ; CHECK: $lr = tMOVr $r12, 14 /* CC::al */, $noreg - ; CHECK: renamable $q0 = MVE_VMULLTs16 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: renamable $r12 = nsw t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 8, 14 /* CC::al */, $noreg - ; CHECK: renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg, $noreg - ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 - ; CHECK: bb.3.while.end: - ; CHECK: liveins: $r2 - ; CHECK: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg - ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 - ; CHECK: bb.4: - ; CHECK: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg - ; CHECK: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg - ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 + ; CHECK-NEXT: successors: %bb.1(0x50000000), %bb.4(0x30000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r3, $r7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: tCMPi8 renamable $r3, 8, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: $r2 = tMOVr $r3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: t2IT 10, 8, implicit-def $itstate + ; CHECK-NEXT: renamable $r2 = tMOVi8 $noreg, 8, 10 /* CC::ge */, killed $cpsr, implicit killed renamable $r2, implicit killed $itstate + ; CHECK-NEXT: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: tBcc %bb.4, 11 /* CC::lt */, killed $cpsr + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.while.body.preheader: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBrr renamable $r3, killed renamable $r2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r12 = t2ADDri killed renamable $r2, 7, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r2, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r2 = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: dead $lr = t2DLS renamable $r2 + ; CHECK-NEXT: $r12 = tMOVr killed $r2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.while.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3, $r12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $vpr = MVE_VCTP16 renamable $r3, 0, $noreg, $noreg + ; CHECK-NEXT: MVE_VPST 4, implicit $vpr + ; CHECK-NEXT: renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.tmp3, align 2) + ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.tmp1, align 2) + ; CHECK-NEXT: $lr = tMOVr $r12, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $q0 = MVE_VMULLTs16 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: renamable $r12 = nsw t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 8, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg, $noreg + ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.while.end: + ; CHECK-NEXT: liveins: $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4: + ; CHECK-NEXT: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 bb.0.entry: successors: %bb.1(0x50000000), %bb.4(0x30000000) liveins: $r0, $r1, $r3, $r7, $lr diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-add-operand-liveout.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-add-operand-liveout.mir index 32ea68ab3312a..8c3ce289a82c2 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-add-operand-liveout.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-add-operand-liveout.mir @@ -109,48 +109,55 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: wrong_vctp_liveout ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 - ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 0, 4, implicit-def $itstate - ; CHECK: renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate - ; CHECK: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate - ; CHECK: bb.1.vector.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg - ; CHECK: renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q1 - ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg - ; CHECK: dead $lr = t2DLS renamable $r12 - ; CHECK: $r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg - ; CHECK: bb.2.vector.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $q1, $r0, $r1, $r2, $r3 - ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg - ; CHECK: $q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, $noreg, undef $q0 - ; CHECK: MVE_VPST 4, implicit $vpr - ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) - ; CHECK: renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2) - ; CHECK: $lr = tMOVr $r3, 14 /* CC::al */, $noreg - ; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1 - ; CHECK: renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg - ; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1 - ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 - ; CHECK: bb.3.middle.block: - ; CHECK: liveins: $q0, $q1, $r2 - ; CHECK: renamable $r0, dead $cpsr = tADDi3 killed renamable $r2, 4, 14 /* CC::al */, $noreg - ; CHECK: renamable $vpr = MVE_VCTP32 killed renamable $r0, 0, $noreg, $noreg - ; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr, $noreg - ; CHECK: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: t2IT 0, 4, implicit-def $itstate + ; CHECK-NEXT: renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate + ; CHECK-NEXT: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.vector.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q1 + ; CHECK-NEXT: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: dead $lr = t2DLS renamable $r12 + ; CHECK-NEXT: $r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.vector.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $q1, $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg + ; CHECK-NEXT: $q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, $noreg, undef $q0 + ; CHECK-NEXT: MVE_VPST 4, implicit $vpr + ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) + ; CHECK-NEXT: renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2) + ; CHECK-NEXT: $lr = tMOVr $r3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1 + ; CHECK-NEXT: renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1 + ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.middle.block: + ; CHECK-NEXT: liveins: $q0, $q1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r0, dead $cpsr = tADDi3 killed renamable $r2, 4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 killed renamable $r0, 0, $noreg, $noreg + ; CHECK-NEXT: renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr, $noreg + ; CHECK-NEXT: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $lr, $r7 diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-in-vpt-2.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-in-vpt-2.mir index 1fb505bbfc7c7..a5ddb4bcd84d4 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-in-vpt-2.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-in-vpt-2.mir @@ -2,7 +2,6 @@ # RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops -verify-machineinstrs %s -o - | FileCheck %s --- | - ; Function Attrs: nofree norecurse nounwind define dso_local void @test(i32* noalias nocapture %arg, i32* noalias nocapture readonly %arg1, i32 %arg2, i16 zeroext %mask) local_unnamed_addr #0 { bb: %tmp = icmp eq i32 %arg2, 0 @@ -105,39 +104,45 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: test ; CHECK: bb.0.bb: - ; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7 - ; CHECK: $sp = frame-setup tSUBspi $sp, 1, 14 /* CC::al */, $noreg - ; CHECK: tCBZ $r2, %bb.3 - ; CHECK: bb.1.bb3: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: $vpr = VMSR_P0 killed $r3, 14 /* CC::al */, $noreg - ; CHECK: VSTR_P0_off killed renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0) - ; CHECK: $r3 = tMOVr $r0, 14 /* CC::al */, $noreg - ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2 - ; CHECK: bb.2.bb9: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $lr, $r0, $r1, $r3 - ; CHECK: renamable $vpr = VLDR_P0_off $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0) - ; CHECK: MVE_VPST 8, implicit $vpr - ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv24, align 4) - ; CHECK: MVE_VPTv4i32r 8, renamable $q0, $zr, 1, implicit-def $vpr - ; CHECK: renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1, align 4) - ; CHECK: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: MVE_VPST 8, implicit $vpr - ; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv1, align 4) - ; CHECK: $r0 = tMOVr $r3, 14 /* CC::al */, $noreg - ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 - ; CHECK: bb.3.bb27: - ; CHECK: $sp = tADDspi $sp, 1, 14 /* CC::al */, $noreg - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc + ; CHECK-NEXT: successors: %bb.3(0x30000000), %bb.1(0x50000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $r7 + ; CHECK-NEXT: $sp = frame-setup tSUBspi $sp, 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: tCBZ $r2, %bb.3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.bb3: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $vpr = VMSR_P0 killed $r3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: VSTR_P0_off killed renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0) + ; CHECK-NEXT: $r3 = tMOVr $r0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.bb9: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $vpr = VLDR_P0_off $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0) + ; CHECK-NEXT: MVE_VPST 8, implicit $vpr + ; CHECK-NEXT: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv24, align 4) + ; CHECK-NEXT: MVE_VPTv4i32r 8, renamable $q0, $zr, 1, implicit-def $vpr + ; CHECK-NEXT: renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1, align 4) + ; CHECK-NEXT: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: MVE_VPST 8, implicit $vpr + ; CHECK-NEXT: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv1, align 4) + ; CHECK-NEXT: $r0 = tMOVr $r3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.bb27: + ; CHECK-NEXT: $sp = tADDspi $sp, 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc bb.0.bb: successors: %bb.3(0x30000000), %bb.1(0x50000000) liveins: $r0, $r1, $r2, $r3, $lr diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-in-vpt.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-in-vpt.mir index 0615fce40b668..fdbbede4f46e9 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-in-vpt.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-in-vpt.mir @@ -1,7 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -verify-machineinstrs -o - | FileCheck %s --- | - ; Function Attrs: nofree norecurse nounwind define dso_local void @test_vldr_p0(i32* noalias nocapture %arg, i32* noalias nocapture readonly %arg1, i32 %arg2, i16 zeroext %mask) local_unnamed_addr #0 { bb: %tmp = icmp eq i32 %arg2, 0 @@ -136,38 +135,44 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: test_vldr_p0 ; CHECK: bb.0.bb: - ; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7 - ; CHECK: $sp = frame-setup tSUBspi $sp, 1, 14 /* CC::al */, $noreg - ; CHECK: tCBZ $r2, %bb.3 - ; CHECK: bb.1.bb3: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: $vpr = VMSR_P0 killed $r3, 14 /* CC::al */, $noreg - ; CHECK: VSTR_P0_off killed renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0) - ; CHECK: $r3 = tMOVr $r0, 14 /* CC::al */, $noreg - ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2 - ; CHECK: bb.2.bb9: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $lr, $r0, $r1, $r3 - ; CHECK: renamable $vpr = VLDR_P0_off $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0) - ; CHECK: MVE_VPST 4, implicit $vpr - ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv24, align 4) - ; CHECK: renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1, align 4) - ; CHECK: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: MVE_VPST 8, implicit $vpr - ; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv1, align 4) - ; CHECK: $r0 = tMOVr $r3, 14 /* CC::al */, $noreg - ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 - ; CHECK: bb.3.bb27: - ; CHECK: $sp = tADDspi $sp, 1, 14 /* CC::al */, $noreg - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc + ; CHECK-NEXT: successors: %bb.3(0x30000000), %bb.1(0x50000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $r7 + ; CHECK-NEXT: $sp = frame-setup tSUBspi $sp, 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: tCBZ $r2, %bb.3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.bb3: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $vpr = VMSR_P0 killed $r3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: VSTR_P0_off killed renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0) + ; CHECK-NEXT: $r3 = tMOVr $r0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.bb9: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $vpr = VLDR_P0_off $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0) + ; CHECK-NEXT: MVE_VPST 4, implicit $vpr + ; CHECK-NEXT: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv24, align 4) + ; CHECK-NEXT: renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1, align 4) + ; CHECK-NEXT: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: MVE_VPST 8, implicit $vpr + ; CHECK-NEXT: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv1, align 4) + ; CHECK-NEXT: $r0 = tMOVr $r3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.bb27: + ; CHECK-NEXT: $sp = tADDspi $sp, 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc bb.0.bb: successors: %bb.3(0x30000000), %bb.1(0x50000000) liveins: $r0, $r1, $r2, $r3, $lr @@ -270,45 +275,51 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: test_vstr_p0 ; CHECK: bb.0.bb: - ; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7 - ; CHECK: $sp = frame-setup tSUBspi $sp, 1, 14 /* CC::al */, $noreg - ; CHECK: tCBZ $r2, %bb.3 - ; CHECK: bb.1.bb3: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: renamable $r12 = t2ADDri renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r12 = t2BICri killed renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $vpr = VMSR_P0 killed $r3, 14 /* CC::al */, $noreg - ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg - ; CHECK: VSTR_P0_off killed renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0) - ; CHECK: $r3 = tMOVr $r0, 14 /* CC::al */, $noreg - ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg - ; CHECK: bb.2.bb9: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 - ; CHECK: renamable $vpr = VLDR_P0_off $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0) - ; CHECK: MVE_VPST 2, implicit $vpr - ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr, $noreg - ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg - ; CHECK: renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, renamable $vpr, $noreg - ; CHECK: VSTR_P0_off renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0) - ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg - ; CHECK: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: MVE_VPST 8, implicit $vpr - ; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr, $noreg - ; CHECK: $r0 = tMOVr $r3, 14 /* CC::al */, $noreg - ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 - ; CHECK: bb.3.bb27: - ; CHECK: $sp = tADDspi $sp, 1, 14 /* CC::al */, $noreg - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc + ; CHECK-NEXT: successors: %bb.3(0x30000000), %bb.1(0x50000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $r7 + ; CHECK-NEXT: $sp = frame-setup tSUBspi $sp, 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: tCBZ $r2, %bb.3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.bb3: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r12 = t2ADDri renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r12 = t2BICri killed renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: $vpr = VMSR_P0 killed $r3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: VSTR_P0_off killed renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0) + ; CHECK-NEXT: $r3 = tMOVr $r0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.bb9: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $vpr = VLDR_P0_off $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0) + ; CHECK-NEXT: MVE_VPST 2, implicit $vpr + ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr, $noreg + ; CHECK-NEXT: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg + ; CHECK-NEXT: renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, renamable $vpr, $noreg + ; CHECK-NEXT: VSTR_P0_off renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0) + ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: MVE_VPST 8, implicit $vpr + ; CHECK-NEXT: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr, $noreg + ; CHECK-NEXT: $r0 = tMOVr $r3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.bb27: + ; CHECK-NEXT: $sp = tADDspi $sp, 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc bb.0.bb: successors: %bb.3(0x30000000), %bb.1(0x50000000) liveins: $r0, $r1, $r2, $r3, $lr @@ -412,45 +423,51 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: test_vmsr_p0 ; CHECK: bb.0.bb: - ; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7 - ; CHECK: $sp = frame-setup tSUBspi $sp, 1, 14 /* CC::al */, $noreg - ; CHECK: tCBZ $r2, %bb.3 - ; CHECK: bb.1.bb3: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: renamable $r12 = t2ADDri renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r12 = t2BICri killed renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $vpr = VMSR_P0 killed $r3, 14 /* CC::al */, $noreg - ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg - ; CHECK: VSTR_P0_off killed renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0) - ; CHECK: $r3 = tMOVr $r0, 14 /* CC::al */, $noreg - ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg - ; CHECK: bb.2.bb9: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 - ; CHECK: renamable $vpr = VLDR_P0_off $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0) - ; CHECK: MVE_VPST 2, implicit $vpr - ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr, $noreg - ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg - ; CHECK: renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, killed renamable $vpr, $noreg - ; CHECK: $vpr = VMSR_P0 $r3, 14 /* CC::al */, $noreg - ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg - ; CHECK: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: MVE_VPST 8, implicit $vpr - ; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr, $noreg - ; CHECK: $r0 = tMOVr $r3, 14 /* CC::al */, $noreg - ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 - ; CHECK: bb.3.bb27: - ; CHECK: $sp = tADDspi $sp, 1, 14 /* CC::al */, $noreg - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc + ; CHECK-NEXT: successors: %bb.3(0x30000000), %bb.1(0x50000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $r7 + ; CHECK-NEXT: $sp = frame-setup tSUBspi $sp, 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: tCBZ $r2, %bb.3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.bb3: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r12 = t2ADDri renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r12 = t2BICri killed renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: $vpr = VMSR_P0 killed $r3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: VSTR_P0_off killed renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0) + ; CHECK-NEXT: $r3 = tMOVr $r0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.bb9: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $vpr = VLDR_P0_off $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0) + ; CHECK-NEXT: MVE_VPST 2, implicit $vpr + ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr, $noreg + ; CHECK-NEXT: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg + ; CHECK-NEXT: renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, killed renamable $vpr, $noreg + ; CHECK-NEXT: $vpr = VMSR_P0 $r3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: MVE_VPST 8, implicit $vpr + ; CHECK-NEXT: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr, $noreg + ; CHECK-NEXT: $r0 = tMOVr $r3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.bb27: + ; CHECK-NEXT: $sp = tADDspi $sp, 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc bb.0.bb: successors: %bb.3(0x30000000), %bb.1(0x50000000) liveins: $r0, $r1, $r2, $r3, $lr @@ -554,45 +571,51 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: test_vmrs_p0 ; CHECK: bb.0.bb: - ; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7 - ; CHECK: $sp = frame-setup tSUBspi $sp, 1, 14 /* CC::al */, $noreg - ; CHECK: tCBZ $r2, %bb.3 - ; CHECK: bb.1.bb3: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: renamable $r12 = t2ADDri renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r12 = t2BICri killed renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $vpr = VMSR_P0 killed $r3, 14 /* CC::al */, $noreg - ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg - ; CHECK: VSTR_P0_off killed renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0) - ; CHECK: $r3 = tMOVr $r0, 14 /* CC::al */, $noreg - ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg - ; CHECK: bb.2.bb9: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 - ; CHECK: renamable $vpr = VLDR_P0_off $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0) - ; CHECK: MVE_VPST 2, implicit $vpr - ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr, $noreg - ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg - ; CHECK: dead renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, renamable $vpr, $noreg - ; CHECK: $r3 = VMRS_P0 $vpr, 14 /* CC::al */, $noreg - ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg - ; CHECK: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: MVE_VPST 8, implicit $vpr - ; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr, $noreg - ; CHECK: $r0 = tMOVr $r3, 14 /* CC::al */, $noreg - ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 - ; CHECK: bb.3.bb27: - ; CHECK: $sp = tADDspi $sp, 1, 14 /* CC::al */, $noreg - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc + ; CHECK-NEXT: successors: %bb.3(0x30000000), %bb.1(0x50000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $r7 + ; CHECK-NEXT: $sp = frame-setup tSUBspi $sp, 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: tCBZ $r2, %bb.3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.bb3: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r12 = t2ADDri renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r12 = t2BICri killed renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: $vpr = VMSR_P0 killed $r3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: VSTR_P0_off killed renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0) + ; CHECK-NEXT: $r3 = tMOVr $r0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.bb9: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $vpr = VLDR_P0_off $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0) + ; CHECK-NEXT: MVE_VPST 2, implicit $vpr + ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr, $noreg + ; CHECK-NEXT: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg + ; CHECK-NEXT: dead renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, renamable $vpr, $noreg + ; CHECK-NEXT: $r3 = VMRS_P0 $vpr, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: MVE_VPST 8, implicit $vpr + ; CHECK-NEXT: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr, $noreg + ; CHECK-NEXT: $r0 = tMOVr $r3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.bb27: + ; CHECK-NEXT: $sp = tADDspi $sp, 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc bb.0.bb: successors: %bb.3(0x30000000), %bb.1(0x50000000) liveins: $r0, $r1, $r2, $r3, $lr diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subi3.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subi3.mir index a9f4d7c1f8126..5a449326e5e08 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subi3.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subi3.mir @@ -99,29 +99,35 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: vctp_tsubi3 ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r7 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 11, 8, implicit-def $itstate - ; CHECK: tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate - ; CHECK: bb.1.vector.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3 - ; CHECK: bb.2.vector.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2 - ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv13, align 4) - ; CHECK: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv1416, align 4) - ; CHECK: renamable $q0 = nsw MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 0, killed $noreg, $noreg :: (store (s128) into %ir.lsr.iv1719, align 4) - ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 - ; CHECK: bb.3.for.cond.cleanup: - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: t2IT 11, 8, implicit-def $itstate + ; CHECK-NEXT: tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.vector.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.vector.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv13, align 4) + ; CHECK-NEXT: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv1416, align 4) + ; CHECK-NEXT: renamable $q0 = nsw MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 0, killed $noreg, $noreg :: (store (s128) into %ir.lsr.iv1719, align 4) + ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.for.cond.cleanup: + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $r3, $r7, $lr diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subri.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subri.mir index d995f11b6c0e1..09eeab51d2c76 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subri.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subri.mir @@ -98,29 +98,35 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: vctp_tsubi3 ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r7 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 11, 8, implicit-def $itstate - ; CHECK: tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate - ; CHECK: bb.1.vector.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3 - ; CHECK: bb.2.vector.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2 - ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv13, align 4) - ; CHECK: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv1416, align 4) - ; CHECK: renamable $q0 = nsw MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 0, killed $noreg, $noreg :: (store (s128) into %ir.lsr.iv1719, align 4) - ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 - ; CHECK: bb.3.for.cond.cleanup: - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: t2IT 11, 8, implicit-def $itstate + ; CHECK-NEXT: tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.vector.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.vector.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv13, align 4) + ; CHECK-NEXT: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv1416, align 4) + ; CHECK-NEXT: renamable $q0 = nsw MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 0, killed $noreg, $noreg :: (store (s128) into %ir.lsr.iv1719, align 4) + ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.for.cond.cleanup: + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $r3, $r7, $lr diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subri12.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subri12.mir index 48e161ded90fd..2869e501e8ea4 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subri12.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subri12.mir @@ -98,29 +98,35 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: vctp_tsubi3 ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r7 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 11, 8, implicit-def $itstate - ; CHECK: tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate - ; CHECK: bb.1.vector.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3 - ; CHECK: bb.2.vector.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2 - ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv13, align 4) - ; CHECK: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv1416, align 4) - ; CHECK: renamable $q0 = nsw MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 0, killed $noreg, $noreg :: (store (s128) into %ir.lsr.iv1719, align 4) - ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 - ; CHECK: bb.3.for.cond.cleanup: - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: t2IT 11, 8, implicit-def $itstate + ; CHECK-NEXT: tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.vector.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.vector.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv13, align 4) + ; CHECK-NEXT: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv1416, align 4) + ; CHECK-NEXT: renamable $q0 = nsw MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 0, killed $noreg, $noreg :: (store (s128) into %ir.lsr.iv1719, align 4) + ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.for.cond.cleanup: + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $r3, $r7, $lr diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vmldava_in_vpt.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vmldava_in_vpt.mir index 082095f713f4f..8b64249dda386 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vmldava_in_vpt.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vmldava_in_vpt.mir @@ -136,41 +136,48 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: vmldava_in_vpt ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.1(0x40000000), %bb.3(0x40000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 16 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -12 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -16 - ; CHECK: renamable $r4 = tLDRspi $sp, 9, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.5) - ; CHECK: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $lr = MVE_WLSTP_32 killed renamable $r4, %bb.3 - ; CHECK: bb.1.for.body.lr.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 - ; CHECK: renamable $r5 = tLDRspi $sp, 4, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8) - ; CHECK: $r6, $r12 = t2LDRDi8 $sp, 28, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.3), (load (s32) from %fixed-stack.4, align 8) - ; CHECK: renamable $q0 = MVE_VDUP32 killed renamable $r12, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: renamable $q1 = MVE_VDUP32 killed renamable $r6, 0, $noreg, $noreg, undef renamable $q1 - ; CHECK: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg - ; CHECK: bb.2.for.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $lr, $q0, $q1, $r0, $r1, $r2, $r3, $r5, $r12 - ; CHECK: renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 4, 0, $noreg, $noreg :: (load (s128) from %ir.input_2_cast, align 4) - ; CHECK: renamable $r0, renamable $q3 = MVE_VLDRWU32_post killed renamable $r0, 4, 0, $noreg, $noreg :: (load (s128) from %ir.input_1_cast, align 4) - ; CHECK: renamable $q2 = MVE_VADD_qr_i32 killed renamable $q2, renamable $r3, 0, $noreg, $noreg, undef renamable $q2 - ; CHECK: renamable $q3 = MVE_VADD_qr_i32 killed renamable $q3, renamable $r2, 0, $noreg, $noreg, undef renamable $q3 - ; CHECK: renamable $q3 = MVE_VMLAS_qr_i32 killed renamable $q3, killed renamable $q2, renamable $r5, 0, $noreg, $noreg - ; CHECK: renamable $q2 = MVE_VMAXu32 killed renamable $q3, renamable $q1, 0, $noreg, $noreg, undef renamable $q2 - ; CHECK: renamable $q3 = MVE_VMINu32 renamable $q2, renamable $q0, 0, $noreg, $noreg, undef renamable $q3 - ; CHECK: renamable $r12 = MVE_VMLADAVas32 killed renamable $r12, killed renamable $q3, killed renamable $q2, 0, killed $noreg, $noreg - ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 - ; CHECK: bb.3.for.cond.cleanup: - ; CHECK: liveins: $r12 - ; CHECK: $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg - ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $pc, implicit killed $r0 + ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.3(0x40000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r6, -8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r5, -12 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -16 + ; CHECK-NEXT: renamable $r4 = tLDRspi $sp, 9, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.5) + ; CHECK-NEXT: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: $lr = MVE_WLSTP_32 killed renamable $r4, %bb.3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.for.body.lr.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r5 = tLDRspi $sp, 4, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8) + ; CHECK-NEXT: $r6, $r12 = t2LDRDi8 $sp, 28, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.3), (load (s32) from %fixed-stack.4, align 8) + ; CHECK-NEXT: renamable $q0 = MVE_VDUP32 killed renamable $r12, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: renamable $q1 = MVE_VDUP32 killed renamable $r6, 0, $noreg, $noreg, undef renamable $q1 + ; CHECK-NEXT: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.for.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $lr, $q0, $q1, $r0, $r1, $r2, $r3, $r5, $r12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 4, 0, $noreg, $noreg :: (load (s128) from %ir.input_2_cast, align 4) + ; CHECK-NEXT: renamable $r0, renamable $q3 = MVE_VLDRWU32_post killed renamable $r0, 4, 0, $noreg, $noreg :: (load (s128) from %ir.input_1_cast, align 4) + ; CHECK-NEXT: renamable $q2 = MVE_VADD_qr_i32 killed renamable $q2, renamable $r3, 0, $noreg, $noreg, undef renamable $q2 + ; CHECK-NEXT: renamable $q3 = MVE_VADD_qr_i32 killed renamable $q3, renamable $r2, 0, $noreg, $noreg, undef renamable $q3 + ; CHECK-NEXT: renamable $q3 = MVE_VMLAS_qr_i32 killed renamable $q3, killed renamable $q2, renamable $r5, 0, $noreg, $noreg + ; CHECK-NEXT: renamable $q2 = MVE_VMAXu32 killed renamable $q3, renamable $q1, 0, $noreg, $noreg, undef renamable $q2 + ; CHECK-NEXT: renamable $q3 = MVE_VMINu32 renamable $q2, renamable $q0, 0, $noreg, $noreg, undef renamable $q3 + ; CHECK-NEXT: renamable $r12 = MVE_VMLADAVas32 killed renamable $r12, killed renamable $q3, killed renamable $q2, 0, killed $noreg, $noreg + ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.for.cond.cleanup: + ; CHECK-NEXT: liveins: $r12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg + ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $pc, implicit killed $r0 bb.0.entry: successors: %bb.1(0x40000000), %bb.3(0x40000000) liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $lr diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vpt-blocks.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vpt-blocks.mir index 84fd81098cd98..fb5e327b2cb31 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vpt-blocks.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vpt-blocks.mir @@ -211,31 +211,37 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: vpt_block ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 11, 8, implicit-def $itstate - ; CHECK: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate - ; CHECK: bb.1.vector.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2 - ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg - ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r1 - ; CHECK: bb.2.vector.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $lr, $q0, $r0, $r2, $r3 - ; CHECK: renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 0, killed $noreg, $noreg - ; CHECK: MVE_VPTv4s32r 4, renamable $q1, renamable $r2, 11, implicit-def $vpr - ; CHECK: renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 12, 1, killed renamable $vpr, $noreg - ; CHECK: renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg - ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 - ; CHECK: bb.3.for.cond.cleanup: - ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: t2IT 11, 8, implicit-def $itstate + ; CHECK-NEXT: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.vector.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.vector.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $lr, $q0, $r0, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 0, killed $noreg, $noreg + ; CHECK-NEXT: MVE_VPTv4s32r 4, renamable $q1, renamable $r2, 11, implicit-def $vpr + ; CHECK-NEXT: renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 12, 1, killed renamable $vpr, $noreg + ; CHECK-NEXT: renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg + ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.for.cond.cleanup: + ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $r7, $lr @@ -328,44 +334,46 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: different_vcpt_reaching_def ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 11, 8, implicit-def $itstate - ; CHECK: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate - ; CHECK: bb.1.vector.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2 - ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg - ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg - ; CHECK: bb.2.vector.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3 - ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg, $noreg - ; CHECK: MVE_VPST 8, implicit $vpr - ; CHECK: renamable $r1 = MVE_VSTRWU32_post renamable $q0, killed renamable $r1, 16, 1, renamable $vpr, $noreg - ; CHECK: renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, killed renamable $vpr, $noreg - ; CHECK: MVE_VPTv4s32r 2, renamable $q1, renamable $r2, 11, implicit-def $vpr - ; CHECK: renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 12, 1, killed renamable $vpr, $noreg - ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r1, 1, killed renamable $vpr, $noreg - ; CHECK: renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg - ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg - ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 - ; CHECK: bb.3.for.cond.cleanup: - ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc - ; - ; Tests that secondary VCTPs are refused when their operand's reaching definition is not the same as the main - ; VCTP's. - ; + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: t2IT 11, 8, implicit-def $itstate + ; CHECK-NEXT: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.vector.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.vector.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $lr, $q0, $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg, $noreg + ; CHECK-NEXT: MVE_VPST 8, implicit $vpr + ; CHECK-NEXT: renamable $r1 = MVE_VSTRWU32_post renamable $q0, killed renamable $r1, 16, 1, renamable $vpr, $noreg + ; CHECK-NEXT: renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, killed renamable $vpr, $noreg + ; CHECK-NEXT: MVE_VPTv4s32r 2, renamable $q1, renamable $r2, 11, implicit-def $vpr + ; CHECK-NEXT: renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 12, 1, killed renamable $vpr, $noreg + ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r1, 1, killed renamable $vpr, $noreg + ; CHECK-NEXT: renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg + ; CHECK-NEXT: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.for.cond.cleanup: + ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $r7, $lr @@ -459,42 +467,45 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: different_vcpt_operand ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 11, 8, implicit-def $itstate - ; CHECK: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate - ; CHECK: bb.1.vector.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2 - ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg - ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg - ; CHECK: bb.2.vector.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3 - ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg, $noreg - ; CHECK: MVE_VPST 8, implicit $vpr - ; CHECK: renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, killed renamable $vpr, $noreg - ; CHECK: MVE_VPTv4s32r 2, renamable $q1, renamable $r2, 11, implicit-def $vpr - ; CHECK: renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 12, 1, killed renamable $vpr, $noreg - ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr, $noreg - ; CHECK: renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg - ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg - ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 - ; CHECK: bb.3.for.cond.cleanup: - ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc - ; - ; Tests that secondary VCTPs are refused when their operand is not the same register as the main VCTP's. - ; + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: t2IT 11, 8, implicit-def $itstate + ; CHECK-NEXT: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.vector.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.vector.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $lr, $q0, $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg, $noreg + ; CHECK-NEXT: MVE_VPST 8, implicit $vpr + ; CHECK-NEXT: renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, killed renamable $vpr, $noreg + ; CHECK-NEXT: MVE_VPTv4s32r 2, renamable $q1, renamable $r2, 11, implicit-def $vpr + ; CHECK-NEXT: renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 12, 1, killed renamable $vpr, $noreg + ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr, $noreg + ; CHECK-NEXT: renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg + ; CHECK-NEXT: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.for.cond.cleanup: + ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $r7, $lr @@ -587,34 +598,37 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: else_vcpt ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 11, 8, implicit-def $itstate - ; CHECK: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate - ; CHECK: bb.1.vector.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2 - ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg - ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r1 - ; CHECK: bb.2.vector.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $lr, $q0, $r0, $r2, $r3 - ; CHECK: renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 0, killed $noreg, $noreg - ; CHECK: MVE_VPTv4s32r 12, renamable $q1, renamable $r2, 10, implicit-def $vpr - ; CHECK: renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 13, 1, killed renamable $vpr, $noreg - ; CHECK: renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 2, killed renamable $vpr, $noreg - ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 - ; CHECK: bb.3.for.cond.cleanup: - ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc - ; - ; Test including a else-predicated VCTP. - ; + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: t2IT 11, 8, implicit-def $itstate + ; CHECK-NEXT: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.vector.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.vector.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $lr, $q0, $r0, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 0, killed $noreg, $noreg + ; CHECK-NEXT: MVE_VPTv4s32r 12, renamable $q1, renamable $r2, 10, implicit-def $vpr + ; CHECK-NEXT: renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 13, 1, killed renamable $vpr, $noreg + ; CHECK-NEXT: renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 2, killed renamable $vpr, $noreg + ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.for.cond.cleanup: + ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $r7, $lr @@ -707,31 +721,37 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: loop_invariant_vpt_operands ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 11, 8, implicit-def $itstate - ; CHECK: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate - ; CHECK: bb.1.vector.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2 - ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg - ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r1 - ; CHECK: bb.2.vector.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $lr, $q0, $r0, $r2, $r3 - ; CHECK: renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 0, killed $noreg, $noreg - ; CHECK: MVE_VPTv4s32r 4, renamable $q0, renamable $r2, 11, implicit-def $vpr - ; CHECK: renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 12, 1, killed renamable $vpr, $noreg - ; CHECK: renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg - ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 - ; CHECK: bb.3.for.cond.cleanup: - ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: t2IT 11, 8, implicit-def $itstate + ; CHECK-NEXT: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.vector.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.vector.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $lr, $q0, $r0, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 0, killed $noreg, $noreg + ; CHECK-NEXT: MVE_VPTv4s32r 4, renamable $q0, renamable $r2, 11, implicit-def $vpr + ; CHECK-NEXT: renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 12, 1, killed renamable $vpr, $noreg + ; CHECK-NEXT: renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg + ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.for.cond.cleanup: + ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $r7, $lr @@ -823,29 +843,35 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: vctp_before_vpt ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: liveins: $lr, $r1, $r2, $r7 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 11, 8, implicit-def $itstate - ; CHECK: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate - ; CHECK: bb.1.vector.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r1, $r2 - ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg - ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r1 - ; CHECK: bb.2.vector.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $lr, $q0, $r2, $r3 - ; CHECK: MVE_VPTv4s32r 8, renamable $q0, renamable $r2, 8, implicit-def $vpr - ; CHECK: dead renamable $vpr = MVE_VCMPs32r renamable $q0, renamable $r3, 12, 1, killed renamable $vpr, $noreg - ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 - ; CHECK: bb.3.for.cond.cleanup: - ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r1, $r2, $r7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: t2IT 11, 8, implicit-def $itstate + ; CHECK-NEXT: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.vector.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.vector.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $lr, $q0, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: MVE_VPTv4s32r 8, renamable $q0, renamable $r2, 8, implicit-def $vpr + ; CHECK-NEXT: dead renamable $vpr = MVE_VCMPs32r renamable $q0, renamable $r3, 12, 1, killed renamable $vpr, $noreg + ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.for.cond.cleanup: + ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $r7, $lr @@ -933,39 +959,42 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: vpt_load_vctp_store ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 11, 8, implicit-def $itstate - ; CHECK: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate - ; CHECK: bb.1.vector.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2 - ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg - ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg - ; CHECK: dead renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg - ; CHECK: bb.2.vector.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $lr, $q0, $r0, $r1, $r2 - ; CHECK: MVE_VPTv4s32r 2, killed renamable $q0, renamable $r2, 2, implicit-def $vpr - ; CHECK: renamable $q0 = MVE_VLDRWU32 renamable $r0, 0, 1, $vpr, $noreg - ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r1, 1, killed $vpr, $noreg - ; CHECK: MVE_VSTRWU32 renamable $q0, renamable $r0, 0, 1, killed $vpr, $noreg - ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg - ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 - ; CHECK: bb.3.for.cond.cleanup: - ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc - ; - ; This shouldn't be tail-predicated because the VLDR isn't predicated on the VCTP. - ; + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: t2IT 11, 8, implicit-def $itstate + ; CHECK-NEXT: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.vector.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: dead renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.vector.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $lr, $q0, $r0, $r1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: MVE_VPTv4s32r 2, killed renamable $q0, renamable $r2, 2, implicit-def $vpr + ; CHECK-NEXT: renamable $q0 = MVE_VLDRWU32 renamable $r0, 0, 1, $vpr, $noreg + ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r1, 1, killed $vpr, $noreg + ; CHECK-NEXT: MVE_VSTRWU32 renamable $q0, renamable $r0, 0, 1, killed $vpr, $noreg + ; CHECK-NEXT: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.for.cond.cleanup: + ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $r7, $lr @@ -1026,37 +1055,43 @@ stack: body: | ; CHECK-LABEL: name: emptyblock ; CHECK: bb.0: - ; CHECK: successors: %bb.1(0x50000000), %bb.3(0x30000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: $sp = frame-setup tSUBspi $sp, 1, 14 /* CC::al */, $noreg - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 12 - ; CHECK: tCMPi8 renamable $r0, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: tBcc %bb.3, 11 /* CC::lt */, killed $cpsr - ; CHECK: bb.1: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2 - ; CHECK: tCMPi8 killed renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: renamable $r2 = t2CSINC $zr, $zr, 0, implicit killed $cpsr - ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: renamable $r12 = t2ANDri killed renamable $r2, 1, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r2 = t2RSBri killed renamable $r12, 0, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $vpr = VMSR_P0 killed $r2, 14 /* CC::al */, $noreg - ; CHECK: VSTR_P0_off killed renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0) - ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r0 - ; CHECK: bb.2 (align 4): - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $lr, $q0, $r1 - ; CHECK: renamable $vpr = VLDR_P0_off $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0) - ; CHECK: MVE_VPST 8, implicit $vpr - ; CHECK: renamable $r1 = MVE_VSTRWU32_post renamable $q0, killed renamable $r1, 16, 1, killed renamable $vpr, $noreg :: (store (s128), align 4) - ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 - ; CHECK: bb.3: - ; CHECK: $sp = frame-destroy tADDspi $sp, 1, 14 /* CC::al */, $noreg - ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit undef $r0 + ; CHECK-NEXT: successors: %bb.1(0x50000000), %bb.3(0x30000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: $sp = frame-setup tSUBspi $sp, 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 12 + ; CHECK-NEXT: tCMPi8 renamable $r0, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: tBcc %bb.3, 11 /* CC::lt */, killed $cpsr + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: tCMPi8 killed renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: renamable $r2 = t2CSINC $zr, $zr, 0, implicit killed $cpsr + ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: renamable $r12 = t2ANDri killed renamable $r2, 1, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r2 = t2RSBri killed renamable $r12, 0, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: $vpr = VMSR_P0 killed $r2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: VSTR_P0_off killed renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0) + ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2 (align 4): + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $lr, $q0, $r1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $vpr = VLDR_P0_off $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0) + ; CHECK-NEXT: MVE_VPST 8, implicit $vpr + ; CHECK-NEXT: renamable $r1 = MVE_VSTRWU32_post renamable $q0, killed renamable $r1, 16, 1, killed renamable $vpr, $noreg :: (store (s128), align 4) + ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3: + ; CHECK-NEXT: $sp = frame-destroy tADDspi $sp, 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit undef $r0 bb.0: successors: %bb.1(0x50000000), %bb.3(0x30000000) liveins: $r0, $r1, $r2, $r7, $lr @@ -1129,34 +1164,41 @@ constants: body: | ; CHECK-LABEL: name: predvcmp ; CHECK: bb.0: - ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: tCMPi8 renamable $r2, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 11, 8, implicit-def $itstate - ; CHECK: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate - ; CHECK: bb.1: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2 - ; CHECK: renamable $r12 = t2LEApcrel %const.0, 14 /* CC::al */, $noreg - ; CHECK: renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q1 - ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r12, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool, align 8) - ; CHECK: renamable $q2 = MVE_VMOVimmi32 4, 0, $noreg, $noreg, undef renamable $q2 - ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2 - ; CHECK: bb.2 (align 4): - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $lr, $q0, $q1, $q2, $r0, $r1 - ; CHECK: MVE_VPTv4s32r 8, renamable $q0, renamable $r1, 11, implicit-def $vpr - ; CHECK: renamable $r0 = MVE_VSTRWU32_post renamable $q1, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128), align 4) - ; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q0, renamable $q2, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 - ; CHECK: bb.3: - ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc - ; CHECK: bb.4 (align 8): - ; CHECK: CONSTPOOL_ENTRY 0, %const.0, 16 + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: tCMPi8 renamable $r2, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: t2IT 11, 8, implicit-def $itstate + ; CHECK-NEXT: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r12 = t2LEApcrel %const.0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q1 + ; CHECK-NEXT: renamable $q0 = MVE_VLDRWU32 killed renamable $r12, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool, align 8) + ; CHECK-NEXT: renamable $q2 = MVE_VMOVimmi32 4, 0, $noreg, $noreg, undef renamable $q2 + ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2 (align 4): + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $lr, $q0, $q1, $q2, $r0, $r1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: MVE_VPTv4s32r 8, renamable $q0, renamable $r1, 11, implicit-def $vpr + ; CHECK-NEXT: renamable $r0 = MVE_VSTRWU32_post renamable $q1, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128), align 4) + ; CHECK-NEXT: renamable $q0 = MVE_VADDi32 killed renamable $q0, renamable $q2, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3: + ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4 (align 8): + ; CHECK-NEXT: CONSTPOOL_ENTRY 0, %const.0, 16 bb.0: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $r7, $lr @@ -1228,41 +1270,48 @@ constants: body: | ; CHECK-LABEL: name: predvpt ; CHECK: bb.0: - ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: tCMPi8 renamable $r2, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 11, 8, implicit-def $itstate - ; CHECK: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate - ; CHECK: bb.1: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2 - ; CHECK: renamable $r12 = t2LEApcrel %const.0, 14 /* CC::al */, $noreg - ; CHECK: renamable $r3, dead $cpsr = nuw tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg - ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q1 - ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r12, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool, align 8) - ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $q2 = MVE_VMOVimmi32 4, 0, $noreg, $noreg, undef renamable $q2 - ; CHECK: bb.2 (align 4): - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $lr, $q0, $q1, $q2, $r0, $r1, $r2 - ; CHECK: MVE_VPTv4s32r 8, renamable $q0, renamable $r1, 11, implicit-def $vpr - ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed $vpr, $noreg - ; CHECK: MVE_VPST 8, implicit $vpr - ; CHECK: renamable $r0 = MVE_VSTRWU32_post renamable $q1, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128), align 4) - ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg - ; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q0, renamable $q2, 0, $noreg, $noreg, undef renamable $q0 - ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 - ; CHECK: bb.3: - ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc - ; CHECK: bb.4 (align 8): - ; CHECK: CONSTPOOL_ENTRY 0, %const.0, 16 + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: tCMPi8 renamable $r2, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: t2IT 11, 8, implicit-def $itstate + ; CHECK-NEXT: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r12 = t2LEApcrel %const.0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r3, dead $cpsr = nuw tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q1 + ; CHECK-NEXT: renamable $q0 = MVE_VLDRWU32 killed renamable $r12, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool, align 8) + ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $q2 = MVE_VMOVimmi32 4, 0, $noreg, $noreg, undef renamable $q2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2 (align 4): + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $lr, $q0, $q1, $q2, $r0, $r1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: MVE_VPTv4s32r 8, renamable $q0, renamable $r1, 11, implicit-def $vpr + ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed $vpr, $noreg + ; CHECK-NEXT: MVE_VPST 8, implicit $vpr + ; CHECK-NEXT: renamable $r0 = MVE_VSTRWU32_post renamable $q1, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128), align 4) + ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $q0 = MVE_VADDi32 killed renamable $q0, renamable $q2, 0, $noreg, $noreg, undef renamable $q0 + ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3: + ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4 (align 8): + ; CHECK-NEXT: CONSTPOOL_ENTRY 0, %const.0, 16 bb.0: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $r7, $lr diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/while.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/while.mir index d91cd958347c7..bc739dea40ef6 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/while.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/while.mir @@ -90,27 +90,33 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: copy ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.1(0x40000000), %bb.3(0x40000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: dead $lr = t2WLS $r2, %bb.3 - ; CHECK: bb.1.while.body.preheader: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $r0, $r1, $r2 - ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 2, 14 /* CC::al */, $noreg - ; CHECK: renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 2, 14 /* CC::al */, $noreg - ; CHECK: $lr = tMOVr killed $r2, 14 /* CC::al */, $noreg - ; CHECK: bb.2.while.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $lr, $r0, $r1 - ; CHECK: renamable $r2, renamable $r1 = t2LDRH_PRE killed renamable $r1, 2, 14 /* CC::al */, $noreg :: (load (s16) from %ir.scevgep4) - ; CHECK: early-clobber renamable $r0 = t2STRH_PRE killed renamable $r2, killed renamable $r0, 2, 14 /* CC::al */, $noreg :: (store (s16) into %ir.scevgep7) - ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 - ; CHECK: bb.3.while.end: - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc + ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.3(0x40000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: dead $lr = t2WLS $r2, %bb.3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.while.body.preheader: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r0, $r1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $lr = tMOVr killed $r2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.while.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r2, renamable $r1 = t2LDRH_PRE killed renamable $r1, 2, 14 /* CC::al */, $noreg :: (load (s16) from %ir.scevgep4) + ; CHECK-NEXT: early-clobber renamable $r0 = t2STRH_PRE killed renamable $r2, killed renamable $r0, 2, 14 /* CC::al */, $noreg :: (store (s16) into %ir.scevgep7) + ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.while.end: + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc bb.0.entry: successors: %bb.1(0x40000000), %bb.3(0x40000000) liveins: $r0, $r1, $r2, $r7, $lr diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-vctp-opcode-liveout.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-vctp-opcode-liveout.mir index 76b08a6418810..c643723025e99 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-vctp-opcode-liveout.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-vctp-opcode-liveout.mir @@ -114,51 +114,58 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: wrong_vctp_liveout ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 - ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 0, 4, implicit-def $itstate - ; CHECK: renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate - ; CHECK: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate - ; CHECK: bb.1.vector.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg - ; CHECK: renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q1 - ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg - ; CHECK: dead $lr = t2DLS renamable $r3 - ; CHECK: $r12 = tMOVr killed $r3, 14 /* CC::al */, $noreg - ; CHECK: $r3 = tMOVr $r2, 14 /* CC::al */, $noreg - ; CHECK: bb.2.vector.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $q1, $r0, $r1, $r2, $r3, $r12 - ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg - ; CHECK: $q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, $noreg, undef $q0 - ; CHECK: MVE_VPST 4, implicit $vpr - ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) - ; CHECK: renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2) - ; CHECK: $lr = tMOVr $r12, 14 /* CC::al */, $noreg - ; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1 - ; CHECK: renamable $r12 = nsw t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg - ; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1 - ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 - ; CHECK: bb.3.middle.block: - ; CHECK: liveins: $q0, $q1, $r2, $r3 - ; CHECK: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r2, 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $q2 = MVE_VDUP32 killed renamable $r0, 0, $noreg, $noreg, undef renamable $q2 - ; CHECK: renamable $r0, dead $cpsr = tADDi3 killed renamable $r3, 4, 14 /* CC::al */, $noreg - ; CHECK: renamable $vpr = MVE_VCMPu32r killed renamable $q2, killed renamable $r0, 8, 0, $noreg, $noreg - ; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr, $noreg - ; CHECK: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: t2IT 0, 4, implicit-def $itstate + ; CHECK-NEXT: renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate + ; CHECK-NEXT: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.vector.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q1 + ; CHECK-NEXT: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: dead $lr = t2DLS renamable $r3 + ; CHECK-NEXT: $r12 = tMOVr killed $r3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: $r3 = tMOVr $r2, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.vector.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $q1, $r0, $r1, $r2, $r3, $r12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg + ; CHECK-NEXT: $q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, $noreg, undef $q0 + ; CHECK-NEXT: MVE_VPST 4, implicit $vpr + ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) + ; CHECK-NEXT: renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2) + ; CHECK-NEXT: $lr = tMOVr $r12, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1 + ; CHECK-NEXT: renamable $r12 = nsw t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1 + ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.middle.block: + ; CHECK-NEXT: liveins: $q0, $q1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r2, 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $q2 = MVE_VDUP32 killed renamable $r0, 0, $noreg, $noreg, undef renamable $q2 + ; CHECK-NEXT: renamable $r0, dead $cpsr = tADDi3 killed renamable $r3, 4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $vpr = MVE_VCMPu32r killed renamable $q2, killed renamable $r0, 8, 0, $noreg, $noreg + ; CHECK-NEXT: renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr, $noreg + ; CHECK-NEXT: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $lr, $r7 diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-vctp-operand-liveout.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-vctp-operand-liveout.mir index ae8870034e91e..4dad166a58523 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-vctp-operand-liveout.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-vctp-operand-liveout.mir @@ -106,47 +106,54 @@ machineFunctionInfo: {} body: | ; CHECK-LABEL: name: wrong_vctp_liveout ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 - ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: t2IT 0, 4, implicit-def $itstate - ; CHECK: renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate - ; CHECK: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate - ; CHECK: bb.1.vector.ph: - ; CHECK: successors: %bb.2(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 - ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 - ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 - ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg - ; CHECK: renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q1 - ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg - ; CHECK: dead $lr = t2DLS renamable $r12 - ; CHECK: $r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg - ; CHECK: bb.2.vector.body: - ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $q1, $r0, $r1, $r2, $r3 - ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg - ; CHECK: $q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, $noreg, undef $q0 - ; CHECK: MVE_VPST 4, implicit $vpr - ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) - ; CHECK: renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2) - ; CHECK: $lr = tMOVr $r3, 14 /* CC::al */, $noreg - ; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1 - ; CHECK: renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg - ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg - ; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1 - ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 - ; CHECK: bb.3.middle.block: - ; CHECK: liveins: $q0, $q1, $r2 - ; CHECK: renamable $vpr = MVE_VCTP32 killed renamable $r2, 0, $noreg, $noreg - ; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr, $noreg - ; CHECK: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg - ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: t2IT 0, 4, implicit-def $itstate + ; CHECK-NEXT: renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate + ; CHECK-NEXT: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.vector.ph: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK-NEXT: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q1 + ; CHECK-NEXT: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: dead $lr = t2DLS renamable $r12 + ; CHECK-NEXT: $r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.vector.body: + ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) + ; CHECK-NEXT: liveins: $q1, $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg + ; CHECK-NEXT: $q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, $noreg, undef $q0 + ; CHECK-NEXT: MVE_VPST 4, implicit $vpr + ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) + ; CHECK-NEXT: renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2) + ; CHECK-NEXT: $lr = tMOVr $r3, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1 + ; CHECK-NEXT: renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1 + ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.middle.block: + ; CHECK-NEXT: liveins: $q0, $q1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 killed renamable $r2, 0, $noreg, $noreg + ; CHECK-NEXT: renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr, $noreg + ; CHECK-NEXT: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg + ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $lr, $r7