diff --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td b/llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td index 50f10114989d0..a02130f8390a7 100644 --- a/llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td +++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td @@ -72,6 +72,10 @@ def : WriteRes { let Latency = 4; } // Define customized scheduler read/write types specific to the Neoverse N2. //===----------------------------------------------------------------------===// + +// Define generic 0 micro-op types +def N2Write_0c : SchedWriteRes<[]> { let Latency = 0; } + // Define generic 1 micro-op types def N2Write_1c_1B : SchedWriteRes<[N2UnitB]> { let Latency = 1; } @@ -645,6 +649,21 @@ def N2Write_11c_9L01_9S_9V : SchedWriteRes<[N2UnitL01, N2UnitL01, N2UnitL01, let NumMicroOps = 27; } +//===----------------------------------------------------------------------===// +// Define predicate-controlled types + +def N2Write_0or1c_1I : SchedWriteVariant<[ + SchedVar, + SchedVar]>; + +def N2Write_0or2c_1V : SchedWriteVariant<[ + SchedVar, + SchedVar]>; + +def N2Write_0or3c_1M0 : SchedWriteVariant<[ + SchedVar, + SchedVar]>; + //===----------------------------------------------------------------------===// // Define types for arithmetic and logical ops with short shifts def N2Write_Arith : SchedWriteVariant<[ @@ -680,6 +699,7 @@ def : InstRW<[N2Write_1c_1B_1S], (instrs BL, BLR)>; // ALU, basic // ALU, basic, flagset def : SchedAlias; +def : InstRW<[N2Write_0or1c_1I], (instregex "^MOVZ[WX]i$")>; // ALU, extend and shift def : SchedAlias; @@ -691,7 +711,8 @@ def : SchedAlias; // Logical, shift, no flagset def : InstRW<[N2Write_1c_1I], - (instregex "^(AND|BIC|EON|EOR|ORN|ORR)[WX]rs$")>; + (instregex "^(AND|BIC|EON|EOR|ORN)[WX]rs$")>; +def : InstRW<[N2Write_0or1c_1I], (instregex "^ORR[WX]rs$")>; // Logical, shift, flagset def : InstRW<[N2Write_Logical], (instregex "^(AND|BIC)S[WX]rs$")>; @@ -882,8 +903,7 @@ def : SchedAlias; def : InstRW<[N2Write_2c_1V], (instrs FMOVHr, FMOVSr, FMOVDr)>; // FP transfer, from gen to low half of vec reg -def : InstRW<[N2Write_3c_1M0], (instrs FMOVWHr, FMOVXHr, FMOVWSr, FMOVXDr, - FMOVHWr, FMOVHXr, FMOVSWr, FMOVDXr)>; +def : InstRW<[N2Write_0or3c_1M0], (instrs FMOVWHr, FMOVXHr, FMOVWSr, FMOVXDr)>; // FP transfer, from gen to high half of vec reg def : InstRW<[N2Write_5c_1M0_1V], (instrs FMOVXDHighr)>; @@ -1225,6 +1245,8 @@ def : InstRW<[N2Write_3c_1V0], (instrs BFCVT)>; // ASIMD unzip/zip // Handled by SchedAlias +def : InstRW<[N2Write_0or2c_1V], (instrs MOVID, MOVIv2d_ns)>; + // ASIMD duplicate, gen reg def : InstRW<[N2Write_3c_1M0], (instregex "^DUPv.+gpr")>; diff --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseN3.td b/llvm/lib/Target/AArch64/AArch64SchedNeoverseN3.td index c73f60a1a7741..0b65a5f6b1e25 100644 --- a/llvm/lib/Target/AArch64/AArch64SchedNeoverseN3.td +++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseN3.td @@ -75,7 +75,7 @@ def : WriteRes { let Latency = 1; } def N3Write_0c : SchedWriteRes<[]> { let Latency = 0; - let NumMicroOps = 0; + let NumMicroOps = 1; } def N3Write_4c : SchedWriteRes<[]> { @@ -553,6 +553,25 @@ def N3Write_16c_16V0 : SchedWriteRes<[N3UnitV0, N3UnitV0, N3UnitV0, N3UnitV0, let NumMicroOps = 16; } + +//===----------------------------------------------------------------------===// +// Define predicate-controlled types + +def N3Write_0or1c_1I : SchedWriteVariant<[ + SchedVar, + SchedVar]>; + +def N3Write_0or2c_1V : SchedWriteVariant<[ + SchedVar, + SchedVar]>; + +def N3Write_0or2c_1M : SchedWriteVariant<[ + SchedVar, + SchedVar]>; + +def N3Write_0or3c_1M0 : SchedWriteVariant<[ + SchedVar, + SchedVar]>; //===----------------------------------------------------------------------===// // Define forwarded types // NOTE: SOG, p. 19, n. 2: Accumulator forwarding is not supported for @@ -682,6 +701,7 @@ def : InstRW<[N3Write_1c_1B_1S], (instrs BL, BLR)>; // Conditional compare // Conditional select def : SchedAlias; +def : InstRW<[N3Write_0or1c_1I], (instregex "^MOVZ[WX]i$")>; // ALU, extend and shift def : SchedAlias; @@ -711,7 +731,8 @@ def : InstRW<[N3Write_1c_1I], (instrs GMI, SUBP, SUBPS)>; // Logical, shift, no flagset def : InstRW<[N3Write_1c_1I], - (instregex "^(AND|BIC|EON|EOR|ORN|ORR)[WX]rs$")>; + (instregex "^(AND|BIC|EON|EOR|ORN)[WX]rs$")>; +def : InstRW<[N3Write_0or1c_1I], (instregex "^ORR[WX]rs$")>; // Logical, shift, flagset def : InstRW<[N3Write_2c_1M], (instregex "^(AND|BIC)S[WX]rs$")>; @@ -957,10 +978,11 @@ def : SchedAlias; def : SchedAlias; // FP move, register -def : InstRW<[N3Write_2c_1V], (instrs FMOVHr, FMOVSr, FMOVDr)>; +def : InstRW<[N3Write_2c_1V], (instrs FMOVHr)>; +def : InstRW<[N3Write_0c], (instrs FMOVSr, FMOVDr)>; // FP transfer, from gen to low half of vec reg -def : InstRW<[N3Write_3c_1M0], (instrs FMOVWHr, FMOVXHr, FMOVWSr, FMOVXDr)>; +def : InstRW<[N3Write_0or3c_1M0], (instrs FMOVWHr, FMOVXHr, FMOVWSr, FMOVXDr)>; // FP transfer, from gen to high half of vec reg def : InstRW<[N3Write_5c_1M0_1V], (instrs FMOVXDHighr)>; @@ -1064,6 +1086,8 @@ def : InstRW<[WriteAdr, N3Write_2c_1L01_1V_1I], (instregex "^STP[SDQ](post|pre)$ // ASIMD compare // ASIMD logical // ASIMD max/min, basic and pair-wise +def : InstRW<[N3Write_0or2c_1V], (instrs ORRv16i8, ORRv8i8)>; + def : SchedAlias; def : SchedAlias; @@ -1290,6 +1314,7 @@ def : InstRW<[N3Write_3c_1V0], (instrs BFCVT)>; // ASIMD transpose // ASIMD unzip/zip // Covered by WriteV[dq] +def : InstRW<[N3Write_0or2c_1V], (instrs MOVID, MOVIv2d_ns)>; // ASIMD duplicate, gen reg def : InstRW<[N3Write_3c_1M0], (instregex "^DUPv.+gpr")>; @@ -1668,10 +1693,11 @@ def : InstRW<[N3Write_2c_1M], (instregex "^REV_PP_[BHSD]")>; def : InstRW<[N3Write_1c_1M], (instrs SEL_PPPP)>; // Predicate set -def : InstRW<[N3Write_2c_1M], (instregex "^PFALSE", "^PTRUE_[BHSD]")>; +def : InstRW<[N3Write_0c], (instrs PFALSE)>; +def : InstRW<[N3Write_0or2c_1M], (instregex "^PTRUE_[BHSD]")>; // Predicate set/initialize, set flags -def : InstRW<[N3Write_2c_1M], (instregex "^PTRUES_[BHSD]")>; +def : InstRW<[N3Write_0or2c_1M], (instregex "^PTRUES_[BHSD]")>; // Predicate find first/next def : InstRW<[N3Write_2c_1M], (instregex "^PFIRST_B$", "^PNEXT_[BHSD]$")>; @@ -1897,10 +1923,11 @@ def : InstRW<[N3Write_5c_1M0_1V], (instregex "^INDEX_(IR|RI|RR)_D$")>; // Logical def : InstRW<[N3Write_2c_1V], (instregex "^(AND|EOR|ORR)_ZI", - "^(AND|BIC|EOR|ORR)_ZZZ", + "^(AND|BIC|EOR)_ZZZ", "^EOR(BT|TB)_ZZZ_[BHSD]", "^(AND|BIC|EOR|NOT|ORR)_(ZPmZ|ZPZZ)_[BHSD]", "^NOT_ZPmZ_[BHSD]")>; +def : InstRW<[N3Write_0or2c_1V], (instrs ORR_ZZZ)>; // Max/min, basic and pairwise def : InstRW<[N3Write_2c_1V], (instregex "^[SU](MAX|MIN)_ZI_[BHSD]", diff --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td index 3cbfc59423c9a..bf65b31f88037 100644 --- a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td +++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td @@ -94,6 +94,7 @@ def : WriteRes { let Latency = 1; } let Latency = 0, NumMicroOps = 0 in def V1Write_0c_0Z : SchedWriteRes<[]>; +def V1Write_0c : SchedWriteRes<[]> { let Latency = 0; } //===----------------------------------------------------------------------===// // Define generic 1 micro-op types @@ -472,6 +473,17 @@ def V1Write_11c_9L01_9S_9V : SchedWriteRes<[V1UnitL01, V1UnitL01, V1UnitL01, V1UnitV, V1UnitV, V1UnitV, V1UnitV, V1UnitV, V1UnitV]>; +//===----------------------------------------------------------------------===// +// Define predicate-controlled types + +def V1Write_0or1c_1I : SchedWriteVariant<[ + SchedVar, + SchedVar]>; + +def V1Write_0or3c_1M0 : SchedWriteVariant<[ + SchedVar, + SchedVar]>; + //===----------------------------------------------------------------------===// // Define forwarded types @@ -603,6 +615,7 @@ def : InstRW<[V1Write_1c_1I_1Flg], "^(ADC|SBC)S[WX]r$", "^ANDS[WX]ri$", "^(AND|BIC)S[WX]rr$")>; +def : InstRW<[V1Write_0or1c_1I], (instregex "^MOVZ[WX]i$")>; // ALU, extend and shift def : SchedAlias; @@ -623,7 +636,8 @@ def : InstRW<[V1WriteISRegS], (instregex "^(ADD|SUB)S(([WX]r[sx])|Xrx64)$")>; // Logical, shift, no flagset -def : InstRW<[V1Write_1c_1I], (instregex "^(AND|BIC|EON|EOR|ORN|ORR)[WX]rs$")>; +def : InstRW<[V1Write_1c_1I], (instregex "^(AND|BIC|EON|EOR|ORN)[WX]rs$")>; +def : InstRW<[V1Write_0or1c_1I], (instregex "^ORR[WX]rs$")>; // Logical, shift, flagset def : InstRW<[V1Write_2c_1M_1Flg], (instregex "^(AND|BIC)S[WX]rs$")>; diff --git a/llvm/lib/Target/AArch64/AArch64SchedPredNeoverse.td b/llvm/lib/Target/AArch64/AArch64SchedPredNeoverse.td index 33b76a4f65f05..f841e6072d2b4 100644 --- a/llvm/lib/Target/AArch64/AArch64SchedPredNeoverse.td +++ b/llvm/lib/Target/AArch64/AArch64SchedPredNeoverse.td @@ -80,5 +80,23 @@ def NeoverseZeroMove : MCSchedPredicate< // MOVI Dd, #0 // MOVI Vd.2D, #0 CheckAll<[CheckOpcode<[MOVID, MOVIv2d_ns]>, - CheckImmOperand<1, 0>]> + CheckImmOperand<1, 0>]>, + // MOV Zd, Zn + CheckAll<[CheckOpcode<[ORR_ZZZ]>, + CheckSameRegOperand<1, 2>]>, + // MOV Vd, Vn + CheckAll<[CheckOpcode<[ORRv16i8, ORRv8i8]>, + CheckSameRegOperand<1, 2>]>, ]>>; + +def NeoverseAllActivePredicate : MCSchedPredicate< + CheckAny<[ + // PTRUE Pd, ALL + // PTRUES Pd, ALL + CheckAll<[ + CheckOpcode<[ + PTRUE_B, PTRUE_H, PTRUE_S, PTRUE_D, + PTRUES_B, PTRUES_H, PTRUES_S, PTRUES_D]>, + CheckIsImmOperand<1>, + CheckImmOperand<1, 31>]>, + ]>>; diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-basic-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-basic-instructions.s index cf1cf0e98c801..f6ea4c4769c0a 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-basic-instructions.s +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-basic-instructions.s @@ -2086,9 +2086,9 @@ drps # CHECK-NEXT: 1 3 0.50 fcvtas x27, d28 # CHECK-NEXT: 1 3 0.50 fcvtau w29, d30 # CHECK-NEXT: 1 3 0.50 fcvtau xzr, d0 -# CHECK-NEXT: 1 3 3.00 fmov w3, s9 +# CHECK-NEXT: 1 2 0.50 fmov w3, s9 # CHECK-NEXT: 1 3 3.00 fmov s9, w3 -# CHECK-NEXT: 1 3 3.00 fmov x20, d31 +# CHECK-NEXT: 1 2 0.50 fmov x20, d31 # CHECK-NEXT: 1 3 3.00 fmov d1, x15 # CHECK-NEXT: 1 2 0.50 fmov x3, v12.d[1] # CHECK-NEXT: 2 5 1.00 fmov v1.d[1], x19 @@ -2508,14 +2508,14 @@ drps # CHECK-NEXT: 1 2 0.50 bics x3, xzr, x3, lsl #1 # CHECK-NEXT: 1 2 0.50 tst w3, w7, lsl #31 # CHECK-NEXT: 1 2 0.50 tst x2, x20, asr #2 -# CHECK-NEXT: 1 1 0.25 mov x3, x6 -# CHECK-NEXT: 1 1 0.25 mov x3, xzr -# CHECK-NEXT: 1 1 0.25 mov wzr, w2 -# CHECK-NEXT: 1 1 0.25 mov w3, w5 +# CHECK-NEXT: 1 0 0.20 mov x3, x6 +# CHECK-NEXT: 1 0 0.20 mov x3, xzr +# CHECK-NEXT: 1 0 0.20 mov wzr, w2 +# CHECK-NEXT: 1 0 0.20 mov w3, w5 # CHECK-NEXT: 1 1 0.25 movz w2, #0, lsl #16 # CHECK-NEXT: 1 1 0.25 mov w2, #-1235 # CHECK-NEXT: 1 1 0.25 mov x2, #5299989643264 -# CHECK-NEXT: 1 1 0.25 mov x2, #0 +# CHECK-NEXT: 1 0 0.20 mov x2, #0 # CHECK-NEXT: 1 1 0.25 movk w3, #0 # CHECK-NEXT: 1 1 0.25 movz x4, #0, lsl #16 # CHECK-NEXT: 1 1 0.25 movk w5, #0, lsl #16 @@ -2557,7 +2557,7 @@ drps # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2] [3.0] [3.1] [4] [5] [6.0] [6.1] [7] [8] -# CHECK-NEXT: 11.00 11.00 33.00 33.00 87.33 151.33 151.33 517.00 251.00 162.50 162.50 215.50 85.50 +# CHECK-NEXT: 11.00 11.00 33.00 33.00 87.33 151.33 151.33 509.75 249.75 161.25 161.25 216.50 86.50 # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2] [3.0] [3.1] [4] [5] [6.0] [6.1] [7] [8] Instructions: @@ -3270,9 +3270,9 @@ drps # CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 fcvtas x27, d28 # CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 fcvtau w29, d30 # CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 fcvtau xzr, d0 -# CHECK-NEXT: - - - - - - - 3.00 - - - - - fmov w3, s9 +# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 fmov w3, s9 # CHECK-NEXT: - - - - - - - 3.00 - - - - - fmov s9, w3 -# CHECK-NEXT: - - - - - - - 3.00 - - - - - fmov x20, d31 +# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 fmov x20, d31 # CHECK-NEXT: - - - - - - - 3.00 - - - - - fmov d1, x15 # CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 fmov x3, v12.d[1] # CHECK-NEXT: - - - - - - - 1.00 - - - 0.50 0.50 fmov v1.d[1], x19 @@ -3692,14 +3692,14 @@ drps # CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - bics x3, xzr, x3, lsl #1 # CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - tst w3, w7, lsl #31 # CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - tst x2, x20, asr #2 -# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - mov x3, x6 -# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - mov x3, xzr -# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - mov wzr, w2 -# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - mov w3, w5 +# CHECK-NEXT: - - - - - - - - - - - - - mov x3, x6 +# CHECK-NEXT: - - - - - - - - - - - - - mov x3, xzr +# CHECK-NEXT: - - - - - - - - - - - - - mov wzr, w2 +# CHECK-NEXT: - - - - - - - - - - - - - mov w3, w5 # CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - movz w2, #0, lsl #16 # CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - mov w2, #-1235 # CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - mov x2, #5299989643264 -# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - mov x2, #0 +# CHECK-NEXT: - - - - - - - - - - - - - mov x2, #0 # CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - movk w3, #0 # CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - movz x4, #0, lsl #16 # CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - movk w5, #0, lsl #16 diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-basic-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-basic-instructions.s index b9758280e2491..5f48217f8fab9 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-basic-instructions.s +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-basic-instructions.s @@ -1888,7 +1888,7 @@ drps # CHECK-NEXT: 1 2 0.50 fccmpe d31, d5, #7, ne # CHECK-NEXT: 1 2 0.50 fcsel s3, s20, s9, pl # CHECK-NEXT: 1 2 0.50 fcsel d9, d10, d11, mi -# CHECK-NEXT: 1 2 0.50 fmov s0, s1 +# CHECK-NEXT: 1 0 0.20 fmov s0, s1 # CHECK-NEXT: 1 2 0.50 fabs s2, s3 # CHECK-NEXT: 1 2 0.50 fneg s4, s5 # CHECK-NEXT: 1 7 1.00 fsqrt s6, s7 @@ -1901,7 +1901,7 @@ drps # CHECK-NEXT: 1 3 1.00 frinta s20, s21 # CHECK-NEXT: 1 3 1.00 frintx s22, s23 # CHECK-NEXT: 1 3 1.00 frinti s24, s25 -# CHECK-NEXT: 1 2 0.50 fmov d0, d1 +# CHECK-NEXT: 1 0 0.20 fmov d0, d1 # CHECK-NEXT: 1 2 0.50 fabs d2, d3 # CHECK-NEXT: 1 2 0.50 fneg d4, d5 # CHECK-NEXT: 1 12 1.00 fsqrt d6, d7 @@ -2508,14 +2508,14 @@ drps # CHECK-NEXT: 1 2 0.50 bics x3, xzr, x3, lsl #1 # CHECK-NEXT: 1 2 0.50 tst w3, w7, lsl #31 # CHECK-NEXT: 1 2 0.50 tst x2, x20, asr #2 -# CHECK-NEXT: 1 1 0.25 mov x3, x6 -# CHECK-NEXT: 1 1 0.25 mov x3, xzr -# CHECK-NEXT: 1 1 0.25 mov wzr, w2 -# CHECK-NEXT: 1 1 0.25 mov w3, w5 +# CHECK-NEXT: 1 0 0.20 mov x3, x6 +# CHECK-NEXT: 1 0 0.20 mov x3, xzr +# CHECK-NEXT: 1 0 0.20 mov wzr, w2 +# CHECK-NEXT: 1 0 0.20 mov w3, w5 # CHECK-NEXT: 1 1 0.25 movz w2, #0, lsl #16 # CHECK-NEXT: 1 1 0.25 mov w2, #-1235 # CHECK-NEXT: 1 1 0.25 mov x2, #5299989643264 -# CHECK-NEXT: 1 1 0.25 mov x2, #0 +# CHECK-NEXT: 1 0 0.20 mov x2, #0 # CHECK-NEXT: 1 1 0.25 movk w3, #0 # CHECK-NEXT: 1 1 0.25 movz x4, #0, lsl #16 # CHECK-NEXT: 1 1 0.25 movk w5, #0, lsl #16 @@ -2557,7 +2557,7 @@ drps # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2] [3.0] [3.1] [4] [5] [6.0] [6.1] [7] [8] -# CHECK-NEXT: 11.00 11.00 33.00 33.00 99.33 163.33 163.33 357.75 212.75 156.25 156.25 184.50 64.50 +# CHECK-NEXT: 11.00 11.00 33.00 33.00 99.33 163.33 163.33 356.50 211.50 155.00 155.00 183.50 63.50 # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2] [3.0] [3.1] [4] [5] [6.0] [6.1] [7] [8] Instructions: @@ -3072,7 +3072,7 @@ drps # CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 fccmpe d31, d5, #7, ne # CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 fcsel s3, s20, s9, pl # CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 fcsel d9, d10, d11, mi -# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 fmov s0, s1 +# CHECK-NEXT: - - - - - - - - - - - - - fmov s0, s1 # CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 fabs s2, s3 # CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 fneg s4, s5 # CHECK-NEXT: - - - - - - - - - - - 1.00 - fsqrt s6, s7 @@ -3085,7 +3085,7 @@ drps # CHECK-NEXT: - - - - - - - - - - - 1.00 - frinta s20, s21 # CHECK-NEXT: - - - - - - - - - - - 1.00 - frintx s22, s23 # CHECK-NEXT: - - - - - - - - - - - 1.00 - frinti s24, s25 -# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 fmov d0, d1 +# CHECK-NEXT: - - - - - - - - - - - - - fmov d0, d1 # CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 fabs d2, d3 # CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 fneg d4, d5 # CHECK-NEXT: - - - - - - - - - - - 1.00 - fsqrt d6, d7 @@ -3692,14 +3692,14 @@ drps # CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - bics x3, xzr, x3, lsl #1 # CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - tst w3, w7, lsl #31 # CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - tst x2, x20, asr #2 -# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - mov x3, x6 -# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - mov x3, xzr -# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - mov wzr, w2 -# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - mov w3, w5 +# CHECK-NEXT: - - - - - - - - - - - - - mov x3, x6 +# CHECK-NEXT: - - - - - - - - - - - - - mov x3, xzr +# CHECK-NEXT: - - - - - - - - - - - - - mov wzr, w2 +# CHECK-NEXT: - - - - - - - - - - - - - mov w3, w5 # CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - movz w2, #0, lsl #16 # CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - mov w2, #-1235 # CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - mov x2, #5299989643264 -# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - mov x2, #0 +# CHECK-NEXT: - - - - - - - - - - - - - mov x2, #0 # CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - movk w3, #0 # CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - movz x4, #0, lsl #16 # CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - movk w5, #0, lsl #16 diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-neon-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-neon-instructions.s index dddaca34f68dd..9ef4dd9877a14 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-neon-instructions.s +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-neon-instructions.s @@ -1445,8 +1445,8 @@ zip2 v0.8h, v0.8h, v0.8h # CHECK-NEXT: 2 5 1.00 mov v0.h[1], w8 # CHECK-NEXT: 2 5 1.00 mov v0.s[2], w8 # CHECK-NEXT: 2 5 1.00 mov v0.d[1], x8 -# CHECK-NEXT: 1 2 0.50 mov v0.16b, v0.16b -# CHECK-NEXT: 1 2 0.50 mov v0.8b, v0.8b +# CHECK-NEXT: 1 0 0.20 mov v0.16b, v0.16b +# CHECK-NEXT: 1 0 0.20 mov v0.8b, v0.8b # CHECK-NEXT: 1 2 0.50 movi d15, #0xff00ff00ff00ff # CHECK-NEXT: 1 2 0.50 movi v0.16b, #31 # CHECK-NEXT: 1 2 0.50 movi v0.2d, #0xff0000ff0000ffff @@ -1467,7 +1467,7 @@ zip2 v0.8h, v0.8h, v0.8h # CHECK-NEXT: 1 2 0.50 mvn v0.16b, v0.16b # CHECK-NEXT: 1 2 0.50 mvn v0.8b, v0.8b # CHECK-NEXT: 1 2 0.50 orn v0.16b, v0.16b, v0.16b -# CHECK-NEXT: 1 2 0.50 mov v0.16b, v0.16b +# CHECK-NEXT: 1 0 0.20 mov v0.16b, v0.16b # CHECK-NEXT: 1 2 0.50 orr v0.8h, #31 # CHECK-NEXT: 1 2 1.00 pmul v0.16b, v0.16b, v0.16b # CHECK-NEXT: 1 2 1.00 pmul v0.8b, v0.8b, v0.8b @@ -2163,7 +2163,7 @@ zip2 v0.8h, v0.8h, v0.8h # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2] [3.0] [3.1] [4] [5] [6.0] [6.1] [7] [8] -# CHECK-NEXT: - - - - 33.00 51.50 51.50 18.75 7.75 7.75 7.75 649.00 584.00 +# CHECK-NEXT: - - - - 33.00 51.50 51.50 18.75 7.75 7.75 7.75 647.50 582.50 # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2] [3.0] [3.1] [4] [5] [6.0] [6.1] [7] [8] Instructions: @@ -2534,8 +2534,8 @@ zip2 v0.8h, v0.8h, v0.8h # CHECK-NEXT: - - - - - - - 1.00 - - - 0.50 0.50 mov v0.h[1], w8 # CHECK-NEXT: - - - - - - - 1.00 - - - 0.50 0.50 mov v0.s[2], w8 # CHECK-NEXT: - - - - - - - 1.00 - - - 0.50 0.50 mov v0.d[1], x8 -# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 mov v0.16b, v0.16b -# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 mov v0.8b, v0.8b +# CHECK-NEXT: - - - - - - - - - - - - - mov v0.16b, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - mov v0.8b, v0.8b # CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 movi d15, #0xff00ff00ff00ff # CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 movi v0.16b, #31 # CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 movi v0.2d, #0xff0000ff0000ffff @@ -2556,7 +2556,7 @@ zip2 v0.8h, v0.8h, v0.8h # CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 mvn v0.16b, v0.16b # CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 mvn v0.8b, v0.8b # CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 orn v0.16b, v0.16b, v0.16b -# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 mov v0.16b, v0.16b +# CHECK-NEXT: - - - - - - - - - - - - - mov v0.16b, v0.16b # CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 orr v0.8h, #31 # CHECK-NEXT: - - - - - - - - - - - 1.00 - pmul v0.16b, v0.16b, v0.16b # CHECK-NEXT: - - - - - - - - - - - 1.00 - pmul v0.8b, v0.8b, v0.8b diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-sve-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-sve-instructions.s index e7160e02c7c7f..0093b28a756ee 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-sve-instructions.s +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-sve-instructions.s @@ -4979,7 +4979,7 @@ zip2 z31.s, z31.s, z31.s # CHECK-NEXT: 1 2 0.50 mov z0.d, p0/m, d0 # CHECK-NEXT: 2 5 1.00 mov z0.d, p0/m, x0 # CHECK-NEXT: 1 3 1.00 mov z0.d, x0 -# CHECK-NEXT: 1 2 0.50 mov z0.d, z0.d +# CHECK-NEXT: 1 0 0.20 mov z0.d, z0.d # CHECK-NEXT: 1 2 0.50 mov z0.h, #-256 # CHECK-NEXT: 1 2 0.50 mov z0.h, #-32768 # CHECK-NEXT: 1 2 0.50 mov z0.h, #0 @@ -5039,7 +5039,7 @@ zip2 z31.s, z31.s, z31.s # CHECK-NEXT: 1 2 0.50 movprfx z31.d, p7/z, z6.d # CHECK-NEXT: 2 5 1.00 mov z31.d, p7/m, sp # CHECK-NEXT: 1 3 1.00 mov z31.d, sp -# CHECK-NEXT: 1 2 0.50 mov z31.d, z0.d +# CHECK-NEXT: 1 0 0.20 mov z31.d, z0.d # CHECK-NEXT: 1 2 0.50 mov z31.d, z31.d[7] # CHECK-NEXT: 1 2 0.50 mov z31.h, p15/m, z31.h # CHECK-NEXT: 1 2 0.50 mov z31.h, p7/m, h31 @@ -5150,7 +5150,7 @@ zip2 z31.s, z31.s, z31.s # CHECK-NEXT: 2 5 1.00 orv d0, p7, z31.d # CHECK-NEXT: 2 5 1.00 orv h0, p7, z31.h # CHECK-NEXT: 2 5 1.00 orv s0, p7, z31.s -# CHECK-NEXT: 1 2 0.50 pfalse p15.b +# CHECK-NEXT: 1 0 0.20 pfalse p15.b # CHECK-NEXT: 1 2 0.50 pfirst p0.b, p15, p0.b # CHECK-NEXT: 1 2 0.50 pfirst p15.b, p15, p15.b # CHECK-NEXT: 1 2 1.00 pmul z0.b, z1.b, z2.b @@ -5280,11 +5280,11 @@ zip2 z31.s, z31.s, z31.s # CHECK-NEXT: 1 2 0.50 ptrue p0.d, pow2 # CHECK-NEXT: 1 2 0.50 ptrue p0.h, pow2 # CHECK-NEXT: 1 2 0.50 ptrue p0.s, pow2 -# CHECK-NEXT: 1 2 0.50 ptrue p15.b -# CHECK-NEXT: 1 2 0.50 ptrue p15.d -# CHECK-NEXT: 1 2 0.50 ptrue p15.h -# CHECK-NEXT: 1 2 0.50 ptrue p15.s -# CHECK-NEXT: 1 2 0.50 ptrue p7.s +# CHECK-NEXT: 1 0 0.20 ptrue p15.b +# CHECK-NEXT: 1 0 0.20 ptrue p15.d +# CHECK-NEXT: 1 0 0.20 ptrue p15.h +# CHECK-NEXT: 1 0 0.20 ptrue p15.s +# CHECK-NEXT: 1 0 0.20 ptrue p7.s # CHECK-NEXT: 1 2 0.50 ptrue p7.s, #14 # CHECK-NEXT: 1 2 0.50 ptrue p7.s, #15 # CHECK-NEXT: 1 2 0.50 ptrue p7.s, #16 @@ -5319,11 +5319,11 @@ zip2 z31.s, z31.s, z31.s # CHECK-NEXT: 1 2 0.50 ptrues p0.d, pow2 # CHECK-NEXT: 1 2 0.50 ptrues p0.h, pow2 # CHECK-NEXT: 1 2 0.50 ptrues p0.s, pow2 -# CHECK-NEXT: 1 2 0.50 ptrues p15.b -# CHECK-NEXT: 1 2 0.50 ptrues p15.d -# CHECK-NEXT: 1 2 0.50 ptrues p15.h -# CHECK-NEXT: 1 2 0.50 ptrues p15.s -# CHECK-NEXT: 1 2 0.50 ptrues p7.s +# CHECK-NEXT: 1 0 0.20 ptrues p15.b +# CHECK-NEXT: 1 0 0.20 ptrues p15.d +# CHECK-NEXT: 1 0 0.20 ptrues p15.h +# CHECK-NEXT: 1 0 0.20 ptrues p15.s +# CHECK-NEXT: 1 0 0.20 ptrues p7.s # CHECK-NEXT: 1 2 0.50 ptrues p7.s, #14 # CHECK-NEXT: 1 2 0.50 ptrues p7.s, #15 # CHECK-NEXT: 1 2 0.50 ptrues p7.s, #16 @@ -5471,7 +5471,7 @@ zip2 z31.s, z31.s, z31.s # CHECK-NEXT: 1 2 0.50 sel z23.d, p11, z13.d, z8.d # CHECK-NEXT: 1 2 0.50 sel z23.h, p11, z13.h, z8.h # CHECK-NEXT: 1 2 0.50 sel z23.s, p11, z13.s, z8.s -# CHECK-NEXT: 0 0 0.00 * U setffr +# CHECK-NEXT: 1 0 0.20 * U setffr # CHECK-NEXT: 1 2 0.50 shadd z0.b, p0/m, z0.b, z1.b # CHECK-NEXT: 1 2 0.50 shadd z0.h, p0/m, z0.h, z1.h # CHECK-NEXT: 1 2 0.50 shadd z29.s, p7/m, z29.s, z30.s @@ -6847,7 +6847,7 @@ zip2 z31.s, z31.s, z31.s # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2] [3.0] [3.1] [4] [5] [6.0] [6.1] [7] [8] -# CHECK-NEXT: - - - - 332.67 481.67 481.67 298.00 230.00 88.50 88.50 1558.00 1401.00 +# CHECK-NEXT: - - - - 332.67 481.67 481.67 292.50 224.50 88.50 88.50 1557.00 1400.00 # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2] [3.0] [3.1] [4] [5] [6.0] [6.1] [7] [8] Instructions: @@ -8410,7 +8410,7 @@ zip2 z31.s, z31.s, z31.s # CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 mov z0.d, p0/m, d0 # CHECK-NEXT: - - - - - - - 1.00 - - - 0.50 0.50 mov z0.d, p0/m, x0 # CHECK-NEXT: - - - - - - - 1.00 - - - - - mov z0.d, x0 -# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 mov z0.d, z0.d +# CHECK-NEXT: - - - - - - - - - - - - - mov z0.d, z0.d # CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 mov z0.h, #-256 # CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 mov z0.h, #-32768 # CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 mov z0.h, #0 @@ -8470,7 +8470,7 @@ zip2 z31.s, z31.s, z31.s # CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 movprfx z31.d, p7/z, z6.d # CHECK-NEXT: - - - - - - - 1.00 - - - 0.50 0.50 mov z31.d, p7/m, sp # CHECK-NEXT: - - - - - - - 1.00 - - - - - mov z31.d, sp -# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 mov z31.d, z0.d +# CHECK-NEXT: - - - - - - - - - - - - - mov z31.d, z0.d # CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 mov z31.d, z31.d[7] # CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 mov z31.h, p15/m, z31.h # CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 mov z31.h, p7/m, h31 @@ -8581,7 +8581,7 @@ zip2 z31.s, z31.s, z31.s # CHECK-NEXT: - - - - - - - - - - - 0.50 1.50 orv d0, p7, z31.d # CHECK-NEXT: - - - - - - - - - - - 0.50 1.50 orv h0, p7, z31.h # CHECK-NEXT: - - - - - - - - - - - 0.50 1.50 orv s0, p7, z31.s -# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - pfalse p15.b +# CHECK-NEXT: - - - - - - - - - - - - - pfalse p15.b # CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - pfirst p0.b, p15, p0.b # CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - pfirst p15.b, p15, p15.b # CHECK-NEXT: - - - - - - - - - - - 1.00 - pmul z0.b, z1.b, z2.b @@ -8711,11 +8711,11 @@ zip2 z31.s, z31.s, z31.s # CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - ptrue p0.d, pow2 # CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - ptrue p0.h, pow2 # CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - ptrue p0.s, pow2 -# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - ptrue p15.b -# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - ptrue p15.d -# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - ptrue p15.h -# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - ptrue p15.s -# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - ptrue p7.s +# CHECK-NEXT: - - - - - - - - - - - - - ptrue p15.b +# CHECK-NEXT: - - - - - - - - - - - - - ptrue p15.d +# CHECK-NEXT: - - - - - - - - - - - - - ptrue p15.h +# CHECK-NEXT: - - - - - - - - - - - - - ptrue p15.s +# CHECK-NEXT: - - - - - - - - - - - - - ptrue p7.s # CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - ptrue p7.s, #14 # CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - ptrue p7.s, #15 # CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - ptrue p7.s, #16 @@ -8750,11 +8750,11 @@ zip2 z31.s, z31.s, z31.s # CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - ptrues p0.d, pow2 # CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - ptrues p0.h, pow2 # CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - ptrues p0.s, pow2 -# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - ptrues p15.b -# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - ptrues p15.d -# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - ptrues p15.h -# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - ptrues p15.s -# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - ptrues p7.s +# CHECK-NEXT: - - - - - - - - - - - - - ptrues p15.b +# CHECK-NEXT: - - - - - - - - - - - - - ptrues p15.d +# CHECK-NEXT: - - - - - - - - - - - - - ptrues p15.h +# CHECK-NEXT: - - - - - - - - - - - - - ptrues p15.s +# CHECK-NEXT: - - - - - - - - - - - - - ptrues p7.s # CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - ptrues p7.s, #14 # CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - ptrues p7.s, #15 # CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - ptrues p7.s, #16 diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-basic-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-basic-instructions.s index eddc3e565c353..787acbe91c057 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-basic-instructions.s +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-basic-instructions.s @@ -2673,14 +2673,14 @@ drps # CHECK-NEXT: 1 2 0.50 bics x3, xzr, x3, lsl #1 # CHECK-NEXT: 1 2 0.50 tst w3, w7, lsl #31 # CHECK-NEXT: 1 2 0.50 tst x2, x20, asr #2 -# CHECK-NEXT: 1 1 0.25 mov x3, x6 -# CHECK-NEXT: 1 1 0.25 mov x3, xzr -# CHECK-NEXT: 1 1 0.25 mov wzr, w2 -# CHECK-NEXT: 1 1 0.25 mov w3, w5 +# CHECK-NEXT: 1 0 0.13 mov x3, x6 +# CHECK-NEXT: 1 0 0.13 mov x3, xzr +# CHECK-NEXT: 1 0 0.13 mov wzr, w2 +# CHECK-NEXT: 1 0 0.13 mov w3, w5 # CHECK-NEXT: 1 1 0.25 movz w2, #0, lsl #16 # CHECK-NEXT: 1 1 0.25 mov w2, #-1235 # CHECK-NEXT: 1 1 0.25 mov x2, #5299989643264 -# CHECK-NEXT: 1 1 0.25 mov x2, #0 +# CHECK-NEXT: 1 0 0.13 mov x2, #0 # CHECK-NEXT: 1 1 0.25 movk w3, #0 # CHECK-NEXT: 1 1 0.25 movz x4, #0, lsl #16 # CHECK-NEXT: 1 1 0.25 movk w5, #0, lsl #16 @@ -2731,7 +2731,7 @@ drps # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2.0] [2.1] [2.2] [3] [4.0] [4.1] [5] [6] [7.0] [7.1] [8] [9] [10] [11] -# CHECK-NEXT: 13.00 13.00 40.50 40.50 48.00 48.00 48.00 96.67 175.17 175.17 322.50 209.50 142.00 142.00 189.00 55.50 65.50 13.00 +# CHECK-NEXT: 13.00 13.00 40.50 40.50 48.00 48.00 48.00 96.67 175.17 175.17 321.25 208.25 140.75 140.75 189.00 55.50 65.50 13.00 # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2.0] [2.1] [2.2] [3] [4.0] [4.1] [5] [6] [7.0] [7.1] [8] [9] [10] [11] Instructions: @@ -3944,14 +3944,14 @@ drps # CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - 0.50 0.50 - - - - - - bics x3, xzr, x3, lsl #1 # CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - 0.50 0.50 - - - - - - tst w3, w7, lsl #31 # CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - 0.50 0.50 - - - - - - tst x2, x20, asr #2 -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - mov x3, x6 -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - mov x3, xzr -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - mov wzr, w2 -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - mov w3, w5 +# CHECK-NEXT: - - - - - - - - - - - - - - - - - - mov x3, x6 +# CHECK-NEXT: - - - - - - - - - - - - - - - - - - mov x3, xzr +# CHECK-NEXT: - - - - - - - - - - - - - - - - - - mov wzr, w2 +# CHECK-NEXT: - - - - - - - - - - - - - - - - - - mov w3, w5 # CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - movz w2, #0, lsl #16 # CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - mov w2, #-1235 # CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - mov x2, #5299989643264 -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - mov x2, #0 +# CHECK-NEXT: - - - - - - - - - - - - - - - - - - mov x2, #0 # CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - movk w3, #0 # CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - movz x4, #0, lsl #16 # CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - movk w5, #0, lsl #16 diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-writeback.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-writeback.s index 1961b24ae6aac..5efe3d0bbf14f 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-writeback.s +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-writeback.s @@ -5272,4 +5272,3 @@ add x0, x27, 1 # CHECK-NEXT: 2. 1 5.0 0.0 0.0 ldr x2, [x1], #254 # CHECK-NEXT: 3. 1 2.0 0.0 6.0 add x0, x27, #1 # CHECK-NEXT: 1 2.5 0.3 2.0 - diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-zero-dependency.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-zero-dependency.s index 3954cbd8c5490..47c5b7cd513b3 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-zero-dependency.s +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-zero-dependency.s @@ -6,13 +6,13 @@ cmp x0, #4 # CHECK: Iterations: 100 # CHECK-NEXT: Instructions: 200 -# CHECK-NEXT: Total Cycles: 54 +# CHECK-NEXT: Total Cycles: 37 # CHECK-NEXT: Total uOps: 200 # CHECK: Dispatch Width: 8 -# CHECK-NEXT: uOps Per Cycle: 3.70 -# CHECK-NEXT: IPC: 3.70 -# CHECK-NEXT: Block RThroughput: 0.5 +# CHECK-NEXT: uOps Per Cycle: 5.41 +# CHECK-NEXT: IPC: 5.41 +# CHECK-NEXT: Block RThroughput: 0.3 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -23,7 +23,7 @@ cmp x0, #4 # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 1 1 0.25 mov x0, x1 +# CHECK-NEXT: 1 0 0.13 mov x0, x1 # CHECK-NEXT: 1 1 0.33 cmp x0, #4 # CHECK: Resources: @@ -48,24 +48,24 @@ cmp x0, #4 # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2.0] [2.1] [2.2] [3] [4.0] [4.1] [5] [6] [7.0] [7.1] [8] [9] [10] [11] -# CHECK-NEXT: - - - - 0.33 0.33 0.34 - - - 0.50 0.50 0.50 0.50 - - - - +# CHECK-NEXT: - - - - 0.33 0.33 0.34 - - - 0.22 0.22 0.28 0.28 - - - - # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2.0] [2.1] [2.2] [3] [4.0] [4.1] [5] [6] [7.0] [7.1] [8] [9] [10] [11] Instructions: -# CHECK-NEXT: - - - - - - - - - - 0.49 0.49 0.01 0.01 - - - - mov x0, x1 -# CHECK-NEXT: - - - - 0.33 0.33 0.34 - - - 0.01 0.01 0.49 0.49 - - - - cmp x0, #4 +# CHECK-NEXT: - - - - - - - - - - - - - - - - - - mov x0, x1 +# CHECK-NEXT: - - - - 0.33 0.33 0.34 - - - 0.22 0.22 0.28 0.28 - - - - cmp x0, #4 # CHECK: Timeline view: -# CHECK-NEXT: Index 012345 +# CHECK-NEXT: Index 01234 -# CHECK: [0,0] DeER . mov x0, x1 -# CHECK-NEXT: [0,1] D=eER. cmp x0, #4 -# CHECK-NEXT: [1,0] DeE-R. mov x0, x1 -# CHECK-NEXT: [1,1] D=eER. cmp x0, #4 -# CHECK-NEXT: [2,0] DeE-R. mov x0, x1 -# CHECK-NEXT: [2,1] D=eER. cmp x0, #4 -# CHECK-NEXT: [3,0] DeE-R. mov x0, x1 -# CHECK-NEXT: [3,1] D==eER cmp x0, #4 +# CHECK: [0,0] DR . mov x0, x1 +# CHECK-NEXT: [0,1] DeER. cmp x0, #4 +# CHECK-NEXT: [1,0] D--R. mov x0, x1 +# CHECK-NEXT: [1,1] DeER. cmp x0, #4 +# CHECK-NEXT: [2,0] D--R. mov x0, x1 +# CHECK-NEXT: [2,1] DeER. cmp x0, #4 +# CHECK-NEXT: [3,0] D--R. mov x0, x1 +# CHECK-NEXT: [3,1] D=eER cmp x0, #4 # CHECK: Average Wait times (based on the timeline view): # CHECK-NEXT: [0]: Executions @@ -74,6 +74,6 @@ cmp x0, #4 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage # CHECK: [0] [1] [2] [3] -# CHECK-NEXT: 0. 4 1.0 1.0 0.8 mov x0, x1 -# CHECK-NEXT: 1. 4 2.3 0.3 0.0 cmp x0, #4 -# CHECK-NEXT: 4 1.6 0.6 0.4 +# CHECK-NEXT: 0. 4 0.0 0.0 1.5 mov x0, x1 +# CHECK-NEXT: 1. 4 1.3 1.3 0.0 cmp x0, #4 +# CHECK-NEXT: 4 0.6 0.6 0.8