diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp index 5e1b623db0561f..fe352296fb736b 100644 --- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp +++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp @@ -35,7 +35,7 @@ using namespace llvm; extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() { RegisterTargetMachine X(getTheRISCV32Target()); RegisterTargetMachine Y(getTheRISCV64Target()); - auto PR = PassRegistry::getPassRegistry(); + auto *PR = PassRegistry::getPassRegistry(); initializeGlobalISel(*PR); initializeRISCVMergeBaseOffsetOptPass(*PR); initializeRISCVExpandPseudoPass(*PR); @@ -43,12 +43,10 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() { } static StringRef computeDataLayout(const Triple &TT) { - if (TT.isArch64Bit()) { + if (TT.isArch64Bit()) return "e-m:e-p:64:64-i64:64-i128:128-n64-S128"; - } else { - assert(TT.isArch32Bit() && "only RV32 and RV64 are currently supported"); - return "e-m:e-p:32:32-i64:64-n32-S128"; - } + assert(TT.isArch32Bit() && "only RV32 and RV64 are currently supported"); + return "e-m:e-p:32:32-i64:64-n32-S128"; } static Reloc::Model getEffectiveRelocModel(const Triple &TT, @@ -143,7 +141,7 @@ class RISCVPassConfig : public TargetPassConfig { void addPreSched2() override; void addPreRegAlloc() override; }; -} +} // namespace TargetPassConfig *RISCVTargetMachine::createPassConfig(PassManagerBase &PM) { return new RISCVPassConfig(*this, PM); diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.h b/llvm/lib/Target/RISCV/RISCVTargetMachine.h index 9d1e04a42f7203..3156333f7ee175 100644 --- a/llvm/lib/Target/RISCV/RISCVTargetMachine.h +++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.h @@ -47,6 +47,6 @@ class RISCVTargetMachine : public LLVMTargetMachine { virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DstAS) const override; }; -} +} // namespace llvm #endif