diff --git a/clang/include/clang/Basic/riscv_vector.td b/clang/include/clang/Basic/riscv_vector.td
index 7e5889812aecc..5bf1916df117b 100644
--- a/clang/include/clang/Basic/riscv_vector.td
+++ b/clang/include/clang/Basic/riscv_vector.td
@@ -990,56 +990,6 @@ multiclass RVVPseudoVNCVTBuiltin<string IR, string MName, string type_range,
   }
 }
 
-// Define vread_csr&vwrite_csr described in RVV intrinsics doc.
-let HeaderCode =
-[{
-enum RVV_CSR {
-  RVV_VSTART = 0,
-  RVV_VXSAT,
-  RVV_VXRM,
-  RVV_VCSR,
-};
-
-static __inline__ __attribute__((__always_inline__, __nodebug__))
-unsigned long __riscv_vread_csr(enum RVV_CSR __csr) {
-  unsigned long __rv = 0;
-  switch (__csr) {
-    case RVV_VSTART:
-      __asm__ __volatile__ ("csrr\t%0, vstart" : "=r"(__rv) : : "memory");
-      break;
-    case RVV_VXSAT:
-      __asm__ __volatile__ ("csrr\t%0, vxsat" : "=r"(__rv) : : "memory");
-      break;
-    case RVV_VXRM:
-      __asm__ __volatile__ ("csrr\t%0, vxrm" : "=r"(__rv) : : "memory");
-      break;
-    case RVV_VCSR:
-      __asm__ __volatile__ ("csrr\t%0, vcsr" : "=r"(__rv) : : "memory");
-      break;
-  }
-  return __rv;
-}
-
-static __inline__ __attribute__((__always_inline__, __nodebug__))
-void __riscv_vwrite_csr(enum RVV_CSR __csr, unsigned long __value) {
-  switch (__csr) {
-    case RVV_VSTART:
-      __asm__ __volatile__ ("csrw\tvstart, %z0" : : "rJ"(__value) : "memory");
-      break;
-    case RVV_VXSAT:
-      __asm__ __volatile__ ("csrw\tvxsat, %z0" : : "rJ"(__value) : "memory");
-      break;
-    case RVV_VXRM:
-      __asm__ __volatile__ ("csrw\tvxrm, %z0" : : "rJ"(__value) : "memory");
-      break;
-    case RVV_VCSR:
-      __asm__ __volatile__ ("csrw\tvcsr, %z0" : : "rJ"(__value) : "memory");
-      break;
-  }
-}
-}] in
-def vread_vwrite_csr: RVVHeader;
-
 let HeaderCode =
 [{
 #define __riscv_vlenb() __builtin_rvv_vlenb()
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vread-csr.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vread-csr.c
deleted file mode 100644
index 9605d0c88b8f5..0000000000000
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vread-csr.c
+++ /dev/null
@@ -1,42 +0,0 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
-// REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm %s -o - \
-// RUN:     | opt -S -O2 | FileCheck  %s
-
-#include <riscv_vector.h>
-
-// CHECK-LABEL: @vread_csr_vstart(
-// CHECK-NEXT:  entry:
-// CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 asm sideeffect "csrr\09$0, vstart", "=r,~{memory}"() #[[ATTR1:[0-9]+]], !srcloc !4
-// CHECK-NEXT:    ret i64 [[TMP0]]
-//
-unsigned long vread_csr_vstart(void) {
-  return __riscv_vread_csr(RVV_VSTART);
-}
-
-// CHECK-LABEL: @vread_csr_vxsat(
-// CHECK-NEXT:  entry:
-// CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 asm sideeffect "csrr\09$0, vxsat", "=r,~{memory}"() #[[ATTR1]], !srcloc !5
-// CHECK-NEXT:    ret i64 [[TMP0]]
-//
-unsigned long vread_csr_vxsat(void) {
-  return __riscv_vread_csr(RVV_VXSAT);
-}
-
-// CHECK-LABEL: @vread_csr_vxrm(
-// CHECK-NEXT:  entry:
-// CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 asm sideeffect "csrr\09$0, vxrm", "=r,~{memory}"() #[[ATTR1]], !srcloc !6
-// CHECK-NEXT:    ret i64 [[TMP0]]
-//
-unsigned long vread_csr_vxrm(void) {
-  return __riscv_vread_csr(RVV_VXRM);
-}
-
-// CHECK-LABEL: @vread_csr_vcsr(
-// CHECK-NEXT:  entry:
-// CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 asm sideeffect "csrr\09$0, vcsr", "=r,~{memory}"() #[[ATTR1]], !srcloc !7
-// CHECK-NEXT:    ret i64 [[TMP0]]
-//
-unsigned long vread_csr_vcsr(void) {
-  return __riscv_vread_csr(RVV_VCSR);
-}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vwrite-csr.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vwrite-csr.c
deleted file mode 100644
index 01da208b7bdce..0000000000000
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vwrite-csr.c
+++ /dev/null
@@ -1,42 +0,0 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
-// REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm %s -o - \
-// RUN:     | opt -S -O2 | FileCheck  %s
-
-#include <riscv_vector.h>
-
-// CHECK-LABEL: @vwrite_csr_vstart(
-// CHECK-NEXT:  entry:
-// CHECK-NEXT:    tail call void asm sideeffect "csrw\09vstart, ${0:z}", "rJ,~{memory}"(i64 [[VALUE:%.*]]) #[[ATTR1:[0-9]+]], !srcloc !4
-// CHECK-NEXT:    ret void
-//
-void vwrite_csr_vstart(unsigned long value) {
-  __riscv_vwrite_csr(RVV_VSTART, value);
-}
-
-// CHECK-LABEL: @vwrite_csr_vxsat(
-// CHECK-NEXT:  entry:
-// CHECK-NEXT:    tail call void asm sideeffect "csrw\09vxsat, ${0:z}", "rJ,~{memory}"(i64 [[VALUE:%.*]]) #[[ATTR1]], !srcloc !5
-// CHECK-NEXT:    ret void
-//
-void vwrite_csr_vxsat(unsigned long value) {
-  __riscv_vwrite_csr(RVV_VXSAT, value);
-}
-
-// CHECK-LABEL: @vwrite_csr_vxrm(
-// CHECK-NEXT:  entry:
-// CHECK-NEXT:    tail call void asm sideeffect "csrw\09vxrm, ${0:z}", "rJ,~{memory}"(i64 [[VALUE:%.*]]) #[[ATTR1]], !srcloc !6
-// CHECK-NEXT:    ret void
-//
-void vwrite_csr_vxrm(unsigned long value) {
-  __riscv_vwrite_csr(RVV_VXRM, value);
-}
-
-// CHECK-LABEL: @vwrite_csr_vcsr(
-// CHECK-NEXT:  entry:
-// CHECK-NEXT:    tail call void asm sideeffect "csrw\09vcsr, ${0:z}", "rJ,~{memory}"(i64 [[VALUE:%.*]]) #[[ATTR1]], !srcloc !7
-// CHECK-NEXT:    ret void
-//
-void vwrite_csr_vcsr(unsigned long value) {
-  __riscv_vwrite_csr(RVV_VCSR, value);
-}