diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp index 3d8a3bfc5f179..4ee2aec191734 100644 --- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp @@ -2108,6 +2108,36 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) { ReplaceNode(Node, Load); return; } + case ISD::PREFETCH: + unsigned Locality = Node->getConstantOperandVal(3); + if (Locality > 2) + break; + + if (auto *LoadStoreMem = dyn_cast(Node)) { + MachineMemOperand *MMO = LoadStoreMem->getMemOperand(); + MMO->setFlags(MachineMemOperand::MONonTemporal); + + int NontemporalLevel = 0; + switch (Locality) { + case 0: + NontemporalLevel = 3; // NTL.ALL + break; + case 1: + NontemporalLevel = 1; // NTL.PALL + break; + case 2: + NontemporalLevel = 0; // NTL.P1 + break; + default: + llvm_unreachable("unexpected locality value."); + } + + if (NontemporalLevel & 0b1) + MMO->setFlags(MONontemporalBit0); + if (NontemporalLevel & 0b10) + MMO->setFlags(MONontemporalBit1); + } + break; } // Select the default instruction. diff --git a/llvm/test/CodeGen/RISCV/prefetch.ll b/llvm/test/CodeGen/RISCV/prefetch.ll index a14ac8921ca06..c34c17ca6cda9 100644 --- a/llvm/test/CodeGen/RISCV/prefetch.ll +++ b/llvm/test/CodeGen/RISCV/prefetch.ll @@ -33,6 +33,7 @@ define void @test_prefetch_read_locality_0(ptr %a) nounwind { ; ; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_read_locality_0: ; RV64ZICBOPZIHINTNTL: # %bb.0: +; RV64ZICBOPZIHINTNTL-NEXT: ntl.all ; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0) ; RV64ZICBOPZIHINTNTL-NEXT: ret call void @llvm.prefetch(ptr %a, i32 0, i32 0, i32 1) @@ -60,6 +61,7 @@ define void @test_prefetch_write_locality_0(ptr %a) nounwind { ; ; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_write_locality_0: ; RV64ZICBOPZIHINTNTL: # %bb.0: +; RV64ZICBOPZIHINTNTL-NEXT: ntl.all ; RV64ZICBOPZIHINTNTL-NEXT: prefetch.w 0(a0) ; RV64ZICBOPZIHINTNTL-NEXT: ret call void @llvm.prefetch(ptr %a, i32 1, i32 0, i32 1) @@ -87,6 +89,7 @@ define void @test_prefetch_instruction_locality_0(ptr %a) nounwind { ; ; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_instruction_locality_0: ; RV64ZICBOPZIHINTNTL: # %bb.0: +; RV64ZICBOPZIHINTNTL-NEXT: ntl.all ; RV64ZICBOPZIHINTNTL-NEXT: prefetch.i 0(a0) ; RV64ZICBOPZIHINTNTL-NEXT: ret call void @llvm.prefetch(ptr %a, i32 0, i32 0, i32 0) @@ -114,6 +117,7 @@ define void @test_prefetch_read_locality_1(ptr %a) nounwind { ; ; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_read_locality_1: ; RV64ZICBOPZIHINTNTL: # %bb.0: +; RV64ZICBOPZIHINTNTL-NEXT: ntl.pall ; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0) ; RV64ZICBOPZIHINTNTL-NEXT: ret call void @llvm.prefetch(ptr %a, i32 0, i32 1, i32 1) @@ -141,6 +145,7 @@ define void @test_prefetch_write_locality_1(ptr %a) nounwind { ; ; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_write_locality_1: ; RV64ZICBOPZIHINTNTL: # %bb.0: +; RV64ZICBOPZIHINTNTL-NEXT: ntl.pall ; RV64ZICBOPZIHINTNTL-NEXT: prefetch.w 0(a0) ; RV64ZICBOPZIHINTNTL-NEXT: ret call void @llvm.prefetch(ptr %a, i32 1, i32 1, i32 1) @@ -168,6 +173,7 @@ define void @test_prefetch_instruction_locality_1(ptr %a) nounwind { ; ; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_instruction_locality_1: ; RV64ZICBOPZIHINTNTL: # %bb.0: +; RV64ZICBOPZIHINTNTL-NEXT: ntl.pall ; RV64ZICBOPZIHINTNTL-NEXT: prefetch.i 0(a0) ; RV64ZICBOPZIHINTNTL-NEXT: ret call void @llvm.prefetch(ptr %a, i32 0, i32 1, i32 0) @@ -195,6 +201,7 @@ define void @test_prefetch_read_locality_2(ptr %a) nounwind { ; ; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_read_locality_2: ; RV64ZICBOPZIHINTNTL: # %bb.0: +; RV64ZICBOPZIHINTNTL-NEXT: ntl.p1 ; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0) ; RV64ZICBOPZIHINTNTL-NEXT: ret call void @llvm.prefetch(ptr %a, i32 0, i32 2, i32 1) @@ -222,6 +229,7 @@ define void @test_prefetch_write_locality_2(ptr %a) nounwind { ; ; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_write_locality_2: ; RV64ZICBOPZIHINTNTL: # %bb.0: +; RV64ZICBOPZIHINTNTL-NEXT: ntl.p1 ; RV64ZICBOPZIHINTNTL-NEXT: prefetch.w 0(a0) ; RV64ZICBOPZIHINTNTL-NEXT: ret call void @llvm.prefetch(ptr %a, i32 1, i32 2, i32 1) @@ -249,6 +257,7 @@ define void @test_prefetch_instruction_locality_2(ptr %a) nounwind { ; ; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_instruction_locality_2: ; RV64ZICBOPZIHINTNTL: # %bb.0: +; RV64ZICBOPZIHINTNTL-NEXT: ntl.p1 ; RV64ZICBOPZIHINTNTL-NEXT: prefetch.i 0(a0) ; RV64ZICBOPZIHINTNTL-NEXT: ret call void @llvm.prefetch(ptr %a, i32 0, i32 2, i32 0)