diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/memtest1.ll b/llvm/test/CodeGen/Mips/Fast-ISel/memtest1.ll index 1a2ad44b0a6b1..8bf41e01a979b 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/memtest1.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/memtest1.ll @@ -1,9 +1,7 @@ ; RUN: llc < %s -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic \ -; RUN: -fast-isel-abort=3 -verify-machineinstrs | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=32R1 +; RUN: -fast-isel-abort=3 -verify-machineinstrs | FileCheck %s ; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \ -; RUN: -fast-isel-abort=3 -verify-machineinstrs | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=32R2 +; RUN: -fast-isel-abort=3 -verify-machineinstrs | FileCheck %s @str = private unnamed_addr constant [12 x i8] c"hello there\00", align 1 @src = global i8* getelementptr inbounds ([12 x i8], [12 x i8]* @str, i32 0, i32 0), align 4 @@ -15,38 +13,37 @@ declare void @llvm.memmove.p0i8.p0i8.i32(i8* nocapture, i8* nocapture readonly, declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i1) define void @cpy(i8* %src, i32 %i) { - ; ALL-LABEL: cpy: + ; CHECK-LABEL: cpy: - ; ALL: lw $[[T0:[0-9]+]], %got(dest)(${{[0-9]+}}) - ; ALL: lw $[[T2:[0-9]+]], %got(memcpy)(${{[0-9]+}}) - ; ALL: jalr $[[T2]] - ; ALL-NEXT: nop - ; ALL-NOT: {{.*}}$2{{.*}} + ; CHECK: lw $[[T0:[0-9]+]], %got(dest)(${{[0-9]+}}) + ; CHECK: lw $[[T2:[0-9]+]], %got(memcpy)(${{[0-9]+}}) + ; CHECK: jalr $[[T2]] + ; CHECK-NEXT: nop + ; CHECK-NOT: {{.*}}$2{{.*}} call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds ([50 x i8], [50 x i8]* @dest, i32 0, i32 0), i8* %src, i32 %i, i1 false) ret void } define void @mov(i8* %src, i32 %i) { - ; ALL-LABEL: mov: + ; CHECK-LABEL: mov: - - ; ALL: lw $[[T0:[0-9]+]], %got(dest)(${{[0-9]+}}) - ; ALL: lw $[[T2:[0-9]+]], %got(memmove)(${{[0-9]+}}) - ; ALL: jalr $[[T2]] - ; ALL-NEXT: nop - ; ALL-NOT: {{.*}}$2{{.*}} + ; CHECK: lw $[[T0:[0-9]+]], %got(dest)(${{[0-9]+}}) + ; CHECK: lw $[[T2:[0-9]+]], %got(memmove)(${{[0-9]+}}) + ; CHECK: jalr $[[T2]] + ; CHECK-NEXT: nop + ; CHECK-NOT: {{.*}}$2{{.*}} call void @llvm.memmove.p0i8.p0i8.i32(i8* getelementptr inbounds ([50 x i8], [50 x i8]* @dest, i32 0, i32 0), i8* %src, i32 %i, i1 false) ret void } define void @clear(i32 %i) { - ; ALL-LABEL: clear: + ; CHECK-LABEL: clear: - ; ALL: lw $[[T0:[0-9]+]], %got(dest)(${{[0-9]+}}) - ; ALL: lw $[[T2:[0-9]+]], %got(memset)(${{[0-9]+}}) - ; ALL: jalr $[[T2]] - ; ALL-NEXT: nop - ; ALL-NOT: {{.*}}$2{{.*}} + ; CHECK: lw $[[T0:[0-9]+]], %got(dest)(${{[0-9]+}}) + ; CHECK: lw $[[T2:[0-9]+]], %got(memset)(${{[0-9]+}}) + ; CHECK: jalr $[[T2]] + ; CHECK-NEXT: nop + ; CHECK-NOT: {{.*}}$2{{.*}} call void @llvm.memset.p0i8.i32(i8* getelementptr inbounds ([50 x i8], [50 x i8]* @dest, i32 0, i32 0), i8 42, i32 %i, i1 false) ret void } diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/ceil_and_floor.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/ceil_and_floor.ll index c3366430d6174..87d642d655cf4 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/ceil_and_floor.ll +++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/ceil_and_floor.ll @@ -1,21 +1,23 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP32 -; RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP64 +; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel \ +; RUN: -verify-machineinstrs %s -o -| FileCheck %s +; RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -global-isel \ +; RUN: -verify-machineinstrs %s -o -| FileCheck %s declare float @llvm.ceil.f32(float) define float @ceil_f32(float %a) { -; MIPS32-LABEL: ceil_f32: -; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: addiu $sp, $sp, -24 -; MIPS32-NEXT: .cfi_def_cfa_offset 24 -; MIPS32-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill -; MIPS32-NEXT: .cfi_offset 31, -4 -; MIPS32-NEXT: jal ceilf -; MIPS32-NEXT: nop -; MIPS32-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload -; MIPS32-NEXT: addiu $sp, $sp, 24 -; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: nop +; CHECK-LABEL: ceil_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addiu $sp, $sp, -24 +; CHECK-NEXT: .cfi_def_cfa_offset 24 +; CHECK-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill +; CHECK-NEXT: .cfi_offset 31, -4 +; CHECK-NEXT: jal ceilf +; CHECK-NEXT: nop +; CHECK-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload +; CHECK-NEXT: addiu $sp, $sp, 24 +; CHECK-NEXT: jr $ra +; CHECK-NEXT: nop entry: %0 = call float @llvm.ceil.f32(float %a) ret float %0 @@ -23,18 +25,18 @@ entry: declare double @llvm.ceil.f64(double) define double @ceil_f64(double %a) { -; MIPS32-LABEL: ceil_f64: -; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: addiu $sp, $sp, -24 -; MIPS32-NEXT: .cfi_def_cfa_offset 24 -; MIPS32-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill -; MIPS32-NEXT: .cfi_offset 31, -4 -; MIPS32-NEXT: jal ceil -; MIPS32-NEXT: nop -; MIPS32-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload -; MIPS32-NEXT: addiu $sp, $sp, 24 -; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: nop +; CHECK-LABEL: ceil_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addiu $sp, $sp, -24 +; CHECK-NEXT: .cfi_def_cfa_offset 24 +; CHECK-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill +; CHECK-NEXT: .cfi_offset 31, -4 +; CHECK-NEXT: jal ceil +; CHECK-NEXT: nop +; CHECK-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload +; CHECK-NEXT: addiu $sp, $sp, 24 +; CHECK-NEXT: jr $ra +; CHECK-NEXT: nop entry: %0 = call double @llvm.ceil.f64(double %a) ret double %0 @@ -42,18 +44,18 @@ entry: declare float @llvm.floor.f32(float) define float @floor_f32(float %a) { -; MIPS32-LABEL: floor_f32: -; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: addiu $sp, $sp, -24 -; MIPS32-NEXT: .cfi_def_cfa_offset 24 -; MIPS32-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill -; MIPS32-NEXT: .cfi_offset 31, -4 -; MIPS32-NEXT: jal floorf -; MIPS32-NEXT: nop -; MIPS32-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload -; MIPS32-NEXT: addiu $sp, $sp, 24 -; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: nop +; CHECK-LABEL: floor_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addiu $sp, $sp, -24 +; CHECK-NEXT: .cfi_def_cfa_offset 24 +; CHECK-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill +; CHECK-NEXT: .cfi_offset 31, -4 +; CHECK-NEXT: jal floorf +; CHECK-NEXT: nop +; CHECK-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload +; CHECK-NEXT: addiu $sp, $sp, 24 +; CHECK-NEXT: jr $ra +; CHECK-NEXT: nop entry: %0 = call float @llvm.floor.f32(float %a) ret float %0 @@ -61,18 +63,18 @@ entry: declare double @llvm.floor.f64(double) define double @floor_f64(double %a) { -; MIPS32-LABEL: floor_f64: -; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: addiu $sp, $sp, -24 -; MIPS32-NEXT: .cfi_def_cfa_offset 24 -; MIPS32-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill -; MIPS32-NEXT: .cfi_offset 31, -4 -; MIPS32-NEXT: jal floor -; MIPS32-NEXT: nop -; MIPS32-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload -; MIPS32-NEXT: addiu $sp, $sp, 24 -; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: nop +; CHECK-LABEL: floor_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addiu $sp, $sp, -24 +; CHECK-NEXT: .cfi_def_cfa_offset 24 +; CHECK-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill +; CHECK-NEXT: .cfi_offset 31, -4 +; CHECK-NEXT: jal floor +; CHECK-NEXT: nop +; CHECK-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload +; CHECK-NEXT: addiu $sp, $sp, 24 +; CHECK-NEXT: jr $ra +; CHECK-NEXT: nop entry: %0 = call double @llvm.floor.f64(double %a) ret double %0 diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fabs.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fabs.ll index e674248a31004..00927689ab5ce 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fabs.ll +++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fabs.ll @@ -1,14 +1,16 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP32 -; RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP64 +; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel \ +; RUN: -verify-machineinstrs %s -o -| FileCheck %s +; RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -global-isel \ +; RUN: -verify-machineinstrs %s -o -| FileCheck %s declare float @llvm.fabs.f32(float) define float @fabs_f32(float %a) { -; MIPS32-LABEL: fabs_f32: -; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: abs.s $f0, $f12 -; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: nop +; CHECK-LABEL: fabs_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: abs.s $f0, $f12 +; CHECK-NEXT: jr $ra +; CHECK-NEXT: nop entry: %0 = call float @llvm.fabs.f32(float %a) ret float %0 @@ -16,11 +18,11 @@ entry: declare double @llvm.fabs.f64(double) define double @fabs_f64(double %a) { -; MIPS32-LABEL: fabs_f64: -; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: abs.d $f0, $f12 -; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: nop +; CHECK-LABEL: fabs_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: abs.d $f0, $f12 +; CHECK-NEXT: jr $ra +; CHECK-NEXT: nop entry: %0 = call double @llvm.fabs.f64(double %a) ret double %0 diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fcmp.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fcmp.ll index bfff4e72d0ab3..9d3b7ce079f92 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fcmp.ll +++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fcmp.ll @@ -1,23 +1,25 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP32 -; RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP64 +; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel \ +; RUN: -verify-machineinstrs %s -o -| FileCheck %s +; RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -global-isel \ +; RUN: -verify-machineinstrs %s -o -| FileCheck %s define i1 @false_s(float %x, float %y) { -; MIPS32-LABEL: false_s: -; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: ori $2, $zero, 0 -; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: nop +; CHECK-LABEL: false_s: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: ori $2, $zero, 0 +; CHECK-NEXT: jr $ra +; CHECK-NEXT: nop entry: %cmp = fcmp false float %x, %y ret i1 %cmp } define i1 @true_s(float %x, float %y) { -; MIPS32-LABEL: true_s: -; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: ori $2, $zero, 1 -; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: nop +; CHECK-LABEL: true_s: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: ori $2, $zero, 1 +; CHECK-NEXT: jr $ra +; CHECK-NEXT: nop entry: %cmp = fcmp true float %x, %y ret i1 %cmp @@ -25,25 +27,25 @@ entry: define i1 @uno_s(float %x, float %y) { -; MIPS32-LABEL: uno_s: -; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: addiu $2, $zero, 1 -; MIPS32-NEXT: c.un.s $f12, $f14 -; MIPS32-NEXT: movf $2, $zero, $fcc0 -; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: nop +; CHECK-LABEL: uno_s: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addiu $2, $zero, 1 +; CHECK-NEXT: c.un.s $f12, $f14 +; CHECK-NEXT: movf $2, $zero, $fcc0 +; CHECK-NEXT: jr $ra +; CHECK-NEXT: nop entry: %cmp = fcmp uno float %x, %y ret i1 %cmp } define i1 @ord_s(float %x, float %y) { -; MIPS32-LABEL: ord_s: -; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: addiu $2, $zero, 1 -; MIPS32-NEXT: c.un.s $f12, $f14 -; MIPS32-NEXT: movt $2, $zero, $fcc0 -; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: nop +; CHECK-LABEL: ord_s: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addiu $2, $zero, 1 +; CHECK-NEXT: c.un.s $f12, $f14 +; CHECK-NEXT: movt $2, $zero, $fcc0 +; CHECK-NEXT: jr $ra +; CHECK-NEXT: nop entry: %cmp = fcmp ord float %x, %y ret i1 %cmp @@ -51,25 +53,25 @@ entry: define i1 @oeq_s(float %x, float %y) { -; MIPS32-LABEL: oeq_s: -; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: addiu $2, $zero, 1 -; MIPS32-NEXT: c.eq.s $f12, $f14 -; MIPS32-NEXT: movf $2, $zero, $fcc0 -; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: nop +; CHECK-LABEL: oeq_s: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addiu $2, $zero, 1 +; CHECK-NEXT: c.eq.s $f12, $f14 +; CHECK-NEXT: movf $2, $zero, $fcc0 +; CHECK-NEXT: jr $ra +; CHECK-NEXT: nop entry: %cmp = fcmp oeq float %x, %y ret i1 %cmp } define i1 @une_s(float %x, float %y) { -; MIPS32-LABEL: une_s: -; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: addiu $2, $zero, 1 -; MIPS32-NEXT: c.eq.s $f12, $f14 -; MIPS32-NEXT: movt $2, $zero, $fcc0 -; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: nop +; CHECK-LABEL: une_s: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addiu $2, $zero, 1 +; CHECK-NEXT: c.eq.s $f12, $f14 +; CHECK-NEXT: movt $2, $zero, $fcc0 +; CHECK-NEXT: jr $ra +; CHECK-NEXT: nop entry: %cmp = fcmp une float %x, %y ret i1 %cmp @@ -77,25 +79,25 @@ entry: define i1 @ueq_s(float %x, float %y) { -; MIPS32-LABEL: ueq_s: -; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: addiu $2, $zero, 1 -; MIPS32-NEXT: c.ueq.s $f12, $f14 -; MIPS32-NEXT: movf $2, $zero, $fcc0 -; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: nop +; CHECK-LABEL: ueq_s: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addiu $2, $zero, 1 +; CHECK-NEXT: c.ueq.s $f12, $f14 +; CHECK-NEXT: movf $2, $zero, $fcc0 +; CHECK-NEXT: jr $ra +; CHECK-NEXT: nop entry: %cmp = fcmp ueq float %x, %y ret i1 %cmp } define i1 @one_s(float %x, float %y) { -; MIPS32-LABEL: one_s: -; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: addiu $2, $zero, 1 -; MIPS32-NEXT: c.ueq.s $f12, $f14 -; MIPS32-NEXT: movt $2, $zero, $fcc0 -; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: nop +; CHECK-LABEL: one_s: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addiu $2, $zero, 1 +; CHECK-NEXT: c.ueq.s $f12, $f14 +; CHECK-NEXT: movt $2, $zero, $fcc0 +; CHECK-NEXT: jr $ra +; CHECK-NEXT: nop entry: %cmp = fcmp one float %x, %y ret i1 %cmp @@ -103,25 +105,25 @@ entry: define i1 @olt_s(float %x, float %y) { -; MIPS32-LABEL: olt_s: -; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: addiu $2, $zero, 1 -; MIPS32-NEXT: c.olt.s $f12, $f14 -; MIPS32-NEXT: movf $2, $zero, $fcc0 -; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: nop +; CHECK-LABEL: olt_s: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addiu $2, $zero, 1 +; CHECK-NEXT: c.olt.s $f12, $f14 +; CHECK-NEXT: movf $2, $zero, $fcc0 +; CHECK-NEXT: jr $ra +; CHECK-NEXT: nop entry: %cmp = fcmp olt float %x, %y ret i1 %cmp } define i1 @uge_s(float %x, float %y) { -; MIPS32-LABEL: uge_s: -; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: addiu $2, $zero, 1 -; MIPS32-NEXT: c.olt.s $f12, $f14 -; MIPS32-NEXT: movt $2, $zero, $fcc0 -; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: nop +; CHECK-LABEL: uge_s: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addiu $2, $zero, 1 +; CHECK-NEXT: c.olt.s $f12, $f14 +; CHECK-NEXT: movt $2, $zero, $fcc0 +; CHECK-NEXT: jr $ra +; CHECK-NEXT: nop entry: %cmp = fcmp uge float %x, %y ret i1 %cmp @@ -129,25 +131,25 @@ entry: define i1 @ult_s(float %x, float %y) { -; MIPS32-LABEL: ult_s: -; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: addiu $2, $zero, 1 -; MIPS32-NEXT: c.ult.s $f12, $f14 -; MIPS32-NEXT: movf $2, $zero, $fcc0 -; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: nop +; CHECK-LABEL: ult_s: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addiu $2, $zero, 1 +; CHECK-NEXT: c.ult.s $f12, $f14 +; CHECK-NEXT: movf $2, $zero, $fcc0 +; CHECK-NEXT: jr $ra +; CHECK-NEXT: nop entry: %cmp = fcmp ult float %x, %y ret i1 %cmp } define i1 @oge_s(float %x, float %y) { -; MIPS32-LABEL: oge_s: -; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: addiu $2, $zero, 1 -; MIPS32-NEXT: c.ult.s $f12, $f14 -; MIPS32-NEXT: movt $2, $zero, $fcc0 -; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: nop +; CHECK-LABEL: oge_s: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addiu $2, $zero, 1 +; CHECK-NEXT: c.ult.s $f12, $f14 +; CHECK-NEXT: movt $2, $zero, $fcc0 +; CHECK-NEXT: jr $ra +; CHECK-NEXT: nop entry: %cmp = fcmp oge float %x, %y ret i1 %cmp @@ -155,25 +157,25 @@ entry: define i1 @ole_s(float %x, float %y) { -; MIPS32-LABEL: ole_s: -; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: addiu $2, $zero, 1 -; MIPS32-NEXT: c.ole.s $f12, $f14 -; MIPS32-NEXT: movf $2, $zero, $fcc0 -; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: nop +; CHECK-LABEL: ole_s: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addiu $2, $zero, 1 +; CHECK-NEXT: c.ole.s $f12, $f14 +; CHECK-NEXT: movf $2, $zero, $fcc0 +; CHECK-NEXT: jr $ra +; CHECK-NEXT: nop entry: %cmp = fcmp ole float %x, %y ret i1 %cmp } define i1 @ugt_s(float %x, float %y) { -; MIPS32-LABEL: ugt_s: -; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: addiu $2, $zero, 1 -; MIPS32-NEXT: c.ole.s $f12, $f14 -; MIPS32-NEXT: movt $2, $zero, $fcc0 -; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: nop +; CHECK-LABEL: ugt_s: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addiu $2, $zero, 1 +; CHECK-NEXT: c.ole.s $f12, $f14 +; CHECK-NEXT: movt $2, $zero, $fcc0 +; CHECK-NEXT: jr $ra +; CHECK-NEXT: nop entry: %cmp = fcmp ugt float %x, %y ret i1 %cmp @@ -181,25 +183,25 @@ entry: define i1 @ule_s(float %x, float %y) { -; MIPS32-LABEL: ule_s: -; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: addiu $2, $zero, 1 -; MIPS32-NEXT: c.ule.s $f12, $f14 -; MIPS32-NEXT: movf $2, $zero, $fcc0 -; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: nop +; CHECK-LABEL: ule_s: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addiu $2, $zero, 1 +; CHECK-NEXT: c.ule.s $f12, $f14 +; CHECK-NEXT: movf $2, $zero, $fcc0 +; CHECK-NEXT: jr $ra +; CHECK-NEXT: nop entry: %cmp = fcmp ule float %x, %y ret i1 %cmp } define i1 @ogt_s(float %x, float %y) { -; MIPS32-LABEL: ogt_s: -; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: addiu $2, $zero, 1 -; MIPS32-NEXT: c.ule.s $f12, $f14 -; MIPS32-NEXT: movt $2, $zero, $fcc0 -; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: nop +; CHECK-LABEL: ogt_s: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addiu $2, $zero, 1 +; CHECK-NEXT: c.ule.s $f12, $f14 +; CHECK-NEXT: movt $2, $zero, $fcc0 +; CHECK-NEXT: jr $ra +; CHECK-NEXT: nop entry: %cmp = fcmp ogt float %x, %y ret i1 %cmp @@ -207,21 +209,21 @@ entry: define i1 @false_d(double %x, double %y) { -; MIPS32-LABEL: false_d: -; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: ori $2, $zero, 0 -; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: nop +; CHECK-LABEL: false_d: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: ori $2, $zero, 0 +; CHECK-NEXT: jr $ra +; CHECK-NEXT: nop entry: %cmp = fcmp false double %x, %y ret i1 %cmp } define i1 @true_d(double %x, double %y) { -; MIPS32-LABEL: true_d: -; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: ori $2, $zero, 1 -; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: nop +; CHECK-LABEL: true_d: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: ori $2, $zero, 1 +; CHECK-NEXT: jr $ra +; CHECK-NEXT: nop entry: %cmp = fcmp true double %x, %y ret i1 %cmp @@ -229,25 +231,25 @@ entry: define i1 @uno_d(double %x, double %y) { -; MIPS32-LABEL: uno_d: -; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: addiu $2, $zero, 1 -; MIPS32-NEXT: c.un.d $f12, $f14 -; MIPS32-NEXT: movf $2, $zero, $fcc0 -; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: nop +; CHECK-LABEL: uno_d: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addiu $2, $zero, 1 +; CHECK-NEXT: c.un.d $f12, $f14 +; CHECK-NEXT: movf $2, $zero, $fcc0 +; CHECK-NEXT: jr $ra +; CHECK-NEXT: nop entry: %cmp = fcmp uno double %x, %y ret i1 %cmp } define i1 @ord_d(double %x, double %y) { -; MIPS32-LABEL: ord_d: -; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: addiu $2, $zero, 1 -; MIPS32-NEXT: c.un.d $f12, $f14 -; MIPS32-NEXT: movt $2, $zero, $fcc0 -; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: nop +; CHECK-LABEL: ord_d: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addiu $2, $zero, 1 +; CHECK-NEXT: c.un.d $f12, $f14 +; CHECK-NEXT: movt $2, $zero, $fcc0 +; CHECK-NEXT: jr $ra +; CHECK-NEXT: nop entry: %cmp = fcmp ord double %x, %y ret i1 %cmp @@ -255,25 +257,25 @@ entry: define i1 @oeq_d(double %x, double %y) { -; MIPS32-LABEL: oeq_d: -; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: addiu $2, $zero, 1 -; MIPS32-NEXT: c.eq.d $f12, $f14 -; MIPS32-NEXT: movf $2, $zero, $fcc0 -; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: nop +; CHECK-LABEL: oeq_d: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addiu $2, $zero, 1 +; CHECK-NEXT: c.eq.d $f12, $f14 +; CHECK-NEXT: movf $2, $zero, $fcc0 +; CHECK-NEXT: jr $ra +; CHECK-NEXT: nop entry: %cmp = fcmp oeq double %x, %y ret i1 %cmp } define i1 @une_d(double %x, double %y) { -; MIPS32-LABEL: une_d: -; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: addiu $2, $zero, 1 -; MIPS32-NEXT: c.eq.d $f12, $f14 -; MIPS32-NEXT: movt $2, $zero, $fcc0 -; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: nop +; CHECK-LABEL: une_d: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addiu $2, $zero, 1 +; CHECK-NEXT: c.eq.d $f12, $f14 +; CHECK-NEXT: movt $2, $zero, $fcc0 +; CHECK-NEXT: jr $ra +; CHECK-NEXT: nop entry: %cmp = fcmp une double %x, %y ret i1 %cmp @@ -281,25 +283,25 @@ entry: define i1 @ueq_d(double %x, double %y) { -; MIPS32-LABEL: ueq_d: -; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: addiu $2, $zero, 1 -; MIPS32-NEXT: c.ueq.d $f12, $f14 -; MIPS32-NEXT: movf $2, $zero, $fcc0 -; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: nop +; CHECK-LABEL: ueq_d: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addiu $2, $zero, 1 +; CHECK-NEXT: c.ueq.d $f12, $f14 +; CHECK-NEXT: movf $2, $zero, $fcc0 +; CHECK-NEXT: jr $ra +; CHECK-NEXT: nop entry: %cmp = fcmp ueq double %x, %y ret i1 %cmp } define i1 @one_d(double %x, double %y) { -; MIPS32-LABEL: one_d: -; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: addiu $2, $zero, 1 -; MIPS32-NEXT: c.ueq.d $f12, $f14 -; MIPS32-NEXT: movt $2, $zero, $fcc0 -; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: nop +; CHECK-LABEL: one_d: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addiu $2, $zero, 1 +; CHECK-NEXT: c.ueq.d $f12, $f14 +; CHECK-NEXT: movt $2, $zero, $fcc0 +; CHECK-NEXT: jr $ra +; CHECK-NEXT: nop entry: %cmp = fcmp one double %x, %y ret i1 %cmp @@ -307,25 +309,25 @@ entry: define i1 @olt_d(double %x, double %y) { -; MIPS32-LABEL: olt_d: -; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: addiu $2, $zero, 1 -; MIPS32-NEXT: c.olt.d $f12, $f14 -; MIPS32-NEXT: movf $2, $zero, $fcc0 -; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: nop +; CHECK-LABEL: olt_d: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addiu $2, $zero, 1 +; CHECK-NEXT: c.olt.d $f12, $f14 +; CHECK-NEXT: movf $2, $zero, $fcc0 +; CHECK-NEXT: jr $ra +; CHECK-NEXT: nop entry: %cmp = fcmp olt double %x, %y ret i1 %cmp } define i1 @uge_d(double %x, double %y) { -; MIPS32-LABEL: uge_d: -; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: addiu $2, $zero, 1 -; MIPS32-NEXT: c.olt.d $f12, $f14 -; MIPS32-NEXT: movt $2, $zero, $fcc0 -; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: nop +; CHECK-LABEL: uge_d: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addiu $2, $zero, 1 +; CHECK-NEXT: c.olt.d $f12, $f14 +; CHECK-NEXT: movt $2, $zero, $fcc0 +; CHECK-NEXT: jr $ra +; CHECK-NEXT: nop entry: %cmp = fcmp uge double %x, %y ret i1 %cmp @@ -333,25 +335,25 @@ entry: define i1 @ult_d(double %x, double %y) { -; MIPS32-LABEL: ult_d: -; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: addiu $2, $zero, 1 -; MIPS32-NEXT: c.ult.d $f12, $f14 -; MIPS32-NEXT: movf $2, $zero, $fcc0 -; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: nop +; CHECK-LABEL: ult_d: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addiu $2, $zero, 1 +; CHECK-NEXT: c.ult.d $f12, $f14 +; CHECK-NEXT: movf $2, $zero, $fcc0 +; CHECK-NEXT: jr $ra +; CHECK-NEXT: nop entry: %cmp = fcmp ult double %x, %y ret i1 %cmp } define i1 @oge_d(double %x, double %y) { -; MIPS32-LABEL: oge_d: -; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: addiu $2, $zero, 1 -; MIPS32-NEXT: c.ult.d $f12, $f14 -; MIPS32-NEXT: movt $2, $zero, $fcc0 -; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: nop +; CHECK-LABEL: oge_d: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addiu $2, $zero, 1 +; CHECK-NEXT: c.ult.d $f12, $f14 +; CHECK-NEXT: movt $2, $zero, $fcc0 +; CHECK-NEXT: jr $ra +; CHECK-NEXT: nop entry: %cmp = fcmp oge double %x, %y ret i1 %cmp @@ -359,25 +361,25 @@ entry: define i1 @ole_d(double %x, double %y) { -; MIPS32-LABEL: ole_d: -; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: addiu $2, $zero, 1 -; MIPS32-NEXT: c.ole.d $f12, $f14 -; MIPS32-NEXT: movf $2, $zero, $fcc0 -; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: nop +; CHECK-LABEL: ole_d: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addiu $2, $zero, 1 +; CHECK-NEXT: c.ole.d $f12, $f14 +; CHECK-NEXT: movf $2, $zero, $fcc0 +; CHECK-NEXT: jr $ra +; CHECK-NEXT: nop entry: %cmp = fcmp ole double %x, %y ret i1 %cmp } define i1 @ugt_d(double %x, double %y) { -; MIPS32-LABEL: ugt_d: -; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: addiu $2, $zero, 1 -; MIPS32-NEXT: c.ole.d $f12, $f14 -; MIPS32-NEXT: movt $2, $zero, $fcc0 -; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: nop +; CHECK-LABEL: ugt_d: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addiu $2, $zero, 1 +; CHECK-NEXT: c.ole.d $f12, $f14 +; CHECK-NEXT: movt $2, $zero, $fcc0 +; CHECK-NEXT: jr $ra +; CHECK-NEXT: nop entry: %cmp = fcmp ugt double %x, %y ret i1 %cmp @@ -385,25 +387,25 @@ entry: define i1 @ule_d(double %x, double %y) { -; MIPS32-LABEL: ule_d: -; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: addiu $2, $zero, 1 -; MIPS32-NEXT: c.ule.d $f12, $f14 -; MIPS32-NEXT: movf $2, $zero, $fcc0 -; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: nop +; CHECK-LABEL: ule_d: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addiu $2, $zero, 1 +; CHECK-NEXT: c.ule.d $f12, $f14 +; CHECK-NEXT: movf $2, $zero, $fcc0 +; CHECK-NEXT: jr $ra +; CHECK-NEXT: nop entry: %cmp = fcmp ule double %x, %y ret i1 %cmp } define i1 @ogt_d(double %x, double %y) { -; MIPS32-LABEL: ogt_d: -; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: addiu $2, $zero, 1 -; MIPS32-NEXT: c.ule.d $f12, $f14 -; MIPS32-NEXT: movt $2, $zero, $fcc0 -; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: nop +; CHECK-LABEL: ogt_d: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addiu $2, $zero, 1 +; CHECK-NEXT: c.ule.d $f12, $f14 +; CHECK-NEXT: movt $2, $zero, $fcc0 +; CHECK-NEXT: jr $ra +; CHECK-NEXT: nop entry: %cmp = fcmp ogt double %x, %y ret i1 %cmp diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/float_arithmetic_operations.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/float_arithmetic_operations.ll index 091640fe64586..3acd365770dac 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/float_arithmetic_operations.ll +++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/float_arithmetic_operations.ll @@ -1,90 +1,92 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP32 -; RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP64 +; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel \ +; RUN: -verify-machineinstrs %s -o -| FileCheck %s +; RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -global-isel \ +; RUN: -verify-machineinstrs %s -o -| FileCheck %s define float @float_add(float %a, float %b) { -; MIPS32-LABEL: float_add: -; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: add.s $f0, $f12, $f14 -; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: nop +; CHECK-LABEL: float_add: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: add.s $f0, $f12, $f14 +; CHECK-NEXT: jr $ra +; CHECK-NEXT: nop entry: %add = fadd float %a, %b ret float %add } define float @float_sub(float %a, float %b) { -; MIPS32-LABEL: float_sub: -; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: sub.s $f0, $f12, $f14 -; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: nop +; CHECK-LABEL: float_sub: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sub.s $f0, $f12, $f14 +; CHECK-NEXT: jr $ra +; CHECK-NEXT: nop entry: %sub = fsub float %a, %b ret float %sub } define float @float_mul(float %a, float %b) { -; MIPS32-LABEL: float_mul: -; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: mul.s $f0, $f12, $f14 -; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: nop +; CHECK-LABEL: float_mul: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: mul.s $f0, $f12, $f14 +; CHECK-NEXT: jr $ra +; CHECK-NEXT: nop entry: %mul = fmul float %a, %b ret float %mul } define float @float_div(float %a, float %b) { -; MIPS32-LABEL: float_div: -; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: div.s $f0, $f12, $f14 -; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: nop +; CHECK-LABEL: float_div: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: div.s $f0, $f12, $f14 +; CHECK-NEXT: jr $ra +; CHECK-NEXT: nop entry: %div = fdiv float %a, %b ret float %div } define double @double_add(double %a, double %b) { -; MIPS32-LABEL: double_add: -; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: add.d $f0, $f12, $f14 -; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: nop +; CHECK-LABEL: double_add: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: add.d $f0, $f12, $f14 +; CHECK-NEXT: jr $ra +; CHECK-NEXT: nop entry: %add = fadd double %a, %b ret double %add } define double @double_sub(double %a, double %b) { -; MIPS32-LABEL: double_sub: -; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: sub.d $f0, $f12, $f14 -; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: nop +; CHECK-LABEL: double_sub: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sub.d $f0, $f12, $f14 +; CHECK-NEXT: jr $ra +; CHECK-NEXT: nop entry: %sub = fsub double %a, %b ret double %sub } define double @double_mul(double %a, double %b) { -; MIPS32-LABEL: double_mul: -; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: mul.d $f0, $f12, $f14 -; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: nop +; CHECK-LABEL: double_mul: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: mul.d $f0, $f12, $f14 +; CHECK-NEXT: jr $ra +; CHECK-NEXT: nop entry: %mul = fmul double %a, %b ret double %mul } define double @double_div(double %a, double %b) { -; MIPS32-LABEL: double_div: -; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: div.d $f0, $f12, $f14 -; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: nop +; CHECK-LABEL: double_div: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: div.d $f0, $f12, $f14 +; CHECK-NEXT: jr $ra +; CHECK-NEXT: nop entry: %div = fdiv double %a, %b ret double %div diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fpext_and_fptrunc.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fpext_and_fptrunc.ll index 2d1965ffa69f0..752bcca07b88e 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fpext_and_fptrunc.ll +++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fpext_and_fptrunc.ll @@ -1,24 +1,26 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP32 -; RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP64 +; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel \ +; RUN: -verify-machineinstrs %s -o -| FileCheck %s +; RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -global-isel \ +; RUN: -verify-machineinstrs %s -o -| FileCheck %s define double @fpext(float %a) { -; MIPS32-LABEL: fpext: -; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: cvt.d.s $f0, $f12 -; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: nop +; CHECK-LABEL: fpext: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: cvt.d.s $f0, $f12 +; CHECK-NEXT: jr $ra +; CHECK-NEXT: nop entry: %conv = fpext float %a to double ret double %conv } define float @fptrunc(double %a) { -; MIPS32-LABEL: fptrunc: -; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: cvt.s.d $f0, $f12 -; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: nop +; CHECK-LABEL: fptrunc: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: cvt.s.d $f0, $f12 +; CHECK-NEXT: jr $ra +; CHECK-NEXT: nop entry: %conv = fptrunc double %a to float ret float %conv diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fsqrt.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fsqrt.ll index 1bca4e893d9c3..96913ee6914e4 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fsqrt.ll +++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fsqrt.ll @@ -1,14 +1,16 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP32 -; RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP64 +; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel \ +; RUN: -verify-machineinstrs %s -o -| FileCheck %s +; RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -global-isel \ +; RUN: -verify-machineinstrs %s -o -| FileCheck %s declare float @llvm.sqrt.f32(float) define float @sqrt_f32(float %a) { -; MIPS32-LABEL: sqrt_f32: -; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: sqrt.s $f0, $f12 -; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: nop +; CHECK-LABEL: sqrt_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sqrt.s $f0, $f12 +; CHECK-NEXT: jr $ra +; CHECK-NEXT: nop entry: %0 = call float @llvm.sqrt.f32(float %a) ret float %0 @@ -16,11 +18,11 @@ entry: declare double @llvm.sqrt.f64(double) define double @sqrt_f64(double %a) { -; MIPS32-LABEL: sqrt_f64: -; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: sqrt.d $f0, $f12 -; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: nop +; CHECK-LABEL: sqrt_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sqrt.d $f0, $f12 +; CHECK-NEXT: jr $ra +; CHECK-NEXT: nop entry: %0 = call double @llvm.sqrt.f64(double %a) ret double %0 diff --git a/llvm/test/CodeGen/Mips/atomicCmpSwapPW.ll b/llvm/test/CodeGen/Mips/atomicCmpSwapPW.ll index ce994c2c18a9b..cf8cf7e539318 100644 --- a/llvm/test/CodeGen/Mips/atomicCmpSwapPW.ll +++ b/llvm/test/CodeGen/Mips/atomicCmpSwapPW.ll @@ -2,7 +2,7 @@ ; RUN: llc -O0 -mtriple=mipsel-unknown-linux-gnu -mcpu=mips32r2 -target-abi=o32 < %s -filetype=asm -o - \ ; RUN: | FileCheck -check-prefixes=O32 %s ; RUN: llc -O0 -mtriple=mips64el-unknown-linux-gnu -mcpu=mips64r2 -target-abi=n32 < %s -filetype=asm -o - \ -; RUN: | FileCheck -check-prefixes=N32,ALL %s +; RUN: | FileCheck -check-prefixes=N32 %s ; RUN: llc -O0 -mtriple=mips64el-unknown-linux-gnu -mcpu=mips64r2 -target-abi=n64 < %s -filetype=asm -o - \ ; RUN: | FileCheck -check-prefixes=N64 %s diff --git a/llvm/test/CodeGen/Mips/cconv/arguments-float.ll b/llvm/test/CodeGen/Mips/cconv/arguments-float.ll index 004f6d94749d8..ccb75a4a8b0b9 100644 --- a/llvm/test/CodeGen/Mips/cconv/arguments-float.ll +++ b/llvm/test/CodeGen/Mips/cconv/arguments-float.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mips -relocation-model=static -mattr=+soft-float < %s | FileCheck --check-prefixes=ALL,SYM32,O32,O32BE %s -; RUN: llc -march=mipsel -relocation-model=static -mattr=+soft-float < %s | FileCheck --check-prefixes=ALL,SYM32,O32,O32LE %s +; RUN: llc -march=mips -relocation-model=static -mattr=+soft-float < %s | FileCheck --check-prefixes=ALL,SYM32,O32 %s +; RUN: llc -march=mipsel -relocation-model=static -mattr=+soft-float < %s | FileCheck --check-prefixes=ALL,SYM32,O32 %s ; RUN-TODO: llc -march=mips64 -relocation-model=static -mattr=+soft-float -target-abi o32 < %s | FileCheck --check-prefixes=ALL,SYM32,O32 %s ; RUN-TODO: llc -march=mips64el -relocation-model=static -mattr=+soft-float -target-abi o32 < %s | FileCheck --check-prefixes=ALL,SYM32,O32 %s diff --git a/llvm/test/CodeGen/Mips/cconv/arguments-varargs.ll b/llvm/test/CodeGen/Mips/cconv/arguments-varargs.ll index 14c0391a25291..898d189d202a1 100644 --- a/llvm/test/CodeGen/Mips/cconv/arguments-varargs.ll +++ b/llvm/test/CodeGen/Mips/cconv/arguments-varargs.ll @@ -1,7 +1,7 @@ ; RUN: llc -mtriple=mips-linux -relocation-model=static < %s \ -; RUN: | FileCheck --check-prefixes=ALL,O32,O32-BE %s +; RUN: | FileCheck --check-prefixes=ALL,O32 %s ; RUN: llc -mtriple=mipsel-linux -relocation-model=static < %s \ -; RUN: | FileCheck --check-prefixes=ALL,O32,O32-LE %s +; RUN: | FileCheck --check-prefixes=ALL,O32 %s ; RUN-TODO: llc -march=mips64 -relocation-model=static -target-abi o32 < %s \ ; RUN-TODO: | FileCheck --check-prefixes=ALL,O32 %s diff --git a/llvm/test/CodeGen/Mips/cconv/callee-saved-fpxx.ll b/llvm/test/CodeGen/Mips/cconv/callee-saved-fpxx.ll index bd33e0c516972..1a604e7b5e89e 100644 --- a/llvm/test/CodeGen/Mips/cconv/callee-saved-fpxx.ll +++ b/llvm/test/CodeGen/Mips/cconv/callee-saved-fpxx.ll @@ -1,12 +1,12 @@ -; RUN: llc -march=mips -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=ALL,O32-FPXX %s -; RUN: llc -march=mipsel -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=ALL,O32-FPXX %s -; RUN: llc -march=mips -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=ALL,O32-FPXX-INV %s -; RUN: llc -march=mipsel -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=ALL,O32-FPXX-INV %s +; RUN: llc -march=mips -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=O32-FPXX %s +; RUN: llc -march=mipsel -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=O32-FPXX %s +; RUN: llc -march=mips -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=O32-FPXX-INV %s +; RUN: llc -march=mipsel -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=O32-FPXX-INV %s -; RUN-TODO: llc -march=mips64 -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=ALL,O32-FPXX %s -; RUN-TODO: llc -march=mips64el -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=ALL,O32-FPXX %s -; RUN-TODO: llc -march=mips64 -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=ALL,O32-FPXX-INV,O32-FPXX-INV %s -; RUN-TODO: llc -march=mips64el -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=ALL,O32-FPXX-INV,O32-FPXX-INV %s +; RUN-TODO: llc -march=mips64 -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=O32-FPXX %s +; RUN-TODO: llc -march=mips64el -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=O32-FPXX %s +; RUN-TODO: llc -march=mips64 -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=O32-FPXX-INV,O32-FPXX-INV %s +; RUN-TODO: llc -march=mips64el -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=O32-FPXX-INV,O32-FPXX-INV %s define void @fpu_clobber() nounwind { entry: diff --git a/llvm/test/CodeGen/Mips/cconv/vector.ll b/llvm/test/CodeGen/Mips/cconv/vector.ll index 071949d7b9e1c..99053f3641f05 100644 --- a/llvm/test/CodeGen/Mips/cconv/vector.ll +++ b/llvm/test/CodeGen/Mips/cconv/vector.ll @@ -1,12 +1,12 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32 -disable-mips-delay-filler | FileCheck %s --check-prefixes=ALL,MIPS32,MIPS32EB -; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -relocation-model=pic -mcpu=mips64 -disable-mips-delay-filler -mips-jalr-reloc=false | FileCheck %s --check-prefixes=ALL,MIPS64,MIPS64EB -; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r5 -mattr=+fp64,+msa -disable-mips-delay-filler | FileCheck %s --check-prefixes=ALL,MIPS32R5,MIPS32R5EB -; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -relocation-model=pic -mcpu=mips64r5 -mattr=+fp64,+msa -disable-mips-delay-filler -mips-jalr-reloc=false | FileCheck %s --check-prefixes=ALL,MIPS64R5,MIPS64R5EB -; RUN: llc < %s -mtriple=mipsel-unknown-linux-gnu -mcpu=mips32 -disable-mips-delay-filler | FileCheck %s --check-prefixes=ALL,MIPS32,MIPS32EL -; RUN: llc < %s -mtriple=mips64el-unknown-linux-gnu -relocation-model=pic -mcpu=mips64 -disable-mips-delay-filler -mips-jalr-reloc=false | FileCheck %s --check-prefixes=ALL,MIPS64,MIPS64EL -; RUN: llc < %s -mtriple=mipsel-unknown-linux-gnu -mcpu=mips32r5 -mattr=+fp64,+msa -disable-mips-delay-filler | FileCheck %s --check-prefixes=ALL,MIPS32R5,MIPS32R5EL -; RUN: llc < %s -mtriple=mips64el-unknown-linux-gnu -relocation-model=pic -mcpu=mips64r5 -mattr=+fp64,+msa -disable-mips-delay-filler -mips-jalr-reloc=false | FileCheck %s --check-prefixes=ALL,MIPS64R5,MIPS64R5EL +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32 -disable-mips-delay-filler | FileCheck %s --check-prefixes=MIPS32,MIPS32EB +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -relocation-model=pic -mcpu=mips64 -disable-mips-delay-filler -mips-jalr-reloc=false | FileCheck %s --check-prefixes=MIPS64,MIPS64EB +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r5 -mattr=+fp64,+msa -disable-mips-delay-filler | FileCheck %s --check-prefixes=MIPS32R5,MIPS32R5EB +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -relocation-model=pic -mcpu=mips64r5 -mattr=+fp64,+msa -disable-mips-delay-filler -mips-jalr-reloc=false | FileCheck %s --check-prefixes=MIPS64R5,MIPS64R5EB +; RUN: llc < %s -mtriple=mipsel-unknown-linux-gnu -mcpu=mips32 -disable-mips-delay-filler | FileCheck %s --check-prefixes=MIPS32,MIPS32EL +; RUN: llc < %s -mtriple=mips64el-unknown-linux-gnu -relocation-model=pic -mcpu=mips64 -disable-mips-delay-filler -mips-jalr-reloc=false | FileCheck %s --check-prefixes=MIPS64,MIPS64EL +; RUN: llc < %s -mtriple=mipsel-unknown-linux-gnu -mcpu=mips32r5 -mattr=+fp64,+msa -disable-mips-delay-filler | FileCheck %s --check-prefixes=MIPS32R5,MIPS32R5EL +; RUN: llc < %s -mtriple=mips64el-unknown-linux-gnu -relocation-model=pic -mcpu=mips64r5 -mattr=+fp64,+msa -disable-mips-delay-filler -mips-jalr-reloc=false | FileCheck %s --check-prefixes=MIPS64R5,MIPS64R5EL ; Test that vector types are passed through the integer register set whether or ; not MSA is enabled. This is a ABI requirement for MIPS. For GCC compatibility diff --git a/llvm/test/CodeGen/Mips/ehframe-indirect.ll b/llvm/test/CodeGen/Mips/ehframe-indirect.ll index ab799ebed3cec..98a2f389ed042 100644 --- a/llvm/test/CodeGen/Mips/ehframe-indirect.ll +++ b/llvm/test/CodeGen/Mips/ehframe-indirect.ll @@ -3,15 +3,17 @@ ; RUN: llc -mtriple=mipsel-linux-android < %s -asm-verbose -relocation-model=pic | \ ; RUN: FileCheck -check-prefixes=ALL,LINUX,LINUX-O32,O32 %s ; RUN: llc -mtriple=mips64el-linux-gnu -target-abi=n32 < %s -asm-verbose -relocation-model=pic | \ -; RUN: FileCheck -check-prefixes=ALL,LINUX,LINUX-N32,N32 %s +; RUN: FileCheck -check-prefixes=ALL,LINUX,LINUX-NEW,N32 %s ; RUN: llc -mtriple=mips64el-linux-gnu < %s -asm-verbose -relocation-model=pic | \ -; RUN: FileCheck -check-prefixes=ALL,LINUX,LINUX-N64,N64 %s +; RUN: FileCheck -check-prefixes=ALL,LINUX,LINUX-NEW,N64 %s ; RUN: llc -mtriple=mips64el-linux-android < %s -asm-verbose -relocation-model=pic | \ -; RUN: FileCheck -check-prefixes=ALL,LINUX,LINUX-N64,N64 %s +; RUN: FileCheck -check-prefixes=ALL,LINUX,LINUX-NEW,N64 %s ; RUN: llc -mtriple=mips64el-linux-gnu < %s -asm-verbose -relocation-model=pic | \ -; RUN: FileCheck -check-prefixes=ALL,LINUX,LINUX-N64,N64 %s +; RUN: FileCheck -check-prefixes=ALL,LINUX,LINUX-NEW,N64 %s +; RUN: llc -mtriple=mips-unknown-freebsd11.0 < %s -asm-verbose -relocation-model=pic | \ +; RUN: FileCheck -check-prefixes=ALL,FREEBSD,FREEBSD-O32,O32 %s ; RUN: llc -mtriple=mips64-unknown-freebsd11.0 < %s -asm-verbose -relocation-model=pic | \ -; RUN: FileCheck -check-prefixes=ALL,FREEBSD,FREEBSD-N64,N64 %s +; RUN: FileCheck -check-prefixes=ALL,FREEBSD,FREEBSD-NEW,N64 %s @_ZTISt9exception = external constant i8* diff --git a/llvm/test/CodeGen/Mips/fmadd1.ll b/llvm/test/CodeGen/Mips/fmadd1.ll index d7f6308ac0b00..4704387bf289b 100644 --- a/llvm/test/CodeGen/Mips/fmadd1.ll +++ b/llvm/test/CodeGen/Mips/fmadd1.ll @@ -5,29 +5,29 @@ ; IEEE 754 (1985) and IEEE 754 (2008). These instructions are therefore only ; available when -enable-no-nans-fp-math is given. -; RUN: llc < %s -march=mipsel -mcpu=mips32 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,32-NOMADD,32-NONAN-NOMADD +; RUN: llc < %s -march=mipsel -mcpu=mips32 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,32-NOMADD ; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,32R2,32R2-NONAN -; RUN: llc < %s -march=mipsel -mcpu=mips32r6 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,32R6-NOMADD,32R6-NONAN-NOMADD +; RUN: llc < %s -march=mipsel -mcpu=mips32r6 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,32R6-NOMADD ; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,64,64-NONAN ; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,64R2,64R2-NONAN -; RUN: llc < %s -march=mips64el -mcpu=mips64r6 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,64R6-NOMADD,64R6-NONAN-NOMADD -; RUN: llc < %s -march=mipsel -mcpu=mips32 | FileCheck %s -check-prefixes=ALL,32-NOMADD,32-NAN-NOMADD +; RUN: llc < %s -march=mips64el -mcpu=mips64r6 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,64R6-NOMADD +; RUN: llc < %s -march=mipsel -mcpu=mips32 | FileCheck %s -check-prefixes=ALL,32-NOMADD ; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefixes=ALL,32R2,32R2-NAN -; RUN: llc < %s -march=mipsel -mcpu=mips32r6 | FileCheck %s -check-prefixes=ALL,32R6-NOMADD,32R6-NAN-NOMADD +; RUN: llc < %s -march=mipsel -mcpu=mips32r6 | FileCheck %s -check-prefixes=ALL,32R6-NOMADD ; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi=n64 | FileCheck %s -check-prefixes=ALL,64,64-NAN ; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 | FileCheck %s -check-prefixes=ALL,64R2,64R2-NAN -; RUN: llc < %s -march=mips64el -mcpu=mips64r6 -target-abi=n64 | FileCheck %s -check-prefixes=ALL,64R6-NOMADD,64R6-NAN-NOMADD +; RUN: llc < %s -march=mips64el -mcpu=mips64r6 -target-abi=n64 | FileCheck %s -check-prefixes=ALL,64R6-NOMADD ; Check that madd.[ds], msub.[ds], nmadd.[ds], and nmsub.[ds] are not generated ; when +nomadd attribute is specified. ; Output for mips32 and mips64r6 reused since aforementioned instructions are ; not generated in those cases. -; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -enable-no-nans-fp-math -mattr=+nomadd4 | FileCheck %s -check-prefixes=ALL,32-NOMADD,32-NONAN-NOMADD -; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi=n64 -enable-no-nans-fp-math -mattr=+nomadd4 | FileCheck %s -check-prefixes=ALL,64R6-NOMADD,64R6-NONAN-NOMADD -; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 -enable-no-nans-fp-math -mattr=+nomadd4 | FileCheck %s -check-prefixes=ALL,64R6-NOMADD,64R6-NONAN-NOMADD -; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -mattr=+nomadd4 | FileCheck %s -check-prefixes=ALL,32-NOMADD,32-NAN-NOMADD -; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi=n64 -mattr=+nomadd4 | FileCheck %s -check-prefixes=ALL,64R6-NOMADD,64R6-NAN-NOMADD -; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 -mattr=+nomadd4 | FileCheck %s -check-prefixes=ALL,64R6-NOMADD,64R6-NAN-NOMADD +; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -enable-no-nans-fp-math -mattr=+nomadd4 | FileCheck %s -check-prefixes=ALL,32-NOMADD +; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi=n64 -enable-no-nans-fp-math -mattr=+nomadd4 | FileCheck %s -check-prefixes=ALL,64R6-NOMADD +; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 -enable-no-nans-fp-math -mattr=+nomadd4 | FileCheck %s -check-prefixes=ALL,64R6-NOMADD +; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -mattr=+nomadd4 | FileCheck %s -check-prefixes=ALL,32-NOMADD +; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi=n64 -mattr=+nomadd4 | FileCheck %s -check-prefixes=ALL,64R6-NOMADD +; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 -mattr=+nomadd4 | FileCheck %s -check-prefixes=ALL,64R6-NOMADD define float @FOO0float(float %a, float %b, float %c) nounwind readnone { entry: diff --git a/llvm/test/CodeGen/Mips/fpbr.ll b/llvm/test/CodeGen/Mips/fpbr.ll index 7fb508f606b28..251c5392575b2 100644 --- a/llvm/test/CodeGen/Mips/fpbr.ll +++ b/llvm/test/CodeGen/Mips/fpbr.ll @@ -1,8 +1,8 @@ -; RUN: llc < %s -march=mipsel -mcpu=mips32 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,FCC,32-FCC -; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,FCC,32-FCC +; RUN: llc < %s -march=mipsel -mcpu=mips32 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,32-FCC +; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,32-FCC ; RUN: llc < %s -march=mipsel -mcpu=mips32r6 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,GPR,32-GPR -; RUN: llc < %s -march=mips64el -mcpu=mips64 | FileCheck %s -check-prefixes=ALL,FCC,64-FCC -; RUN: llc < %s -march=mips64el -mcpu=mips64r2 | FileCheck %s -check-prefixes=ALL,FCC,64-FCC +; RUN: llc < %s -march=mips64el -mcpu=mips64 | FileCheck %s -check-prefixes=ALL,64-FCC +; RUN: llc < %s -march=mips64el -mcpu=mips64r2 | FileCheck %s -check-prefixes=ALL,64-FCC ; RUN: llc < %s -march=mips64el -mcpu=mips64r6 | FileCheck %s -check-prefixes=ALL,GPR,64-GPR define void @func0(float %f2, float %f3) nounwind { diff --git a/llvm/test/CodeGen/Mips/llvm-ir/mul.ll b/llvm/test/CodeGen/Mips/llvm-ir/mul.ll index c75bda3f394ad..9be26cc88db0c 100644 --- a/llvm/test/CodeGen/Mips/llvm-ir/mul.ll +++ b/llvm/test/CodeGen/Mips/llvm-ir/mul.ll @@ -15,11 +15,11 @@ ; RUN: llc < %s -march=mips64 -mcpu=mips64 -relocation-model=pic | \ ; RUN: FileCheck %s -check-prefixes=ALL,64R1-R5,GP64-NOT-R6 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 -relocation-model=pic | \ -; RUN: FileCheck %s -check-prefixes=ALL,64R1-R5,GP64,GP64-NOT-R6 +; RUN: FileCheck %s -check-prefixes=ALL,64R1-R5,GP64-NOT-R6 ; RUN: llc < %s -march=mips64 -mcpu=mips64r3 -relocation-model=pic | \ -; RUN: FileCheck %s -check-prefixes=ALL,64R1-R5,GP64,GP64-NOT-R6 +; RUN: FileCheck %s -check-prefixes=ALL,64R1-R5,GP64-NOT-R6 ; RUN: llc < %s -march=mips64 -mcpu=mips64r5 -relocation-model=pic | \ -; RUN: FileCheck %s -check-prefixes=ALL,64R1-R5,GP64,GP64-NOT-R6 +; RUN: FileCheck %s -check-prefixes=ALL,64R1-R5,GP64-NOT-R6 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | \ ; RUN: FileCheck %s -check-prefixes=ALL,64R6 ; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | \ diff --git a/llvm/test/CodeGen/Mips/llvm-ir/ret.ll b/llvm/test/CodeGen/Mips/llvm-ir/ret.ll index 6f9894f9855d2..7b37784370662 100644 --- a/llvm/test/CodeGen/Mips/llvm-ir/ret.ll +++ b/llvm/test/CodeGen/Mips/llvm-ir/ret.ll @@ -163,7 +163,7 @@ define float @ret_float_0x0() { ; MTHC1-DAG: mtc1 $zero, $f0 -; DMTC-DAG: dmtc1 $zero, $f0 +; DMTC1-DAG: mtc1 $zero, $f0 ; NOT-R6-DAG: jr $ra # %2 = load volatile <16 x i8>, <16 x i8>* %1 - ; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], 0($sp) + ; CHECK: ld.b [[R1:\$w[0-9]+]], 0($sp) store volatile <16 x i8> %2, <16 x i8>* %1 - ; MIPS32-AE: st.b [[R1]], 0($sp) + ; CHECK: st.b [[R1]], 0($sp) ret void - ; MIPS32-AE: .size loadstore_v16i8_near + ; CHECK: .size loadstore_v16i8_near } define void @loadstore_v16i8_just_under_simm10() nounwind { - ; MIPS32-AE: loadstore_v16i8_just_under_simm10: + ; CHECK: loadstore_v16i8_just_under_simm10: %1 = alloca <16 x i8> %2 = alloca [492 x i8] ; Push the frame--acounting for the emergency spill ; slot--right up to 512 bytes %3 = load volatile <16 x i8>, <16 x i8>* %1 - ; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], 496($sp) + ; CHECK: ld.b [[R1:\$w[0-9]+]], 496($sp) store volatile <16 x i8> %3, <16 x i8>* %1 - ; MIPS32-AE: st.b [[R1]], 496($sp) + ; CHECK: st.b [[R1]], 496($sp) ret void - ; MIPS32-AE: .size loadstore_v16i8_just_under_simm10 + ; CHECK: .size loadstore_v16i8_just_under_simm10 } define void @loadstore_v16i8_just_over_simm10() nounwind { - ; MIPS32-AE: loadstore_v16i8_just_over_simm10: + ; CHECK: loadstore_v16i8_just_over_simm10: %1 = alloca <16 x i8> %2 = alloca [497 x i8] ; Push the frame--acounting for the emergency spill ; slot--right up to 512 bytes %3 = load volatile <16 x i8>, <16 x i8>* %1 - ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 512 - ; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], 0([[BASE]]) + ; CHECK: addiu [[BASE:\$([0-9]+|gp)]], $sp, 512 + ; CHECK: ld.b [[R1:\$w[0-9]+]], 0([[BASE]]) store volatile <16 x i8> %3, <16 x i8>* %1 - ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 512 - ; MIPS32-AE: st.b [[R1]], 0([[BASE]]) + ; CHECK: addiu [[BASE:\$([0-9]+|gp)]], $sp, 512 + ; CHECK: st.b [[R1]], 0([[BASE]]) ret void - ; MIPS32-AE: .size loadstore_v16i8_just_over_simm10 + ; CHECK: .size loadstore_v16i8_just_over_simm10 } define void @loadstore_v16i8_just_under_simm16() nounwind { - ; MIPS32-AE: loadstore_v16i8_just_under_simm16: + ; CHECK: loadstore_v16i8_just_under_simm16: %1 = alloca <16 x i8> %2 = alloca [32752 x i8] ; Push the frame--acounting for the emergency spill ; slot--right up to 32768 bytes %3 = load volatile <16 x i8>, <16 x i8>* %1 - ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768 - ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]] - ; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], 0([[BASE]]) + ; CHECK: ori [[R2:\$([0-9]+|gp)]], $zero, 32768 + ; CHECK: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]] + ; CHECK: ld.b [[R1:\$w[0-9]+]], 0([[BASE]]) store volatile <16 x i8> %3, <16 x i8>* %1 - ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768 - ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]] - ; MIPS32-AE: st.b [[R1]], 0([[BASE]]) + ; CHECK: ori [[R2:\$([0-9]+|gp)]], $zero, 32768 + ; CHECK: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]] + ; CHECK: st.b [[R1]], 0([[BASE]]) ret void - ; MIPS32-AE: .size loadstore_v16i8_just_under_simm16 + ; CHECK: .size loadstore_v16i8_just_under_simm16 } define void @loadstore_v16i8_just_over_simm16() nounwind { - ; MIPS32-AE: loadstore_v16i8_just_over_simm16: + ; CHECK: loadstore_v16i8_just_over_simm16: %1 = alloca <16 x i8> %2 = alloca [32753 x i8] ; Push the frame--acounting for the emergency spill ; slot--just over 32768 bytes %3 = load volatile <16 x i8>, <16 x i8>* %1 - ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768 - ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]] - ; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], 0([[BASE]]) + ; CHECK: ori [[R2:\$([0-9]+|gp)]], $zero, 32768 + ; CHECK: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]] + ; CHECK: ld.b [[R1:\$w[0-9]+]], 0([[BASE]]) store volatile <16 x i8> %3, <16 x i8>* %1 - ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768 - ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]] - ; MIPS32-AE: st.b [[R1]], 0([[BASE]]) + ; CHECK: ori [[R2:\$([0-9]+|gp)]], $zero, 32768 + ; CHECK: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]] + ; CHECK: st.b [[R1]], 0([[BASE]]) ret void - ; MIPS32-AE: .size loadstore_v16i8_just_over_simm16 + ; CHECK: .size loadstore_v16i8_just_over_simm16 } define void @loadstore_v8i16_near() nounwind { - ; MIPS32-AE: loadstore_v8i16_near: + ; CHECK: loadstore_v8i16_near: %1 = alloca <8 x i16> %2 = load volatile <8 x i16>, <8 x i16>* %1 - ; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], 0($sp) + ; CHECK: ld.h [[R1:\$w[0-9]+]], 0($sp) store volatile <8 x i16> %2, <8 x i16>* %1 - ; MIPS32-AE: st.h [[R1]], 0($sp) + ; CHECK: st.h [[R1]], 0($sp) ret void - ; MIPS32-AE: .size loadstore_v8i16_near + ; CHECK: .size loadstore_v8i16_near } define void @loadstore_v8i16_unaligned() nounwind { - ; MIPS32-AE: loadstore_v8i16_unaligned: + ; CHECK: loadstore_v8i16_unaligned: %1 = alloca [2 x <8 x i16>] %2 = bitcast [2 x <8 x i16>]* %1 to i8* @@ -113,105 +111,105 @@ define void @loadstore_v8i16_unaligned() nounwind { %5 = getelementptr [2 x <8 x i16>], [2 x <8 x i16>]* %4, i32 0, i32 0 %6 = load volatile <8 x i16>, <8 x i16>* %5 - ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1 - ; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], 0([[BASE]]) + ; CHECK: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1 + ; CHECK: ld.h [[R1:\$w[0-9]+]], 0([[BASE]]) store volatile <8 x i16> %6, <8 x i16>* %5 - ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1 - ; MIPS32-AE: st.h [[R1]], 0([[BASE]]) + ; CHECK: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1 + ; CHECK: st.h [[R1]], 0([[BASE]]) ret void - ; MIPS32-AE: .size loadstore_v8i16_unaligned + ; CHECK: .size loadstore_v8i16_unaligned } define void @loadstore_v8i16_just_under_simm10() nounwind { - ; MIPS32-AE: loadstore_v8i16_just_under_simm10: + ; CHECK: loadstore_v8i16_just_under_simm10: %1 = alloca <8 x i16> %2 = alloca [1004 x i8] ; Push the frame--acounting for the emergency spill ; slot--right up to 1024 bytes %3 = load volatile <8 x i16>, <8 x i16>* %1 - ; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], 1008($sp) + ; CHECK: ld.h [[R1:\$w[0-9]+]], 1008($sp) store volatile <8 x i16> %3, <8 x i16>* %1 - ; MIPS32-AE: st.h [[R1]], 1008($sp) + ; CHECK: st.h [[R1]], 1008($sp) ret void - ; MIPS32-AE: .size loadstore_v8i16_just_under_simm10 + ; CHECK: .size loadstore_v8i16_just_under_simm10 } define void @loadstore_v8i16_just_over_simm10() nounwind { - ; MIPS32-AE: loadstore_v8i16_just_over_simm10: + ; CHECK: loadstore_v8i16_just_over_simm10: %1 = alloca <8 x i16> %2 = alloca [1009 x i8] ; Push the frame--acounting for the emergency spill ; slot--just over 1024 bytes %3 = load volatile <8 x i16>, <8 x i16>* %1 - ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1024 - ; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], 0([[BASE]]) + ; CHECK: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1024 + ; CHECK: ld.h [[R1:\$w[0-9]+]], 0([[BASE]]) store volatile <8 x i16> %3, <8 x i16>* %1 - ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1024 - ; MIPS32-AE: st.h [[R1]], 0([[BASE]]) + ; CHECK: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1024 + ; CHECK: st.h [[R1]], 0([[BASE]]) ret void - ; MIPS32-AE: .size loadstore_v8i16_just_over_simm10 + ; CHECK: .size loadstore_v8i16_just_over_simm10 } define void @loadstore_v8i16_just_under_simm16() nounwind { - ; MIPS32-AE: loadstore_v8i16_just_under_simm16: + ; CHECK: loadstore_v8i16_just_under_simm16: %1 = alloca <8 x i16> %2 = alloca [32752 x i8] ; Push the frame--acounting for the emergency spill ; slot--right up to 32768 bytes %3 = load volatile <8 x i16>, <8 x i16>* %1 - ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768 - ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]] - ; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], 0([[BASE]]) + ; CHECK: ori [[R2:\$([0-9]+|gp)]], $zero, 32768 + ; CHECK: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]] + ; CHECK: ld.h [[R1:\$w[0-9]+]], 0([[BASE]]) store volatile <8 x i16> %3, <8 x i16>* %1 - ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768 - ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]] - ; MIPS32-AE: st.h [[R1]], 0([[BASE]]) + ; CHECK: ori [[R2:\$([0-9]+|gp)]], $zero, 32768 + ; CHECK: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]] + ; CHECK: st.h [[R1]], 0([[BASE]]) ret void - ; MIPS32-AE: .size loadstore_v8i16_just_under_simm16 + ; CHECK: .size loadstore_v8i16_just_under_simm16 } define void @loadstore_v8i16_just_over_simm16() nounwind { - ; MIPS32-AE: loadstore_v8i16_just_over_simm16: + ; CHECK: loadstore_v8i16_just_over_simm16: %1 = alloca <8 x i16> %2 = alloca [32753 x i8] ; Push the frame--acounting for the emergency spill ; slot--just over 32768 bytes %3 = load volatile <8 x i16>, <8 x i16>* %1 - ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768 - ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]] - ; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], 0([[BASE]]) + ; CHECK: ori [[R2:\$([0-9]+|gp)]], $zero, 32768 + ; CHECK: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]] + ; CHECK: ld.h [[R1:\$w[0-9]+]], 0([[BASE]]) store volatile <8 x i16> %3, <8 x i16>* %1 - ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768 - ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]] - ; MIPS32-AE: st.h [[R1]], 0([[BASE]]) + ; CHECK: ori [[R2:\$([0-9]+|gp)]], $zero, 32768 + ; CHECK: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]] + ; CHECK: st.h [[R1]], 0([[BASE]]) ret void - ; MIPS32-AE: .size loadstore_v8i16_just_over_simm16 + ; CHECK: .size loadstore_v8i16_just_over_simm16 } define void @loadstore_v4i32_near() nounwind { - ; MIPS32-AE: loadstore_v4i32_near: + ; CHECK: loadstore_v4i32_near: %1 = alloca <4 x i32> %2 = load volatile <4 x i32>, <4 x i32>* %1 - ; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0($sp) + ; CHECK: ld.w [[R1:\$w[0-9]+]], 0($sp) store volatile <4 x i32> %2, <4 x i32>* %1 - ; MIPS32-AE: st.w [[R1]], 0($sp) + ; CHECK: st.w [[R1]], 0($sp) ret void - ; MIPS32-AE: .size loadstore_v4i32_near + ; CHECK: .size loadstore_v4i32_near } define void @loadstore_v4i32_unaligned() nounwind { - ; MIPS32-AE: loadstore_v4i32_unaligned: + ; CHECK: loadstore_v4i32_unaligned: %1 = alloca [2 x <4 x i32>] %2 = bitcast [2 x <4 x i32>]* %1 to i8* @@ -220,105 +218,105 @@ define void @loadstore_v4i32_unaligned() nounwind { %5 = getelementptr [2 x <4 x i32>], [2 x <4 x i32>]* %4, i32 0, i32 0 %6 = load volatile <4 x i32>, <4 x i32>* %5 - ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1 - ; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[BASE]]) + ; CHECK: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1 + ; CHECK: ld.w [[R1:\$w[0-9]+]], 0([[BASE]]) store volatile <4 x i32> %6, <4 x i32>* %5 - ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1 - ; MIPS32-AE: st.w [[R1]], 0([[BASE]]) + ; CHECK: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1 + ; CHECK: st.w [[R1]], 0([[BASE]]) ret void - ; MIPS32-AE: .size loadstore_v4i32_unaligned + ; CHECK: .size loadstore_v4i32_unaligned } define void @loadstore_v4i32_just_under_simm10() nounwind { - ; MIPS32-AE: loadstore_v4i32_just_under_simm10: + ; CHECK: loadstore_v4i32_just_under_simm10: %1 = alloca <4 x i32> %2 = alloca [2028 x i8] ; Push the frame--acounting for the emergency spill ; slot--right up to 2048 bytes %3 = load volatile <4 x i32>, <4 x i32>* %1 - ; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 2032($sp) + ; CHECK: ld.w [[R1:\$w[0-9]+]], 2032($sp) store volatile <4 x i32> %3, <4 x i32>* %1 - ; MIPS32-AE: st.w [[R1]], 2032($sp) + ; CHECK: st.w [[R1]], 2032($sp) ret void - ; MIPS32-AE: .size loadstore_v4i32_just_under_simm10 + ; CHECK: .size loadstore_v4i32_just_under_simm10 } define void @loadstore_v4i32_just_over_simm10() nounwind { - ; MIPS32-AE: loadstore_v4i32_just_over_simm10: + ; CHECK: loadstore_v4i32_just_over_simm10: %1 = alloca <4 x i32> %2 = alloca [2033 x i8] ; Push the frame--acounting for the emergency spill ; slot--just over 2048 bytes %3 = load volatile <4 x i32>, <4 x i32>* %1 - ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 2048 - ; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[BASE]]) + ; CHECK: addiu [[BASE:\$([0-9]+|gp)]], $sp, 2048 + ; CHECK: ld.w [[R1:\$w[0-9]+]], 0([[BASE]]) store volatile <4 x i32> %3, <4 x i32>* %1 - ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 2048 - ; MIPS32-AE: st.w [[R1]], 0([[BASE]]) + ; CHECK: addiu [[BASE:\$([0-9]+|gp)]], $sp, 2048 + ; CHECK: st.w [[R1]], 0([[BASE]]) ret void - ; MIPS32-AE: .size loadstore_v4i32_just_over_simm10 + ; CHECK: .size loadstore_v4i32_just_over_simm10 } define void @loadstore_v4i32_just_under_simm16() nounwind { - ; MIPS32-AE: loadstore_v4i32_just_under_simm16: + ; CHECK: loadstore_v4i32_just_under_simm16: %1 = alloca <4 x i32> %2 = alloca [32752 x i8] ; Push the frame--acounting for the emergency spill ; slot-- right up to 32768 bytes %3 = load volatile <4 x i32>, <4 x i32>* %1 - ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768 - ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]] - ; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[BASE]]) + ; CHECK: ori [[R2:\$([0-9]+|gp)]], $zero, 32768 + ; CHECK: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]] + ; CHECK: ld.w [[R1:\$w[0-9]+]], 0([[BASE]]) store volatile <4 x i32> %3, <4 x i32>* %1 - ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768 - ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]] - ; MIPS32-AE: st.w [[R1]], 0([[BASE]]) + ; CHECK: ori [[R2:\$([0-9]+|gp)]], $zero, 32768 + ; CHECK: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]] + ; CHECK: st.w [[R1]], 0([[BASE]]) ret void - ; MIPS32-AE: .size loadstore_v4i32_just_under_simm16 + ; CHECK: .size loadstore_v4i32_just_under_simm16 } define void @loadstore_v4i32_just_over_simm16() nounwind { - ; MIPS32-AE: loadstore_v4i32_just_over_simm16: + ; CHECK: loadstore_v4i32_just_over_simm16: %1 = alloca <4 x i32> %2 = alloca [32753 x i8] ; Push the frame--acounting for the emergency spill ; slot--just over 32768 bytes %3 = load volatile <4 x i32>, <4 x i32>* %1 - ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768 - ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]] - ; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[BASE]]) + ; CHECK: ori [[R2:\$([0-9]+|gp)]], $zero, 32768 + ; CHECK: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]] + ; CHECK: ld.w [[R1:\$w[0-9]+]], 0([[BASE]]) store volatile <4 x i32> %3, <4 x i32>* %1 - ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768 - ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]] - ; MIPS32-AE: st.w [[R1]], 0([[BASE]]) + ; CHECK: ori [[R2:\$([0-9]+|gp)]], $zero, 32768 + ; CHECK: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]] + ; CHECK: st.w [[R1]], 0([[BASE]]) ret void - ; MIPS32-AE: .size loadstore_v4i32_just_over_simm16 + ; CHECK: .size loadstore_v4i32_just_over_simm16 } define void @loadstore_v2i64_near() nounwind { - ; MIPS32-AE: loadstore_v2i64_near: + ; CHECK: loadstore_v2i64_near: %1 = alloca <2 x i64> %2 = load volatile <2 x i64>, <2 x i64>* %1 - ; MIPS32-AE: ld.d [[R1:\$w[0-9]+]], 0($sp) + ; CHECK: ld.d [[R1:\$w[0-9]+]], 0($sp) store volatile <2 x i64> %2, <2 x i64>* %1 - ; MIPS32-AE: st.d [[R1]], 0($sp) + ; CHECK: st.d [[R1]], 0($sp) ret void - ; MIPS32-AE: .size loadstore_v2i64_near + ; CHECK: .size loadstore_v2i64_near } define void @loadstore_v2i64_unaligned() nounwind { - ; MIPS32-AE: loadstore_v2i64_unaligned: + ; CHECK: loadstore_v2i64_unaligned: %1 = alloca [2 x <2 x i64>] %2 = bitcast [2 x <2 x i64>]* %1 to i8* @@ -327,85 +325,85 @@ define void @loadstore_v2i64_unaligned() nounwind { %5 = getelementptr [2 x <2 x i64>], [2 x <2 x i64>]* %4, i32 0, i32 0 %6 = load volatile <2 x i64>, <2 x i64>* %5 - ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1 - ; MIPS32-AE: ld.d [[R1:\$w[0-9]+]], 0([[BASE]]) + ; CHECK: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1 + ; CHECK: ld.d [[R1:\$w[0-9]+]], 0([[BASE]]) store volatile <2 x i64> %6, <2 x i64>* %5 - ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1 - ; MIPS32-AE: st.d [[R1]], 0([[BASE]]) + ; CHECK: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1 + ; CHECK: st.d [[R1]], 0([[BASE]]) ret void - ; MIPS32-AE: .size loadstore_v2i64_unaligned + ; CHECK: .size loadstore_v2i64_unaligned } define void @loadstore_v2i64_just_under_simm10() nounwind { - ; MIPS32-AE: loadstore_v2i64_just_under_simm10: + ; CHECK: loadstore_v2i64_just_under_simm10: %1 = alloca <2 x i64> %2 = alloca [4076 x i8] ; Push the frame--acounting for the emergency spill ; slot--right up to 4096 bytes %3 = load volatile <2 x i64>, <2 x i64>* %1 - ; MIPS32-AE: ld.d [[R1:\$w[0-9]+]], 4080($sp) + ; CHECK: ld.d [[R1:\$w[0-9]+]], 4080($sp) store volatile <2 x i64> %3, <2 x i64>* %1 - ; MIPS32-AE: st.d [[R1]], 4080($sp) + ; CHECK: st.d [[R1]], 4080($sp) ret void - ; MIPS32-AE: .size loadstore_v2i64_just_under_simm10 + ; CHECK: .size loadstore_v2i64_just_under_simm10 } define void @loadstore_v2i64_just_over_simm10() nounwind { - ; MIPS32-AE: loadstore_v2i64_just_over_simm10: + ; CHECK: loadstore_v2i64_just_over_simm10: %1 = alloca <2 x i64> %2 = alloca [4081 x i8] ; Push the frame--acounting for the emergency spill ; slot--just over 4096 bytes %3 = load volatile <2 x i64>, <2 x i64>* %1 - ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 4096 - ; MIPS32-AE: ld.d [[R1:\$w[0-9]+]], 0([[BASE]]) + ; CHECK: addiu [[BASE:\$([0-9]+|gp)]], $sp, 4096 + ; CHECK: ld.d [[R1:\$w[0-9]+]], 0([[BASE]]) store volatile <2 x i64> %3, <2 x i64>* %1 - ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 4096 - ; MIPS32-AE: st.d [[R1]], 0([[BASE]]) + ; CHECK: addiu [[BASE:\$([0-9]+|gp)]], $sp, 4096 + ; CHECK: st.d [[R1]], 0([[BASE]]) ret void - ; MIPS32-AE: .size loadstore_v2i64_just_over_simm10 + ; CHECK: .size loadstore_v2i64_just_over_simm10 } define void @loadstore_v2i64_just_under_simm16() nounwind { - ; MIPS32-AE: loadstore_v2i64_just_under_simm16: + ; CHECK: loadstore_v2i64_just_under_simm16: %1 = alloca <2 x i64> %2 = alloca [32752 x i8] ; Push the frame--acounting for the emergency spill ; slot--right up to 32768 bytes %3 = load volatile <2 x i64>, <2 x i64>* %1 - ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768 - ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]] - ; MIPS32-AE: ld.d [[R1:\$w[0-9]+]], 0([[BASE]]) + ; CHECK: ori [[R2:\$([0-9]+|gp)]], $zero, 32768 + ; CHECK: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]] + ; CHECK: ld.d [[R1:\$w[0-9]+]], 0([[BASE]]) store volatile <2 x i64> %3, <2 x i64>* %1 - ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768 - ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]] - ; MIPS32-AE: st.d [[R1]], 0([[BASE]]) + ; CHECK: ori [[R2:\$([0-9]+|gp)]], $zero, 32768 + ; CHECK: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]] + ; CHECK: st.d [[R1]], 0([[BASE]]) ret void - ; MIPS32-AE: .size loadstore_v2i64_just_under_simm16 + ; CHECK: .size loadstore_v2i64_just_under_simm16 } define void @loadstore_v2i64_just_over_simm16() nounwind { - ; MIPS32-AE: loadstore_v2i64_just_over_simm16: + ; CHECK: loadstore_v2i64_just_over_simm16: %1 = alloca <2 x i64> %2 = alloca [32753 x i8] ; Push the frame--acounting for the emergency spill ; slot--just over 32768 bytes %3 = load volatile <2 x i64>, <2 x i64>* %1 - ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768 - ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]] - ; MIPS32-AE: ld.d [[R1:\$w[0-9]+]], 0([[BASE]]) + ; CHECK: ori [[R2:\$([0-9]+|gp)]], $zero, 32768 + ; CHECK: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]] + ; CHECK: ld.d [[R1:\$w[0-9]+]], 0([[BASE]]) store volatile <2 x i64> %3, <2 x i64>* %1 - ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768 - ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]] - ; MIPS32-AE: st.d [[R1]], 0([[BASE]]) + ; CHECK: ori [[R2:\$([0-9]+|gp)]], $zero, 32768 + ; CHECK: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]] + ; CHECK: st.d [[R1]], 0([[BASE]]) ret void - ; MIPS32-AE: .size loadstore_v2i64_just_over_simm16 + ; CHECK: .size loadstore_v2i64_just_over_simm16 } diff --git a/llvm/test/CodeGen/Mips/msa/i5-s.ll b/llvm/test/CodeGen/Mips/msa/i5-s.ll index cbc21edfa52fd..179320e0813c8 100644 --- a/llvm/test/CodeGen/Mips/msa/i5-s.ll +++ b/llvm/test/CodeGen/Mips/msa/i5-s.ll @@ -1,8 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s \ -; RUN: | FileCheck %s --check-prefixes=ALL,MIPS -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s \ -; RUN: | FileCheck %s --check-prefixes=ALL,MIPSEL +; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r5 < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r5 < %s | FileCheck %s ; Test the MSA intrinsics that are encoded with the I5 instruction format. ; There are lots of these so this covers those beginning with 's' @@ -11,16 +9,16 @@ @llvm_mips_subvi_b_RES = global <16 x i8> , align 16 define void @llvm_mips_subvi_b_test() nounwind { -; ALL-LABEL: llvm_mips_subvi_b_test: -; ALL: # %bb.0: # %entry -; ALL-NEXT: lui $1, %hi(llvm_mips_subvi_b_RES) -; ALL-NEXT: addiu $1, $1, %lo(llvm_mips_subvi_b_RES) -; ALL-NEXT: lui $2, %hi(llvm_mips_subvi_b_ARG1) -; ALL-NEXT: addiu $2, $2, %lo(llvm_mips_subvi_b_ARG1) -; ALL-NEXT: ld.b $w0, 0($2) -; ALL-NEXT: subvi.b $w0, $w0, 14 -; ALL-NEXT: jr $ra -; ALL-NEXT: st.b $w0, 0($1) +; CHECK-LABEL: llvm_mips_subvi_b_test: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: lui $1, %hi(llvm_mips_subvi_b_RES) +; CHECK-NEXT: addiu $1, $1, %lo(llvm_mips_subvi_b_RES) +; CHECK-NEXT: lui $2, %hi(llvm_mips_subvi_b_ARG1) +; CHECK-NEXT: addiu $2, $2, %lo(llvm_mips_subvi_b_ARG1) +; CHECK-NEXT: ld.b $w0, 0($2) +; CHECK-NEXT: subvi.b $w0, $w0, 14 +; CHECK-NEXT: jr $ra +; CHECK-NEXT: st.b $w0, 0($1) entry: %0 = load <16 x i8>, <16 x i8>* @llvm_mips_subvi_b_ARG1 %1 = tail call <16 x i8> @llvm.mips.subvi.b(<16 x i8> %0, i32 14) @@ -34,16 +32,16 @@ declare <16 x i8> @llvm.mips.subvi.b(<16 x i8>, i32) nounwind @llvm_mips_subvi_h_RES = global <8 x i16> , align 16 define void @llvm_mips_subvi_h_test() nounwind { -; ALL-LABEL: llvm_mips_subvi_h_test: -; ALL: # %bb.0: # %entry -; ALL-NEXT: lui $1, %hi(llvm_mips_subvi_h_RES) -; ALL-NEXT: addiu $1, $1, %lo(llvm_mips_subvi_h_RES) -; ALL-NEXT: lui $2, %hi(llvm_mips_subvi_h_ARG1) -; ALL-NEXT: addiu $2, $2, %lo(llvm_mips_subvi_h_ARG1) -; ALL-NEXT: ld.h $w0, 0($2) -; ALL-NEXT: subvi.h $w0, $w0, 14 -; ALL-NEXT: jr $ra -; ALL-NEXT: st.h $w0, 0($1) +; CHECK-LABEL: llvm_mips_subvi_h_test: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: lui $1, %hi(llvm_mips_subvi_h_RES) +; CHECK-NEXT: addiu $1, $1, %lo(llvm_mips_subvi_h_RES) +; CHECK-NEXT: lui $2, %hi(llvm_mips_subvi_h_ARG1) +; CHECK-NEXT: addiu $2, $2, %lo(llvm_mips_subvi_h_ARG1) +; CHECK-NEXT: ld.h $w0, 0($2) +; CHECK-NEXT: subvi.h $w0, $w0, 14 +; CHECK-NEXT: jr $ra +; CHECK-NEXT: st.h $w0, 0($1) entry: %0 = load <8 x i16>, <8 x i16>* @llvm_mips_subvi_h_ARG1 %1 = tail call <8 x i16> @llvm.mips.subvi.h(<8 x i16> %0, i32 14) @@ -57,16 +55,16 @@ declare <8 x i16> @llvm.mips.subvi.h(<8 x i16>, i32) nounwind @llvm_mips_subvi_w_RES = global <4 x i32> , align 16 define void @llvm_mips_subvi_w_test() nounwind { -; ALL-LABEL: llvm_mips_subvi_w_test: -; ALL: # %bb.0: # %entry -; ALL-NEXT: lui $1, %hi(llvm_mips_subvi_w_RES) -; ALL-NEXT: addiu $1, $1, %lo(llvm_mips_subvi_w_RES) -; ALL-NEXT: lui $2, %hi(llvm_mips_subvi_w_ARG1) -; ALL-NEXT: addiu $2, $2, %lo(llvm_mips_subvi_w_ARG1) -; ALL-NEXT: ld.w $w0, 0($2) -; ALL-NEXT: subvi.w $w0, $w0, 14 -; ALL-NEXT: jr $ra -; ALL-NEXT: st.w $w0, 0($1) +; CHECK-LABEL: llvm_mips_subvi_w_test: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: lui $1, %hi(llvm_mips_subvi_w_RES) +; CHECK-NEXT: addiu $1, $1, %lo(llvm_mips_subvi_w_RES) +; CHECK-NEXT: lui $2, %hi(llvm_mips_subvi_w_ARG1) +; CHECK-NEXT: addiu $2, $2, %lo(llvm_mips_subvi_w_ARG1) +; CHECK-NEXT: ld.w $w0, 0($2) +; CHECK-NEXT: subvi.w $w0, $w0, 14 +; CHECK-NEXT: jr $ra +; CHECK-NEXT: st.w $w0, 0($1) entry: %0 = load <4 x i32>, <4 x i32>* @llvm_mips_subvi_w_ARG1 %1 = tail call <4 x i32> @llvm.mips.subvi.w(<4 x i32> %0, i32 14) @@ -80,16 +78,16 @@ declare <4 x i32> @llvm.mips.subvi.w(<4 x i32>, i32) nounwind @llvm_mips_subvi_d_RES = global <2 x i64> , align 16 define void @llvm_mips_subvi_d_test() nounwind { -; ALL-LABEL: llvm_mips_subvi_d_test: -; ALL: # %bb.0: # %entry -; ALL-NEXT: lui $1, %hi(llvm_mips_subvi_d_RES) -; ALL-NEXT: addiu $1, $1, %lo(llvm_mips_subvi_d_RES) -; ALL-NEXT: lui $2, %hi(llvm_mips_subvi_d_ARG1) -; ALL-NEXT: addiu $2, $2, %lo(llvm_mips_subvi_d_ARG1) -; ALL-NEXT: ld.d $w0, 0($2) -; ALL-NEXT: subvi.d $w0, $w0, 14 -; ALL-NEXT: jr $ra -; ALL-NEXT: st.d $w0, 0($1) +; CHECK-LABEL: llvm_mips_subvi_d_test: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: lui $1, %hi(llvm_mips_subvi_d_RES) +; CHECK-NEXT: addiu $1, $1, %lo(llvm_mips_subvi_d_RES) +; CHECK-NEXT: lui $2, %hi(llvm_mips_subvi_d_ARG1) +; CHECK-NEXT: addiu $2, $2, %lo(llvm_mips_subvi_d_ARG1) +; CHECK-NEXT: ld.d $w0, 0($2) +; CHECK-NEXT: subvi.d $w0, $w0, 14 +; CHECK-NEXT: jr $ra +; CHECK-NEXT: st.d $w0, 0($1) entry: %0 = load <2 x i64>, <2 x i64>* @llvm_mips_subvi_d_ARG1 %1 = tail call <2 x i64> @llvm.mips.subvi.d(<2 x i64> %0, i32 14) diff --git a/llvm/test/CodeGen/Mips/reloc-jalr.ll b/llvm/test/CodeGen/Mips/reloc-jalr.ll index ef360266a1bb4..10fc3ac5f5af6 100644 --- a/llvm/test/CodeGen/Mips/reloc-jalr.ll +++ b/llvm/test/CodeGen/Mips/reloc-jalr.ll @@ -105,6 +105,7 @@ entry: ; JALR-32: .reloc ([[TMPLABEL:\$.+]]), R_MIPS_JALR, foo ; JALR-64: .reloc [[TMPLABEL:\..+]], R_MIPS_JALR, foo ; JALR-MM: .reloc ([[TMPLABEL:\$.+]]), R_MICROMIPS_JALR, foo +; NORELOC-NOT: .reloc ; JALR-ALL-NEXT: [[TMPLABEL]]: ; JALR-32R2-NEXT: jalr $25 ; JALR-64R2-NEXT: jalr $25 @@ -124,6 +125,7 @@ entry: ; JALR-64: .reloc [[TMPLABEL:\..+]], R_MIPS_JALR, foo ; JALR-MM: .reloc ([[TMPLABEL:\$.+]]), R_MICROMIPS_JALR, foo ; JALR-ALL-NEXT: [[TMPLABEL]]: +; NORELOC-NOT: .reloc ; TAILCALL-32R2-NEXT: jr $25 ; TAILCALL-64R2-NEXT: jr $25 ; TAILCALL-MM-NEXT: jrc $25 @@ -178,6 +180,7 @@ entry: ; JALR-ALL: .reloc {{.+}}MIPS_JALR, __tls_get_addr ; ALL-NOT: MIPS_JALR ; JALR-ALL: .reloc {{.+}}MIPS_JALR, __tls_get_addr +; NORELOC-NOT: .reloc ; ALL-NOT: _MIPS_JALR %func_gd = load void()*, void()** @tls_fnptr_gd call void %func_gd() diff --git a/llvm/test/CodeGen/Mips/unalignedload.ll b/llvm/test/CodeGen/Mips/unalignedload.ll index ba476b6c4554f..9a4a0456a7e59 100644 --- a/llvm/test/CodeGen/Mips/unalignedload.ll +++ b/llvm/test/CodeGen/Mips/unalignedload.ll @@ -1,9 +1,9 @@ -; RUN: llc < %s -march=mipsel -mcpu=mips32 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,ALL-EL,MIPS32-EL -; RUN: llc < %s -march=mips -mcpu=mips32 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,ALL-EB,MIPS32-EB -; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,ALL-EL,MIPS32-EL -; RUN: llc < %s -march=mips -mcpu=mips32r2 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,ALL-EB,MIPS32-EB -; RUN: llc < %s -march=mipsel -mcpu=mips32r6 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,ALL-EL,MIPS32R6-EL -; RUN: llc < %s -march=mips -mcpu=mips32r6 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,ALL-EB,MIPS32R6-EB +; RUN: llc < %s -march=mipsel -mcpu=mips32 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,MIPS32-EL +; RUN: llc < %s -march=mips -mcpu=mips32 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,MIPS32-EB +; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,MIPS32-EL +; RUN: llc < %s -march=mips -mcpu=mips32r2 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,MIPS32-EB +; RUN: llc < %s -march=mipsel -mcpu=mips32r6 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,MIPS32R6-EL +; RUN: llc < %s -march=mips -mcpu=mips32r6 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,MIPS32R6-EB %struct.S2 = type { %struct.S1, %struct.S1 } %struct.S1 = type { i8, i8 } %struct.S4 = type { [7 x i8] } diff --git a/llvm/test/MC/Mips/elf_header.s b/llvm/test/MC/Mips/elf_header.s index eb6252061c4b5..a7dfeaa4ca92e 100644 --- a/llvm/test/MC/Mips/elf_header.s +++ b/llvm/test/MC/Mips/elf_header.s @@ -1,5 +1,5 @@ # Default ABI for MIPS32 is O32. -# RUN: llvm-mc -filetype=obj -triple mips-unknown-linux -mcpu=mips1 %s -o - | llvm-readobj -h - | FileCheck --check-prefixes=ALL,ELF32,BE,O32,NAN1985,MIPS1 %s +# RUN: llvm-mc -filetype=obj -triple mips-unknown-linux -mcpu=mips1 %s -o - | llvm-readobj -h - | FileCheck --check-prefixes=ALL,ELF32,BE,O32,NAN1985 %s # RUN: llvm-mc -filetype=obj -triple mips-unknown-linux -mcpu=mips2 %s -o - | llvm-readobj -h - | FileCheck --check-prefixes=ALL,ELF32,BE,O32,NAN1985,MIPS2 %s # RUN: llvm-mc -filetype=obj -triple mips-unknown-linux -mcpu=mips3 %s -o - | llvm-readobj -h - | FileCheck --check-prefixes=ALL,ELF32,BE,O32,NAN1985,MIPS3,32BITMODE %s # RUN: llvm-mc -filetype=obj -triple mips-unknown-linux -mcpu=mips4 %s -o - | llvm-readobj -h - | FileCheck --check-prefixes=ALL,ELF32,BE,O32,NAN1985,MIPS4,32BITMODE %s @@ -16,7 +16,7 @@ # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32r6 %s -o - | llvm-readobj -h - | FileCheck --check-prefixes=ALL,ELF32,LE,O32,NAN2008,MIPS32R6 %s # Selected ABI O32 takes precedence over target triple. -# FIXME: llvm-mc -filetype=obj -triple mips64-unknown-linux -mcpu=mips1 -target-abi=o32 %s -o - | llvm-readobj -h - | FileCheck --check-prefixes=ALL,ELF32,BE,O32,NAN1985,MIPS1 %s +# FIXME: llvm-mc -filetype=obj -triple mips64-unknown-linux -mcpu=mips1 -target-abi=o32 %s -o - | llvm-readobj -h - | FileCheck --check-prefixes=ALL,ELF32,BE,O32,NAN1985 %s # FIXME: llvm-mc -filetype=obj -triple mips64-unknown-linux -mcpu=mips2 -target-abi=o32 %s -o - | llvm-readobj -h - | FileCheck --check-prefixes=ALL,ELF32,BE,O32,NAN1985,MIPS2 %s # FIXME: llvm-mc -filetype=obj -triple mips64-unknown-linux -mcpu=mips3 -target-abi=o32 %s -o - | llvm-readobj -h - | FileCheck --check-prefixes=ALL,ELF32,BE,O32,NAN1985,MIPS3,32BITMODE %s # FIXME: llvm-mc -filetype=obj -triple mips64-unknown-linux -mcpu=mips4 -target-abi=o32 %s -o - | llvm-readobj -h - | FileCheck --check-prefixes=ALL,ELF32,BE,O32,NAN1985,MIPS4,32BITMODE %s @@ -139,5 +139,6 @@ # OCTEON-NEXT: EF_MIPS_MACH_OCTEON +# NAN1985-NOT: EF_MIPS_NAN2008 # NAN2008-NEXT: EF_MIPS_NAN2008 # ALL-NEXT: ]