diff --git a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
index 7f7d6e56874c2..32fd64f1140dd 100644
--- a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
@@ -872,7 +872,8 @@ void GCNSchedStage::setupNewBlock() {
   DAG.startBlock(CurrentMBB);
   // Get real RP for the region if it hasn't be calculated before. After the
   // initial schedule stage real RP will be collected after scheduling.
-  if (StageID == GCNSchedStageID::OccInitialSchedule)
+  if (StageID == GCNSchedStageID::OccInitialSchedule ||
+      StageID == GCNSchedStageID::ILPInitialSchedule)
     DAG.computeBlockPressure(RegionIdx, CurrentMBB);
 }
 
diff --git a/llvm/test/CodeGen/AMDGPU/schedule-ilp-liveness-tracking.mir b/llvm/test/CodeGen/AMDGPU/schedule-ilp-liveness-tracking.mir
new file mode 100644
index 0000000000000..4b6e204ecf957
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/schedule-ilp-liveness-tracking.mir
@@ -0,0 +1,33 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -amdgpu-enable-max-ilp-scheduling-strategy -verify-machineinstrs -run-pass=machine-scheduler -verify-misched -o - %s | FileCheck %s
+
+---
+name:            max-ilp-liveness-tracking
+tracksRegLiveness: true
+body:             |
+  ; CHECK-LABEL: name: max-ilp-liveness-tracking
+  ; CHECK: bb.0:
+  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   %src0:vgpr_32 = V_MOV_B32_e64 0, implicit $exec
+  ; CHECK-NEXT:   %src1:vgpr_32 = V_MOV_B32_e64 1, implicit $exec
+  ; CHECK-NEXT:   %live0:vgpr_32 = V_ADD_U32_e32 %src0, %src1, implicit $exec
+  ; CHECK-NEXT:   %live1:vgpr_32 = V_ADD_U32_e32 %live0, %src1, implicit $exec
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1:
+  ; CHECK-NEXT:   %out0:vgpr_32 = V_ADD_U32_e32 %live0, %live1, implicit $exec
+  ; CHECK-NEXT:   dead %out1:vgpr_32 = V_ADD_U32_e32 %out0, %live1, implicit $exec
+  ; CHECK-NEXT:   S_ENDPGM 0
+  bb.0:
+    successors: %bb.1
+    %src0:vgpr_32 = V_MOV_B32_e64 0, implicit $exec
+    %src1:vgpr_32 = V_MOV_B32_e64 1, implicit $exec
+    %live0:vgpr_32 = V_ADD_U32_e32 %src0:vgpr_32, %src1:vgpr_32, implicit $exec
+    %live1:vgpr_32 = V_ADD_U32_e32 %live0:vgpr_32, %src1:vgpr_32, implicit $exec
+
+  bb.1:
+    %out0:vgpr_32 = V_ADD_U32_e32 %live0:vgpr_32, %live1:vgpr_32, implicit $exec
+    %out1:vgpr_32 = V_ADD_U32_e32 %out0:vgpr_32, %live1:vgpr_32, implicit $exec
+    S_ENDPGM 0
+
+...